Semiconductor memory device and method for manufacturing semiconductor memory device

Abstract

The embodiment of the invention relates to a semiconductor memory device and a manufacturing method of the semiconductor memory device. According to one embodiment, a semiconductor memory device includes a first stacked body, a second stacked body, a source line, a first columnar portion, a second columnar portion, a first bit line, and a second bit line. The source line is disposed between the first laminate and the second laminate in the first direction. The first columnar portion extends in a first direction through the inside of the first laminated body. The second columnar portion extends through the inside of the second laminated body in the first direction. The first bit line is disposed on the opposite side of the source line with respect to the first stacked body. The second bit line is disposed on the opposite side of the source line with respect to the second stacked body.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device and a method for manufacturing a semiconductor memory device. Background Technology

[0002] NAND flash memory with storage cells arranged in three dimensions is known (for example, see Japanese Patent Application Publication No. 2018-152419). Summary of the Invention

[0003] A semiconductor memory device according to one embodiment includes a first stacked layer, a second stacked layer, a source line, a first pillar portion, a second pillar portion, a first bit line, and a second bit line. The first stacked layer includes a plurality of first gate electrode layers and a plurality of first insulating layers. The plurality of first gate electrode layers and the plurality of first insulating layers are stacked alternately layer by layer in a first direction. The second stacked layer is disposed on a first side in the first direction relative to the first stacked layer. The second stacked layer includes a plurality of second gate electrode layers and a plurality of second insulating layers. The plurality of second gate electrode layers and the plurality of second insulating layers are stacked alternately layer by layer in the first direction. The source line is disposed between the first stacked layer and the second stacked layer in the first direction. The source line extends in a second direction intersecting the first direction. The first pillar portion extends through the first stacked layer in the first direction. The first pillar portion includes a first storage film having a charge storage portion and a first semiconductor film. The second columnar portion extends through the second stacked body in the first direction. The second columnar portion includes a second storage film having a charge storage portion and a second semiconductor film. The first bit line is disposed on the opposite side of the source line relative to the first stacked body. The first bit line is electrically connected to the first columnar portion. The second bit line is disposed on the opposite side of the source line relative to the second stacked body. The second bit line is electrically connected to the second columnar portion. Attached Figure Description

[0004] Figure 1 This is a block diagram showing a portion of the semiconductor memory device according to the first embodiment.

[0005] Figure 2 This is a diagram showing an equivalent circuit of a portion of the memory cell array in the first embodiment.

[0006] Figure 3 This is a diagram used to illustrate the semiconductor memory device of the first embodiment.

[0007] Figure 4 This is a diagram illustrating the region division of the storage cell array in the first embodiment.

[0008] Figure 5 yes Figure 4 The cross-sectional view of the semiconductor memory device shown along line F5-F5.

[0009] Figure 6 yes Figure 4 The cross-sectional view of the semiconductor memory device shown along line F6-F6.

[0010] Figure 7 It is Figure 4 The diagram shows an enlarged representation of the area enclosed by line F7.

[0011] Figure 8 It is Figure 7 The diagram shows an enlarged representation of the area enclosed by line F8.

[0012] Figure 9 This is a cross-sectional view used to illustrate the storage column of the first embodiment.

[0013] Figure 10 yes Figure 9 The structure shown is a cross-sectional view along line F10-F10.

[0014] Figure 11 This is a cross-sectional view schematically illustrating the structure of the semiconductor memory device according to the first embodiment.

[0015] Figure 12 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0016] Figure 13 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0017] Figure 14 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0018] Figure 15 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0019] Figure 16 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0020] Figure 17 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0021] Figure 18 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0022] Figure 19This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0023] Figure 20 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0024] Figure 21 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0025] Figure 22 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0026] Figure 23 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0027] Figure 24 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0028] Figure 25 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0029] Figure 26 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0030] Figure 27 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0031] Figure 28 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0032] Figure 29 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0033] Figure 30 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0034] Figure 31 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0035] Figure 32 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0036] Figure 33 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0037] Figure 34 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0038] Figure 35 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0039] Figure 36 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0040] Figure 37 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0041] Figure 38 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0042] Figure 39 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0043] Figure 40 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0044] Figure 41 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0045] Figure 42 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0046] Figure 43 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0047] Figure 44 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0048] Figure 45 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0049] Figure 46 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0050] Figure 47 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0051] Figure 48This is a cross-sectional view showing a portion of the semiconductor memory device according to the second embodiment.

[0052] Figure 49 This is a cross-sectional view used to illustrate the storage column of the second embodiment.

[0053] Figure 50 yes Figure 48 The structure shown is a cross-sectional view along line F50-F50.

[0054] Figure 51 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0055] Figure 52 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0056] Figure 53 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0057] Figure 54 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0058] Figure 55 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0059] Figure 56 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment. Detailed Implementation

[0060] Hereinafter, with reference to the accompanying drawings, a semiconductor memory device according to an embodiment and a method for manufacturing a semiconductor memory device will be described. In the following description, components having the same or similar functions will be labeled with the same symbols. Furthermore, repeated descriptions of these components may sometimes be omitted. In the following description, reference symbols ending with numbers or letters for distinction may sometimes be omitted if there is no need to distinguish them. In the accompanying drawings described below, illustrations of components unrelated to the description may sometimes be omitted.

[0061] In this application, the terms are defined as follows. "Parallel," "orthogonal," or "identical" may respectively include cases of "generally parallel," "generally orthogonal," or "generally identical." "Connection" is not limited to mechanical connections and may include electrical connections. That is, "connection" is not limited to the direct connection of multiple elements and may include the connection of multiple elements with other elements intervening in between. "Adjacent" is not limited to the contact of multiple elements and may include the adjacent arrangement of multiple elements with other elements intervening in between.

[0062] The definitions of +X direction, -X direction, +Y direction, -Y direction, +Z direction, and -Z direction are as follows. The +X direction is the extension direction of the following word line WL (refer to...). Figure 5 The -X direction is the opposite of the +X direction. When there is no need to distinguish between the +X and -X directions, it is simply referred to as the "X direction". The +Y direction is the direction that intersects (e.g., is orthogonal) the X direction. The +Y direction is the extension direction of the bit line BL (see reference). Figure 7 The -Y direction is the opposite of the +Y direction. When there is no need to distinguish between the +Y and -Y directions, it is simply referred to as the "Y direction". The +Z direction is the direction that intersects (e.g., orthogonally) the X and Y directions. The +Z direction is the direction from the first laminate 40A to the second laminate 40B (see reference). Figure 5 The -Z direction is the opposite of the +Z direction. When there is no need to distinguish between the +Z and -Z directions, it is simply referred to as the "Z direction". In this application, the +Z direction side is sometimes referred to as "upper" and the -Z direction side as "lower". Additionally, in this application, the position of the Z direction is sometimes referred to as "height". However, these expressions are only for ease of explanation and are not intended to define the direction of gravity. The Z direction is an example of a "first direction". The +Z direction side is an example of a "first side". The -Z direction side is an example of a "second side". The X direction is an example of a "second direction".

[0063] (First Embodiment)

[0064] <A1. Structure of Semiconductor Memory Devices>

[0065] Figure 1 This is a block diagram illustrating a portion of the semiconductor memory device 1 according to the first embodiment. The semiconductor memory device 1 is, for example, a non-volatile semiconductor memory device. The semiconductor memory device 1 is a NAND flash memory. The semiconductor memory device 1 can be connected to an external host device. The semiconductor memory device 1 serves as storage space for the host device. The semiconductor memory device 1 includes, for example, a memory cell array 11, an instruction register 12, an address register 13, a control circuit (sequencer) 14, a driver module 15, a line decoder module 16, and a sense amplifier module 17.

[0066] The memory cell array 11 contains multiple blocks BLK0 to BLK(k-1) (where k is an integer greater than or equal to 1). A block BLK is a collection of memory cell transistors. Block BLK is used as the unit for data erasure. The memory cell array 11 has multiple bit lines and multiple word lines. Each memory cell transistor is associated with one bit line and one word line.

[0067] Instruction register 12 stores the instruction CMD received by semiconductor memory device 1 from the host device. Address register 13 stores the address information ADD received by semiconductor memory device 1 from the host device. The address information ADD is used for the selection of block BLK, word line, and bit line. Control circuit 14 controls various operations of semiconductor memory device 1. For example, based on the instruction CMD stored in instruction register 12, control circuit 14 performs data writing, reading, or erasing operations.

[0068] Driver module 15 includes voltage generation circuitry that generates the voltages required for various operations of semiconductor memory device 1. Row decoder module 16 transmits the voltage applied to the signal lines corresponding to the select word lines to the select word lines. Sensing amplifier module 17 applies the desired voltage to each bit line during write operations. During read operations, sensing amplifier module 17 determines the data stored in each memory cell transistor based on the voltage of each bit line and transmits the determination result as read data DAT to the host device. Sensing amplifier module 17 is an example of a "circuit".

[0069] <A2. Electrical Configuration of Memory Cell Array>

[0070] <A2.1 Composition related to a single block BLK>

[0071] Figure 2 This is a diagram showing the equivalent circuit of a portion of the memory cell array 11. Figure 2 The diagram shows a block BLK contained in the storage cell array 11. The block BLK contains multiple strings STR (e.g., four strings STR0 to STR3).

[0072] Each string STR contains multiple NAND strings NS that are associated with bit lines BL0 to BLm (where m is an integer greater than or equal to 1). Each NAND string NS contains multiple memory cell transistors MT0 to MTn (where n is an integer greater than or equal to 1), one or more drain-side select transistors STD, and one or more source-side select transistors STS.

[0073] In each NAND string NS, memory cell transistors MT0 to MTn are connected in series. Each memory cell transistor MT includes a control gate and a charge storage section. The control gate of the memory cell transistor MT is connected to any one of the word lines WL0 to WLn. In each memory cell transistor MT, charge is stored in the charge storage section according to the voltage applied to the control gate via the word line WL. Thus, each memory cell transistor MT non-volatilely stores data.

[0074] The drain of the drain-side select transistor STD is connected to the bit line BL corresponding to the NAND string NS. The source of the drain-side select transistor STD is connected to one end of the series-connected memory cell transistors MT0 to MTn. The control gate of the drain-side select transistor STD is connected to any one of the drain-side select gate lines SGD0 to SGD3. The drain-side select transistor STD is electrically connected to the row decoder module 16 via the drain-side select gate line SGD. When a specified voltage is applied to the corresponding drain-side select gate line SGD, the drain-side select transistor STD connects the NAND string NS to the bit line BL.

[0075] The drain of the source-side select transistor STS is connected to the other end of the series-connected memory cell transistors MT0 to MTn. The source of the source-side select transistor STS is connected to the source line SL. The control gate of the source-side select transistor STS is connected to the source-side select gate line SGS. When a specified voltage is applied to the source-side select gate line SGS, the source-side select transistor STS connects the NAND string NS to the source line SL.

[0076] Within the same BLK, the control gates of memory cell transistors MT0 to MTn are commonly connected to their respective word lines WL0 to WLn. Within the same STR string, the control gates of drain-side select transistors STD are commonly connected to their corresponding drain-side select gate line SGD. The control gates of source-side select transistors STS are commonly connected to their source-side select gate line SGS. In the memory cell array 11, the bit line BL is shared by NAND strings NS that are assigned the same column address in multiple STR strings.

[0077] <A2.2 Structure Related to Multiple Block BLKs>

[0078] Figure 3 This is a diagram used to illustrate semiconductor memory device 1. Figure 3 The diagram illustrates a plurality of blocks BLK contained in the memory cell array 11. The memory cell array 11 contains a plurality of blocks BLK. Each block BLK contains a plurality of blocks BLKA (blocks BLKA0 to BLKAj (j being an integer greater than or equal to 1)) and a plurality of blocks BLKB (blocks BLKB0 to BLKBj (j being an integer greater than or equal to 1)). Block BLKA is the first stacked layer 40A described below (refer to...). Figure 5 The block BLK is contained within ) . The block BLKB is the second build body 40B described below (refer to Figure 5 The BLK block contained in ).

[0079] In this embodiment, the memory cell array 11 includes multiple bit lines BL. The multiple bit lines BL include multiple bit lines BLA (bit lines BLA0 to BLAAm (m is an integer greater than or equal to 1)) and multiple bit lines BLB (bit lines BLB0 to BLBm (m is an integer greater than or equal to 1)).

[0080] Multiple bit lines BLA are set corresponding to multiple blocks BLKA. For example, multiple bit lines BLA are set commonly relative to multiple blocks BLKA. Hereinafter, for ease of explanation, bit lines BLA are sometimes referred to as "lower bit lines BLA". The lower bit line BLA is an example of "bit line 1".

[0081] Multiple bit lines (BLBs) are set corresponding to multiple blocks (BLKBs). For example, multiple bit lines (BLBs) are set commonly relative to multiple blocks (BLKBs). Hereinafter, for ease of explanation, bit lines (BLBs) are sometimes referred to as "upper bit lines (BLBs)". The upper bit line (BLB) is an example of a "second bit line".

[0082] The sensing amplifier module 17 has a plurality of sensing amplifier units 17a. The plurality of sensing amplifier units 17a are configured corresponding to a plurality of bit lines BL. Each sensing amplifier unit 17a is, for example, a circuit controlled by a signal from the control circuit 14. For example, the sensing amplifier unit 17a has a latching circuit electrically connected to the corresponding bit line BL. The sensing amplifier unit 17a applies a voltage to the corresponding bit line BL based on the signal from the control circuit 14. Each sensing amplifier unit 17a has a terminal 17t connected to the electrical connection line 18 described below. Terminal 17t is an example of a "first terminal".

[0083] In this embodiment, in addition to the above-described configuration, the storage cell array 11 also includes multiple electrical connection lines 18 and a switching circuit 19.

[0084] Multiple electrical connection lines 18 are disposed between multiple sense amplifier units 17a and multiple bit lines BL. The multiple electrical connection lines 18 are connection lines that electrically connect the multiple sense amplifier units 17a and the multiple bit lines BL. The multiple electrical connection lines 18 are arranged in a one-to-one relationship with the multiple sense amplifier units 17a. For example, the multiple electrical connection lines 18 are electrically connected to the terminals 17t of the multiple sense amplifier units 17a in a one-to-one relationship.

[0085] The switching circuit 19 is a circuit capable of switching between at least a first state and a second state. The first state is a state in which the terminals 17t of the plurality of sense amplifier units 17a are electrically connected one-to-one to the plurality of lower-level lines BLA. The second state is a state in which the terminals 17t of the plurality of sense amplifier units 17a are electrically connected one-to-one to the plurality of upper-level lines BLB. The switching circuit 19 includes, for example, switching circuit 19A and switching circuit 19B.

[0086] A switching circuit 19A is disposed between a plurality of electrical connection lines 18 and a plurality of lower-level lines BLA. The switching circuit 19A includes a plurality of switching elements 19Aa that electrically connect the plurality of electrical connection lines 18 and the plurality of lower-level lines BLA in a one-to-one relationship. The plurality of switching elements 19Aa are controlled, for example, by a common signal issued from the control circuit 14 to the plurality of switching elements 19Aa. The switching circuit 19A is capable of switching between a first state and a second state. The first state is a state in which the plurality of electrical connection lines 18 are electrically connected to the plurality of lower-level lines BLA. The second state is a state in which the plurality of electrical connection lines 18 are electrically disconnected from the plurality of lower-level lines BLA.

[0087] A switching circuit 19B is disposed between a plurality of electrical connection lines 18 and a plurality of upper-level lines BLB. The switching circuit 19B includes a plurality of switching elements 19Ba that electrically connect the plurality of electrical connection lines 18 and the plurality of upper-level lines BLB in a one-to-one relationship. The plurality of switching elements 19Ba are controlled, for example, by a common signal issued from the control circuit 14 to the plurality of switching elements 19Ba. The switching circuit 19B is capable of switching between a first state and a second state. The first state is a state in which the plurality of electrical connection lines 18 are electrically connected to the plurality of upper-level lines BLB. The second state is a state in which the plurality of electrical connection lines 18 are electrically disconnected from the plurality of upper-level lines BLB.

[0088] <A3. Structure of Semiconductor Memory Devices>

[0089] Next, the structure of semiconductor memory device 1 will be described.

[0090] <A3.1 Area Division of Storage Cell Array>

[0091] Here, we will first explain the area division of the storage cell array 11.

[0092] Figure 4 This is a diagram illustrating the area division of the memory cell array 11. The memory cell array 11 includes, for example, multiple array areas AR, multiple wiring areas FR, and multiple bit line access areas BR.

[0093] The array region AR is provided with the following multiple storage pillars MH. The array region AR is a region capable of storing data. The wiring region FR is a region provided with the following multiple contacts CC, and the following multiple gate electrode layers 41 are electrically connected to the wiring section 60. Figure 4 In the example shown, the wiring area FR is located on one side of the array area AR in the X direction. However, the wiring area FR can also be located on both sides of the array area AR in the X direction.

[0094] The bit line access area BR has multiple contacts CS. The bit line access area BR is the area where the switching circuit 19 (or the sensing amplifier module 17) is electrically connected to multiple upper bit lines BLB. The bit line access area BR can also be called a "bit line connection area". The bit line access area BR is located between two adjacent array areas AR in the Y direction. The bit line access area BR extends along the X direction.

[0095] <A3.2 Bonding Structure>

[0096] Next, the bonding structure of semiconductor memory device 1 will be described.

[0097] Figure 5 yes Figure 4 The diagram shows a cross-sectional view of the semiconductor memory device 1 along line F5-F5. The semiconductor memory device 1, for example, has a first chip 2 and a second chip 3. The second chip 3 is a chip bonded to the first chip 2.

[0098] (Chip 1)

[0099] The first chip 2 is a circuit chip that includes peripheral circuitry. The first chip 2 includes, for example, a semiconductor substrate 21, peripheral circuitry 22, an insulating portion 23, and multiple solder pads 24.

[0100] The semiconductor substrate 21 is, for example, a substrate that serves as the base for the first chip 2. At least a portion of the semiconductor substrate 21 is plate-shaped along both the X and Y directions. The semiconductor substrate 21 is formed, for example, from a semiconductor material such as silicon.

[0101] The peripheral circuit 22 is a circuit used to enable the memory cell array 11 to function. The peripheral circuit 22 includes multiple transistors 22a and multiple electrical connections 22b. The peripheral circuit 22 includes one or more of the instruction register 12, address register 13, control circuit 14, driver module 15, line decoder module 16, sense amplifier module 17, multiple electrical connections 18, and switching circuit 19. For example, the switching elements 19Aa and 19Ba of the switching circuit 19 are each formed from transistors 22a disposed on the semiconductor substrate 21. An insulating portion 23 covers the peripheral circuit 22. Multiple solder pads 24 are disposed on the surface of the insulating portion 23. Each solder pad 24 is electrically connected to the peripheral circuit 22.

[0102] (Chip 2)

[0103] The second chip 3 is an array chip that includes a memory cell array 11. The second chip 3, for example, has a memory cell array 11, an insulating portion 31, and a plurality of solder pads 32. Here, the insulating portion 31 and the plurality of solder pads 32 will be described, and the memory cell array 11 will be described below.

[0104] An insulating portion 31 covers the memory cell array 11 from the -Z direction side. Multiple solder pads 32 are disposed on the surface of the insulating portion 31. Each solder pad 32 is electrically connected to an electrical connection line (e.g., electrical connection lines 61, 62, 63, 64) included in the wiring portion 60 of the memory cell array 11. In this embodiment, by bonding the multiple solder pads 24 of the first chip 2 to the multiple solder pads 32 of the second chip 3, the first chip 2 and the second chip 3 become a single unit.

[0105] <A4. Structure of the array area and wiring area>

[0106] Next, the structure of the array area AR and the wiring area FR will be explained.

[0107] like Figure 5 As shown, the memory cell array 11 includes, for example, a stacked layer 40, an insulating portion 45, multiple memory pillars MH, multiple lower bit lines BLA, multiple upper bit lines BLB, multiple contacts CH for memory pillars, multiple contacts VY for memory pillars, contacts CC for the gate electrode layer, and multiple interruptions 50 (see reference). Figure 6 The stack 40 includes a first stack 40A, a second stack 40B, and a source line SL. Furthermore, the memory cylinder MH will be described below.

[0108] <A4.1 First Layer>

[0109] The first stacked layer 40A is a stacked layer forming the plurality of block BLKAs. The first stacked layer 40A includes, for example, a plurality of gate electrode layers 41A, a plurality of insulating layers 42A, and an insulating layer 43. The plurality of gate electrode layers 41A and the plurality of insulating layers 42A are stacked alternately layer by layer in the Z direction.

[0110] Gate electrode layer 41A is a conductive layer along the X and Y directions. Each gate electrode layer 41A contains a conductive material (e.g., tungsten, molybdenum, or doped silicon). Gate electrode layer 41A is an example of a "first gate electrode layer".

[0111] Of the plurality of gate electrode layers 41A, one or more (e.g., multiple) of the upper gate electrode layers 41A function as source-side selected gate lines (SGS) for block BLKA. The source-side selected gate lines SGSA are commonly provided with respect to the lower columnar portions 91 (hereinafter) of the plurality of memory pillars MH arranged in the X or Y direction. The intersection portions of the source-side selected gate lines SGSA and the channel layers 72 (hereinafter) of each memory pillar MH function as the source-side selected transistors (STS).

[0112] Of the multiple gate electrode layers 41A, one or more (e.g., multiple) of the lower gate electrode layers 41A function as drain-side selected gate lines SGD (drain-side selected gate lines SGDA) for block BLKA. The drain-side selected gate lines SGDA are commonly provided with respect to the lower columnar portions 91 (hereinafter) of the multiple memory pillars MH arranged in the X or Y direction. The intersection of the drain-side selected gate lines SGDA with the channel layers 72 (hereinafter) of each memory pillar MH functions as the drain-side selected transistor STD.

[0113] Of the plurality of gate electrode layers 41A, the remaining gate electrode layers 41A are those gate electrode layers 41A disposed between the gate electrode layers 41A that function as source-side select gate line SGSA and drain-side select gate line SGDA. At least a portion of these remaining gate electrode layers 41A function as word lines WL (WLA) for block BLKA. The word lines WL are commonly provided with respect to the lower columnar portions 91 (hereinafter) of the plurality of memory pillars MH arranged in the X and Y directions. In this embodiment, the intersection portion of the word lines WL with the channel layer 72 (hereinafter) of each memory pillar MH functions as the memory cell transistor MT.

[0114] In the wiring region FR, the lengths of the multiple gate electrode layers 41A in the X direction are not the same. For example, regarding the length of the multiple gate electrode layers 41A stacked in the Z direction in the X direction, the length of the gate electrode layer 41A located on the +Z direction side in the X direction is greater than the length of the gate electrode layer 41A located on the -Z direction side in the X direction. That is, the longer the gate electrode layer 41A is located on the +Z direction side, the greater its length in the X direction. As a result, the ends of the multiple gate electrode layers 41A are arranged in a stepped manner in the wiring region FR.

[0115] An insulating layer 42A is disposed between two adjacent gate electrode layers 41A in the Z direction. The insulating layer 42A is an interlayer insulating film that insulates the two gate electrode layers 41A. The insulating layer 42A extends along both the X and Y directions. The insulating layer 42A is formed, for example, from a film comprising silicon and oxygen (e.g., a silicon oxide film). The insulating layer 42A is an example of a "first insulating layer".

[0116] The insulating layer 43 is disposed above the uppermost gate electrode layer 41A. In other words, the insulating layer 43 can also be described as an insulating layer disposed above the uppermost gate electrode layer. The insulating layer 43 is disposed between the uppermost gate electrode layer 41A and the source line SL. The insulating layer 43 extends along the X and Y directions. The insulating layer 43 is formed, for example, from a film containing silicon and oxygen (e.g., a silicon oxide film). For example, the thickness of the insulating layer 43 in the Z direction is greater than the thickness of the insulating layer 42A in the Z direction.

[0117] <A4.2 Second Layer>

[0118] The second stacked layer 40B is a stacked layer forming the plurality of blocks BLKB. The second stacked layer 40B is disposed on the upper side (+Z direction side) relative to the first stacked layer 40A. The second stacked layer 40B includes, for example, a plurality of gate electrode layers 41B, a plurality of insulating layers 42B, and an insulating layer 44. The plurality of gate electrode layers 41B and the plurality of insulating layers 42B are stacked alternately layer by layer in the Z direction.

[0119] Gate electrode layer 41B is a conductive layer along the X and Y directions. Each gate electrode layer 41B contains a conductive material (e.g., tungsten, molybdenum, or doped silicon). Gate electrode layer 41B is an example of a "second gate electrode layer".

[0120] Of the multiple gate electrode layers 41B, one or more (e.g., multiple) of the lower gate electrode layers 41B function as source-side selected gate lines (SGS, SGSB) for the block BLKB. The source-side selected gate lines SGSB are commonly provided relative to the upper columnar portions 92 (hereinafter) of the multiple memory pillars MH arranged in the X or Y direction. The intersection of the source-side selected gate lines SGSB with the channel layer 72 (hereinafter) of each memory pillar MH functions as the source-side selected transistor STS.

[0121] Of the multiple gate electrode layers 41B, one or more (e.g., multiple) of the upper gate electrode layers 41B function as drain-side selected gate lines SGD (drain-side selected gate lines SGDB) for the block BLKB. The drain-side selected gate lines SGDB are commonly provided relative to the upper columnar portions 92 (hereinafter) of the multiple memory pillars MH arranged in the X or Y direction. The intersection of the drain-side selected gate lines SGDB with the channel layer 72 (hereinafter) of each memory pillar MH functions as the drain-side selected transistor STD.

[0122] Of the plurality of gate electrode layers 41B, the remaining gate electrode layers 41B are those gate electrode layers 41B that function as source-side select gate line SGSB and drain-side select gate line SGDB. At least a portion of these gate electrode layers 41B function as word lines WL (WLB) for the block BLKB. The word lines WL are commonly provided with respect to the upper columnar portions 92 (hereinafter) of the plurality of memory pillars MH arranged in the X and Y directions. In this embodiment, the intersection of the word lines WL with the channel layers 72 (hereinafter) of each memory pillar MH functions as the memory cell transistor MT.

[0123] In the wiring region FR, the lengths of the multiple gate electrode layers 41B in the X direction are not identical. For example, regarding the length of the multiple gate electrode layers 41B stacked in the Z direction, the length of the gate electrode layer 41B located on the +Z direction side is greater than the length of the gate electrode layer 41B located on the -Z direction side. That is, the closer the gate electrode layer 41B is to the +Z direction side, the greater its length in the X direction. As a result, the ends of the multiple gate electrode layers 41B are arranged in a stepped manner in the wiring region FR.

[0124] An insulating layer 42B is disposed between two adjacent gate electrode layers 41B in the Z direction. The insulating layer 42B is an interlayer insulating film that insulates the two gate electrode layers 41B. The insulating layer 42B extends along both the X and Y directions. The insulating layer 42B is formed, for example, from a film comprising silicon and oxygen (e.g., a silicon oxide film). The insulating layer 42B is an example of a "second insulating layer".

[0125] The insulating layer 44 is disposed below the bottommost gate electrode layer 41B. In other words, the insulating layer 44 can also be described as an insulating layer disposed below the bottommost gate electrode layer. The insulating layer 44 is disposed between the bottommost gate electrode layer 41B and the source line SL. The insulating layer 44 extends along both the X and Y directions. The insulating layer 44 is formed, for example, from a film containing silicon and oxygen (e.g., a silicon oxide film). For example, the thickness of the insulating layer 44 in the Z direction is greater than the thickness of the insulating layer 42B in the Z direction.

[0126] In one example of the semiconductor memory device 1, the number of gate electrode layers 41A included in the first stacked layer 40A is different from the number of gate electrode layers 41B included in the second stacked layer 40B. In this case, the size of the block BLKA included in the first stacked layer 40A is different from the size of the block BLKB included in the second stacked layer 40B. This will be explained in detail below. Alternatively, the number of gate electrode layers 41A included in the first stacked layer 40A may be the same as the number of gate electrode layers 41B included in the second stacked layer 40B.

[0127] Furthermore, in the following text, when there is no need to distinguish between the first gate electrode layer 41A and the second gate electrode layer 41B, they will be referred to as "gate electrode layer 41". When there is no need to distinguish between the first insulating layer 42A and the second insulating layer 42B, they will be referred to as "insulating layer 42".

[0128] <A4.3 Source Line>

[0129] The source line SL is disposed between the first stacked layer 40A and the second stacked layer 40B in the Z direction. The source line SL extends in both the X and Y directions. The source line SL is a conductive or semiconductor layer along both the X and Y directions. The source line SL is formed, for example, from a semiconductor material containing silicon. The source line SL is formed, for example, from polycrystalline silicon doped with impurities. However, the material of the source line SL is not limited to the examples described. The source line SL can also be formed from a metallic material such as tungsten or molybdenum. The thickness of the source line SL in the Z direction is, for example, greater than the sum of the thickness of the gate electrode layer 41 in the Z direction and the thickness of the insulating layer 42 in the Z direction.

[0130] In this embodiment, the source line SL extends across the array region AR and the wiring region FR. The source line SL includes a first portion SLa disposed in the array region AR and a second portion SLb disposed in the wiring region FR. In this embodiment, the thicknesses of the first portion SLa and the second portion SLb in the Z direction are different. The thickness T1 of the first portion SLa in the Z direction is greater than the thickness T2 of the second portion SLb in the Z direction. For example, the thickness T1 of the first portion SLa in the Z direction is more than twice the thickness T2 of the second portion SLb in the Z direction. There is a step difference between the first portion SLa and the second portion SLb.

[0131] <Insulation section of A4.4 wiring area>

[0132] The insulating portion 45 is an insulating portion disposed in the wiring region FR. The insulating portion 45 is formed, for example, using TEOS (tetraethoxysilane (Si(OC2H5)4). A portion of the insulating portion 45 covers the ends of a plurality of gate electrode layers 41A arranged in a stepped manner from the -Z direction side. A portion of the insulating portion 45 covers the ends of a plurality of gate electrode layers 41B arranged in a stepped manner from the -Z direction side. A portion of the insulating portion 45 is disposed between the second portion SLb of the source line SL and the first stacked body 40A, covering the second portion SLb of the source line SL from the -Z direction side.

[0133] <A4.5 Lower Line>

[0134] The lower-level line BLA is an electrical connection line used to select one lower columnar portion 91 from the plurality of lower columnar portions 91. The plurality of lower-level lines BLA are disposed on the lower side (-Z direction side) relative to the first stacked body 40A. The plurality of lower-level lines BLA are disposed on the opposite side of the source line SL relative to the first stacked body 40A. The plurality of lower-level lines BLA are spaced apart in the X direction. The lower-level lines BLA extend in the Y direction (see reference). Figure 6 The lower line BLA extends by passing beneath the corresponding plurality of lower columnar portions 91.

[0135] The lower bit line BLA is electrically connected to the channel layer 72 of the lower columnar portion 91 via contacts VY and CH. Thus, by combining the word line WLA and the lower bit line BLA, it is possible to arbitrarily select a memory cell transistor MT from a plurality of memory cell transistors MT arranged in three dimensions within the first stacked layer 40A.

[0136] <A4.6 Upper Line>

[0137] The upper-level line BLB is an electrical connection line used to select one of the plurality of upper columnar portions 92. The plurality of upper-level lines BLB are disposed on the upper side (+Z direction side) relative to the second stack 40B. The plurality of upper-level lines BLB are disposed on the opposite side of the source line SL relative to the second stack 40B. The plurality of upper-level lines BLB are arranged in the X direction at intervals. The upper-level lines BLB extend in the Y direction (see reference). Figure 6 The upper line BLB extends by passing over the corresponding plurality of upper columnar sections 92.

[0138] The upper bit line BLB is electrically connected to the channel layer 72 of the upper columnar portion 92 via contacts VY and CH. Thus, by combining the word line WLB and the upper bit line BLB, it is possible to arbitrarily select a memory cell transistor MT from a plurality of memory cell transistors MT arranged in three dimensions within the second stack 40B.

[0139] <A4.7 Contacts for the gate electrode layer>

[0140] The contact CC is an electrical connection portion that electrically connects the gate electrode layer 41 to the electrical connection line 63 (hereinafter referred to as the connection line) included in the wiring portion 60. Multiple contacts CC are provided, for example, in the wiring region FR of the memory cell array 11. The multiple contacts CC extend through the stack 40 in the Z direction. The lengths of the multiple contacts CC in the Z direction are different from each other, and they are respectively connected to different gate electrode layers 41. The contacts CC are conductive. The contacts CC are formed of a conductive material (e.g., tungsten, molybdenum, or silicon doped with impurities).

[0141] In this embodiment, contact CC is connected from the -Z direction side to the plurality of gate electrode layers 41A included in the first stacked layer 40A. Similarly, contact CC is connected from the -Z direction side to the plurality of gate electrode layers 41B included in the second stacked layer 40B.

[0142] <A4.8 breaking part>

[0143] Next, the segment 50 will be explained.

[0144] Figure 6 yes Figure 4The diagram shows a cross-sectional view of a semiconductor memory device along line F6-F6. Multiple break sections 50 are disposed on the stacked body 40. The multiple break sections 50 are arranged separately in the Y direction. The multiple break sections 50 extend through the stacked body 40 in the Z direction. The multiple break sections 50 break one or more gate electrode layers 41, including the bottommost or topmost layer, along the Y direction. The multiple break sections 50 may include, for example, multiple break sections ST( Figure 6 Only one (SHE) and multiple segmented parts are shown in the figure.

[0145] (Breaking part ST)

[0146] The segment ST is a wall portion that divides the laminate 40 along the Y direction. Multiple segment STs are arranged separately in the Y direction. The segment STs extend in the Z direction. The segment STs penetrate the laminate 40. For example, the segment STs penetrate the first laminate 40A, the source line SL, and the second laminate 40B in the Z direction.

[0147] The segment ST extends in the X direction (see reference). Figure 7 For example, the segment ST extends in the X direction, spanning the array region AR and the wiring region FR. The segment ST is a wall portion along both the X and Z directions. The segment ST segments all gate electrode layers 41 (all gate electrode layers 41A and all gate electrode layers 41B) included in the stack 40 along the Y direction. In this embodiment, in the first stack 40A, the region sandwiched between two adjacent segment STs in the Y direction corresponds to one block BLKA. Similarly, in the second stack 40B, the region sandwiched between two adjacent segment STs in the Y direction corresponds to one block BLKB.

[0148] In this embodiment, the segment ST has an insulating film 51 and a conductive layer (conductive portion) 52. The insulating film 51 extends in the Z direction. The insulating film 51 penetrates the laminate 40. The insulating film 51 is provided across the entire length of the segment ST in the X direction. The insulating film 51 covers the conductive layer 52. The insulating film 51 has an insulating film 51s1 forming the surface of the segment ST in the +Y direction and an insulating film 51s2 forming the surface of the segment ST in the -Y direction. The insulating film 51 is formed, for example, from a film containing silicon and oxygen (e.g., a silicon oxide film).

[0149] A conductive layer 52 is disposed inside the insulating film 51. For example, the conductive layer 52 is disposed between insulating films 51s1 and 51s2 in the Y direction. The conductive layer 52 extends in the Z direction. The conductive layer 52 penetrates the stack 40. The conductive layer 52 is formed of a conductive material such as tungsten, molybdenum, or silicon doped with impurities. The upper end of the conductive layer 52 is electrically connected to an electrical connection line 64 within the memory cell array 11 via contacts 55 and 56.

[0150] In this embodiment, the break section ST has a first portion STa and a second portion STb. The insulating film 51 and the conductive layer 52 are disposed across the first portion STa and the second portion STb.

[0151] Part 1 STa extends through the first stacked layer 40A in the Z direction. Part 1 STa divides the multiple gate electrode layers 41A along the Y direction. Part 1 STa extends from the lower side to the upper side of the first stacked layer 40A. The upper end of Part 1 STa is located inside the source line SL.

[0152] The second part STb is positioned on the upper side (+Z direction side) relative to the first part STa. The second part STb extends through the second stacked layer 40B in the Z direction. The second part STb divides the multiple gate electrode layers 41B along the Y direction. The second part STb extends from the lower side to the upper side of the second stacked layer 40B. The lower end of the second part STb is located inside the source line SL. The lower end of the second part STb, inside the source line SL, connects to the upper end of the first part STa. The boundary between the first part STa and the second part STb is located inside the source line SL.

[0153] The width W1 in the Y direction of the first part STa is greater than the width W2 in the Y direction of the second part STb. For example, the width W1 in the Y direction of the first part STa is more than twice the thickness of the insulating film 51s1 in the Y direction of the width W2 in the Y direction of the second part STb. At the boundary between the first part STa and the second part STb, a step difference Ts is formed based on the difference between the width W1 in the Y direction of the first part STa and the width W2 in the Y direction of the second part STb. The step difference Ts is a step difference in the Y direction. The step difference Ts is located inside the source line SL.

[0154] In this embodiment, the insulating film 51 is not provided at the step Ts of the segment ST. The insulating film 51 is segmented along the Y direction at the boundary (step Ts) between the first portion STa and the second portion STb of the segment ST. For example, the insulating film 51 includes a first insulating film 51a located in the first portion STa of the segment ST and a second insulating film 51b located in the second portion STb of the segment ST. The first insulating film 51a extends in the Z direction in the first portion STa. The first insulating film 51a is located between the conductive layer 52 and the plurality of gate electrode layers 41A. The second insulating film 51b extends in the Z direction in the second portion STb. The second insulating film 51b is located between the conductive layer 52 and the plurality of gate electrode layers 41B. In this embodiment, the first insulating film 51a and the second insulating film 51b are separated in the Y direction at the step Ts.

[0155] On the other hand, conductive layer 52 is disposed in the first portion STa and the second portion STb. For example, conductive layer 52 is continuous across the first portion STa and the second portion STb. Therefore, in the region where the insulating film 51 is interrupted (at the step difference Ts), conductive layer 52 is exposed outside the interrupted portion 50 (outside the insulating film 51) and connected to the source line SL. Thus, conductive layer 52 is electrically connected to source line SL. A voltage is applied to source line SL via the electrical connection lines 64, contacts 55 and 56, and conductive layer 52 at the interrupted portion ST.

[0156] (Breaking part SHE)

[0157] The segmented section SHE is a segment whose length in the Z direction is shorter than that of the segmented section ST. The segmented section SHE is a wall portion that severs the lower or upper end of the laminate 40 along the Y direction. Multiple segmented sections SHE may include, for example, multiple segmented sections SHEA and multiple segmented sections SHEB.

[0158] The SHEA section is a wall portion that severs the lower end of the first laminate 40A along the Y direction. Multiple SHEA sections are arranged separately in the Y direction. In this embodiment, multiple (e.g., three) SHEA sections exist between two adjacent SHEA sections ST in the Y direction. The SHEA section extends in the Z direction to the middle of the first laminate 40A. The SHEA section extends in the X direction. The SHEA section is a wall portion along both the X and Z directions.

[0159] The SHEA section penetrates a portion of the gate electrode layers 41A, including the lowest layer. The SHEA section divides this portion of the gate electrode layers 41A along the Y direction. For example, the SHEA section penetrates all gate electrode layers 41A that function as the drain-side select gate line (SGDA). On the other hand, the SHEA section does not reach the gate electrode layers 41A that function as word lines (WLA). The SHEA section only divides the gate electrode layers 41A that function as the drain-side select gate line (SGDA) along the Y direction. The SHEA section is formed, for example, from a film containing silicon and oxygen (e.g., a silicon oxide film). In this embodiment, the region between two adjacent SHEA sections in the Y direction corresponds to one string STR.

[0160] The slit section SHEB is a wall portion that severs the upper end of the second laminate 40B along the Y direction. Multiple slit sections SHEB are arranged separately in the Y direction. In this embodiment, multiple (e.g., three) slit sections SHEB exist between two adjacent slit sections ST in the Y direction. The slit section SHEB extends in the Z direction to the middle of the second laminate 40B. The slit section SHEB extends in the X direction. The slit section SHEB is a wall portion along both the X and Z directions.

[0161] The SHEB segment penetrates a portion of the gate electrode layers 41B, including the uppermost layer. The SHEB segment divides this portion of the gate electrode layer 41B along the Y direction. For example, the SHEB segment penetrates all gate electrode layers 41B that function as drain-side select gate lines (SGDB). On the other hand, the SHEB segment does not reach the gate electrode layers 41B that function as word lines (WLB). The SHEB segment only divides the gate electrode layers 41B that function as drain-side select gate lines (SGDB) along the Y direction. The SHEB segment is formed, for example, from a film containing silicon and oxygen (e.g., a silicon oxide film). In this embodiment, the region between two adjacent SHEB segments in the Y direction corresponds to one string (STR).

[0162] <A4.9 Wiring Department>

[0163] The wiring section 60 is an electrical connection section that connects multiple solder pads 32 to each component included in the memory cell array 11. The wiring section 60 includes, for example, wiring section 60A and wiring section 60B.

[0164] Wiring section 60A is a wiring section disposed between the first laminate 40A and the semiconductor substrate 21. Wiring section 60A includes, for example, a plurality of electrical connection lines 61, a plurality of electrical connection lines 62, and a plurality of electrical connection lines 63 (see reference). Figure 5 ).

[0165] Multiple electrical connection lines 61 are arranged on the lower side (-Z direction side), for example, relative to multiple lower line BLAs. Each electrical connection line 61 extends, for example, in the X or Y direction. A through hole VA is provided between the electrical connection line 61 and the lower line BLA to electrically connect the electrical connection line 61 and the lower line BLA.

[0166] Electrical connection line 61 electrically connects peripheral circuitry (e.g., sense amplifier unit 17a) to the lower-level line BLA. For example, electrical connection line 61 electrically connects switching circuit 19 (e.g., switching circuit 19A) to the lower-level line BLA. For example, electrical connection line 61 electrically connects the switching element 19Aa of switching circuit 19A to the lower-level line BLA. In this embodiment, electrical connection line 61 is electrically connected to bonding pad 32. Electrical connection line 61 is electrically connected to switching circuit 19A via bonding pads 24 and 32.

[0167] Multiple electrical connection lines 62, for example, multiple contacts CS set relative to the bit line access area BR. Figure 6 Only one is shown in the figure), configured on the lower side (-Z direction side). Each electrical connection line 62 extends, for example, in the X or Y direction. A contact VB is provided between the electrical connection line 62 and the contact CS to electrically connect the electrical connection line 62 and the contact CS.

[0168] Electrical connection line 62 electrically connects peripheral circuitry (e.g., sense amplifier unit 17a) to contact CS. For example, electrical connection line 62 electrically connects switching circuit 19 (e.g., switching circuit 19B) to contact CS. For example, electrical connection line 62 electrically connects the switching element 19Ba of switching circuit 19B to contact CS. In this embodiment, electrical connection line 62 is electrically connected to bonding pad 32. Electrical connection line 62 is electrically connected to switching circuit 19B via bonding pads 24 and 32.

[0169] Electrical connection wire 63 electrically connects the external circuit to contact CC (see reference). Figure 5 In this embodiment, the electrical connection line 63 is electrically connected to the bonding pad 32. A voltage is applied to the electrical connection line 63 to select the gate electrode layer 41 (word line WL, drain-side select gate line SGD, or source-side select gate line SGS).

[0170] <A5. Structure of the bit line access area>

[0171] Next, the structure of the bit line access region BR will be explained.

[0172] like Figure 6 As shown, the bit line access area BR has a third laminate 40C, a fourth laminate 40D, an insulating portion 47, and multiple contacts CS. Figure 6 Only one is shown in the image.

[0173] <A5.1 Third Layer>

[0174] The third laminate 40C is a laminate located around a portion of the contact CS. The third laminate 40C includes, for example, multiple insulating layers 46A and multiple insulating layers 42A. The multiple insulating layers 46A and multiple insulating layers 42A are laminated alternately in the Z direction.

[0175] Insulating layer 46A is located at the same height as gate electrode layer 41A. Insulating layer 46A extends along both the X and Y directions. In the Y direction, insulating layer 46A is connected to gate electrode layer 41A. Insulating layer 46A is formed, for example, by retaining a portion of the sacrificial layer (hereinafter, sacrificial layer 111A) to be replaced into gate electrode layer 41A during a manufacturing process, thus preventing its replacement. Insulating layer 46A is formed of a different material than insulating layer 42A. Insulating layer 46A is, for example, formed of a film comprising silicon and nitrogen (e.g., silicon nitride film).

[0176] An insulating layer 42A is disposed between two adjacent insulating layers 46A in the Z direction. The insulating layer 42A extends along both the X and Y directions. The insulating layer 42A is formed, for example, of a film comprising silicon and oxygen (e.g., a silicon oxide film). The insulating layer 42A included in the bit line access region BR is at the same height as the insulating layer 42A included in the array region AR. The insulating layer 42A included in the bit line access region BR is continuous with the insulating layer 42A included in the array region AR.

[0177] <A5.2 Fourth Layer>

[0178] The fourth laminate 40D is a laminate located around another portion of the contact CS. The fourth laminate 40D is positioned on the upper side (+Z direction side) relative to the third laminate 40C. The fourth laminate 40D, for example, includes multiple insulating layers 46B and multiple insulating layers 42B. The multiple insulating layers 46B and multiple insulating layers 42B are laminated alternately layer by layer in the Z direction.

[0179] Insulating layer 46B is located at the same height as gate electrode layer 41B. Insulating layer 46B extends along both the X and Y directions. In the Y direction, insulating layer 46B is connected to gate electrode layer 41B. Insulating layer 46B is formed, for example, by retaining a portion of the sacrificial layer (hereinafter, sacrificial layer 111B) to be replaced into gate electrode layer 41B during the manufacturing process, thus preventing its replacement. Insulating layer 46B is formed of a different material than insulating layer 42B. Insulating layer 46B is, for example, formed of a film comprising silicon and nitrogen (e.g., silicon nitride film).

[0180] An insulating layer 42B is disposed between two adjacent insulating layers 46B in the Z direction. The insulating layer 42B extends along both the X and Y directions. The insulating layer 42B is formed, for example, of a film comprising silicon and oxygen (e.g., a silicon oxide film). The insulating layer 42B included in the bit line access region BR is at the same height as the insulating layer 42B included in the array region AR. The insulating layer 42B included in the bit line access region BR is continuous with the insulating layer 42B included in the array region AR.

[0181] <A5.3 Insulation Section>

[0182] The insulating portion 47 is disposed between the third laminate 40C and the fourth laminate 40D in the Z direction. The insulating portion 47 is embedded between the third laminate 40C and the fourth laminate 40D. The insulating portion 47 is adjacent to the source line SL in the Y direction.

[0183] <A5.4 contact>

[0184] The contact CS is an electrical connection that connects peripheral circuitry (e.g., the sensing amplifier unit 17a) to the upper-level line BLB. In this embodiment, the contact CS connects the switching circuit 19 to the upper-level line BLB. For example, the contact CS connects the switching element 19Ba of the switching circuit 19B to the upper-level line BLB.

[0185] In this embodiment, the contact CS is a columnar body extending in the Z direction. The contact CS penetrates the third laminate 40C, the fourth laminate 40D, and the insulating portion 47 in the Z direction. The contact CS extends across the lower side of the third laminate 40C and the upper side of the fourth laminate 40D.

[0186] The upper end of contact VB is electrically connected to the upper line BLB, for example, via contact VC. The lower end of contact CS is electrically connected to the switching circuit 19, for example, via contact VB. Alternatively, in another example of the semiconductor memory device 1, the switching circuit 19 may be absent. In a configuration without the switching circuit 19, the lower end of contact CS is electrically connected to the sense amplifier unit 17a, for example, via contact VB.

[0187] Figure 7 It is Figure 4 The diagram shows an enlarged representation of the area enclosed by line F7. (See diagram for example.) Figure 7 As shown, the upper line BLB extends in the Y direction in a manner that overlaps with the junction CS and multiple blocks BLK when viewed from the Z direction.

[0188] Figure 8 It is Figure 7 The diagram shows an enlarged representation of the area enclosed by line F8. (See diagram for example.) Figure 7 As shown, in the bit line access area BR, multiple contacts CS are configured separately from each other. For example, the multiple contacts CS are staggered in the X and Y directions. Multiple upper bit lines BLB are electrically connected to their corresponding contacts CS in a one-to-one relationship via the contacts VC in the bit line access area BR.

[0189] <A6. Storage Column>

[0190] <A6.1 Internal Structure of Storage Columns>

[0191] Next, the memory column MH will be explained. Multiple memory columns MH are arranged in the X and Y directions (see reference). Figure 7 Each storage column MH extends through the stack 40 in the Z direction. Each storage column MH penetrates the stack 40. The storage column MH is an example of a "column".

[0192] Figure 9 This is a cross-sectional view used to illustrate the storage column MH. The storage column MH, for example, has a storage film (multilayer film) 71, a channel layer 72, an insulating portion 73, and a cap portion 74.

[0193] A storage film 71 is disposed on the outer periphery of the storage pillar MH. The storage film 71 extends in the Z direction. For example, the storage film 71 is disposed such that it spans the entire Z-direction length of the storage pillar MH, excluding the upper end and middle portion of the storage pillar MH. The storage film 71 is located between the plurality of gate electrode layers 41 and the channel layer 72.

[0194] Figure 10 yes Figure 9 The structure shown is a cross-sectional view along line F10-F10. The storage membrane 71 includes, for example, a block insulating membrane 81, a charge trapping membrane 82, and a tunnel insulating membrane 83.

[0195] A block insulating film 81 is disposed at the outermost periphery of the memory pillar MH. The block insulating film 81 is disposed between the plurality of gate electrode layers 41 and the charge trapping film 82. The block insulating film 81 is an insulating film that suppresses reverse tunneling. Reverse tunneling refers to the phenomenon of charge returning from the word line WL to the charge trapping film 82. The block insulating film 81 is formed in a ring shape. The block insulating film 81 extends in the Z direction. For example, the block insulating film 81 is disposed in a manner that spans the entire Z-direction of the memory pillar MH, excluding the upper end and middle portion of the memory pillar MH. The block insulating film 81 is, for example, a multilayer structure film formed by stacking multiple insulating films, such as films containing silicon and oxygen, or films containing metal and oxygen. An example of a film containing metal and oxygen is an aluminum oxide film. The block insulating film 81 may also contain a high dielectric constant material (high-k material) such as silicon nitride or hafnium oxide.

[0196] A charge trapping film 82 is disposed on the inner periphery of the block insulating film 81 in both the X and Y directions. The charge trapping film 82 is located between the block insulating film 81 and the tunnel insulating film 83. The charge trapping film 82 is formed in a ring shape. The charge trapping film 82 extends in the Z direction. For example, the charge trapping film 82 is disposed such that it spans the entire length of the storage column MH in the Z direction, excluding the upper end and middle portion of the storage column MH. The charge trapping film 82 is a functional film having many crystal defects (trapping energy levels) and capable of trapping charge at the crystal defects. The charge trapping film 82 is formed, for example, from a film containing silicon and nitrogen. An example of a "charge storage section 82a" in the charge trapping film 82, adjacent to each word line WL, is formed that can store information by storing charge.

[0197] A tunnel insulating film 83 is disposed on the inner peripheral side of the charge trapping film 82 in both the X and Y directions. The tunnel insulating film 83 is disposed between the charge trapping film 82 and the channel layer 72. The tunnel insulating film 83 is formed, for example, in an annular shape along the outer peripheral surface of the channel layer 72. The tunnel insulating film 83 extends along the channel layer 72 in the Z direction. The tunnel insulating film 83 is disposed, for example, spanning the entire Z-direction length of the storage column MH, excluding the upper end and middle portion. The tunnel insulating film 83 acts as a potential barrier between the charge trapping film 82 and the channel layer 72. The tunnel insulating film 83 is formed of a film containing silicon and oxygen, or a film containing silicon, oxygen, and nitrogen.

[0198] Channel layer 72 is disposed on the inner peripheral side of memory film 71 in both the X and Y directions. Channel layer 72 is formed in a ring shape. Channel layer 72 extends in the Z direction. Channel layer 72 is disposed, for example, spanning the entire length of memory pillar MH in the Z direction. Channel layer 72 is formed of a semiconductor material such as polysilicon. Channel layer 72 may also be doped with impurities. When a voltage is applied to word line WL, channel layer 72 forms a channel, electrically connecting bit line BL to source line SL. Channel layer 72 is an example of a "semiconductor film".

[0199] With the aforementioned configuration, a MANOS (Metal-Al-Nitride-Oxide-Silicon) type memory cell transistor MT is formed at the same height as each word line WL. The memory cell transistor MT includes the edge of the word line WL adjacent to the memory pillar MH, a block insulating film 81, a charge trapping film 82, a tunnel insulating film 83, and a channel layer 72. Furthermore, regarding the charge storage section, the storage film 71 may have a floating gate type charge storage section (floating gate electrode) instead of a charge trapping film 82. The floating gate type charge storage section is, for example, formed of polysilicon containing impurities.

[0200] Back Figure 9 The remaining composition of the storage column MH will be explained.

[0201] An insulating portion 73 is disposed on the inner peripheral side of the channel layer 72 in both the X and Y directions. At least a portion of the interior of the channel layer 72 is embedded in the insulating portion 73. The insulating portion 73 is formed of a film comprising silicon and oxygen (e.g., a silicon oxide film). The insulating portion 73 extends in the Z direction. For example, the insulating portion 73 is disposed such that it spans the entire length of the storage column MH in the Z direction, excluding the lower end of the storage column MH.

[0202] A cover portion 74 is disposed below the insulating portion 73. The cover portion 74 is a semiconductor portion formed of a semiconductor material such as amorphous silicon or polycrystalline silicon. The cover portion 74 may also be doped with impurities, for example. The cover portion 74 is disposed on the inner peripheral side of the lower end of the storage film 71. The cover portion 74 is integrally formed with the channel layer 72. The cover portion 74 and the lower end of the channel layer 72 together form the lower end of the storage column MH.

[0203] <A6.2 Multi-segment structure of storage columns>

[0204] In this embodiment, the storage column MH is formed from multiple (e.g., three) columnar sections. For example, the storage column MH includes columnar sections Ma, Mb, and Mc. Columnar sections Ma, Mb, and Mc each have the storage film (multilayer film) 71, the channel layer 72, and the insulating portion 73.

[0205] The lower columnar body Ma is disposed in the first laminate 40A. Columnar body Ma extends through the interior of the first laminate 40A in the Z direction. The lower end of columnar body Ma is electrically connected to the lower line BLA via contacts CH and VY. The upper end of columnar body Ma is located inside the first laminate 40A. As columnar body Ma advances from top to bottom, its circumference (diameter) gradually increases along the cross-sections in the X and Y directions.

[0206] The central columnar body Mb is positioned above columnar body Ma (on the +Z direction side). Columnar body Mb is positioned across the first stacked body 40A and the second stacked body 40B. Columnar body Mb penetrates the source line SL in the Z direction. Columnar body Mb extends through the interiors of the first stacked body 40A and the second stacked body 40B in the Z direction. The lower end of columnar body Mb is located inside the first stacked body 40A and connects to the upper end of columnar body Ma. The upper end of columnar body Mb is located inside the second stacked body 40B and connects to the lower end of columnar body Mc. As columnar body Mb extends from the top to the bottom, its circumference (diameter) gradually increases along the X and Y direction sections.

[0207] The upper columnar body Mc is positioned on the upper side (+Z direction side) relative to columnar body Mb. Columnar body Mc is located within the second laminate 40B. Columnar body Mc extends through the interior of the second laminate 40B in the Z direction. The upper end of columnar body Mc is electrically connected to the upper line BLB via contacts CH and VY. As columnar body Mc advances from the upper side to the lower side, its circumference (diameter) gradually increases along the cross-sections in the X and Y directions.

[0208] Furthermore, the configuration of the storage column MH is not limited to the examples described. For example, in addition to a structure formed by three columnar segments, the storage column MH can also be formed by one or two columnar segments, or even by four or more columnar segments.

[0209] <A6.3 Lower columnar portion and upper columnar portion>

[0210] like Figure 9 As shown, the storage column MH includes a lower columnar portion 91, an upper columnar portion 92, and a middle portion 93.

[0211] (Lower columnar part)

[0212] The lower columnar portion 91 is a portion of the storage column MH that corresponds to the first stacked body 40A. The lower columnar portion 91 extends through the first stacked body 40A in the Z direction and penetrates the first stacked body 40A in the Z direction. In this embodiment, the lower columnar portion 91 is formed by the entirety of the columnar body Ma and the lower portion of the columnar body Mb. In this embodiment, the portion of the lower columnar portion 91 that occupies more than half in the Z direction is the portion whose circumference (diameter) gradually increases along the cross-section in the X and Y directions as it moves from the top to the bottom.

[0213] The lower columnar portion 91 includes a portion of each of the storage film 71, the channel layer 72, and the insulating portion 73, as well as a cover portion 74. Hereinafter, for ease of explanation, the portion of the storage film 71 included in the lower columnar portion 91 is sometimes referred to as the "lower storage film 71A". The lower storage film 71A is an example of a "first storage film". Furthermore, hereafter, for ease of explanation, the portion of the channel layer 72 included in the lower columnar portion 91 is sometimes referred to as the "lower semiconductor film 72A". The lower semiconductor film 72A is an example of a "first semiconductor film".

[0214] The contact CH is connected to the lower end of the lower columnar portion 91 from the -Z direction side. The lower end of the channel layer 72 (lower semiconductor film 72A) of the lower columnar portion 91 is electrically connected to the lower line BLA via the contact CH and the contact VY. The upper end of the channel layer 72 (lower semiconductor film 72A) of the lower columnar portion 91 is electrically connected to the source line SL via the intermediate portion 93 described below.

[0215] (Upper columnar part)

[0216] The upper columnar portion 92 is disposed on the upper side (+Z direction side) relative to the lower columnar portion 91. The upper columnar portion 92 is the portion of the storage column MH that corresponds to the second stack 40B. The upper columnar portion 92 extends through the second stack 40B in the Z direction. The upper columnar portion 92 penetrates the second stack 40B in the Z direction. In this embodiment, the upper columnar portion 92 is formed by the entirety of the columnar body Mc and the upper part of the columnar body Mb. In this embodiment, when viewed from the Z direction, the lower columnar portion 91 and the upper columnar portion 92 overlap. In this embodiment, the portion of the upper columnar portion 92 that occupies more than half in the Z direction is the portion whose circumference (diameter) gradually increases along the cross-section in the X and Y directions as it moves from the upper side to the lower side.

[0217] The upper columnar portion 92 includes a portion of each of the storage film 71, the channel layer 72, and the insulating portion 73. Hereinafter, for ease of explanation, the portion of the storage film 71 included in the upper columnar portion 92 is sometimes referred to as the "upper storage film 71B". The upper storage film 71B is an example of a "second storage film". Additionally, hereafter, for ease of explanation, the portion of the channel layer 72 included in the upper columnar portion 92 is sometimes referred to as the "upper semiconductor film 72B". The upper semiconductor film 72B is an example of a "second semiconductor film".

[0218] The contact CH is connected to the upper end of the upper columnar portion 92 from the +Z direction side. The upper end of the channel layer 72 (upper semiconductor film 72B) of the upper columnar portion 92 is electrically connected to the upper line BLB via the contact CH and the contact VY. The lower end of the channel layer 72 (upper semiconductor film 72B) of the upper columnar portion 92 is electrically connected to the source line SL via the intermediate portion 93 described below.

[0219] (Middle section)

[0220] An intermediate portion (intermediate columnar portion) 93 is disposed between the lower columnar portion 91 and the upper columnar portion 92 in the Z direction. The intermediate portion 93 extends through the source line SL in the Z direction. In this embodiment, the intermediate portion 93 is formed from a portion of the columnar body Mb. The intermediate portion 93 includes a portion of each of the storage film 71, the channel layer 72, and the insulating portion 73.

[0221] On the other hand, at least a portion of the intermediate portion 93 lacks the storage film 71. In this embodiment, the storage film 71 of the lower columnar portion 91 (lower storage film 71A) and the storage film 71 of the upper columnar portion 92 (upper storage film 71B) are separated in the Z direction. Therefore, in the region of the intermediate portion 93 where the storage film 71 is absent (the region between the lower storage film 71A and the upper storage film 71B), the channel layer 72 is exposed outside the storage column MH and connected to the source line SL. Thus, the channel layer 72 is electrically connected to the source line SL.

[0222] <A7. Example of the configuration of the segment and bit line access area>

[0223] <A7.1 Breaking Section Arrangement Example>

[0224] like Figure 6 As shown, the segment ST is configured between multiple memory columns MH (memory column MHA and memory column MHB) arranged in the Y direction.

[0225] The lower columnar portion 91 included in the storage column MHA is an example of a "first columnar portion". The lower storage film 71A of the lower columnar portion 91 included in the storage column MHA is an example of a "first storage film". The lower semiconductor film 72A of the lower columnar portion 91 included in the storage column MHA is an example of a "first semiconductor film".

[0226] The upper columnar portion 92 included in the storage column MHA is an example of a "second columnar portion". The upper storage film 71B of the upper columnar portion 92 included in the storage column MHA is an example of a "second storage film". The upper semiconductor film 72B of the upper columnar portion 92 included in the storage column MHA is an example of a "second semiconductor film".

[0227] In one viewpoint, the lower columnar portion 91 included in the memory column MHB is an example of a "third columnar portion". The lower memory film 71A of the lower columnar portion 91 included in the memory column MHB is an example of a "third memory film". The lower semiconductor film 72A of the lower columnar portion 91 included in the memory column MHB is an example of a "third semiconductor film".

[0228] In one viewpoint, the upper columnar portion 92 included in the memory column MHB is an example of a "fourth columnar portion". The upper storage film 71B of the upper columnar portion 92 included in the memory column MHA is an example of a "fourth storage film". The upper semiconductor film 72B of the upper columnar portion 92 included in the memory column MHB is an example of a "fourth semiconductor film".

[0229] In this embodiment, the conductive layer 52 of the interruption section ST is disposed in at least one of the following two regions. One region (the first region) is the region between the lower columnar portion 91 (the first columnar portion) of the storage column MHA and the lower columnar portion 91 (the third columnar portion) of the storage column MHB. The other region (the second region) is the region between the upper columnar portion 92 (the second columnar portion) of the storage column MHA and the upper columnar portion 92 (the fourth columnar portion) of the storage column MHB. Furthermore, the conductive layer 52 of the interruption section ST extends through the aforementioned region in the Z direction and is connected to the source line SL.

[0230] <A7.2 Configuration Example of Bit Line Access Area>

[0231] like Figure 6 As shown, the bit line access area BR is configured between multiple memory cylinders MH (memory cylinder MHA and memory cylinder MHC) arranged in the Y direction.

[0232] In one viewpoint, the lower columnar portion 91 included in the memory column MHC is an example of a "fifth columnar portion". The lower memory film 71A of the lower columnar portion 91 included in the memory column MHC is an example of a "fifth memory film". The lower semiconductor film 72A of the lower columnar portion 91 included in the memory column MHC is an example of a "fifth semiconductor film".

[0233] In one viewpoint, the upper columnar portion 92 included in the memory column MHC is an example of a "sixth columnar portion". The upper storage film 71B of the upper columnar portion 92 included in the memory column MHC is an example of a "sixth storage film". The upper semiconductor film 72B of the upper columnar portion 92 included in the memory column MHC is an example of a "sixth semiconductor film".

[0234] In this embodiment, the peripheral circuitry (e.g., the sense amplifier module 17 or the switching circuit 19) is disposed on the opposite side (-Z direction side) of the second stacked layer 40B relative to the first stacked layer 40A. Furthermore, the contact CS of the bit line access region BS is provided in the following two regions. One region (the first region) is the area between the lower columnar portion 91 (first columnar portion) of the memory column MHA and the lower columnar portion 91 (fifth columnar portion) of the memory column MHC. The other region (the second region) is the area between the upper columnar portion 92 (second columnar portion) of the memory column MHA and the upper columnar portion 92 (sixth columnar portion) of the memory column MHC. Moreover, the contact CS of the bit line access region BS extends through these regions in the Z direction. The contact CS of the bit line access region BS electrically connects the peripheral circuitry to the upper bit line BLB.

[0235] <A8. Manufacturing Method>

[0236] Next, the manufacturing method of semiconductor memory device 1 will be described.

[0237] here, Figure 11 This is a schematic cross-sectional view illustrating the structure of semiconductor memory device 1. Figure 11 For ease of explanation, the wiring area FR, bit line access area BR, and array area AR are represented together. Figure 11 The structures related to the X direction and the structures related to the Y direction are schematically integrated and represented together. Below, we will use... Figure 11 The manufacturing method will be explained using the structure shown as an example.

[0238] Figures 12 to 47 This is a cross-sectional view used to illustrate the manufacturing method of semiconductor memory device 1. Furthermore, Figures 12 to 47 Therefore, relative to Figure 11 The posture after being reversed indicates the structure in the middle of the manufacturing process.

[0239] First, such as Figure 12 As shown, an insulating layer 101 is formed on the semiconductor substrate 100. The insulating layer 101 is formed, for example, from a film containing silicon and oxygen (e.g., a silicon oxide film). Then, as... Figure 13 As shown, sacrificial layers 111B and insulating layers 42B are alternately deposited one layer at a time in the Z direction. This forms a structure 40MA comprising an insulating layer 101, multiple sacrificial layers 111B, and multiple insulating layers 42B. The sacrificial layer 111B is formed, for example, from a film comprising silicon and nitrogen (e.g., a silicon nitride film).

[0240] Next, as Figure 14 As shown, a cavity H1 corresponding to the columnar body Mc is formed in the structure 40MA. The cavity H1 is embedded in the sacrificial material 112. Then, as... Figure 15 As shown, sacrificial layers 111B and insulating layers 42B are alternately stacked in the Z direction. Furthermore, an insulating layer 44 is formed on top of the uppermost sacrificial layer 111B. Thus, a structure 40MB is formed in which multiple sacrificial layers 111B, multiple insulating layers 42B, and an insulating layer 44 are added to the structure 40MA. Structure 40MB is an example of a "first-stage laminated structure." Sacrificial layer 111B is an example of a "first layer." Insulating layer 42B is an example of a "second layer."

[0241] Next, as Figure 16 As shown, a conductive layer 121, a sacrificial layer 122, a sacrificial layer 123, a sacrificial layer 124, a conductive layer 125, and a barrier layer 126 are sequentially deposited on top of the 40MB structure. The conductive layers 121, 122, 123, 124, 125, and 126 extend in the X and Y directions, respectively. The conductive layers 121 and 125 are formed, for example, from polycrystalline silicon doped with impurities. The sacrificial layers 122 and 124 are formed, for example, from a film containing silicon and oxygen (e.g., a silicon oxide film). The sacrificial layer 123 and the barrier layer 126 are formed, for example, from a film containing silicon and nitrogen (e.g., a silicon nitride film). The sacrificial layer 123 is an example of a "third layer." Next, as... Figure 17 As shown, in the sacrificial layers 122, 123, 124, the conductive layer 125, and the barrier layer 126, the portions included in the bit line access area BR and the wiring area FR are removed.

[0242] Next, as Figure 18 As shown, in the conductive layer 121, the portion included in the bit line access area BR and the useless portion included in the wiring area FR are removed. Then, as... Figure 19 As shown, the barrier layer 126 is removed. Next, TEOS is supplied to the array region AR, the bit line access region BR, and the wiring region FR. This forms a portion of the insulating layer 43, the insulating layer 44, and the insulating portion 45. This forms the structure 40MC.

[0243] Next, as Figure 20 As shown, sacrificial layer 111A and insulating layer 42A are alternately deposited one layer at a time on structure 40MC in the Z direction. This forms structure 40MD comprising multiple sacrificial layers 111A and multiple insulating layers 42A. Then, as... Figure 21 As shown, a cavity H2 is formed corresponding to the columnar body Mb. The cavity H2 will be embedded in the sacrificial material 112.

[0244] Next, as Figure 22 As shown, sacrificial layer 111A and insulating layer 42A are alternately deposited on structure 40MD in the Z direction. This forms structure 40ME with multiple sacrificial layers 111A and multiple insulating layers 42A added to structure 40MD. Structure 40ME is an example of a "second-stage laminate". Sacrificial layer 111A is an example of a "fourth layer". Insulating layer 42A is an example of a "fifth layer". Next, holes H3 corresponding to columnar bodies Ma are formed. Then, sacrificial material 112 embedded in holes H1 and H2 is removed by etching through holes H3.

[0245] Next, as Figure 23 As shown, a storage film 71, a channel layer 72, and an insulating portion 73 are sequentially deposited on the inner peripheral surfaces of cells H1, H2, and H3. Then, a cap portion 74 is formed. This forms the basic structure of the storage column MH. The upper columnar portion 92 of the storage column MH is an example of a "first-stage columnar portion." The lower columnar portion 91 of the storage column MH is an example of a "second-stage columnar portion."

[0246] Next, an insulating layer 131 is formed on the structure 40ME. The insulating layer 131 is formed, for example, from a film containing silicon and oxygen (e.g., a silicon oxide film). Thus, the structure 40MF is formed.

[0247] Next, as Figure 24 As shown, a trench G1 is formed at the position corresponding to the break ST in the structure 40MF. The trench G1 extends in both the Z and X directions. The trench G1 is formed, for example, by using conductive layer 121 or conductive layer 125 as a barrier. Then, as... Figure 25 As shown, conductive layers 121 and 125 are removed at the bottom of trench G1 by etching. As a result, sacrificial layer 124 is exposed at the bottom of trench G1 in array region AR.

[0248] Next, as Figure 26 As shown, a semiconductor film 132 is formed on the inner surface of trench G1. The semiconductor film 132 is formed, for example, from amorphous silicon. Then, as... Figure 27As shown, a semiconductor film 132 is used as a protective film to protect the second sacrificial layer 112B and the second insulating layer 42B, while the bottom of the semiconductor film 132 and a portion of the sacrificial layer 124 are removed. Thus, an opening K1 reaching the sacrificial layer 123 is formed.

[0249] Next, as Figure 28 As shown, an etchant (e.g., hot phosphoric acid) capable of removing the silicon nitride film is supplied to the opening K1 to remove the sacrificial layer 123. Then, as... Figure 29 As shown, an etchant capable of removing the silicon oxide film is supplied to the opening K1 to remove the sacrificial layers 122 and 124, and to remove the memory film 71 exposed in the space S1 between the conductive layers 121 and 125. Thus, the channel layer 72 is exposed in the space S1 between the conductive layers 121 and 125. At this point, the memory pillar MH is complete.

[0250] Next, as Figure 30 As shown, insulating layer 131 is removed. Then, conductive layer 141 is formed in the space S1 between conductive layers 121 and 125 through trench G1. Conductive layer 141 is formed of polysilicon doped with impurities. Conductive layer 141 is connected to the channel layer 72 of the memory pillar MH and is integral with conductive layers 121 and 125. Thus, source line SL is formed through conductive layers 121, 125, and 141.

[0251] Next, as Figure 31 As shown, an insulating film 146 is formed as a protective film on the inner surface of trench G1. The insulating film 146 is formed, for example, from a film containing silicon and oxygen (e.g., a silicon oxide film). Then, as... Figure 32 As shown, a mask 147 is formed on the inner surface of the insulating film 146. The mask 147 is formed, for example, from a metallic material such as titanium nitride or tungsten.

[0252] Next, as Figure 33 As shown, a trench G2 is formed, which penetrates the mask 147 and the insulating film 146 at the bottom of the trench G1, and penetrates the structure 40MF in the Z direction. Here, since the mask 147 and the insulating film 146 are provided on the inner surface of the trench G1, the width of the trench G2 in the Y direction is smaller than the width of the trench G1 in the Y direction and is correspondingly smaller than the thickness of the mask 147 and the insulating film 146. Then, as... Figure 34 As shown, the insulating film 146 and the mask 147 are removed. As a result, a trench G3 with a step difference Ts in the Z direction of the source line SL is formed through trench G1 and trench G2.

[0253] Next, as Figure 35As shown, an insulating film 151 is formed on the inner surface of trench G3 at the portion corresponding to the source line SL. The insulating film 151 is formed, for example, from a film containing silicon and oxygen (e.g., a silicon oxide film). The insulating film 151 is formed, for example, by oxidizing the surface of the source line SL. The insulating film 151 is a protective film that protects the source line SL in the alternative steps described below.

[0254] Next, as Figure 36 As shown, an etchant (e.g., hot phosphoric acid) capable of removing the silicon nitride film is supplied to the trench G3. This removes multiple first sacrificial layers 111A and multiple second sacrificial layers 111B. At this point, the bit line access region BR is located far from the trench G3, making it difficult for the etchant to reach. Therefore, in the bit line access region BR, the multiple first sacrificial layers 111A and multiple second sacrificial layers 111B remain as multiple insulating layers 46A and multiple insulating layers 46B.

[0255] Next, as Figure 37 As shown, conductive material is supplied through trench G3 to the space where multiple first sacrificial layers 111A and multiple second sacrificial layers 111B have been removed. This forms multiple first gate electrode layers 41A and multiple second gate electrode layers 41B. Then, an insulating film 152 is formed on the inner surface of trench G3. The insulating film 152 is formed, for example, from a film containing silicon and oxygen (e.g., a silicon oxide film).

[0256] Next, as Figure 38 As shown, the insulating film 151 (the portion of the insulating film 151 along the X and Y directions) present at the step Ts of trench G3 is removed by reactive ion etching (RIE). As a result, the source line SL is exposed at the step Ts of trench G3. In this embodiment, the insulating film 51 of the break ST is formed by the insulating films 151 and 152. Next, as... Figure 39 As shown, conductive material is supplied to the interior of trench G3. This forms a conductive layer 52. This forms the break section ST.

[0257] Next, as Figure 40 As shown, a segment SHEA is formed, and a contact CH is formed that connects to the lower columnar portion 91 of the storage column MH. Then, as... Figure 41 As shown, contact CS is formed in the bit line access area BR, and contact CC is formed in the wiring area FR. Next, as... Figure 42 As shown, the contact VY, bit line BLA, and wiring section 60A are formed. This forms the basic structure of the second chip 3, namely structure 40MG.

[0258] Next, as Figure 43As shown, the structure 40MG is flipped upside down, and the separately prepared first chip 2 is attached to the structure 40MG. Then, the semiconductor substrate 100 is removed. Next, at the upper end of the memory pillar MH, the memory film 71 is removed, exposing the channel layer 72. In addition, at this stage, a step of thickening the upper end of the channel layer 72 can also be performed.

[0259] Next, as Figure 44 As shown, an insulating portion 161 is formed on the structure 40MG. Then, a break portion SHEB is formed. Next, as... Figure 45 As shown, a contact CH is formed that connects to the upper columnar portion 92 of the storage column MH, and a contact 55 is formed that connects to the break portion ST.

[0260] Next, as Figure 46 As shown, the upper boundary line BLB is formed. Then, as... Figure 47 As shown, an insulating portion 162 covering the upper line BLB is formed. Next, an electrical connection line 84 electrically connected to the source line SL via a break portion ST is formed on the insulating portion 162. Then, an insulating portion covering the electrical connection line 84 is formed. At this point, the semiconductor memory device 1 is completed.

[0261] <A9. Advantages>

[0262] In recent years, with the increasing capacity of semiconductor memory devices, there has been a trend towards increasing the number of gate electrode layers. If the number of gate electrode layers increases, the resistance of the series STR (Structured String Transmission) becomes larger, making it difficult to ensure the current flowing through the channel layer of the memory pillar.

[0263] In this embodiment, the semiconductor memory device 1 includes a first stacked layer 40A, a second stacked layer 40B, a source line SL, a lower columnar portion 91, an upper columnar portion 92, a lower bit line BLA, and an upper bit line BLB. The source line SL is disposed between the first stacked layer 40A and the second stacked layer 40B in the Z direction. The lower columnar portion 91 extends through the first stacked layer 40A in the Z direction. The lower columnar portion 91 includes a storage film 71A having a charge storage portion 82a and a lower semiconductor film 72A. The upper columnar portion 92 extends through the second stacked layer 40B in the Z direction. The upper columnar portion 92 includes a storage film 71B having a charge storage portion 82a and an upper semiconductor film 72B. The lower bit line BLA is disposed opposite to the source line SL relative to the first stacked layer 40A. The lower bit line BLA is electrically connected to the lower columnar portion 91. The upper line BLB is positioned opposite the source line SL to the second stack 40B. The upper line BLB is electrically connected to the upper columnar portion 92.

[0264] With this configuration, for example, compared to the case where a source line SL exists on the +Z direction side relative to the first stacked layer 40A and the second stacked layer 40B, the resistance of the series STR is reduced, making it easier to ensure the current flowing through the channel layer 72. When the current flowing through the channel layer 72 is easily ensured, the reliability of the write operation of the semiconductor memory device 1 can be improved. Therefore, a semiconductor memory device 1 with improved electrical characteristics can be provided.

[0265] In this embodiment, when viewed from the Z direction, the lower columnar portion 91 and the upper columnar portion 92 overlap. With this configuration, the lower columnar portion 91 and the upper columnar portion 92 can be arranged at a higher density in the semiconductor memory device 1. This facilitates achieving a larger capacity in the semiconductor memory device 1.

[0266] In this embodiment, the semiconductor memory device 1 includes a memory pillar MH. The memory pillar MH includes a lower pillar-shaped portion 91 and an upper pillar-shaped portion 92. The memory pillar MH extends through the first stacked layer 40A, the second stacked layer 40B, and the source line SL in the Z direction. With this configuration, the lower pillar-shaped portion 91 and the upper pillar-shaped portion 92 can be formed using a single memory pillar MH. Therefore, compared to forming the lower pillar-shaped portion 91 and the upper pillar-shaped portion 92 using different memory pillars MH, the manufacturability of the semiconductor memory device 1 can be improved.

[0267] In this embodiment, the storage film 71 of the lower columnar portion 91 and the storage film 71 of the upper columnar portion 92 are separated in the Z direction. The storage column MH has the storage film 71 of the lower columnar portion 91, the storage film 71 of the upper columnar portion 92, and a channel layer 72. The channel layer 72 is connected to the source line SL in the region between the storage film 71 of the lower columnar portion 91 and the storage film 71 of the upper columnar portion 92. With this configuration, the electrical connection between the storage column MH and the source line SL can be ensured midway in the Z direction of the storage column MH.

[0268] In this embodiment, the number of gate electrode layers 41A included in the first stacked layer 40A is different from the number of gate electrode layers 41B included in the second stacked layer 40B. With this configuration, the capacity of the block BLKA included in the first stacked layer 40A can be different from the capacity of the block BLKB included in the second stacked layer 40B. Because the capacity of the block BLKA included in the first stacked layer 40A can be different from the capacity of the block BLKB included in the second stacked layer 40B, more suitable write operations can be performed. For example, by making the capacity of the block BLKA smaller than that of the block BLKB, the smaller data size can be written preferentially to the block BLKA over the block BLKB, thereby achieving high-speed write operations.

[0269] In this embodiment, the semiconductor memory device 1 includes a sense amplifier module 17 having a terminal 17t and a switching circuit 19. The switching circuit 19 is capable of switching between a first state and a second state. The first state is a state in which the terminal 17t of the sense amplifier module 17 is electrically connected to the lower bit line BLA. The second state is a state in which the terminal 17t of the sense amplifier module 17 is electrically connected to the upper bit line BLB. According to this configuration, for example, compared to the case where the write target is switched between the first stack 40A and the second stack 40B using drain-side select gate lines SGDA and SGDB, the power consumption associated with switching the write target can be reduced.

[0270] In this embodiment, the semiconductor memory device 1 has a contact CS. The contact CS is disposed between the memory pillar MHA and the memory pillar MHC. The contact CS extends in the Z direction and electrically connects the switching circuit 19 (or the sense amplifier module 17) to the upper line BLB. With this configuration, the electrical connection path between the switching circuit 19 (or the sense amplifier module 17) and the upper line BLB can be shortened. As a result, the processing speed of the semiconductor memory device 1 can be improved or the power consumption can be reduced.

[0271] In this embodiment, the semiconductor memory device 1 has a segmentation section ST. The segmentation section ST includes a first portion STa in which multiple gate electrode layers 41A are each segmented along the Y direction, and a second portion STb in which multiple gate electrode layers 41B are each segmented along the Y direction. The segmentation section ST has a conductive layer 52 and an insulating film 51 covering the conductive layer 52. The conductive layer 52 and the insulating film 51 are disposed across the first portion STa and the second portion STb. The width W1 of the first portion STa in the Y direction is greater than the width W2 of the second portion STb in the Y direction. The boundary between the first portion STa and the second portion STb is located inside the source line SL and has a step difference Ts in the Y direction. At the step difference Ts, the insulating film 51 is segmented along the Y direction, and the conductive layer 52 is exposed outside the insulating film 51 and connected to the source line SL.

[0272] With this configuration, the electrical connection path connected to the source line SL can be located inside the array region AR. Compared to locating the electrical connection path in the wiring region FR, this configuration easily improves the electrical characteristics of the semiconductor memory device 1. For example, with this configuration, at least one of the following effects can be obtained.

[0273] • Compared to setting the electrical connection path in the wiring area FR, the number of electrical connection paths can be increased.

[0274] • It can reduce the resistance of the electrical connection path to the source line SL.

[0275] • It can shorten the path length between the electrical connection path and each storage column MH.

[0276] <A9. Variation Example>

[0277] Hereinafter, several variations of the first embodiment will be described. Furthermore, these variations can also be applied to the second embodiment described below.

[0278] In the semiconductor memory device 1 of the first embodiment, a switching circuit 19 is provided, and the lower bit line BLA and the upper bit line BLB are switched by the switching circuit 19. In a variation, the switching circuit 19 may not be provided. In this case, the switching between the lower bit line BLA and the upper bit line BLB may be performed, for example, using the drain-side selected gate line SGDA of the first stacked layer 40A and the drain-side selected gate line SGDB of the second stacked layer 40B.

[0279] In the semiconductor memory device 1 of the first embodiment, the electrical connection between the source line SL and the electrical connection line 64 is ensured by the conductive layer 52 of the disconnection section ST. Alternatively, the conductive layer 52 of the disconnection section ST may be omitted. In this case, a contact CC for electrically connecting the source line SL and the electrical connection line 64 may also be provided in the wiring area FR.

[0280] (Second Implementation)

[0281] Next, the semiconductor memory device 1A according to the second embodiment will be described. In the second embodiment, the lower columnar portion 91 and the upper columnar portion 92 are formed by different memory columns, which differs from the first embodiment. Furthermore, apart from the configuration described below, the other configurations are the same as those in the first embodiment.

[0282] <B1. Storage Column>

[0283] Figure 48 This is a cross-sectional view showing a portion of the semiconductor memory device 1A according to the second embodiment. In this embodiment, the semiconductor memory device 1A has a plurality of first memory pillars MH1 and a plurality of second memory pillars MH2, instead of having a plurality of memory pillars MH as in the first embodiment.

[0284] (Storage column 1)

[0285] Multiple first storage columns MH1 are arranged in the X and Y directions. The first storage column MH1 extends through the first stacked body 40A in the Z direction. The first storage column MH1 penetrates the first stacked body 40A in the Z direction. In this embodiment, the entire length of the first storage column MH1 in the Z direction forms the entire length of the lower columnar portion 91 in the Z direction. The lower columnar portion 91 is an example of a "first columnar portion". Furthermore, the first storage column MH1 is not limited to a single-segment storage column in the Z direction, but may also be a two-segment or more storage column formed by stacking multiple columnar bodies in the Z direction.

[0286] (Second storage column)

[0287] Multiple second storage pillars MH2 are arranged in the X and Y directions. The second storage pillars MH2 extend through the second stacked body 40B in the Z direction. The second storage pillars MH2 penetrate the second stacked body 40B in the Z direction. In this embodiment, the entire length of the upper columnar portion 92 in the Z direction is formed by the entire length of the second storage pillars MH2. The second storage pillar MH2 is an example of a "second columnar portion". Furthermore, the second storage pillar MH2 is not limited to a single-segment storage pillar in the Z direction, but may also be a two-segment or more storage pillar formed by stacking multiple columnar bodies in the Z direction.

[0288] Figure 49 This is a cross-sectional view illustrating the memory pillars MH1 and MH2 of the second embodiment. The first memory pillar MH1 (lower pillar 91) includes a memory film 71 (lower memory film 71A), a channel layer 72 (lower semiconductor film 72A), an insulating portion 73, and a cover portion 74. The memory film 71 included in the first memory pillar MH1 is an example of a "first memory film". The channel layer 72 included in the first memory pillar MH1 is an example of a "first semiconductor film".

[0289] The first storage column MH1 does not penetrate the source line SL. The upper end of the first storage column MH1 is physically and electrically connected to the source line SL. The contact CH is connected to the lower end of the first storage column MH1 from the -Z direction side. The channel layer 72 of the first storage column MH1 is electrically connected to the lower line BLA via the contact CH and the contact VY. In this embodiment, as the first storage column MH1 (lower columnar portion 91) advances from the upper side to the lower side, the circumference (diameter) of the first storage column MH1 in the cross-section along the X and Y directions gradually increases.

[0290] The first storage column MH1 has a first end MHe1 (the end on the +Z direction side) connected to the source line SL, and a second end MHe2 (the end on the -Z direction side) located on the opposite side of the first end MHe1. The second end MHe2 is connected to the contact CH. The second end MHe2 is electrically connected to the bit line BLA via the contact CH. In this embodiment, the circumference (diameter) of the first storage column MH1 with the second end MHe2 is greater than the circumference (diameter) of the first storage column MH1 with the first end MHe1.

[0291] The second storage pillar MH2 (upper pillar portion 92) includes a storage film 71 (upper storage film 71B), a channel layer 72 (upper semiconductor film 72B), an insulating portion 73, and a cover portion 74. The storage film 71 included in the second storage pillar MH2 is an example of a "second storage film". The channel layer 72 included in the second storage pillar MH2 is an example of a "second semiconductor film".

[0292] The second storage column MH2 does not penetrate the source line SL. The lower end of the second storage column MH2 is physically and electrically connected to the source line SL. The contact CH is connected to the upper end of the second storage column MH2 from the +Z direction side. The channel layer 72 of the second storage column MH2 is electrically connected to the upper line BLB via the contact CH and the contact VY. In this embodiment, as the second storage column MH2 (upper column 92) moves from the top to the bottom, the circumference (diameter) of the second storage column MHB in the cross-section along the X and Y directions gradually increases.

[0293] The second storage column MH2 has a third terminal MHe3 (the terminal on the -Z direction side) connected to the source line SL, and a fourth terminal MHe4 (the terminal on the +Z direction side) located opposite to the third terminal MHe3. The fourth terminal MHe4 is connected to the contact CH. The fourth terminal MHe4 is electrically connected to the bit line BLB via the contact CH. In this embodiment, the circumference (diameter) of the second storage column MH2 with the fourth terminal MHe4 is smaller than the circumference (diameter) of the second storage column MH2 with the third terminal MHe3.

[0294] In this embodiment, the second storage pillar MH2 is separated from the first storage pillar MH1 in the Z direction. The first storage pillar MH1 and the second storage pillar MH2 are disconnected from each other. For example, the channel layer 72 (lower semiconductor film 72A) contained in the first storage pillar MH1 and the channel layer 72 (upper semiconductor film 72B) contained in the second storage pillar MH2 are separated in the Z direction. The channel layer 72 (lower semiconductor film 72A) contained in the first storage pillar MH1 and the channel layer 72 (upper semiconductor film 72B) contained in the second storage pillar MH2 are electrically connected to the source line SL. The channel layer 72 contained in the first storage pillar MH1 and the channel layer 72 contained in the second storage pillar MH2 are electrically connected to each other via the source line SL.

[0295] <B2.Breaking part>

[0296] Figure 50 yes Figure 48 The diagram shows a cross-sectional view of the semiconductor memory device 1A along line F50-F50. In this embodiment, the semiconductor memory device 1A includes a first segment ST1 and a second segment ST2, instead of the segment ST of the first embodiment.

[0297] (1st branch)

[0298] The first break section ST1 is a wall portion along both the Z and Y directions. The first break section ST1 extends through the first stacked body 40A in the Z direction. The first break section ST1 penetrates the first stacked body 40A in the Z direction. The first break section ST1 breaks all the gate electrode layers 41 contained in the first stacked body 40A along the Y direction. The first break section ST1 does not penetrate the source line SL. Figure 50 In the example shown, the first break section ST1 does not have a conductive layer 52, but is formed only by an insulating film 51. Furthermore, besides the example described, the first break section ST1 may also have both an insulating film 51 and a conductive layer 52.

[0299] (Second breaking part)

[0300] The second break section ST2 is a wall portion along both the Z and Y directions. The second break section ST2 extends through the second stacked body 40B in the Z direction. The second break section ST2 penetrates the second stacked body 40B in the Z direction. The second break section ST2 breaks all the gate electrode layers 41 contained in the second stacked body 40B along the Y direction. In this embodiment, the second break section ST2 does not penetrate the source line SL. In this embodiment, the second break section ST2 is separated from the first break section ST1 in the Z direction. Figure 50 In the example shown, the second break portion ST2 has an insulating film 51 and a conductive layer 52. Alternatively, if the first break portion ST1 has a conductive layer 52, the second break portion ST2 may not have a conductive layer 52 and may be formed only by the insulating film 51.

[0301] <B3. Manufacturing Method>

[0302] The manufacturing method of semiconductor memory device 1A will now be described.

[0303] Figures 51 to 56 This is a diagram illustrating a manufacturing method for semiconductor memory device 1A. First, as... Figure 51As shown, an insulating layer 101 is formed on a semiconductor substrate 100. Next, sacrificial layers 111B and insulating layers 42B are alternately deposited in the Z direction. Then, the ends of the plurality of sacrificial layers 111B are formed in a stepped manner. Additionally, a second memory pillar MH2 and a second breakout ST2 are formed. Next, through a replacement step, the plurality of sacrificial layers 111B are replaced with a plurality of gate electrode layers 41B. Thus, a structure 40NA is formed.

[0304] Next, as Figure 52 As shown, a source line SL is placed on top of structure 40NA. This forms structure 40NB. The source line SL is an example of a "layer 3".

[0305] Next, as Figure 53 As shown, sacrificial layers 111A and insulating layers 42A are alternately deposited on the structure 40NA in the Z direction. Then, the ends of the plurality of sacrificial layers 111A are formed in a stepped manner. In addition, a first storage pillar MH1 and a first breakout ST1 are provided. Next, through a replacement step, the plurality of sacrificial layers 111A are replaced with a plurality of gate electrode layers 41A. Thus, the structure 40NC is formed.

[0306] Next, as Figure 54 As shown, the following components are formed: SHEA (segmentation section), CH (contact), VY (contact), BLA (lower-level line), pad 32, and wiring section 60A. This forms structure 40ND. Structure 40ND contains the basic parts of the second chip 3.

[0307] Next, as Figure 55 As shown, the structure 40ND is flipped vertically, and the separately prepared first chip 2 is attached to the structure 40ND. Then, the semiconductor substrate 100 is removed. Next, as... Figure 56 As shown, the upper line BLB is formed. Then, the wiring section 60B and the insulating section are provided. At this point, the semiconductor memory device 1A is completed.

[0308] <B4. Advantages>

[0309] According to this configuration, similar to the first embodiment, the electrical characteristics of the semiconductor memory device 1A can be improved.

[0310] <B5. Examples of Changes in Manufacturing Methods>

[0311] In the second embodiment, the replacement step of replacing the plurality of sacrificial layers 111B with the plurality of gate electrode layers 41B is performed before the source line SL is formed. Alternatively, the replacement step of replacing the plurality of sacrificial layers 111B with the plurality of gate electrode layers 41B can be performed after the source line SL is formed. For example, the replacement step of replacing the plurality of sacrificial layers 111B with the plurality of gate electrode layers 41B can be performed simultaneously with the replacement step of replacing the plurality of sacrificial layers 111A with the plurality of gate electrode layers 41A.

[0312] The above describes several implementation methods and variations. However, the implementation methods and variations are not limited to the examples described. For example, the implementation methods and variations can be appropriately combined. In addition, the source line SL can also be set to be segmented into series STRs. In addition, the lower line BLB and the upper line BLB can be directly electrically connected to the sensing amplifier module 17 without passing through the switching circuit 19.

[0313] According to at least one embodiment described above, a semiconductor memory device includes a first stacked layer, a second stacked layer, a source line, a first pillar portion, a second pillar portion, a first bit line, and a second bit line. The first stacked layer includes a plurality of first gate electrode layers and a plurality of first insulating layers. The plurality of first gate electrode layers and the plurality of first insulating layers are stacked alternately layer by layer in a first direction. The second stacked layer is disposed on a first side in the first direction relative to the first stacked layer. The second stacked layer includes a plurality of second gate electrode layers and a plurality of second insulating layers. The plurality of second gate electrode layers and the plurality of second insulating layers are stacked alternately layer by layer in the first direction. The source line is disposed between the first stacked layer and the second stacked layer in the first direction. The source line extends in a second direction different from the first direction. The first pillar portion extends through the first stacked layer in the first direction. The first pillar portion includes a first storage film having a charge storage portion and a first semiconductor film. The second columnar portion extends through the second stacked body in the first direction. The second columnar portion includes a second storage film having a charge storage portion and a second semiconductor film. The first bit line is disposed on a second side opposite to the first side in the first direction relative to the first stacked body. The first bit line is electrically connected to the first columnar portion. The second bit line is disposed on the first side in the first direction relative to the second stacked body. The second bit line is electrically connected to the second columnar portion. With this configuration, the electrical characteristics of the semiconductor memory device can be improved.

[0314] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as within the scope of the invention described in the claims and its equivalents.

[0315] [Explanation of Symbols]

[0316] 1,1A Semiconductor Memory Device

[0317] 17. Sensing Amplifier Module (Circuit)

[0318] 17a Sensing Amplifier Unit

[0319] 17t terminal (1st terminal)

[0320] 19. Switching circuit (circuit)

[0321] 40A First Layer

[0322] 40B Second Layer

[0323] 41A Gate electrode layer (first gate electrode layer)

[0324] 41B Gate electrode layer (second gate electrode layer)

[0325] 42A Insulation Layer (First Insulation Layer)

[0326] 42B Insulation Layer (Second Insulation Layer)

[0327] 71 Storage membrane

[0328] 72 Channel Layer

[0329] 91. Lower columnar portion (first columnar portion)

[0330] 92 Upper columnar portion (second columnar portion)

[0331] MH storage column (column)

[0332] MH1 Storage Column 1

[0333] MH2 Storage Column 2

[0334] SL source line

[0335] BLA Lower Line (First Line)

[0336] BLB top line (second line).

Claims

1. A semiconductor memory device comprising: The first stacked body includes a plurality of first gate electrode layers and a plurality of first insulating layers, wherein the plurality of first gate electrode layers and the plurality of first insulating layers are stacked alternately layer by layer in a first direction; The second stacked body is disposed on the first side in the first direction relative to the first stacked body, and includes a plurality of second gate electrode layers and a plurality of second insulating layers, wherein the plurality of second gate electrode layers and the plurality of second insulating layers are stacked alternately layer by layer in the first direction; The source line is disposed between the first stack and the second stack in the first direction, and extends in a second direction intersecting the first direction; The first columnar portion extends through the first laminate in the first direction and includes a first storage film having a charge storage portion and a first semiconductor film. The second columnar portion extends through the second laminate in the first direction and includes a second storage film having a charge storage portion and a second semiconductor film. The first bit line, relative to the first stacked body, is disposed on the opposite side of the source line and is electrically connected to the first columnar portion; and The second bit line is disposed on the opposite side of the source line relative to the second stacked body, and is electrically connected to the second columnar portion.

2. The semiconductor memory device according to claim 1, wherein When viewed from the first direction, the first columnar portion overlaps with the second columnar portion.

3. The semiconductor memory device according to claim 1 or 2, It comprises a columnar body including the first columnar portion and the second columnar portion, and The columnar body extends through the first stack, the second stack, and the source line in the first direction.

4. The semiconductor memory device according to claim 3, wherein The first storage film and the second storage film are separated in the first direction, and The columnar body has a semiconductor film comprising the first semiconductor film and the second semiconductor film. The semiconductor film is connected to the source line in the region between the first storage film and the second storage film.

5. The semiconductor memory device according to claim 1 or 2, wherein The first semiconductor film and the second semiconductor film are separated from each other in the first direction, and the first semiconductor film and the second semiconductor film are respectively electrically connected to the source line.

6. The semiconductor memory device according to claim 1 or 2, wherein The portion of the first columnar portion that occupies more than half in the first direction is the portion whose perimeter increases in the cross-section intersecting the first direction as it moves from the first side to the second side opposite to the first side. The portion of the second columnar portion that occupies more than half in the first direction is the portion whose circumference increases as it moves from the first side to the second side and intersects the first direction.

7. The semiconductor memory device according to claim 1 or 2, wherein The first columnar portion has a first end connected to the source line and a second end located on the opposite side of the first end. The perimeter of the first columnar portion at the second end is greater than the perimeter of the first columnar portion at the first end, and The second columnar portion has a third end connected to the source line and a fourth end located on the opposite side of the third end. The perimeter of the second columnar portion at the fourth end is smaller than the perimeter of the second columnar portion at the third end.

8. The semiconductor memory device according to claim 1 or 2, further comprising: The third columnar portion extends through the first laminate in the first direction and includes a third storage film having a charge storage portion and a third semiconductor film. The fourth columnar portion extends through the second laminate in the first direction and includes a fourth storage film having a charge storage portion and a fourth semiconductor film; and A conductive layer is disposed at at least one location between the first columnar portion and the third columnar portion, and between the second columnar portion and the fourth columnar portion, and extends in the first direction to be connected to the source line.

9. The semiconductor memory device according to claim 1 or 2, wherein The number of the plurality of first gate electrode layers contained in the first stacked body is different from the number of the plurality of second gate electrode layers contained in the second stacked body.

10. The semiconductor memory device according to claim 1 or 2, wherein The number of the plurality of first gate electrode layers contained in the first stacked body is the same as the number of the plurality of second gate electrode layers contained in the second stacked body.

11. The semiconductor memory device according to claim 1 or 2, further comprising: The sensing amplifier module has a first terminal; and The switching circuit is capable of switching between a first state and a second state, wherein the first state is a state in which the first terminal is electrically connected to the first bit line, and the second state is a state in which the first terminal is electrically connected to the second bit line.

12. The semiconductor memory device according to claim 1 or 2, further comprising: The fifth columnar portion extends through the first laminate in the first direction and includes a fifth storage film having a charge storage portion and a fifth semiconductor film. The sixth columnar portion extends through the second laminate in the first direction and includes a sixth storage film having a charge storage portion and a sixth semiconductor film. The circuit, relative to the first stacked layer, is disposed on the opposite side of the second stacked layer; and A contact is disposed between the first columnar portion and the fifth columnar portion, and between the second columnar portion and the sixth columnar portion, and extends in the first direction to electrically connect the circuit to the second line.

13. The semiconductor memory device according to claim 1 or 2, It also includes a severing portion, which comprises a first portion that severs the plurality of first gate electrode layers respectively along the second direction, and a second portion that severs the plurality of second gate electrode layers respectively along the second direction; and The segmented portion has a conductive layer and an insulating film covering the conductive layer, the conductive layer and the insulating film being disposed across the first portion and the second portion. The width of the first part in the second direction is greater than the width of the second part in the second direction. The boundary between the first part and the second part is located inside the source line and has a step difference in the second direction. At the step difference, the insulating film is broken along the second direction, and the conductive layer is exposed outside the insulating film and connected to the source line.

14. A method for manufacturing a semiconductor memory device, comprising: A first-stage laminate is formed, which comprises a plurality of first layers and a plurality of second layers, wherein the plurality of first layers and the plurality of second layers are laminated alternately one layer at a time in a first direction; A third layer is formed above the first-stage laminate, and the third layer extends in a direction intersecting the first direction; A second-stage laminate is formed above the third layer, the second-stage laminate comprising a plurality of fourth layers and a plurality of fifth layers, wherein the plurality of fourth layers and the plurality of fifth layers are laminated alternately one layer at a time in the first direction; A columnar portion is formed in the first stage, which extends through the stacked body of the first stage in the first direction and includes a storage film having a charge storage portion and a semiconductor film. The columnar portion of the second stage is formed, which extends through the stacked body of the second stage in the first direction and includes a storage film having a charge storage portion and a semiconductor film. A bit line is formed, which is located on the opposite side of the third layer relative to the columnar portion of the second stage, and is electrically connected to the columnar portion of the second stage; and A bit line is formed, which is located on the opposite side of the third layer relative to the columnar portion of the first stage, and is electrically connected to the columnar portion of the first stage.

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