Semiconductor memory device and method for manufacturing semiconductor memory device

Abstract

The embodiment of the invention provides a semiconductor memory device and a method for manufacturing the semiconductor memory device. The semiconductor memory device can reduce a dummy region of an end portion of a laminated body. A semiconductor memory device according to one embodiment includes: a stacked body including a plurality of conductive layers and a plurality of first insulating layers alternately stacked layer by layer; a plurality of slits extending in the laminated body in a first direction intersecting the lamination direction of the laminated body and the lamination direction, and dividing the laminated body in a second direction intersecting the first direction and the lamination direction; and a plurality of pillars disposed between the plurality of slits and extending in the lamination direction within the lamination body. A first material covers the entire upper end portion of a first slit, which is disposed near the outermost end portion of the laminated body in the second direction, among the plurality of slits. A part of the upper end portion of each of a plurality of second slits other than the first slit is covered with a first material among the plurality of slits.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device and a method for manufacturing a semiconductor memory device. Background Technology

[0002] Semiconductor memory devices such as 3D nonvolatile memories have, for example, a stacked body with multiple conductive layers, and memory cells are arranged in 3D at the height of each conductive layer. In order to suppress the characteristic deviation of the memory cells, the vicinity of the ends of the stacked body is designated as a dummy region. Summary of the Invention

[0003] One embodiment aims to provide a semiconductor memory device and a method for manufacturing a semiconductor memory device capable of reducing the pseudo-region at the end of a stack.

[0004] One embodiment of a semiconductor memory device includes: a stack body comprising a plurality of conductive layers and a plurality of first insulating layers alternately stacked layer by layer; a plurality of slits extending within the stack body in a first direction intersecting the stacking direction and in the stacking direction, and dividing the stack body in a second direction intersecting the first direction and the stacking direction; and a plurality of pillars disposed between the plurality of slits and extending within the stack body along the stacking direction; and a first material covering the entire upper end of a first slit disposed near the outermost end of the stack body in the second direction; and the first material covering a portion of the upper end of each of a plurality of second slits other than the first slit. Attached Figure Description

[0005] Figure 1 Figures (a) to (b) in the figure show a schematic configuration example of a semiconductor memory device according to an embodiment.

[0006] Figure 2 This is a schematic diagram illustrating an example of the configuration of a semiconductor memory device according to an embodiment.

[0007] Figures 3(a) to 3(d) This is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to an embodiment.

[0008] Figure 4 Figures (a) to (d) in the figure are a part of the sequence illustrating the manufacturing method of the semiconductor memory device according to the embodiments.

[0009] Figure 5 Figures (a) to (d) in the figure are a part of the sequence illustrating the manufacturing method of the semiconductor memory device according to the embodiments.

[0010] Figure 6Figures (a) to (c) in the figure are a part of the sequence illustrating the manufacturing method of the semiconductor memory device according to the embodiments.

[0011] Figure 7 Figures (a) to (d) in the figure are a part of the sequence illustrating the manufacturing method of the semiconductor memory device according to the embodiments.

[0012] Figure 8 Figures (a) to (d) in the figure are a part of the sequence illustrating the manufacturing method of the semiconductor memory device according to the embodiments.

[0013] Figure 9 Figures (a) to (c) in the figure are a part of the sequence illustrating the manufacturing method of the semiconductor memory device according to the embodiments.

[0014] Figure 10 (a) to (b) are cross-sectional views showing an example of the configuration of a semiconductor memory device according to a variation of the implementation. Detailed Implementation

[0015] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0016] Furthermore, the invention is not limited to the embodiments described below. Additionally, the constituent elements in the following embodiments include elements readily conceived by those skilled in the art or substantially the same elements.

[0017] (Example of a semiconductor memory device)

[0018] Figure 1 This is a diagram illustrating a schematic configuration example of the semiconductor memory device 1 according to an embodiment. More specifically, Figure 1 (a) is a cross-sectional view of semiconductor memory device 1 along the X direction. Figure 1 (b) is a schematic top view showing the layout of semiconductor memory device 1.

[0019] However, in Figure 1 In (a) of the figure, the shading is omitted for ease of observation. Furthermore, in Figure 1 In (a), in addition to indicating that the components may not exist in the same cross section, some upper-level wiring is also omitted.

[0020] Furthermore, in this specification, the X and Y directions refer to the directions along the plane of the word line WL, and the X and Y directions are orthogonal to each other. Additionally, the electrical lead-out direction of the word line WL is sometimes referred to as the first direction, which is along the X direction. Furthermore, the direction intersecting the first direction is sometimes referred to as the second direction, which is along the Y direction. However, because the semiconductor memory device 1 may contain manufacturing errors, the first and second directions may not be orthogonal.

[0021] like Figure 1 As shown in (a), the semiconductor memory device 1 includes, from the bottom side of the paper, an electrode film EL, a source line SL, one or more select gate lines SGS, multiple word lines WL, one or more select gate lines SGD, and a semiconductor substrate SB on which peripheral circuitry CBA is disposed.

[0022] On the electrode film EL, a source line SL is disposed on a dielectric insulating layer 60. Multiple plugs PG are disposed in the insulating layer 60, and the source line SL and the electrode film EL are electrically connected via the plugs PG. Although not shown, electrode pads for supplying power and signals to the semiconductor memory device 1 from the outside are disposed on the same layer as the electrode film EL. A select gate line SGS, multiple word lines WL, and a select gate line SGD are sequentially deposited on the source line SL.

[0023] like Figure 1 As shown in (a) and (b), a memory region MR is arranged at the center of the multiple word lines WL in the X direction, and stepped regions SR are arranged at both ends of the multiple word lines WL in the X direction. These memory regions MR and stepped regions SR are divided into multiple regions by multiple plate-shaped portions LI that penetrate the multiple word lines WL and extend in the X direction.

[0024] Furthermore, the region located between adjacent plate-shaped portions LI in the Y direction, and containing the memory region MR and the stepped region SR, is called the block region BLK. As described later, the memory region MR contains multiple storage cells that non-volatilely store data, and the block region BLK becomes the unit for erasing this data.

[0025] Furthermore, between adjacent plate-shaped portions LI in the Y direction, multiple separation layers SHE are arranged to pass through the select gate line SGD and extend in the X direction. The multiple separation layers SHE extend throughout the entire memory region MR in the X direction and reach a portion of the stepped regions SR at both ends in the X direction.

[0026] In the memory region MR, multiple pillars PL are arranged, extending along the word lines WL and select gate lines SGD and SGS. The lower end of the pillar PL reaches the source line SL. Multiple memory cells are formed at the intersection of the pillar PL and the word lines WL. Thus, the semiconductor memory device 1 is configured, for example, as a 3D non-volatile memory in which memory cells are arranged in 3D within the memory region MR. Therefore, the semiconductor memory device 1 of the embodiment is also a semiconductor memory device.

[0027] In the stepped region SR, multiple word lines WL and select gate lines SGD and SGS are processed into a stepped shape and terminated. At this time, as the multiple word lines WL and select gate lines SGD and SGS that constitute the platform portion move away from the memory region MR in the X direction, they move from the upper layer side to the lower layer side, so the height position of the platform portion decreases towards the source line SL side.

[0028] In addition, in this specification, the direction in which the platform surfaces of the multiple word lines WL and the select gate lines SGD and SGS face is defined as the upper side of the semiconductor memory device 1.

[0029] The separation layer SHE extends from the memory region MR to the stepped region SR, where the select gate lines SGD are processed into stepped portions. Thus, within a block region BLK, the select gate lines SGD are separated into multiple regions. In other words, the separation layer SHE penetrates portions above multiple word lines WL, dividing these upper portions into patterns of multiple select gate lines SGD.

[0030] In each stage of the platform section, which consists of multiple word lines (WL) and select gate lines (SGD, SGS), a contact (CC) is configured to connect to the word lines (WL) and select gate lines (SGD, SGS) of each layer. In the word lines (WL) and select gate lines (SGS), one contact (CC) is connected for each layer. In the select gate lines (SGD), one contact (CC) is connected for each region separated by the separation layer (SHE) in each layer.

[0031] Here, within a single block region BLK, multiple contact points CC are configured on one side of the stepped regions SR on both sides of the X direction. Furthermore, when viewed from one side of the X direction, multiple contact points CC are configured, for example, in quantities equal to every two block regions BLK.

[0032] In other words, Figure 1In example (b), in the topmost block region BLK of the paper, multiple contacts CC are arranged in the stepped regions SR at both ends in the X direction, for example, on the left side of the paper. Furthermore, in the block regions BLK one and two blocks down from the aforementioned block region BLK, multiple contacts CC are arranged in the stepped regions SR at both ends in the X direction on the right side of the paper. Additionally, in the bottommost block region BLK of the paper, multiple contacts CC are again arranged in the stepped regions SR on the left side of the paper.

[0033] therefore, Figure 1 In (a) shown in the figure, the junctions CC of the stepped regions SR at both ends in the X direction belong to different block regions BLK and are not actually located on the same cross section.

[0034] Through these contacts CC, word lines WL of multiple layers are individually led out. More specifically, from these contacts CC, write voltages and read voltages are applied to the memory cells contained in the memory region MR at the center of multiple word lines WL via word lines WL at the same height position as the memory cells.

[0035] Multiple word lines WL, select gate lines SGD, SGS, pillar PL, and contact CC are covered by insulating layer 50. Insulating layer 50 also extends around the aforementioned configuration, which includes multiple word lines WL, etc.

[0036] The semiconductor substrate SB covering the insulating layer 50 is, for example, a silicon substrate. Peripheral circuitry CBA, including transistors TR and wiring, is disposed on the surface of the semiconductor substrate SB. Through the peripheral circuitry CBA electrically connected to these contacts CC, various voltages applied from the contacts CC to the memory cells are controlled. Thus, the peripheral circuitry CBA controls the electrical operation of the memory cells.

[0037] The peripheral circuit CBA is covered by an insulating layer 40. By bonding the insulating layer 40 with an insulating layer 50 covering multiple word lines WL, a semiconductor memory device 1 is formed, which includes multiple word lines WL, select gate lines SGD, SGS, pillars PL, and contacts CC, and the peripheral circuit CBA.

[0038] Next, use Figure 2 Figure 3 and a detailed configuration example of semiconductor memory device 1 will be described.

[0039] Figure 2 This is a schematic diagram illustrating an example of the configuration of the semiconductor memory device 1 according to an embodiment. More specifically, Figure 2 This is an XY cross-sectional view of the semiconductor memory device 1 at the height of the select gate line SGD, and shows the vicinity of the end position in the Y direction of the stack LM containing the plurality of word lines WL and select gate lines SGD and SGS.

[0040] like Figure 2 As shown, in each block region BLK sandwiched by multiple plate-like portions LI, multiple pillars PL are arranged in a periodic pattern. Figure 2 In the example, these pillars (PLs) are arranged in an alternating pattern when viewed from the top surface. However, these pillars (PLs) can also have other periodic arrangements, such as a grid pattern.

[0041] Furthermore, as described above, within a block region BLK between adjacent plate-shaped portions LI in the Y direction, multiple separation layers SHE that divide the select gate line SGD into multiple regions extend in the X direction. In order to maintain a periodic arrangement among the multiple pillars PL, the separation layers SHE may also overlap with several arrangements of the multiple pillars PL extending in the X direction when viewed from the top surface.

[0042] In this way, by maintaining a periodic configuration in multiple pillars PL, the individual pillars PL can be formed more precisely and with reduced processing errors in the manufacturing steps of the semiconductor memory device 1 described later.

[0043] Additionally, as mentioned above, stepped regions SR are arranged on both sides of the X direction of each block region BLK (see reference). Figure 1 (b)). In the stepped region SR, only the contact points CC, which are specifically configured to connect to each layer such as the word line WL, are provided. Therefore, in the remaining space generated in the stepped region SR, pseudo-pillars (not shown) are arranged in a periodic configuration following the plurality of pillars PL. As a result, even at both ends of the memory region MR in the X direction, each pillar PL can be formed with greater precision and with reduced manufacturing errors.

[0044] On the other hand, a pseudo-block region BLKd is disposed at the end of the laminate LM in the Y direction. The pseudo-block region BLKd is disposed adjacent to the outer side of the plurality of block regions BLK arranged in the Y direction, and is the region between the pseudo-plate-like portion LId on the outer side in the Y direction and the plate-like portion LI adjacent to the pseudo-plate-like portion LId in the Y direction.

[0045] In other words, the pseudo-plate-like portion LId is located on the outermost side in the Y direction among the multiple plate-like portions LI and LId. One difference between the pseudo-plate-like portion LId and the multiple plate-like portions LI is that the cross-linking portions BR and BRw at their respective upper ends are different.

[0046] Multiple plate-shaped portions LI each have multiple cross-linked portions BR arranged along the X direction with specified intervals at their upper ends. For example... Figure 2As shown in the example, the positions of the multiple crosslinking portions BR in the X direction of each of these plate-like portions LI are approximately equal, and they can also be arranged in the Y direction among the multiple plate-like portions LI. Alternatively, these crosslinking portions BR can be arranged in different positions in the X direction among the multiple plate-like portions LI, and not arranged in the Y direction.

[0047] In the pseudo-block region BLKd, multiple pseudo pillars PLd are arranged to replace the multiple pillars PL. These pseudo pillars PLd are a configuration that does not benefit the function of the semiconductor memory device 1, and are provided at both ends of the stacked layer LM in the Y direction to suppress characteristic deviations of memory cells at both ends of the stacked layer LM. Furthermore, the area between the plate-shaped portions LI and LId where these pillars PLd are arranged also becomes the pseudo-block region BLKd, which does not benefit the function of the semiconductor memory device 1.

[0048] Furthermore, the configuration of pillars PLd in the pseudo-block region BLKd also follows the periodic configuration of pillars PL in the block region BLK. That is, in Figure 2 In the example, the pseudo-pillar PLds are also staggered. In addition, in order to maintain the periodicity of these pillar PLd configurations, the arrangement of several pillar PLds can also coincide with the separation layer SHE.

[0049] In this way, by setting pseudo-pillars PLd, multiple pillars PL that contribute to the function of the semiconductor memory device 1 can be formed more precisely and with reduced processing errors, even at both ends in the Y direction.

[0050] Furthermore, from a designated position in the Y direction between the plate-shaped portions LI and LId, extending further outward from the plate-shaped portion LId, the laminated body LM becomes a laminated body LMs in which multiple sacrificial layers are laminated to replace the multiple letter lines WL, etc., present in the laminated body LMs. A pseudo-stepped region SRd is arranged on the outer side of the plate-shaped portion LId in the Y direction, and each layer of the laminated body LMs is processed into a stepped shape extending along the Y direction and terminating thereafter.

[0051] As will be described later, the pseudo-stepped region SRd is a stepped region formed during the fabrication of the semiconductor memory device 1 when a stepped region SR is formed. Therefore, the stepped region SRd and the stacked layer LM are positioned on either side of the stepped region SR (refer to...) in the X direction. Figure 1 Unlike (b) in the previous section, it does not function as a lead-out area for word lines WL and is not equipped with contacts CC, etc. Furthermore, since the stepped region SRd is an ineffective region that does not contribute to the function of the semiconductor memory device 1, the area occupied by the stepped region SRd in the semiconductor memory device 1 is reduced compared to the stepped region SR.

[0052] In addition, although Figure 2 The diagram is omitted, but the pseudo-step region SRd and the outer side of the step region SR in the Y direction are also covered by the insulating layer 50 (see reference). Figure 1(a) in the middle.

[0053] Figure 3 is a cross-sectional view showing an example of the configuration of the semiconductor memory device 1 according to the embodiment.

[0054] More specifically, Figures 3(a) and 3(b) are cross-sectional views along the Y direction in the memory region MR of the semiconductor memory device 1. Figure 3(a) shows a cross-section in the block region BLK, and Figure 3(b) shows a cross-section in the pseudo-block region BLKd. Furthermore, in Figures 3(a) and 3(b), the structures below the insulating layer 60 and above the insulating layer 53 (described later) are omitted.

[0055] Figure 3(c) is an enlarged cross-sectional view of the pillar PL in the select gate lines SGD and SGS. Figure 3(d) is an enlarged cross-sectional view of the pillar PL at the height position of the word line WL.

[0056] As shown in Figure 3(a), in the block region BLK, the source line SL has a multilayer structure in which, for example, a lower source line DSLa, an intermediate source line BSL, and an upper source line DSLb are sequentially deposited on the insulating layer 60. The lower source line DSLa, the intermediate source line BSL, and the upper source line DSLb are, for example, polysilicon layers. Among them, at least the intermediate source line BSL can be a conductive polysilicon layer with diffused impurities.

[0057] Additionally, the source line SL is located within the insulating layer 50 outside the stacked body LM, and is connected to the peripheral circuit CBA via an unshown through-connection extending from the electrode film EL to the peripheral circuit CBA.

[0058] A stacked layer LM is configured on the source line SL. The stacked layer LM comprises stacked layers LMa and LMb in which multiple word lines WL and multiple insulating layers OL are stacked alternately layer by layer.

[0059] The stacked layer LMa is positioned above the source line SL. Below the bottom word line WL of the stacked layer LMa, an insulating layer OL separates the select gate lines SGS0 and SGS1, arranged sequentially from the top layer of the stacked layer LMa. The stacked layer LMb is positioned on the stacked layer LMa. Above the top word line WL of the stacked layer LMb, an insulating layer OL separates the select gate lines SGD0 and SGD1, arranged sequentially from the top layer of the stacked layer LMb.

[0060] However, the number of word lines WL and select gate lines SGD and SGS in the stacked body LM is arbitrary. The word lines WL and select gate lines SGD and SGS are, for example, tungsten or molybdenum layers. The insulating layer OL is, for example, a silicon oxide layer.

[0061] The upper surface of the laminate LM is covered by insulating layer 52. Insulating layer 52 is covered by insulating layer 53. Insulating layers 52 and 53 respectively constitute Figure 1 Part of the insulating layer 50.

[0062] As described above, the laminated body LM is divided into multiple plate-like portions LI along the Y direction. That is, the plate-like portions LI are arranged relative to each other in the Y direction and extend in the lamination direction of the laminated body LM and in the direction along the X direction.

[0063] Thus, the plate-shaped portion LI extends continuously within the laminate LM, spanning from one end to the other in the X direction. Furthermore, the plate-shaped portion LI penetrates the laminate LM and the upper source line DSLb to reach the intermediate source line BSL.

[0064] The plate-like portion LI may, for example, have a tapered shape in which the width in the Y direction decreases from the upper end to the lower end. Alternatively, the plate-like portion LI may, for example, have a curved shape in which the width in the Y direction is greatest at a specified position between the upper end and the lower end.

[0065] Each plate-shaped portion LI includes an insulating layer 54, a conductive layer 24, and a cross-linking portion BR. The insulating layer 54 is, for example, a silicon oxide layer. The conductive layer 24 is, for example, a tungsten layer or a conductive polycrystalline silicon layer. The cross-linking portion BR is the same as the insulating layer 54, for example, a silicon oxide layer. The cross-linking portion BR may also be a polycrystalline silicon layer.

[0066] The insulating layer 54 covers the opposing sidewalls of the plate-shaped portion LI in the Y direction. The conductive layer 24 fills the inner side of the insulating layer 54. As described... Figure 2 As shown, the cross-linked portion BR covers a portion of the upper end of the conductive layer 24 in the plate-shaped portion LI that extends in the X direction.

[0067] In the Figure 2 In the example, although the crosslinking portion BR is shown to be arranged in the Y direction among multiple plate-shaped portions LI, since Figure 3(a) shows the plate-shaped portions LI with and without the crosslinking portion BR respectively, the cross-section of the plate-shaped portion LI with the crosslinking portion BR is shown on the left side of the paper, and the cross-section of the plate-shaped portion LI without the crosslinking portion BR is shown on the right side of the paper.

[0068] Between adjacent plate-shaped portions LI in the Y direction, multiple separation layers SHE are disposed, extending through the upper portion of the stacked body LMb and extending in the X direction. These separation layers SHE are insulating layers 56 such as silicon oxide layers that penetrate the select gate lines SGD0 and SGD1 and reach the insulating layer OL directly below the select gate line SGD1.

[0069] In other words, by extending these separation layers SHE, which penetrate the upper portion of the stacked body LMb, between the plate-shaped portion LI, and in a portion of the memory region MR and the stepped region SR along the X direction, the upper portion of the stacked body LMb is divided into the selected gate lines SGD0 and SGD1.

[0070] Multiple pillars PL are distributed throughout the memory region MR, connecting the stacked layer LM, the upper source line DSLb, and the intermediate source line BSL to the lower source line DSLa. Each pillar PL has a cross-sectional shape along the layer direction of the stacked layer LM, that is, along the XY plane, and may have shapes such as circular, elliptical, or oblong (oval).

[0071] Furthermore, in the portions of the laminated body LMa and LMb, column PL has a conical shape in which the diameter and cross-sectional area decrease from the upper layer side to the lower layer side. Alternatively, in the portions of the laminated body LMa and LMb, column PL has a curved shape in which the diameter and cross-sectional area are maximized, for example, at a designated position between the upper and lower layers.

[0072] Each of the multiple pillars PL has a memory layer ME extending along the stacking direction within the stacked body LM, a channel layer CN penetrating within the stacked body LM and connected to the intermediate source line BSL, a capping layer CP covering the upper surface of the channel layer CN, and a core layer CR that becomes the core material of the pillar PL.

[0073] More specifically, the channel layer CN is directly connected to the intermediate source line BSL at its depth. In other words, the memory layer ME is disposed on the side of the pillar PL, excluding the depth of the intermediate source line BSL. Furthermore, the memory layer ME is also disposed on the bottom surface of the pillar PL, reaching the depth of the lower source line DSLa.

[0074] As described above, the channel layer CN further penetrates the stacked layer LM, the upper source line DSLb, and the intermediate source line BSL inside the memory layer ME, reaching the depth of the lower source line DSLa, and makes contact with the intermediate source line BSL on the side. Thus, the channel layer CN is electrically connected to the source line SL containing the intermediate source line BSL.

[0075] Furthermore, the capping layer CP is disposed on the upper end of the pillar PL such that it at least covers the upper end of the channel layer CN, and is connected to the channel layer CN. Additionally, the capping layer CP is connected to the bit line BL disposed in the insulating layer 53 via a plug CH disposed in the insulating layer 52. The bit line BL extends above the stacked body LM in the Y direction, intersecting the lead-out direction of the word line WL.

[0076] Furthermore, in Figure 3(a), a separation layer SHE is arranged between multiple adjacent pillars PL in the Y direction. However, as Figure 2 As shown in the example, the separator layer SHE can also be configured to coincide with several pillars PL in the stacking direction of the stack body LM. In this case, since the separator layer SHE extends from the upper end of the pillars PL to the height of the selected gate line SGD, these pillars PL can also be treated as dummy pillars.

[0077] Furthermore, in Figure 3(a), the plug CH is only connected to the three selected gate lines SGD, which are separated into three of the six pillars PL, and electrically connected to the bit line BL shown in Figure 3(a). The other pillars PL, at a different location from the cross-section shown in Figure 3(a), are connected via the plug CH (not shown in Figure 3(a)) to other bit lines BL that extend parallel to the bit line BL in the Y direction.

[0078] As shown in Figures 3(c) and 3(d), the memory layer ME has a stacked structure comprising a barrier insulating layer BK, a tunnel insulating layer TN, and a charge storage layer CT.

[0079] The memory layer ME consists of a barrier insulating layer BK, a tunnel insulating layer TN, and a core layer CR, which may be a silicon oxide layer. The charge storage layer CT may be a silicon nitride layer. The channel layer CN and the capping layer CP may be semiconductor layers such as polycrystalline silicon or amorphous silicon.

[0080] As shown in Figure 3(d), with the above structure, memory cells MC are formed on each part of the side of the column PL that faces the word line WL. Data is written to and read from the memory cells MC by applying a specified voltage from the word line WL.

[0081] As shown in Figure 3(c), select gate STDs are formed on the side of pillar PL opposite to the select gate lines SGD0 and SGD1 on the upper layer of the bit line WL. Furthermore, select gate STSs are formed on the side of pillar PL opposite to the select gate lines SGS0 and SGS1 on the lower layer of the bit line WL.

[0082] By applying specified voltages from the select gate lines SGD and SGS respectively, the select gates STD and STS can be turned on or off, and the memory cell MC of the column PL to which the select gates STD and STS belong can be set to a selected state or a non-selected state.

[0083] As shown in Figure 3(b), the pseudo-block region BLKd is disposed between the plate-shaped portion LI and the pseudo-plate-shaped portion LId on the side of the block region BLK that is adjacent to the block region BLKd in the Y direction, and the pseudo-plate-shaped portion LId is further out in the Y direction of the block region BLKd, and separates the area where the pseudo-stepped region SRd and the like are disposed from the block region BLKd.

[0084] On the outer side of the pseudo-block region BLKd in the Y direction, that is, in the region to the right of the pseudo-plate-like part LId on the paper, an intermediate sacrificial layer SCN is arranged to replace the intermediate source line BSL of the source line SL.

[0085] In other words, corresponding to the lower source line DSLa, the middle source line BSL and the upper source line DSLb configured in the block region BLK, the lower source line DSLa, the middle sacrificial layer SCN and the upper source line DSLb are sequentially configured in the block region BLKd starting from the insulating layer 60 side.

[0086] The intermediate sacrificial layer SCN is, for example, a silicon nitride layer, and functions as a sacrificial layer when forming the intermediate source line BSL in the block region BLK during the manufacturing process of the semiconductor memory device 1 described later. In the block region BLKd, the intermediate source line BSL is not formed by the intermediate sacrificial layer SCN, and the sacrificial layer, i.e., the intermediate sacrificial layer SCN, is retained as is.

[0087] Furthermore, in the block region BLKd, above the upper source line DSLb, there is a stacked body LMs, which has multiple insulating layers NL stacked and has stacked bodies LMsa and LMsb, instead of a stacked body LM, which has multiple word lines WL and select gate lines SGD and SGS stacked and has stacked bodies LMa and LMb.

[0088] In other words, the stacked structure LMs comprises stacked structures LMsa and LMsb in which multiple insulating layers NL and multiple insulating layers OL are stacked alternately. Stacked structure LMsa corresponds to stacked structure LMa of block region BLK and is disposed above the upper source line DSLb. Stacked structure LMsb corresponds to stacked structure LMb of block region BLK and is disposed on stacked structure LMsa.

[0089] The multiple insulating layers NL included in the stacked layers LMsa and LMsb are, for example, silicon nitride layers, and function as sacrificial layers when word lines WL, etc., are formed in the semiconductor memory device 1 described later. In the block region BLKd, word lines WL, etc., are not formed by insulating layers NL, and the sacrificial layer, i.e., the insulating layer NL, is retained as is.

[0090] Furthermore, the number of insulating layers NL included in the stacked layer LMsa is equal to the total number of word lines WL and select gate lines SGS included in the stacked layer LMa of the block region BLK. Similarly, the number of insulating layers NL included in the stacked layer LMsb is equal to the total number of word lines WL and select gate lines SGD included in the stacked layer LMb of the block region BLK. Additionally, insulating layers 52 and 53 covering the upper surface of the stacked layer LM also cover the upper surface of the stacked layer LMs.

[0091] The stacked layers LMs thus constructed, and the intermediate sacrificial layer SCN disposed between the lower source line DSLa and the upper source line DSLb, can also be configured within a portion of the block region BLKd. That is, in this case, as described... Figure 2 As shown, the laminated bodies LMs and the intermediate sacrificial layer SCN are arranged on both sides of the pseudo-plate-like part LId in the Y direction.

[0092] Therefore, within the pseudo-block region BLKd, stacked layers LM and intermediate source lines BSL can be configured within a specified distance from the plate-shaped portion LI on one side of the Y direction in the Y direction, and stacked layers LMs and intermediate sacrificial layers SCN can be configured within a specified distance from the plate-shaped portion LId on the other side of the Y direction in the Y direction.

[0093] In this case, the stacked LM and stacked LMs may not have a clear boundary. By gradually replacing the metal atoms such as tungsten contained in the word line WL of the stacked LM with molecules such as silicon nitride contained in the insulating layer NL of the stacked LMs, the stacked LM can also be gradually replaced with the stacked LMs.

[0094] Furthermore, the intermediate source line BSL and the intermediate sacrificial layer SCN may not have a clear boundary. By gradually replacing silicon atoms in the intermediate source line BSL with silicon nitride molecules in the intermediate sacrificial layer SCN, the intermediate source line BSL can also be gradually replaced with the intermediate sacrificial layer SCN.

[0095] The stacked layer LM and the intermediate source line BSL may occupy at least about half of the block region BLKd. However, the volume occupied by the stacked layer LM and the intermediate source line BSL within the block region BLKd may vary depending on the conditions in the manufacturing steps of the semiconductor memory device 1 described later. Therefore, the stacked layer LM and the intermediate source line BSL may occupy more than half of the volume within the block region BLKd, or they may occupy the entire block region BLKd.

[0096] Furthermore, in the example of Figure 3(b), the boundaries between the stacked bodies LM and LMs, and the boundaries between the intermediate source line BSL and the intermediate sacrificial layer SCN, are located at approximately the same distance from the plate-like portion LI on one side of the block region BLKd. However, these boundaries can also be located at different distances from the plate-like portion LI on one side of the block region BLKd. As an example, the distance from the boundary between the stacked bodies LM and LMs to the plate-like portion LI can be shorter than the distance from the boundary between the intermediate source line BSL and the intermediate sacrificial layer SCN to the plate-like portion LI.

[0097] The pseudo-plate-like portion LId is disposed on one side of the block region BLKd in the Y direction, and extends continuously within the stacked body LMs, spanning from one end to the other in the X direction. Furthermore, the plate-like portion LId penetrates the stacked body LMs and the upper source line DSLb to reach the intermediate sacrificial layer SCN.

[0098] The plate-like portion LId, for example, has a tapered shape in which the width in the Y direction decreases from the upper end to the lower end. Alternatively, the plate-like portion LId, for example, has a curved shape in which the width in the Y direction is greatest at a specified position between the upper end and the lower end.

[0099] Furthermore, the plate-shaped portion LId includes an insulating layer 54, a sacrificial layer 25, and a crosslinking portion BRw. The sacrificial layer 25 is, for example, an amorphous silicon layer, and functions as a sacrificial layer until the conductive layer 24 is formed in the plate-shaped portion LI during the manufacturing process of the semiconductor memory device 1 described later. In the plate-shaped portion LId, the conductive layer 24 is not formed, and the sacrificial layer 25 is retained as is. The crosslinking portion BRw is the same as that of the insulating layer 54 and the crosslinking portion BR of the plate-shaped portion LI, for example, a silicon oxide layer. The crosslinking portion BRw may also be a polycrystalline silicon layer.

[0100] The insulating layer 54 also covers the opposing sidewalls in the Y direction within the plate-like portion L1d. The sacrificial layer 25 fills the inner side of the insulating layer 54. As described... Figure 2 As shown, the crosslinked portion BRw covers the entire upper end of the sacrificial layer 25 in the plate-like portion LId extending in the X direction.

[0101] Within the pseudo-block region BLKd, between adjacent plate-shaped portions LI and LId in the Y direction, multiple separator layers SHE are disposed, extending through the upper portion of the stacked body LMsb and extending in the X direction. The penetration depth of the separator layers SHE within the block region BLKd is equivalent to the depth of the select gate line SGD within the block region BLK.

[0102] Within the block region BLKd, multiple pseudopillars PLd are dispersed, connecting the stacked layer LM or stacked layer LMs, the upper source line DSLb, and the intermediate source line BSL or intermediate sacrificial layer SCN to reach the lower source line DSLa.

[0103] Each column PLd has the same configuration as the column PL. That is, each of the multiple columns PLd has a pseudo-layer MEd extending along the lamination direction within the laminate LM or laminates LMs, a pseudo-layer CNd penetrating within the laminate LM or laminates LMs, a pseudo-layer CPd covering the upper surface of the pseudo-layer CNd, and a pseudo-layer CRd that serves as the core material of the column PLd.

[0104] In a pillar PLd disposed within a stacked matrix LM, a pseudo-layer CNd penetrates the stacked matrix LM and is directly connected to the intermediate source line BSL at a depth of BSL. Conversely, in a pillar PLd disposed within stacked matrix LMs, a pseudo-layer MEd is disposed around the pseudo-layer CNd penetrating the stacked matrix LMs; the pseudo-layer CNd is not directly connected to the intermediate sacrificial layer SCN. Furthermore, in either case, the pseudo-layer MEd is disposed on the bottom surface of the pillar PLd up to the depth of the lower source line DSLa.

[0105] Furthermore, the dummy layer CPd is disposed on the upper end of the post PLd such that it at least covers the upper end of the dummy layer CNd and is connected to the dummy layer CNd. In addition, the dummy layer CPd is connected to the dummy bit line BLd disposed in the insulating layer 53 via the dummy plug CHd disposed in the insulating layer 52.

[0106] However, the bit line BL, which is connected to the pillar PL of the block region BLK via the plug CH, is electrically connected to the peripheral circuit CBA. In contrast, the bit line BLd, which is connected to the dummy pillar PLd in the block region BLKd, is not connected to the peripheral circuit CBA. This is because the dummy pillar PLd does not contribute to the function of the semiconductor memory device 1 and is a configuration that does not require electrical operation.

[0107] (Manufacturing method of semiconductor memory device)

[0108] Next, use Figures 4-9 The manufacturing method of the semiconductor memory device 1 according to the embodiment will be described. Figures 4-9 This diagram is a part of the sequence illustrating the manufacturing method of the semiconductor memory device 1 according to the embodiments. Figures 4-9 In the figure, a cross-section along the Y direction of the region that will later be referred to as the memory region MR is shown.

[0109] like Figure 4 As shown in (a), a lower source line DSLa, an intermediate sacrificial layer SCN, and an upper source line DSLb are sequentially formed on a supporting substrate SS.

[0110] The supporting substrate SS can be a semiconductor substrate such as a silicon substrate, an insulating substrate such as a ceramic substrate, or a conductive substrate. The insulating layer 60 can also be formed on the upper surface of the supporting substrate SS (see reference). Figure 2 (etc.). The intermediate sacrificial layer SCN is, for example, a silicon nitride layer, as described above, which is later replaced by a polysilicon layer or the like to become the intermediate source line BSL.

[0111] On the upper source line DSLb, a multilayer body LMsa is formed by alternating layers of multiple insulating layers NL and multiple insulating layers OL. The insulating layer NL is, for example, a silicon nitride layer, and as described above, functions as a sacrificial layer that will later be replaced with a conductive material to become the word line WL or the select gate line SGS.

[0112] Subsequently, although not illustrated, insulating layers NL and OL are processed into a stepped shape at both ends of the stacked layer LMsa in the X direction. This processing can be performed by repeatedly refining the mask pattern such as the photoresist layer and etching the insulating layers NL and OL of the stacked layer LMsa.

[0113] In other words, a mask pattern is formed on the upper surface of the stacked matrix LMsa, and the exposed portions of the insulating layers NL and OL are etched away layer by layer. Furthermore, during processing with oxygen plasma or similar methods, the ends of the mask pattern are retracted to re-expose the upper surface of the stacked matrix LMsa, and the insulating layers NL and OL are further etched away layer by layer. By repeating this process multiple times, a stacked matrix LMsa with a stepped shape is formed at both ends in the X direction.

[0114] Additionally, at this time, the two ends of the laminate LMsa in the Y direction are also similarly processed into a stepped shape, forming a structure that becomes part of the pseudo-stepped region SRd after formation. Subsequently, the insulating layer 50 (reference) Figure 1 (a)) The stepped structure covering both ends in the X direction and both ends in the Y direction.

[0115] like Figure 4 As shown in (b), multiple memory holes MHa are formed in the stacked layer LMsa extending along the stacking direction. The multiple memory holes MHa penetrate the stacked layer LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN to reach the lower source line DSLa. These memory holes MHa then form the lower structure of the pillar PL or pillar PLd.

[0116] Subsequently, plate-shaped portions LI and LId are provided in the portion with a larger gap where these memory holes MHa are located on page 2. Therefore, the two memory holes MHa on the left side of the page are the lower structure portion that will later become the pillar PL, and the six memory holes MHa in the center of the page are the lower structure portion that will later become the pillar PLd.

[0117] like Figure 4As shown in (c), these memory holes MHa are filled with a sacrificial layer 27, such as an amorphous silicon layer or a CVD (Chemical Vapor Deposition)-carbon layer. This forms a pillar PLc that fills the multiple memory holes MHa with the sacrificial layer 27.

[0118] like Figure 4 As shown in (d), a multilayer stack LMsa is formed by alternating layers of multiple insulating layers NL and multiple insulating layers OL. The insulating layer NL of the multilayer stack LMsb functions as a sacrificial layer that is later replaced by a conductive layer to become the word line WL or the select gate line SGD.

[0119] Subsequently, although not illustrated, in a portion of the stacked matrix LMsb, the insulating layers NL and OL are processed into a stepped shape. This processing is similar to the processing of the stacked matrix LMsa, and can be performed by repeatedly refining the mask pattern such as the photoresist layer and etching the insulating layers NL and OL of the stacked matrix LMsb.

[0120] At this point, the uppermost layer of the stepped portion already formed in the laminate LMsa is brought close to the lowermost layer of the stepped portion already formed in the laminate LMsb, forming a stepped shape in a manner that continuously connects from the lower layer side of the laminate LMsa to the upper layer side of the laminate LMsb. Thus, laminates LMsa and LMsb, with a stepped region SR spanning from the laminate LMsa to the laminate LMsb, are formed at both ends in the X direction.

[0121] Additionally, at this time, the two ends of the laminated body LMsb in the Y direction are also processed into a stepped shape, forming part of the pseudo-stepped region SRd. Subsequently, the insulating layer 50 (reference) Figure 1 (a) further covers the stepped structure at both ends in the X direction and both ends in the Y direction.

[0122] like Figure 5 As shown in (a), a through-layer LMsb is formed, and multiple memory holes MHb are connected to multiple pillars PLc that have been formed in the layer LMsa. The memory holes MHb are the upper structure that later becomes pillar PL or pillar PLd.

[0123] like Figure 5 As shown in (b), the sacrificial layer 27 is removed from the pillar PLc at the bottom of the memory hole MHb. As a result, memory holes MHa are formed at the bottom of the multiple memory holes MHb, forming multiple memory holes MH that penetrate the stacked layers LMsb, LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN to reach the lower source line DSLa.

[0124] In addition, the two memory holes MH on the left side of the paper are the structure that will later become pillar PL, and the six memory holes MH in the center of the paper are the structure that will later become pillar PLd.

[0125] Furthermore, when the sacrificial layer 27 filled into the column PLC is a CVD-carbon layer or the like, the sacrificial layer can be removed by ashing with oxygen plasma or the like. Figure 5 When forming the memory hole MHb in (a) of the sample layer, the sacrificial layer 27 can be removed from these pillars PLC together with the mask pattern used.

[0126] like Figure 5 As shown in (c), multiple insulating layers MEb, semiconductor layers CNb, and insulating layers CRb are sequentially formed within the memory hole MH. Thus, multiple insulating layers MEb and semiconductor layers CNb are formed on the side surface of the memory hole MH and on the bottom surface where the source line DSLa is exposed, while the insulating layer CRb is filled in the center of the memory hole MH. The multiple insulating layers MEb, semiconductor layers CNb, and insulating layers CRb correspond to the memory layer ME, the channel layer CN, and the core layer CR, or the pseudo-layers CRd, CNd, and MEd, respectively. Furthermore, multiple insulating layers MEb, semiconductor layers CNb, and insulating layers CRb are also sequentially formed on the upper surface of the stack LMsb.

[0127] like Figure 5 As shown in (d), the insulating layer CRb, the semiconductor layer CNb, and the multilayer insulating layer MEb on the upper surface of the stack LMsb are removed sequentially, and they are set as layers separated according to each memory hole MH. Thus, in the memory hole MH that subsequently becomes pillar PL on the left side of the paper, the core layer CR, the channel layer CN, and the memory layer ME are formed. Furthermore, in the memory hole MH that subsequently becomes pillar PLd in the center of the paper, pseudo-layers CRd, CNd, and MEd are formed.

[0128] In addition, when removing the insulating layer CRb, semiconductor layer CNb and multilayer insulating layer MEb on the upper surface of the stacked body LMsb, the upper ends of the core layer CR and channel layer CN, and the upper ends of the pseudo layers CRd and CNd are respectively moved back from the upper surface of the memory hole MH, forming a recess DN at the upper end of the memory hole MH.

[0129] like Figure 6 As shown in (a), a semiconductor layer CPb is formed in the recess DN at the upper end of the memory hole MH. The semiconductor layer CPb, which later becomes the capping layer CP or the pseudo layer CPd, is also formed on the upper surface of the stack LMsb.

[0130] like Figure 6As shown in (b), the semiconductor layer CPb on the upper surface of the stacked matrix LMsb is removed by CMP (Chemical Mechanical Polishing) or similar methods to form a capping layer CP or a dummy layer CPd disposed at the upper end of the memory hole MH. At this time, the uppermost insulating layer OL of the stacked matrix LMsb is also removed by a specified amount of layer thickness.

[0131] like Figure 6 As shown in (c), an insulating layer OL is added to the top layer of the laminate LMsb, which is thinned by CMP, etc. As a result, a capping layer CP is formed with pillar PL embedded in the top insulating layer OL, and a pseudo-layer CPd is formed with pillar PLd embedded in the top insulating layer OL.

[0132] However, at this point, the memory layer ME covers the entire sidewall of the pillar PL, and a portion of the sidewall of the channel layer CN is not exposed from the memory layer ME. The same applies to the pseudo-pillar PLd.

[0133] like Figure 7 As shown in (a), a slit ST is formed that penetrates the stacked layers LMsb and LMsa and the upper source line DSLb to reach the intermediate sacrificial layer SCN. The slit ST extends within the stacked layers LMsa and LMsb and also extends in the X direction.

[0134] like Figure 7 As shown in (b), an insulating layer 54 is formed on the opposing sidewalls of the slit ST in the Y direction. Furthermore, a sacrificial layer 25, such as an amorphous silicon layer, is filled inside the insulating layer 54 covering the sidewalls of the slit ST.

[0135] like Figure 7 As shown in (c), the upper end of the sacrificial layer 25 filling the slit ST is removed. At this time, in the slit ST that becomes a plate-like portion LI after the slit ST on the left side of the paper, a portion of the sacrificial layer 25 extending in the X direction is removed intermittently. On the other hand, in the slit ST that becomes a plate-like portion LId after the slit ST on the right side of the paper, the entire upper end of the sacrificial layer 25 extending in the X direction is removed.

[0136] like Figure 7 As shown in (d), a silicon oxide layer or polysilicon layer is formed to cover the portion after the sacrificial layer 25 at the upper end of the slit ST has been removed. As a result, a crosslinked portion BR is formed on the slit ST on the left side of the paper, and a crosslinked portion BRw is formed on the slit ST on the right side of the paper. Furthermore, a pseudo-plate-like portion LId, comprising an insulating layer 54, a sacrificial layer 25, and a crosslinked portion BRw, is formed on the right side of the paper.

[0137] like Figure 8As shown in (a), the sacrificial layer within the slit ST is removed from the crosslinked portions BR between the upper ends of the multiple slits ST intermittently formed on the left side of the paper surface. At this time, a crosslinked portion BRw covering the entire upper surface is formed on the plate-like portion LId on the right side of the paper surface. Therefore, the sacrificial layer 25 is not removed from the plate-like portion LId.

[0138] like Figure 8 As shown in (b), the sacrificial layer 25 is removed through multiple slits ST, such as the slit ST on the left side of the paper, and the sidewalls are protected by the insulating layer 54. A removal solution for the intermediate sacrificial layer SCN, such as hot phosphoric acid, flows in, thereby removing the intermediate sacrificial layer SCN sandwiched between the lower source line DSLa and the upper source line DSLb. However, because the sidewalls of these slits ST are protected by the insulating layer 54, the removal of the insulating layer NL within the laminates LMsa and LMsb is also prevented.

[0139] Thus, a gap layer GPs is formed between the lower source line DSLa and the upper source line DSLb. Furthermore, a portion of the memory layer ME on the outer periphery of the pillar PL is exposed within the gap layer GPs.

[0140] At this point, the treatment time for hot phosphoric acid and other removal solutions is determined based on the time required to remove all intermediate sacrificial layers SCN within a region equivalent to one block region BLK when the removal solution flows in from both sides of the Y direction using adjacent slits ST in the Y direction.

[0141] On the other hand, because the sacrificial layer 25 is still filled in the plate-shaped portion LId on the right side of the paper, the removal liquid will not flow in from the plate-shaped portion LId. Therefore, in the area where the six columns PLd in the center of the paper are arranged, the intermediate sacrificial layer SCN is removed only from the slit ST on the left side of the paper, and in the area near the plate-shaped portion LId on the right side of the paper, the intermediate sacrificial layer SCN is not completely removed and remains.

[0142] In this case, in a portion of the column PLd in the slit ST configuration near the left side of the paper, the dummy layer MEd is exposed within the gap layer GPs formed between the lower source line DSLa and the upper source line DSLb. In a portion of the column PLd in the plate-like portion LId configuration near the right side of the paper, the dummy layer MEd is still covered by the intermediate sacrificial layer SCN.

[0143] like Figure 8 As shown in (c), the drug solution is allowed to flow appropriately into the interstitial layers GPs through multiple slits ST, sequentially removing the barrier insulating layer BK, charge storage layer CT, and tunnel insulating layer TN of the memory layer ME exposed within the interstitial layers GPs (see reference). Figure 2(c)(d)). Thus, the memory layer ME is removed from a portion of the sidewall of the pillar PL, and a portion of the inner channel layer CN is exposed within the gap layers GPs.

[0144] At this time, in the region of the six pillars PLd in the center of the paper, the pseudo-layer MEd of a portion of the pillars PLd in the region where the gap layers GPs are formed can also be removed in the same way as the multiple pillars PL, and the pseudo-layer CNd is exposed in the gap layers GPs.

[0145] like Figure 8 As shown in (d), a raw material gas, such as amorphous silicon, is injected through multiple slits ST with sidewalls protected by insulating layer 54, and the interstitial layers GPs are filled with amorphous silicon. Furthermore, the supporting substrate SS is heated to polycrystalline the amorphous silicon filled within the interstitial layers GPs, forming an intermediate source line BSL containing polycrystalline silicon.

[0146] Thus, a portion of the channel layer CN of pillar PL is connected to the source line SL on the side via the intermediate source line BSL. Similarly, a portion of the exposed pseudo-layer CNd of pillar PLd can be connected to the source line SL on the side via the intermediate source line BSL.

[0147] like Figure 9 As shown in (a), the insulating layer 54 of the multiple slit ST sidewalls, where the sacrificial layer 25 has been removed, is temporarily removed. At this time, if the cross-linked portion BR is formed using a material such as polycrystalline silicon, which is different from the insulating layer 54, then damage to the cross-linked portion BR during the removal of the insulating layer 54 can also be suppressed.

[0148] like Figure 9 As shown in (b), a removal liquid for insulating layer NL, such as hot phosphoric acid, is introduced into the interior of the laminates LMsa and LMsb through multiple slits ST to remove the insulating layer NL of the laminates LMsa and LMsb.

[0149] At this point, the treatment time for hot phosphoric acid and other removal solutions is determined based on the time required to remove all insulation layers NL within a region equivalent to one block area BLK when the removal solution flows in from both sides of the Y direction using adjacent slits ST in the Y direction.

[0150] On the other hand, because the sacrificial layer 25 is still filled in the plate-shaped portion LId on the right side of the paper, the removal liquid will not flow in from the plate-shaped portion LId. Therefore, in the area where the six pillars PLd in the center of the paper are arranged, the insulation layer NL is removed only from the slit ST on the left side of the paper, and in the area near the plate-shaped portion LId on the right side of the paper, the insulation layer NL is not completely removed and remains.

[0151] Based on the above, in a portion of the area between the multiple slits ST containing the slit ST on the left side of the paper surface where the sacrificial layer 25 has been removed, and between the plate-shaped portion LId on the right side of the paper surface where the sacrificial layer 25 is still filled and the slit ST on the left side of the paper surface where the sacrificial layer 25 has been removed, a laminate LMga and LMgb having multiple gap layers GP after the insulation layer NL between the insulation layers OL has been removed are formed.

[0152] The laminates LMga and LMgb containing multiple interstitial layers GP become fragile structures. Multiple pillars PL support these fragile laminates LMga and LMgb. Thus, it is possible to suppress the deflection of the insulating layer OL retained in the laminates LMga and LMgb, or the deformation or collapse of the laminates LMga and LMgb.

[0153] However, the pseudo-step regions SRd at both ends of the laminates LMga and LMgb in the Y direction and the insulating layer 50 covering their outer sides (reference) Figure 1 In (a) of the above, an expansion stress (tensile stress) is generated that expands outward from the center portion of the insulating layer 50. Therefore, the laminates LMga and LMgb are subjected to a contraction stress in the center portion in the Y direction toward the laminates LMga and LMgb.

[0154] Therefore, there is a concern that the multiple pillars PL formed in the laminates LMga and LMgb may shift in position in the Y direction. When this shift occurs among the multiple pillars PL, it may overlap with the subsequently formed plug CH, potentially resulting in poor connection between the pillars PL and the plug CH.

[0155] Furthermore, the width of multiple slits ST in the Y direction may decrease due to compression in the laminations LMga and LMgb caused by shrinkage stress. This could lead to the closure of multiple slits ST, potentially hindering subsequent processing. There is also concern that this variation in slit ST width could further contribute to the positional displacement of multiple columns PL in the Y direction.

[0156] The positional offset described above is more significant closer to the Y-direction end of the stacked layer LM. This is one of the reasons why dummy pillars PLd are configured at the ends of the stacked layer LM. In other words, in areas where positional offset may occur due to stress on the insulating layer 50, dummy pillars PLd are configured to replace pillars PL that contribute to the function of the semiconductor memory device 1.

[0157] In the semiconductor memory device 1 of the embodiment, in addition to the countermeasures described above, a pseudo-plate-like portion LId is provided at the end of the stacked layers LMga and LMgb in the Y direction, and stacked layers LMsa and LMsb with the insulating layer NL not removed are retained at the end of the stacked layers LMga and LMgb in the Y direction. This separates the stacked layers LMga and LMgb disposed inside the stacked layers LMsa and LMsb in the Y direction from the insulating layer 50 disposed outside the stacked layers LMsa and LMsb, thereby suppressing the influence of stress generated by the insulating layer 50 on the stacked layers LMga and LMgb.

[0158] Therefore, it can suppress the positional displacement of the column PL and the change in the width of the slit ST caused by the shrinkage stress in the laminated bodies LMga and LMgb.

[0159] Furthermore, multiple slits ST have cross-linking portions BR at their upper ends. This alleviates the stress on both sides of the slit ST in the Y direction, further suppressing changes in the width of the slit ST.

[0160] like Figure 9 As shown in (c), a raw material gas containing conductive materials such as tungsten or molybdenum is injected into the laminates LMga and LMgb through the slit ST, and the interstitial layer GP of the laminates LMga and LMgb is filled with conductive material to form multiple word lines WL, etc.

[0161] Thus, a stacked body LM is formed, comprising stacked bodies LMa and LMb in which multiple word lines WL and the like are alternately stacked with multiple insulating layers OL. As described above, at this time, stacked bodies LMs are still retained in a portion of the regions at both ends of the stacked body LM in the Y direction.

[0162] As mentioned above, the process of forming the intermediate source line BSL from the intermediate sacrificial layer SCN and the process of forming the word line WL from the insulating layer NL are also referred to as replacement processes.

[0163] Subsequently, an insulating layer 54 is reformed on the sidewall of the slit ST, and a conductive layer 24 is filled in the insulating layer 54 to form a plate-like portion LI.

[0164] In addition, a trench is formed through one or more conductive layers containing the uppermost conductive layer of the stacked body LMb, and an insulating layer 56 is filled in the trench, thereby forming a separation layer SHE that divides these conductive layers into a pattern of select gate lines SGD.

[0165] In addition, multiple contacts CC are formed, which are word lines WL and select gate lines SGD and SGS respectively, extending from the upper side of the stepped region SR to each level of the stepped structure constituting the stepped region SR.

[0166] Furthermore, an insulating layer 52 is formed on the upper surface of the multilayer assembly LM, and plugs CH are formed that penetrate the insulating layer 52 and are respectively connected to multiple posts PL, and plugs are formed that are connected to contacts CC. Furthermore, an insulating layer 53 is formed on the insulating layer 52, and bit lines BL are formed that are connected to the plugs CH, and upper layer wiring is formed that is connected to contacts CC via the plugs CC. Furthermore, electrode pads for obtaining electrical conduction with the peripheral circuit CBA are formed on the upper surface of the insulating layer 53.

[0167] In addition, as described above, for example, a double-layer mosaic method can be used to form the plug CH and bit line BL at the same time.

[0168] In addition, for the pseudo-pillar PLd, the formation of pseudo-plug CHd and pseudo-bit line BLd are also performed in parallel with the aforementioned processing.

[0169] On the other hand, a peripheral circuit CBA is formed on a semiconductor substrate SB, which is separate from the support substrate SS on which the multilayer LM is formed, and is covered by an insulating layer 40. In the insulating layer 40, contacts, vias, wirings, etc., are formed to lead the peripheral circuit CBA to the surface of the insulating layer 40, and are connected to electrode pads, etc., formed on the upper surface of the insulating layer 40.

[0170] Next, the support substrate SS and the semiconductor substrate SB are bonded together with their respective insulating layers 50 and 40, and the electrode pads in the insulating layers 50 and 40 are connected. Subsequently, the support substrate SS is removed to expose the source line SL, and the electrode film EL is connected by an insulating layer 60 with the plug PG formed between them.

[0171] Based on the above, a semiconductor memory device 1 is manufactured according to the embodiment.

[0172] (Summary)

[0173] In semiconductor memory devices such as 3D non-volatile memory, the periodic arrangement of pillars terminating at both ends of the stacked layer in the Y direction easily leads to processing errors during pillar formation. Furthermore, only relatively small pseudo-step regions are configured at both ends of the stacked layer in the Y direction; during stack replacement, stress from the outside of the stack can easily cause pillar displacement. Therefore, pillars near the ends of the stacked layer in the Y direction are designated as pseudo-pillars, and the regions containing these pseudo-pillars are designated as pseudo-blocks.

[0174] Taking into account the positional offset that occurs in the pillars near both ends of the stacked layer in the Y direction, it is preferable to arrange multiple dummy blocks at each end of the stacked layer in the Y direction. However, this increases the area occupied by the dummy blocks in the semiconductor memory device, increases the storage capacity of the semiconductor memory device, and makes miniaturization of the semiconductor memory device more difficult.

[0175] According to the embodiment of the semiconductor memory device 1, the entire upper end of the plate-shaped portion LId disposed near the outermost end of the stacked layers LM, LMs in the Y direction is covered by the crosslinking portion BRw.

[0176] In this way, by covering the entire plate-shaped portion LId at the end of the laminated body LM and LMs with the cross-linking portion BRw, it is possible to prevent the replacement of the laminated body LMs near the end in the Y direction and suppress the shrinkage stress of the laminated body LM formed on the inside of the laminated body LMs in the Y direction.

[0177] As a result, the range of the end positions of the stacked volumes LM and LMs that may cause the positional offset of the column PL is reduced, for example, the pseudo-block region BLKd can be reduced without configuring multiple pseudo-blocks.

[0178] Furthermore, since two different plate-shaped portions LI and LId can be formed simply by changing the shape of the crosslinking portion BRw, it is possible to form a plate-shaped portion LI for replacing laminates LM and the like, and a plate-shaped portion LId not for replacing laminates LM and the like, without increasing the number of steps.

[0179] According to the embodiment of the semiconductor memory device 1, a sacrificial layer 25 is filled in the plate-shaped portion LId disposed near the outermost end of the stacked layers LMs and LMs in the Y direction. In this way, by pre-reserving the sacrificial layer 25 in the plate-shaped portion LId at the end of the stacked layers LMs and LMs, replacement of the stacked layers LMs near the end in the Y direction can be prevented.

[0180] According to an embodiment, a semiconductor memory device 1 includes stacked layers LMs disposed near the outer side of a plate-like portion LId disposed at the end of the stacked layers LMs in the Y direction. Multiple insulating layers NL and OL are alternately stacked layer by layer, replacing multiple word lines WL, etc. In this way, by pre-retaining the stacked layers LMs at the ends of the stacked layers LMs, shrinkage stress on the stacked layers LMs formed inside the stacked layers LMs in the Y direction can be suppressed.

[0181] According to the embodiment of the semiconductor memory device 1, a plurality of pillars PL, PLd are selectively disposed in the region between the plate-shaped portion LId disposed near the end of the stacked layers LM, LMs in the Y direction and the end of the stacked layers LM, LMs in the Y direction, the region between plate-shaped portions LI and LId adjacent to the plate-shaped portion LId in the Y direction, and the region between plate-shaped portions LId and LI in the region between plate-shaped portions LI that are adjacent to each other in the Y direction.

[0182] As described above, since the laminates LMs located at least outside the plate-like portion LId in the Y direction are not replaced, they do not need to be supported by multiple pillars PL and PLd. Therefore, since multiple pillars PL and PLd are not located in the region outside the plate-like portion LId in the Y direction, the pseudo-block region BLKd can be further reduced.

[0183] According to the embodiment of the semiconductor memory device 1, the pillar PLd disposed in the region between the plate-shaped portions LId and LI is a dummy pillar. In this way, by setting the pillar PLd, which is prone to processing errors and positional displacement due to stress, as a dummy pillar that does not benefit the function of the semiconductor memory device 1, the quality of the semiconductor memory device 1 can be improved.

[0184] (Example of variation)

[0185] Next, use Figure 10 A variation of the semiconductor memory device 2 according to the embodiment will be described. The variation of the semiconductor memory device 2 differs from the embodiment in that at points where the multiple plate-shaped portions LI2 do not have a conductive layer 24.

[0186] Figure 10 This is a cross-sectional view showing an example of the configuration of a semiconductor memory device 2, which is a variation of the implementation method.

[0187] In more detail, Figure 10 (a) is a cross-sectional view along the Y direction in the memory region MR of the semiconductor memory device 2, showing a cross-section along the Y direction in the block region BLK. Figure 10 (b) is a cross-sectional view along the Y direction in the memory region MR of the semiconductor memory device 2, showing a cross-section in the pseudo-block region BLKd. Additionally, in Figure 10 In (a) and (b), the structure below the insulating layer 60 and above the insulating layer 53, which will be described later, is omitted.

[0188] In addition, Figure 10 In this document, the same symbols are used to mark the same components as in the described embodiments, and their descriptions are sometimes omitted.

[0189] like Figure 10 As shown, the semiconductor memory device 2 of the variation example has a plurality of plate-shaped portions LI2 that penetrate the stacked body LM in the stacking direction and extend in the direction along the X direction, instead of the plate-shaped portions LI of the semiconductor memory device 1 of the embodiment.

[0190] Each plate-shaped portion LI2 has an insulating layer 55, such as a silicon oxide layer, instead of the conductive layer 24 provided in the plate-shaped portion LI of the described embodiment. That is, an insulating layer 54 is disposed on the opposing sidewalls in the Y direction of the plate-shaped portion LI2, and an insulating layer 55 is filled inside the insulating layer 54. Furthermore, at the upper end of the insulating layer 55, a plurality of cross-linking portions BR are disposed at specified intervals in the X direction.

[0191] These plate-shaped portions LI2 are formed by replacing the intermediate source line BSL and the laminate LM with an insulating layer 55 filling the slit ST instead of the conductive layer 24. Furthermore, since the insulating layers 54 and 55 are made of the same material such as silicon oxide, their boundaries may be indistinguishable. Additionally, if the crosslinking portion BR is a silicon oxide layer or the like, the boundary between the crosslinking portion BR and the insulating layers 54 and 55 may also be indistinguishable.

[0192] According to the modified example of the semiconductor memory device 2, an insulating layer 55 is filled in the plate-shaped portion LI. This configuration also achieves the same effect as the described embodiment.

[0193] Furthermore, in the aforementioned embodiments and variations, semiconductor memory devices 1 and 2 are provided to have a stacked layer LM with a two-layer (2-Tier) structure in which two stacked layers LMa and LMb are stacked on top of each other. However, the structure of the stacked layer is not limited to a two-layer architecture; it can be a single layer (1-Tier) or three layers (3-Tier) or more.

[0194] Furthermore, in the described embodiments and variations, the pillar PL is connected to the source line SL on the side of the channel layer CN, but this is not a limitation. For example, the pillar can also be constructed by removing the memory layer at the bottom of the pillar and connecting it to the source line at the lower end of the channel layer.

[0195] Furthermore, in the described embodiments and variations, the peripheral circuit CBA is disposed above the stacked body LM. However, the peripheral circuit may be disposed below the stacked body or on the same layer as the stacked body. When the peripheral circuit is disposed below the stacked body, the stacked body can be formed above the semiconductor substrate on which the peripheral circuit is formed. When the peripheral circuit is disposed on the same layer as the stacked body, the stacked body can be formed at a different location on the semiconductor substrate on which the peripheral circuit is formed.

[0196] While several embodiments of the invention have been described, these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in many other ways, with various omissions, substitutions, and modifications possible without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0197] [Explanation of Symbols]

[0198] 1,2 Semiconductor memory devices

[0199] 24 Conductive Layer

[0200] 25 Sacrificial Layer

[0201] 54, 55 Insulation layer

[0202] BLK,BLKd block region

[0203] BR, BRw crosslinking section

[0204] LI, LI2, LId plate-shaped part

[0205] LM, LMs laminates

[0206] MC storage unit

[0207] MR memory region

[0208] NL,OL insulation layer

[0209] PL,PLd column

[0210] SR,SRd stepped area

[0211] SGD, SGS Select Gate Line

[0212] ST slit

[0213] WL lettering.

Claims

1. A semiconductor memory device comprising: A laminate comprising multiple conductive layers and multiple first insulating layers stacked alternately layer by layer; Multiple slits extend within the laminate in a first direction intersecting the lamination direction and in the lamination direction, and divide the laminate in a second direction intersecting the first direction and the lamination direction; and Multiple columns, disposed between the multiple slits, extend within the laminated body along the lamination direction; and The first material covers the entire upper end of the first slit, which is located near the outermost end of the laminate in the second direction; The first material covers a portion of the upper end of each of the plurality of second slits, excluding the first slit.

2. The semiconductor memory device according to claim 1, wherein The first slit is filled with the second material; and A third material, different from the second material, is filled into the plurality of second slits.

3. The semiconductor memory device according to claim 1, wherein... The stack comprises: A first laminate, disposed between the plurality of second slits, wherein the plurality of conductive layers and the plurality of first insulating layers are alternately laminated layer by layer; and A second laminate, disposed between the end of the laminate in the second direction and the first slit, replaces the plurality of conductive layers, and alternately laminates the plurality of second insulating layers with the plurality of first insulating layers layer by layer.

4. The semiconductor memory device according to claim 3, wherein Among the plurality of second slits, the first and second laminates are arranged together between the second slit adjacent to the first slit in the second direction and the first slit.

5. The semiconductor memory device according to claim 4, wherein Between the first and second slits, The first laminate is positioned in the region near the second slit. The second laminate is disposed in the region near the first slit.

6. A semiconductor memory device comprising: A laminate comprising multiple conductive layers and multiple first insulating layers stacked alternately layer by layer; Multiple slits extend within the laminate in a first direction intersecting the lamination direction and in the lamination direction, and divide the laminate in a second direction intersecting the first direction and the lamination direction; and Multiple columns, disposed between the multiple slits, extend within the laminated body along the lamination direction; and Of the plurality of slits, the first slit located near the far end of the laminate in the second direction, and the plurality of second slits other than the first slit, contain different materials and have different layer structures.

7. A method for manufacturing a semiconductor memory device, Forming a laminate by alternately stacking multiple first insulating layers and multiple second insulating layers; Forming a plurality of columns extending within the laminated body along the lamination direction of the laminated body; A plurality of slits are formed in a first direction intersecting the stacking direction and in the stacking direction, extending within the stacking body, and dividing the stacking body in a second direction intersecting the first direction and the stacking direction; A first cross-linking portion is formed, covering the entire upper end of the first slit, which is located near the far end of the laminate in the second direction, and a second cross-linking portion is formed, covering a portion of the upper end of each of the plurality of second slits other than the first slit; and The plurality of second insulating layers are replaced with a plurality of conductive layers via the plurality of second slits.

8. The method for manufacturing a semiconductor memory device according to claim 7, wherein... The formation of the first and second cross-linking portions includes: A sacrificial layer is filled within the first slit and within the plurality of second slits; and Recesses for forming the first and second crosslinking portions are formed at the upper end of the sacrificial layer, respectively.

9. The method for manufacturing a semiconductor memory device according to claim 8, wherein... The replacement of the plurality of second insulating layers with the plurality of conductive layers includes: The sacrificial layer filling the second slit is removed from between the second cross-linking portions covering a portion of each of the plurality of second slits.

10. The method for manufacturing a semiconductor memory device according to claim 9, wherein... After replacing the plurality of second insulating layers with the plurality of conductive layers, the plurality of second slits are filled with a material different from the sacrificial layers.

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