Semiconductor device
By setting a first impurity region and a second well region with specific structures in the semiconductor device, the leakage current problem during miniaturization is solved, the storage capacity and reliability are improved, and the performance of the storage device is enhanced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-26
- Publication Date
- 2026-03-13
AI Technical Summary
In existing technologies, leakage current issues exist in semiconductor devices during miniaturization, affecting the performance and reliability of memory devices.
By setting a first impurity region and a second well region with specific structures in a semiconductor device, leakage current can be reduced by utilizing combinations of different conductivity types and impurity concentrations.
It effectively suppresses leakage current, improves the storage capacity and reliability of semiconductor devices, and enhances the performance of storage devices.
Smart Images
Figure CN121665572A_ABST
Abstract
Description
Technical Field
[0001] The implementation generally relates to a semiconductor device. Background Technology
[0002] Semiconductor devices include memory devices. Examples of memory devices include memory devices containing memory cells arranged in a three-dimensional configuration. To increase the storage capacity of memory devices, the components of memory devices are constantly being miniaturized. Summary of the Invention
[0003] The present invention provides a semiconductor device that suppresses leakage current.
[0004] A semiconductor device according to one embodiment includes a first substrate, a first insulator, a first conductor, a second substrate, a first well region, a first impurity region, and a second well region. The first insulator is located in a first direction beyond the first substrate. The first conductor is located within the first insulator. The second substrate is located in the first direction beyond the first insulator. The first well region has a first conductivity type, is disposed in the second substrate, and has a first impurity concentration. The first impurity region has the first conductivity type, is located in the second substrate, is adjacent to the first well region in a second direction beyond the first well region, and has a first impurity concentration of at least 4 times (1×10⁻⁶). 8 The concentration of the second impurity is less than twice that of the first impurity region. The second well region has a second conductivity type and is in contact with the first impurity region in the second substrate in the second direction, which is closer to the first impurity region than the first impurity region. Attached Figure Description
[0005] Figure 1 Examples illustrating the constituent elements of the semiconductor device according to the first embodiment and the connections between the constituent elements.
[0006] Figure 2 This shows the constituent elements of a block of the semiconductor device according to the first embodiment and the connections between the constituent elements.
[0007] Figure 3 This shows the appearance of the semiconductor device according to the first embodiment.
[0008] Figure 4 An example showing the structure of a portion of the surface of the semiconductor device according to the first embodiment.
[0009] Figure 5 An example showing the structure of a partial cross-section of the semiconductor device of the first embodiment.
[0010] Figure 6 An example of the structure of a cross-section along the xy plane of a memory column of a semiconductor device according to the first embodiment.
[0011] Figure 7 This shows a partial structure of the semiconductor device according to the first embodiment.
[0012] Figure 8 An example of the state during the manufacturing process of a first example representing a part of the semiconductor device of the first embodiment.
[0013] Figure 9 An example of the state during the manufacturing process of a first example representing a part of the semiconductor device of the first embodiment.
[0014] Figure 10 An example of the state during the manufacturing process of a first example representing a part of the semiconductor device of the first embodiment.
[0015] Figure 11 An example of the state during the manufacturing process of a first example representing a part of the semiconductor device of the first embodiment.
[0016] Figure 12 An example of the state during the manufacturing process of a first example representing a part of the semiconductor device of the first embodiment.
[0017] Figure 13 An example of the state during the manufacturing process of a first example representing a part of the semiconductor device of the first embodiment.
[0018] Figure 14 An example of the state during the manufacturing process of a first example representing a part of the semiconductor device of the first embodiment.
[0019] Figure 15 An example of the state during manufacturing of a second example representing a part of the semiconductor device of the first embodiment.
[0020] Figure 16 An example of the structure of a partial cross-section of a semiconductor device, representing a variation of the first embodiment. Detailed Implementation
[0021] Hereinafter, embodiments will be described with reference to the accompanying drawings. For multiple components having substantially the same function and structure in a particular embodiment or different embodiments, numbers or characters may be added to the end of the reference numerals to distinguish them from each other.
[0022] The attached diagrams are schematic diagrams, and the relationship between thickness and planar dimensions, as well as the thickness ratios of each layer, may differ from the actual object. Furthermore, the attached diagrams may also include dimensional relationships, configurations, and parts with different ratios.
[0023] In this specification and claims, the term "connecting" a first element to another second element includes connecting the first element directly, or always or selectively, to the second element via an element that is conductive.
[0024] The following description uses a three-dimensional orthogonal coordinate system. The direction of the x-axis is called the X-direction. The direction opposite to the X-direction is called the -X-direction. The direction of the y-axis is called the Y-direction. The direction opposite to the Y-direction is called the -Y-direction. The direction of the z-axis is called the Z-direction (as in the image above). The direction opposite to the Z-direction is called the -Z-direction.
[0025] 1. First Implementation Method
[0026] 1.1. Composition (Structure)
[0027] As an example of a semiconductor device according to the first embodiment, there is a memory device. Hereinafter, memory device 1, as an example of a semiconductor device, will be described.
[0028] Figure 1 This illustrates the constituent elements of the semiconductor device according to the first embodiment and an example of the connections between these elements. Storage device 1 is a device that uses storage cells to store data. Storage device 1 is controlled by an external memory controller. Storage device 1 operates, for example, based on instructions CMD and address information ADD received from the memory controller. Storage device 1 receives data DAT to be written and outputs the data stored in storage device 1.
[0029] The storage device 1 includes components such as a storage cell array 10, a line decoder 11, a register 12, a sequence generator 13, a voltage generation circuit 14, a driver 15, and a sensing amplifier 17.
[0030] The memory cell array 10 is a collection of arranged memory cells. The memory cell array 10 contains multiple memory blocks (BLKs). Each block BLK contains multiple memory cell transistors MTs (not shown). The area where the memory cell array 10 is located also includes wiring such as word lines WLs (not shown) and bit lines BLs (not shown).
[0031] The line decoder 11 is a circuit used to select a block BLK. The line decoder 11 transmits the voltage supplied from the driver 15 to a block BLK, which is selected by the line decoder 11 based on the block address received from the register 12.
[0032] Register 12 is a circuit that stores the instruction CMD and address information ADD received from storage device 1. The instruction CMD directs various actions, including data reading, data writing, and data erasure, to the sequence generator 13. The address information ADD specifies the access object in the memory cell array 10.
[0033] The sequence generator 13 is a circuit that controls the overall operation of the storage device 1. Based on the instruction CMD received by the sequence generator 13, the sequence generator 13 controls the line decoder 11, the driver 15 and the sense amplifier 17 to perform various operations including data reading, data writing and data erasure.
[0034] The voltage generation circuit 14 is a circuit that generates multiple voltages of different magnitudes. The voltage generation circuit 14 receives a power supply voltage from an external source of the storage device 1 and generates multiple voltages from the power supply voltage. The voltage generation circuit 14 supplies the generated voltages to components such as the storage cell array 10, the driver 15, and the sense amplifier 17.
[0035] The driver 15 is a circuit that applies various voltages required for the operation of the storage device 1 to some of its components. The driver 15 receives multiple voltages from the voltage generation circuit 14 and supplies a selected voltage from the multiple voltages to one or more line decoders 11.
[0036] The sense amplifier 17 is a circuit that outputs a signal based on data stored in the memory cell array 10. The sense amplifier 17 senses the state of the memory cell transistor MT and generates read data based on the sensed state. The sense amplifier 17 applies a voltage based on the write data to the bit line BL.
[0037] Figure 2 This describes the constituent elements of a block in the semiconductor device of the first embodiment and the connections between these constituent elements. Multiple blocks BLK, for example, all blocks BLK, are included. Figure 2 The constituent elements and connections are shown.
[0038] A block BLK contains multiple string components SU. Figure 2 This represents an example of 5 string components SU_0 to SU_4.
[0039] like Figure 2 As shown, m bit lines BL_0 to BL_m-1 are connected to one NAND string NS from each of the string components SU_0 to SU_4 in each block BLK. m is a positive integer.
[0040] Each NAND string NS contains one select-gate transistor ST, n memory cell transistors MT (MT_0 to MT_n-1), and one select-gate transistor DT (DT_0, DT_1, DT_2, DT_3, or DT_4). n is a positive integer. The memory cell transistor MT is a device that functions as a memory cell and non-volatilely stores data. The memory cell transistor MT includes a control gate electrode or gate electrode (word line WL) and a charge accumulation film insulated from the surroundings, and stores data non-volatilely based on the charge in the charge accumulation film. Data is written to the memory cell transistor MT by injecting electrons into the charge accumulation film.
[0041] The select gate transistor ST, the memory cell transistors MT_0 to MT_n-1, and the select gate transistor DT are connected in series between the source line SL and one bit line BL.
[0042] Multiple NAND strings NS connected to different bit lines BL constitute a string assembly SU. In each string assembly SU, the control gate electrodes of memory cell transistors MT_0 to MT_n-1 are connected to word lines WL_0 to WL_n-1 respectively. The group of memory cell transistors MT that share word line WL in a string assembly SU is called a cell assembly CU.
[0043] Gate transistors DT_0 to DT_4 are selected to belong to string components SU_0 to SU_4, respectively. Figure 2 The diagrams of select gate transistors DT_2, DT_3, and DT_4 are omitted. The gates of the select gate transistors DT0 for each of the multiple NAND strings NS in string assembly SU_0 are connected to the select gate line SGDL_0. Similarly, the gates of the select gate transistors DT_1, DT_2, DT_3, and DT_4 for each of the multiple NAND strings NS in string assemblies SU_1, SU_2, SU_3, and SU_4 are connected to the select gate lines SGDL_1, SGDL_2, SGDL_3, and SGDL_4, respectively.
[0044] The gate of the select gate transistor ST is connected to the select gate line SGSL.
[0045] Figure 3 This shows the appearance of the semiconductor device according to the first embodiment. For example... Figure 3 As shown, the storage device 1 includes a first structure 100, a second structure 200, and a third structure 300. The first structure 100, the second structure 200, and the third structure 300 extend along the xy plane and are arranged in the Z direction. The second structure 200 is located on the Z-direction side (upper surface) of the first structure 100. The third structure 300 is located on the upper surface of the second structure 200.
[0046] The first structure 100, the second structure 200, and the third structure 300 each include a plurality of semiconductors, a plurality of various conductors, and a plurality of insulators formed on a substrate using a substrate. The first structure 100, the second structure 200, and the third structure 300 each include a plurality of components and wiring implemented from the semiconductors, conductors, and insulators. The first structure 100, the second structure 200, and the third structure 300 each include an electrical circuit containing components and wiring. The components and wiring in the first structure 100, the second structure 200, and the third structure 300 are electrically connected to each other.
[0047] The first structure 100 and the second structure 200 include a line decoder 11, a register 12, a sequence generator 13, a voltage generation circuit 14, a driver 15, and a sense amplifier 17. The first structure 100 may include any of the following components: the line decoder 11, the register 12, the sequence generator 13, the voltage generation circuit 14, the driver 15, and the sense amplifier 17. The second structure 200 may include any of the following components: the line decoder 11, the register 12, the sequence generator 13, the voltage generation circuit 14, the driver 15, and the sense amplifier 17.
[0048] The third structure 300 includes a memory cell array 10 and multiple external connection terminals PD. The external connection terminals PD are exposed on the upper surface of the third structure 300.
[0049] Figure 4 An example showing the structure of a portion of the surface of the semiconductor device according to the first embodiment. Figure 4 Shown in decomposition Figure 3 The structure.
[0050] like Figure 4 As shown, the first structure 100 includes a plurality of conductive connection terminals BP1. The connection terminals BP1 are exposed in the Z-direction side (upper surface) of the first structure 100. The connection terminals BP1 are connected to the components in the first structure 100.
[0051] The second structure 200 includes multiple conductive connection terminals BP2L and multiple conductive connection terminals BP2U. The connection terminals BP2L are exposed in the -Z direction side (lower surface) of the second structure 200. The connection terminals BP2L are connected to components in the second structure 200. The connection terminals BP2L have the same layout as the connection terminals BP1 of the first structure 100. The connection terminals BP2L are arranged such that when the first structure 100 and the second structure 200 are joined, each connection terminal BP2L is connected to one connection terminal BP1 of the first structure 100 that corresponds to that connection terminal BP2L. A specific connection terminal BP2L and the one connection terminal BP1 of the first structure 100 that corresponds to that specific connection terminal BP2L are elements that function as the same node in the circuit.
[0052] The engagement terminal BP2U is exposed in the upper surface of the second structure 200. The engagement terminal BP2U is connected to the components in the second structure 200.
[0053] The third structure 300 includes a plurality of conductive connection terminals BP3. The connection terminals BP3 are exposed in the lower surface of the third structure 300. The connection terminals BP3 are connected to components in the third structure 300. The connection terminals BP3 have the same layout as the connection terminals BP2U of the second structure 200. The connection terminals BP3 are arranged such that when the second structure 200 and the third structure 300 are joined, each connection terminal BP3 is connected to one corresponding connection terminal BP2U of the connection terminals BP2U in the second structure 200. A particular connection terminal BP3, the connection terminal BP2U in the second structure 200, and the one corresponding connection terminal BP2U are elements that function as the same node in the circuit.
[0054] Figure 5 An example showing a partial cross-section of the semiconductor device according to the first embodiment. For example... Figure 5 As shown, the first structure 100 further includes a substrate W1, a transistor Tr1, contacts CS1, C0, C1, C2 and C3, conductors L0, L1 and L2, and insulators 21 and 22. In the following description, the conductors further comprise semiconductors that are conductive by containing impurities. In one example, the substrate W1 comprises silicon. In one example, the contacts CS1, C0, C1, C2 and C3, and the conductors L0, L1 and L2 comprise copper (Cu), aluminum (Al), or tungsten (W). In one example, the insulators 21 and 22 comprise silicon oxide.
[0055] Transistor Tr1 is located in the region above and near the upper surface of substrate W1. Transistor Tr1 includes a gate insulator on the upper surface of substrate W1, a gate electrode on the upper surface of the gate insulator, and a pair of source / drain regions sandwiching the lower region of the gate electrode.
[0056] Each contact C0 is located on the lower surface and is connected to the upper surface of the gate electrode of a transistor Tr1. Each contact CS1 is located on the lower surface and is connected to a source / drain region.
[0057] Each conductor L0 is located on the lower surface and connected to one contact C0 or CS1. Each contact C1 is located on the lower surface and connected to the upper surface of one conductor L0.
[0058] Each conductor L1 is located on the lower surface and is connected to the upper surface of one contact C1. Each contact C2 is located on the lower surface and is connected to the upper surface of one conductor L1.
[0059] Each conductor L2 is located on the lower surface and is connected to the upper surface of one contact C2. Each contact C3 is located on the lower surface and is connected to the upper surface of one conductor L2.
[0060] The transistor Tr1, contacts CS1, C0, C1, C2 and C3, and conductors L0, L1 and L2 form the circuit included in the first structure 100. Therefore, the first structure 100 has transistors Tr1, contacts CS1, C0, C1, C2 and C3, and conductors L0, L1 and L2 of arbitrary shape and configuration that implement the circuit included in the first structure 100.
[0061] The insulator 21 extends from the height of the upper surface of the substrate W1 to the height of the upper surface of the contact C3. The insulator 21 fills the area in the first structure 100 where no constituent elements are provided, that is, the area where transistor Tr1, contacts CS1, C0, C1, C2 and C3, and conductors L0, L1 and L2 are not provided.
[0062] Each mating terminal BP1 is located on the lower surface and is connected to the upper surface of one contact C3. The insulator 22 fills the area in the layer where the mating terminal BP1 is located that is not provided with a mating terminal BP1.
[0063] The second structure 200 further includes a substrate W2, a transistor Tr2, contacts CS2, CS5, C4, C5, C7, C8, C9 and C10, conductors L3, L4, L5 and L6, and insulators 24, 25, 26 and 27. In one example, the substrate W2 comprises silicon. In one example, the contacts CS2, CS5, C4, C5, C7, C8, C9 and C10, and the conductors L3, L4, L5 and L6 comprise copper, aluminum, or tungsten. In one example, the insulators 24, 25, 26 and 27 comprise silicon oxide.
[0064] Each bonding terminal BP2L is located in the bottom layer of the second structure 200. The insulator 24 fills the area in the layer where the bonding terminal BP2L is located that does not have a bonding terminal BP2L.
[0065] Each contact C4 is located on the lower surface and is connected to the upper surface of a mating terminal BP2L.
[0066] Each conductor L3 is located on its lower surface and connected to the upper surface of one contact C4. Each contact C5 is located on its lower surface and connected to the upper surface of one conductor L3. Conductors L3 are electrically connected to the voltage generating circuit 14 and receive a higher positive voltage.
[0067] The insulator 25 extends from the upper surface of the junction terminal BP2L and the upper surface of the insulator 24 to the upper surface of the contact C5. The insulator 25 fills the area above the junction terminal BP2L and the insulator 24 where the contacts C4 and C5 are not located, as well as the area of the conductor L3.
[0068] Substrate W2 is located on the upper surface of insulator 25. Vias TS span both the upper and lower surfaces of substrate W2 and penetrate it. Each via TS is located on the lower surface and connects to the upper surface of a contact C5. Insulators SP span both the upper and lower surfaces of substrate W2 and penetrate it. Each insulator SP covers the side of one via TS.
[0069] Transistor Tr2 is located in the region above and near the upper surface of substrate W2. Transistor Tr2 includes a gate insulator on the upper surface of substrate W2, a gate electrode on the upper surface of the gate insulator, and a pair of source / drain regions sandwiching the lower region of the gate electrode.
[0070] Each contact C7 is located on the lower surface and is connected to the upper surface of the gate electrode of a transistor Tr2. Each contact CS2 is located on the lower surface and is connected to a source / drain region. Each contact CS5 is located on the lower surface and is connected to the upper surface of a via TS.
[0071] Each conductor L4 is located on its lower surface and is connected to the upper surface of one contact C7, CS2, or CS5. Each contact C8 is located on its lower surface and is connected to the upper surface of one conductor L4.
[0072] Each conductor L5 is located on the lower surface and is connected to the upper surface of one contact C8. Each contact C9 is located on the lower surface and is connected to the upper surface of one conductor L5.
[0073] Each conductor L6 is located on the lower surface and is connected to the upper surface of one contact C9. Each contact C10 is located on the lower surface and is connected to the upper surface of one conductor L6.
[0074] The transistor Tr2, contacts CS2, CS5, C4, C5, C7, C8, C9 and C10, and conductors L3, L4, L5 and L6 together implement the circuit included in the second structure 200. Therefore, the second structure 200 has transistors Tr2, contacts CS2, CS5, C4, C5, C7, C8, C9 and C10, and conductors L3, L4, L5 and L6 of arbitrary shape and configuration to implement the circuit included in the second structure 200.
[0075] The insulator 26 extends from the height of the upper surface of the substrate W2 to the height of the upper surface of the contact C10. The insulator 26 fills the area from the height of the upper surface of the substrate W2 to the height of the upper surface of the contact C10 where no constituent elements are provided, that is, the area where transistor Tr2, contacts CS2, C7, C8, C9 and C10, and conductors L4, L5 and L6 are not provided.
[0076] Each mating terminal BP2U is located on the lower surface and is connected to the upper surface of one contact C10. The insulator 27 fills the area in the layer where the mating terminal BP2U is located that is not provided with a mating terminal BP2U.
[0077] The third structure 300 also includes contacts C11, C12 and C13, conductors L7, L8, 31, 33, 36 and 38, insulators 29, 32, 34, 35, 37, 40 and 41, and memory pillar MP.
[0078] Each bonding terminal BP3 is located in the lowest layer of the third structure 300. The insulator 29 fills the area in the layer where the bonding terminal BP3 is located that does not have a bonding terminal BP3.
[0079] Each contact C11 is located on the lower surface and is connected to the upper surface of a mating terminal BP3.
[0080] Each conductor L7 is located on the lower surface and is connected to the upper surface of one contact C11. Each contact C12 is located on the lower surface and is connected to the upper surface of one conductor L7.
[0081] Each conductor L8 is located on the lower surface and is connected to the upper surface of a contact C12.
[0082] Conductor 31 is located above conductor L8. Conductor 31 has a plate-like shape along the xy plane. Conductor 31 functions as at least a part of the select gate line SGDL. The lower surface of conductor 31 is exposed at its end and has a stepped shape.
[0083] Insulator 32 is located on the upper surface of conductor 31. Insulator 32 has a plate-like shape along the xy plane.
[0084] Conductors 33 and insulators 34 are alternately deposited on the upper surface of insulator 32. Conductors 33 and insulators 34 have a plate-like shape along the xy plane. Each conductor 33 functions as at least a part of the word line WL. Figure 5 An example with n=8 is shown, where n is the number of memory cell transistors MT. Conductors 33, from bottom to top, function as at least a portion of word lines WL_0, WL_1, WL_2, WL_3, WL_4, WL_5, WL_6, and WL_7. The lower surface of each conductor 33 is exposed at its end and has a stepped design.
[0085] The insulator 35 is located on the upper surface of the uppermost conductor 33.
[0086] Conductor 36 is located on the upper surface of insulator 35. Conductor 36 functions as at least a part of the select gate line SGSL.
[0087] Insulator 37 is located on the upper surface of conductor 36. Conductor 38 is located on the upper surface of insulator 37. The lower surface of conductor 38 is exposed at its end and has a stepped design.
[0088] Memory pillars MP extend along the z-axis and penetrate the group of conductors 31, 33, and 36, and insulators 32, 34, 35, and 37. Each memory pillar MP includes an insulator CI, a semiconductor SM, and a stacked body SS. The semiconductor SM covers the sidewalls of the insulator CI. The stacked body SS covers the sidewalls of the semiconductor SM. The stacked body SS has an opening at the top end of the memory pillar MP. A portion of the semiconductor SM is located in the opening and is in contact with conductor 38 on its upper surface.
[0089] Alternatively, the upper part of the memory column MP is located in the conductor 38, the stack SS has an opening in the part facing the conductor 38, and a part of the semiconductor SM is located in the opening.
[0090] The portion of each memory column MP facing conductor 31 functions as a select gate transistor DT. The portion of each memory column MP facing conductor 33 functions as a memory cell transistor MT. The portion of each memory column MP facing conductor 36 functions as a select gate transistor ST. The lower surface of the semiconductor SM is exposed in the lower surface of each memory column MP.
[0091] Each contact C13 is located on the lower surface and is connected to the upper surface of a conductor L8. Some contacts C13 are located on the upper surface and are connected to the lower surface of a semiconductor SM of a memory pillar MP. Some contacts C13 are located on the upper surface and are connected to the lower surface of a stepped portion of one of the conductors 31, 33, and 36.
[0092] The insulator 40 extends from the height of the upper surface of the insulator 29 to the height of the upper surface of the conductor 38. The insulator 40 fills the area in the third structure 300 where no constituent elements are provided, that is, the area where contacts C11, C12 and C13, conductors L7, L8, 31, 33, 36, 38, insulators 40, 32, 34, 35, 37, and memory pillar MP are not provided.
[0093] Insulator 41 is located on the upper surface of conductor 38 and insulator 40 respectively.
[0094] Figure 6 An example showing the structure of a cross-section along the xy plane of the memory pillar of the semiconductor device of the first embodiment. For example... Figure 6 As shown, in one example, the stack SS comprises a tunnel insulator TI, a charge storage membrane CA, and a barrier insulator BI.
[0095] The tunnel insulator TI surrounds the sides of the semiconductor SM. The charge storage film CA surrounds the sides of the tunnel insulator TI. The barrier insulator BI surrounds the sides of the charge storage film CA. Conductors 31, 33, or 36 surround the sides of the barrier insulator BI.
[0096] The semiconductor SM functions as a channel (current path) for the memory cell transistor MT and the select gate transistors DT and ST. In one example, the tunnel insulator TI and the barrier insulator BI are both made of silicon oxide. The charge storage film CA stores charge. In one example, the charge storage film CA is made of silicon nitride.
[0097] Figure 7 This shows a partial structure of the semiconductor device according to the first embodiment. Figure 7 This section details the substrate W2 and its surrounding structure.
[0098] like Figure 7 As shown, the second structure 200 also includes structure STI, n-well region nw, p-well region pw and impurity region DA. Figure 7 Only one p-well region pw is shown, but more than two p-well regions pw are set.
[0099] The substrate W2 contains p-type impurities. An example of a p-type impurity is boron (B).
[0100] The STI structure isolates the component and contains an insulator, having a structure based on STI (Shallow Trench Isolation). The STI structure is located in the region containing the upper surface of the substrate W2. The STI structure extends downward from the upper surface of the substrate W2. In one example, the STI structure contains silicon oxide.
[0101] The n-well region nw is located between two adjacent structural STIs. The n-well region nw extends from the upper surface of substrate W2 to the lower surface. The n-well region nw contains n-type impurities. Examples of n-type impurities include phosphorus (P) and arsenic (As).
[0102] The p-well region pw is located between two adjacent structural STIs. The p-well region pw extends from the upper surface to the lower surface of the substrate W2. The p-well region pw contains p-type impurities. In one example, the p-well region pw contains a concentration of 1 × 10⁻⁶ impurities in the region including the boundary with insulator 25. 14 [atoms / cm 3 ] Above 2×10 16 [atoms / cm 3 The following are p-type impurities. In one example, the impurity concentration is the average concentration.
[0103] Transistor Tr2 includes p-type transistor Tr2_p and n-type transistor Tr2_n.
[0104] Transistor Tr2_p is located between two adjacent STI structures. Transistor Tr2_p is situated within and above the n-well region nw. Transistor Tr2_p includes a gate insulator GO, a gate electrode GC, and a pair of source / drain regions SD_p. The gate insulator GO is located on the upper surface of the substrate W2. In one example, the gate insulator GO comprises silicon oxide. The gate electrode GC is located on the upper surface of the gate insulator GO. In one example, the gate electrode GC comprises polysilicon that has become conductive by introducing impurities. The source / drain regions SD_p sandwich the lower portion of the gate electrode GC within the region encompassing the upper surface of the substrate W2. The source / drain regions SD_p contain p-type impurities.
[0105] Transistor Tr2_n is located between two adjacent structures STI. Transistor Tr2_n is situated within and above the p-well region pw. Transistor Tr2_n includes a gate insulator GO, a gate electrode GC, and a pair of source / drain regions SD_n. The source / drain regions SD_n sandwich the portion below the gate electrode GC in the region containing the upper surface of the substrate W2. The source / drain regions SD_n contain n-type impurities.
[0106] Each impurity region DA is located below one structure STI in substrate W2. Impurity region DA is in contact with the lower surface of structure STI and reaches the lower surface of substrate W2. Impurity region DA is in contact with two adjacent regions in n-well region nw and p-well region pw, and these two adjacent regions are electrically separated. Impurity region DA contains p-type impurities. An example of p-type impurities is boron. Impurity region DA is formed separately from p-well region pw by ion implantation or the like. Therefore, impurity region DA has a higher impurity concentration than p-well region pw, and a higher p-type impurity concentration than the p-type impurity concentration that should be present in the location region of impurity region DA formed by the diffusion of p-type impurities in p-well region pw without the formation of impurity region DA. In one example, impurity region DA contains a concentration of 1 × 10⁻⁶. 16 [atoms / cm 3 ] Above 3×10 18 [atoms / cm 3 The following are p-type impurities. In one example, the impurity region DA, in the region encompassing the boundary with insulator 25, contains a concentration of 8 × 10⁻⁶. 16 [atoms / cm 3 ] Above 1×10 22 [atoms / cm 3 The following are p-type impurities. In one example, the p-type impurity concentration in impurity region DA is more than 4 times (1×10) times the p-type impurity concentration in p-well region pw. 8 Less than twice.
[0107] Contacts CS2, CS5, and C7, as well as structure STI, have a tapered shape. The tapered components have a larger area at the upper end than at the lower end; in one example, the area decreases from the upper end to the lower end (area along the xy plane). That is, contacts CS2, CS5, and C7, as well as structure STI, have a larger area at the Z-direction end than at the -Z-direction end.
[0108] The through-hole TS, insulator SP, and contact C5 have an inverted conical shape. The components with the inverted conical shape have a smaller area at the upper end than at the lower end; in one example, the area increases from the upper end to the lower end. That is, the through-hole TS, insulator SP, and contact C5 have a smaller area at the Z-direction side end than at the -Z-direction side end.
[0109] The p-well region pw, together with another p-well region pw (not shown), encloses an n-well region nw.
[0110] 1.2. Manufacturing Method
[0111] The manufacturing process of storage device 1 includes: a process of manufacturing the first structure 100, the second structure 200, and the third structure 300 using separate processes; and a process of bonding the manufactured first structure 100, second structure 200, and third structure 300 together. Hereinafter, the manufacturing method of the second structure 200 will be described.
[0112] 1.2.1. Example 1 of the manufacturing method of the second structure
[0113] Figures 8 to 14 An example of the state during manufacturing of the first example of the second structure of the semiconductor device of the first embodiment.
[0114] like Figure 8 As shown, an n-well region nwA and a p-well region pwA are formed in substrate W2A. Substrate W2A is an element that will become substrate W2 through subsequent processes. The n-well region nwA includes the n-well region nw and is also located in the predetermined region where the impurity region DA is to be formed. The p-well region pwA includes the p-well region pw and is also located in the predetermined region where the impurity region DA is to be formed.
[0115] Alternatively, either the n-well region (nwA) or the p-well region (pwA) can be formed first. Examples of methods for forming the n-well region (nwA) and the p-well region (pwA) include ion implantation using a mask.
[0116] like Figure 9 As shown, source / drain regions SDA_n and SDA_p are formed in substrate W2A. Source / drain region SDA_n includes source / drain region SD_n and is also located in a predetermined region where impurity region DA is to be formed. Source / drain region SDA_p includes source / drain region SD_p and is also located in a predetermined region where impurity region DA is to be formed.
[0117] Alternatively, either the source / drain regions SDA_n or SDA_p can be formed first. Examples of methods for forming the source / drain regions SDA_n and SDA_p include ion implantation using a mask.
[0118] like Figure 10As shown, trench 51 is formed. Trench 51 occupies a predetermined area where the STI structure is to be formed. An example of the formation method includes a combination of photolithography and anisotropic etching, where RIE (Reactive Ion Etching) is an example of anisotropic etching. Specifically, a mask 52 is formed on the upper surface of the substrate W2A. The mask 52 has an opening above the predetermined area where the STI structure is to be formed, exposing the upper surface of the substrate W2A in the opening. Then, by anisotropic etching of the mask 52, trench 51 is formed below the opening of the mask 52. By forming trench 51, the n-well region nwA becomes the n-well region nw, and the p-well region pwA becomes the p-well region pw. Furthermore, by forming trench 51, the source / drain region SDA_n becomes the source / drain region SD_n, and the source / drain region SDA_p becomes the source / drain region SD_p.
[0119] like Figure 11 As shown, an impurity region DA is formed. That is, the impurity region DA is formed below the trench 51 in the substrate W2A by ion implantation into the mask 52. The implanted ions contain the impurity elements contained in the impurity region DA.
[0120] like Figure 12 As shown, the structure STI, gate insulator GO, gate electrode GC, sidewall insulator SW, insulator 26, and contacts CS2, CS5, and C7 are formed. That is, firstly, the material of the structure STI is deposited in trench 51. Examples of deposition methods include CVD (Chemical Vapor Deposition).
[0121] A gate insulator (GO), a gate electrode (GC), and a sidewall insulator (SW) are formed. Examples of methods for forming the gate insulator (GO) include thermal oxidation. Examples of methods for forming the gate electrode (GC) include CVD, photolithography, and anisotropic etching. Examples of methods for forming the sidewall insulator (SW) include CVD, photolithography, and anisotropic etching.
[0122] An insulator 26 is formed on the upper surface of the structure obtained through the processes up to this point. Examples of formation methods include CVD.
[0123] Contacts CS2, CS5, and CS7 are formed. Examples of formation methods include photolithography and anisotropic etching, as well as CVD.
[0124] Next, it forms Figure 5 The contacts C8, C9 and C10, conductors L4, L5 and L6, insulator 27, and mating terminal BP2U (not shown) are shown.
[0125] like Figure 13 As shown, the structure obtained through the processes up to this point is inverted relative to the xy plane. Regarding... Figure 13 and Figure 14 In the description, "upper surface" refers to the surface on the -Z direction side.
[0126] The upper surface of substrate W2A is removed by CMP (Chemical Mechanical Polishing). This thins substrate W2A, resulting in substrate W2. CMP is performed until the impurity region DA is exposed.
[0127] On the upper surface of the substrate W2, a portion of the insulator 25 is formed. Examples of formation methods include CVD.
[0128] Forming vias (TS) and insulators (SP). Examples of formation methods include photolithography and anisotropic etching, as well as CVD.
[0129] like Figure 14 As shown, the remaining portion of insulator 25, contact C5, and conductor L3 are formed. Examples of formation methods include photolithography and anisotropic etching, as well as CVD.
[0130] Next, it forms Figure 5 The contact C4, insulator 24, and terminal BP1 are shown.
[0131] 1.2.2. Second example of the manufacturing method of the second structure
[0132] Figure 15 This is an example showing the state during manufacturing of a second example of the second structure of the semiconductor device according to the first embodiment. (See also...) Figure 15 The described procedures are attached to the reference. Figure 9 After the aforementioned process.
[0133] like Figure 15 As shown, by reference Figure 9 A mask 54 is formed on the upper surface of the structure obtained by the process. The mask 54 has an opening above a predetermined area where the impurity region DA is to be formed.
[0134] An impurity region DAA is formed below the opening of mask 54 in substrate W2A by ion implantation. The impurity region DAA extends from the upper surface of substrate W2A to the lower end of the predetermined region where the impurity region DAA is to be formed.
[0135] like Figure 11 As shown, trench 51 is formed. That is, mask 54 is removed to form mask 52, which is then compared with the reference. Figure 10Similarly, in the same process, a groove 51 is formed below the opening of mask 52. Mask 52 can also be the same as mask 54. Subsequent processes are the same as in the first example.
[0136] 1.3. Advantages (Effects)
[0137] According to the first embodiment, as described below, a storage device that suppresses leakage current is provided.
[0138] As a reference structure for comparison, a structure that does not include the impurity region DA of the first embodiment is considered. This structure includes, for example... Figure 10 The p-well region pwA and n-well region nwA shown here replace the p-well region pw and n-well region nw of the first embodiment, respectively. Two adjacent regions in the n-well region nwA, p-well region pwA, and n-well region nwA are adjacent to each other. In the reference structure, when a positive high voltage is applied to the conductor L3, an inversion layer is formed in the p-well region pwA. That is, due to the electric field caused by the positive high voltage, electrons concentrate in the portion of the p-well region pwA facing the conductor L3, forming an n-type region. The n-type region makes the n-well regions nw on both sides electrically conductive. As a result, leakage current flows between the n-well regions nwA via the n-type region.
[0139] If the conductor L3 is close to the p-well region pwA, electrons are more easily concentrated. The distance between the conductor L3 and the p-well region pwA depends on the thickness of the substrate W2 (especially the distance between the lower end of the p-well region pwA and the lower end of the substrate W2) and the thickness of the insulator 25. To achieve high-density vias TS, a small depth-to-width ratio of the vias TS is desirable; therefore, it is ideal for the substrate W2 and the insulator 25 to be relatively thin. By thinning the substrate W2, the lower end of the p-well region pw coincides with the lower end of the substrate W2, resulting in a smaller distance between the conductor L3 and the p-well region pw.
[0140] The storage device 1 of the first embodiment includes an n-well region nw and a p-well region pw side by side, and a p-type impurity region DA between the n-well region nw and the p-well region pw. The impurity region DA has a higher impurity concentration than the p-well region pw. Therefore, even when a positive high voltage is applied to the conductor L3, it is more difficult to form an n-type region in the region facing the conductor L3 in the impurity region DA than in the region facing the conductor L3 in the p-well region pw. Therefore, even if an n-type region is formed in the p-well region pw by applying a positive high voltage to the conductor L3, the impurity region DA will suppress the electrical connection between the two n-well regions nw through the n-type region in the p-well region pw. Therefore, leakage current between the n-well regions nw is suppressed.
[0141] 1.4. Variation Example
[0142] The descriptions so far have described an example where the impurity region DA contains a higher concentration of p-type impurities than the p-well region pw. The impurity region DA can also contain a higher concentration of n-type impurities than the n-well region nw. Following the same mechanism as leakage current generation by forming an n-type region in the p-well region pw, leakage current can be generated by forming a p-type region in the n-well region nw. That is, by applying a negative high voltage to the conductor L3, a p-type region is formed in the n-well region nw, which electrically conducts to the p-well regions pw on both sides.
[0143] Even in this case, leakage current can be suppressed using the first embodiment. That is, because the impurity region DA contains a higher concentration of n-type impurities than the n-well region nw, even when a negative high voltage is applied to the conductor L3, it is difficult for a p-type region to form in the region of the impurity region DA facing the conductor L3. Therefore, even if a p-type region is formed in the n-well region nw by applying a negative high voltage to the conductor L3, the impurity region DA will suppress the electrical connection between the two p-well regions pw through the p-type region in the n-well region nw.
[0144] The conductor L3 may also be located in the first structure 100, the conductor L3 facing the p-well region pw and capable of generating an n-type region in the p-well region pw by applying a positive high voltage. Figure 16 This example illustrates a partial cross-sectional structure of the storage device of a variation of the first embodiment. Figure 16 It shows the relationship with Figure 5 The same area shown.
[0145] like Figure 16 As shown, the second structure 200 does not include the conductor L3 and the contact C4. On the other hand, the third structure 300 also includes the conductor L10 and the contact C15.
[0146] Contact C5 is located on the lower surface and connects to the upper surface of the mating terminal BP2L. Contact C3 is located on the upper surface and connects to the lower surface of a conductor L10. Contact C15 is located on the lower surface and connects to the upper surface of a conductor L10. Contact C15 is located on the upper surface and connects to the lower surface of a mating terminal BP1. Conductor L10, like conductor L3, is capable of receiving either a positive or negative high voltage.
[0147] According to the modified structure, similarly, if the thickness of the insulator 25 and the thickness of the portion of the insulator 21 above the upper surface of the conductor L10 are thinner, then an n-type region will be formed in the p-well region pw, and a p-type region will be formed in the n-well region nw. By setting the impurity region DA, leakage current caused by the formed n-type or p-type regions is suppressed.
[0148] The description up to this point is based on the example of a memory device using the semiconductor device of the first embodiment. The first embodiment can be applied to structures like the first structure 100 and the second structure 200, which are interconnected and include transistor Tr2 and conductor L3 (or L10). Examples of other semiconductor devices include image sensors and integrated circuits (ICs). In this case, the third structure 300 is not provided. Several embodiments of the invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and likewise included in the scope of the invention as set forth in the claims and its equivalents.
[0149] [Explanation of Symbols]
[0150] 100: Structure 1
[0151] 200: Structure 2
[0152] 300: Third Structure
[0153] BP1, BP2L, BP2U: bonding terminals
[0154] W1, W2, W3: Substrates
[0155] Tr1, Tr2: Transistors
[0156] CS1, CS2, CS5, C0, C1, C2, C3, C4, C5, C7, C8, C9, C10, C11, C12, C13: Contacts
[0157] L0, L1, L2, L3, L4, L5, L6, L7, L8, 31, 33, 36, 38: Conductors; 21, 22, 24, 25, 26, 27, 29, 32, 34, 35, 37, 40, 41: Insulators
[0158] nw: n-well region
[0159] pw: p-well region
[0160] DA: Impurity region.
Claims
1. A semiconductor device comprising: First substrate; The first insulator is located in a first direction further than the first substrate; The first conductor in the first insulator; The second substrate is located further along the first direction than the first insulator; A first well region having a first conductivity type is disposed in the second substrate and having a first impurity concentration; The first impurity region, having the first conductivity type, is connected to the first well region in the second substrate in a second direction further than the first well region, and has a first impurity concentration of at least 4 times (1×10⁻⁶). 8 The concentration of the second impurity is less than twice that of the first impurity; and The second well region, having a second conductivity type, is in contact with the first impurity region in the second substrate in a second direction more closely than the first impurity region.
2. The semiconductor device according to claim 1, wherein The first well region, the second well region, and the first impurity region are in contact with the first insulator.
3. The semiconductor device according to claim 1, wherein The first conductor and the first well region are arranged in the first direction.
4. The semiconductor device according to claim 1, further comprising a first transistor, The first transistor includes a source / drain region in the first well region and a gate electrode located further in the first direction than the first well region.
5. The semiconductor device according to claim 1, further comprising a second conductor. The second conductor penetrates the second substrate in the first direction.
6. The semiconductor device according to claim 5, wherein The second conductor is located further along the second direction than the second well region and is electrically connected to the first conductor.
7. The semiconductor device according to claim 1, wherein The first well region has the first impurity concentration at its end on the first direction side. The first impurity region has the second impurity concentration at its end on the first direction side.
8. The semiconductor device according to claim 1, wherein The first conductivity type is p-type. The first well region and the first impurity region contain boron (B). The second conductivity type is n-type. The second well region contains either phosphorus (P) or arsenic (As).
9. The semiconductor device according to claim 1, wherein The first conductivity type is n-type. The first well region and the first impurity region contain phosphorus (P) or arsenic (As). The second conductivity type is p-type. The second well region contains boron (B).
10. The semiconductor device according to claim 1, further comprising: A second impurity region, having the first conductivity type, is connected to the first well region in the second substrate in a third direction opposite to the second direction, and has the second impurity concentration; and The third well region, having a second conductivity type, is in contact with the second impurity region in the second substrate in the third direction, which is closer to the second impurity region than the second impurity region.
11. The semiconductor device of claim 10, wherein The first well region, the second well region, the third well region, and the first impurity region are in contact with the first insulator.
12. The semiconductor device of claim 10, wherein The first conductor and the first well region are arranged in the first direction.
13. The semiconductor device of claim 10, further comprising a first transistor, The first transistor includes a source / drain region in the first well region and a gate electrode located further in the first direction than the first well region.
14. The semiconductor device according to claim 10, further comprising a second conductor. The second conductor penetrates the second substrate in the first direction.
15. The semiconductor device of claim 14, wherein The second conductor is located further along the second direction than the second well region and is electrically connected to the first conductor.
16. The semiconductor device of claim 10, wherein The first well region has the first impurity concentration at its end on the first direction side. The first impurity region and the second impurity region are respectively located at the ends on the first direction side, and have the second impurity concentration.
17. The semiconductor device of claim 10, wherein The first conductivity type is p-type. The first well region and the first impurity region contain boron (B). The second conductivity type is n-type. The second and third well regions contain phosphorus (P) or arsenic (As).
18. The semiconductor device of claim 10, wherein The first conductivity type is n-type. The first well region and the first impurity region contain phosphorus (P) or arsenic (As). The second conductivity type is p-type. The second and third well regions contain boron (B).
19. The semiconductor device of claim 1, wherein The first insulator includes the second insulator and the third insulator. The semiconductor device further includes a third conductor in the second insulator and a fourth conductor in the third insulator. The third conductor is connected to the fourth conductor. The first conductor is located within the third insulator.
20. The semiconductor device of claim 1, wherein The first insulator includes the second insulator and the third insulator. The semiconductor device further includes a third conductor in the second insulator and a fourth conductor in the third insulator. The third conductor is connected to the fourth conductor. The first conductor is located within the second insulator.