Memory array and method for forming memory circuitry

Abstract

The invention relates to a memory array and a method for forming memory circuitry. A memory array is provided that includes a stack including vertically alternating insulating layers and conductive layers. The channel material strings extend through the insulating layer and the conductive layer and are arranged in sets spaced apart from each other in horizontal X and Y directions. The channel material strings in individual ones of the sets are arranged in groups spaced apart from each other in the Y-direction. Individual ones of the groups include a plurality of rows of strings of channel material spaced apart from each other in the Y-direction. A Y-direction distance between immediately adjacent groups is greater than a Y-direction distance between immediately adjacent rows within an individual group. The stack includes memory blocks spaced apart from each other in a Y-direction. Between adjacent memory blocks there are walls extending through the stack and elongated horizontally in the X-direction, through many of the sets and through spaces between individual groups in individual sets. Methods are disclosed.

Description

Technical Field

[0001] The embodiments disclosed herein relate to memory arrays and methods for forming memory circuit systems. Background Technology

[0002] Memory is a type of integrated circuit system used in computer systems to store data. Memory can be manufactured as one or more arrays of individual memory cells. Memory cells can be written to or read from using digital lines (also called bit lines, data lines, or sense lines) and access lines (also called word lines). Sense lines electrically interconnect memory cells along columns of the array, and access lines electrically interconnect memory cells along rows of the array. Each memory cell is uniquely addressed by a combination of sense lines and access lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods without power. Non-volatile memory is typically specified as memory with a retention time of at least approximately 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory can have retention times of milliseconds or less. In any case, memory cells are configured to retain or store memory in at least two different optional states. In binary systems, states are considered to be "0" or "1". In other systems, at least some individual memory cells can be configured to store information in more than two levels or states.

[0004] Field-effect transistors (FETs) are a type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semi-conductive channel region therebetween. A conductive gate is adjacent to the channel region and separated from the channel region by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow through the channel region from one of the source / drain regions to the other. When the voltage is removed from the gate, current flow through the channel region is greatly prevented. FETs may also include additional structures, such as a reversible programmable charge storage region as part of the gate construction between the gate insulator and the conductive gate.

[0005] Flash memory is a type of memory widely used in modern computers and devices. For example, modern personal computers store the BIOS on flash memory chips. As another example, it is increasingly common for computers and other devices to use flash memory, in the form of solid-state drives, instead of traditional hard disk drives. As yet another example, flash memory is prevalent in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized, and allows manufacturers to provide the ability to remotely upgrade devices for enhanced features.

[0006] NAND can be a basic architecture for integrated flash memory. A NAND cell unit includes at least one selection device of a series combination (often referred to as a NAND string) of memory cells coupled in series to them. The NAND architecture can be configured in a three-dimensional arrangement comprising vertically stacked memory cells, each of which individually includes a vertically stacked transistor that can be reversibly programmed. Control circuitry or other circuitry may be formed beneath the vertically stacked memory cells. Other volatile or non-volatile memory array architectures may also include vertically stacked memory cells that individually include transistors.

[0007] Memory arrays can be arranged in memory pages, memory blocks, and portions of blocks (e.g., sub-blocks) and memory planes, as shown and described, for example, in any of U.S. Patent Application Publications Nos. 2015 / 0228651, 2016 / 0267984, and 2017 / 0140833. A memory block may at least partially define the longitudinal profile of individual word lines in individual word line layers of vertically stacked memory cells. Connections to these word lines may occur in a so-called “stepped structure” at the ends or edges of the array of vertically stacked memory cells. The stepped structure includes individual “steps” (alternatively referred to as “steps” or “staircases”) defining contact areas for individual word lines, with vertically extending conductive vias contacting said contact areas to provide electrical access to the word lines. Summary of the Invention

[0008] In one aspect, this disclosure relates to a method for forming a memory circuit system, comprising: forming a stack comprising vertically alternating first and second layers, wherein in the finished circuit system configuration, the first layer is conductive and the second layer is insulating; channel material strings extending through the first and second layers, the channel material strings being arranged into sets spaced apart from each other in horizontal X and Y directions orthogonal to each other; the channel material strings in individual sets being arranged into groups spaced apart from each other in the Y direction; each group comprising a plurality of rows of the channel material strings spaced apart from each other in the Y direction; the Y-direction distance between adjacent groups being greater than the Y-direction distance between adjacent rows within the individual groups; dividing the stack into memory block regions spaced apart from each other in the Y direction; and forming a wall between adjacent memory block regions extending through the stack and horizontally elongating in the X direction, passing through the plurality of sets and through the space between the individual groups in the individual sets.

[0009] In another aspect, this disclosure relates to a method for forming a memory circuit system, comprising: forming a stack comprising vertically alternating first and second layers, the first layer comprising a sacrificial material and the second layer comprising an insulating material having a composition different from that of the sacrificial material; channel material strings extending through the first and second layers; the channel material strings being arranged into sets, the sets being spaced apart from each other in horizontal X and Y directions orthogonal to each other; the channel material strings in individual sets being arranged into groups, the groups being spaced apart from each other in the Y direction; each group comprising a plurality of rows of channel material strings and spaced apart from each other in the Y direction; the Y-direction distance between adjacent groups being greater than the Y-direction distance between adjacent rows within the individual groups; and the individual groups within the individual sets being... An opening is formed in the space through the stack, the opening extending individually in the X direction to expose the sacrificial material to the opening, the opening being formed in those individual sets through which the trench will be formed; through the opening, the sacrificial material is replaced with a conductive material that completely surrounds the individual groups and individual sets in the individual of the first layer; the conductive material extends along the X direction between the openings adjacent to each other in the X direction; the conductive material is sufficiently removed from the opening and in the individual first layer to form the trench extending horizontally in the X direction through the stack, and to form memory blocks spaced apart from each other in the Y direction, the individual in the trench extending through the multiple in the set and through the space between the individual groups in the individual set; and a wall is formed in the individual trench.

[0010] In another aspect, this disclosure relates to a memory array comprising: a stack including vertically alternating insulating and conductive layers; a string of channel material extending through the insulating and conductive layers, the string of channel material arranged in sets spaced apart from each other in horizontal X and Y directions orthogonal to each other, wherein the individual string of channel material in the sets is arranged in groups spaced apart from each other in the Y direction, the individual groups comprising multiple rows of the string of channel material spaced apart from each other in the Y direction, the Y-direction distance between adjacent groups being greater than the Y-direction distance between adjacent rows within the individual groups; and the stack including memory blocks spaced apart from each other in the Y direction, with a wall between adjacent memory blocks extending through the stack and horizontally elongating in the X direction, through the multiple sets and through the space between the individual groups in the individual sets. Attached Figure Description

[0011] Figures 1 to 7This is a schematic cross-sectional view or plan view of a portion of a memory circuit system in a process according to an embodiment of the present invention.

[0012] Figures 8 to 41 for Figures 1 to 7 Diagrammatic cross-sectional views, extended views, magnified views, and / or partial views of the construction of the embodiments and / or alternative embodiments. Detailed Implementation

[0013] Embodiments of the present invention cover methods for forming integrated circuit systems, such as memory circuit systems including memory arrays, which are arrays of NAND or other memory cells (e.g., integrated circuit system components) that may have at least some peripheral control circuitry below the array. Alternatively, and only by way of example, the peripheral control circuitry may be above the array or on one side of the array. Embodiments of the present invention cover so-called “post-gate” or “replacement gate” processes, so-called “gate-before” processes, and other processes, whether existing or developed in the future, that are independent of the formation time of the transistor gate. Embodiments of the present invention also cover integrated circuit systems, for example, including memory arrays (e.g., NAND architectures) comprising strings of memory cells independent of the manufacturing method. Reference Figures 1 to 41 Some exemplary embodiments are described.

[0014] Figures 1 to 7 An exemplary configuration 10 with array 12 is shown, in which a string of memory cells will be formed. The exemplary configuration 10 may include a lowermost substrate (not shown) having any one or more of the following: conductive / conductive / conductive, semiconductive / semiconductor / semiconductive, or insulating / insulator / insulator (i.e., electrically) materials. Various materials may be formed above the substrate. The materials may be... Figures 1 to 7 The material depicted is adjacent to, vertically inward, or vertically outward. For example, components fabricated or fully fabricated in other parts of an integrated circuit system may be disposed above, around, or inside the substrate. Control circuitry systems and / or other peripheral circuitry systems for operating components within a vertically extending string array (e.g., array 12) of memory cells may also be fabricated, and these circuitry systems may be partially or completely within the array or subarrays. Additionally, multiple subarrays may be fabricated and operated independently, sequentially, or otherwise relative to each other. In this document, "subarray" may also be considered as an array.

[0015] Exemplary configuration 10 includes a conductor layer 16, which includes a conductor material 17 (e.g., WSi beneath conductive doped polysilicon). xConductor layer 16 may include portions of a control circuitry (e.g., peripheral array under-circuit system and / or common source line or board) for controlling read and write access to transistors and / or memory cells in array 12. Construction 10 includes a stack 18 comprising vertically alternating (in the Z direction) first / conductive layer 22 and second / insulating layer 20. An exemplary thickness of each of layers 20 and 22 is 20 nanometers to 60 nanometers. An exemplary uppermost layer 20 may be thicker / the thickest compared to one or more other layers 20 and / or 22. Only a small number of layers 20 and 22 are shown, and stack 18 is more likely to include dozens, hundreds, or more layers 20 and 22, etc. Other circuitry, which may or may not be portions of the peripheral and / or control circuitry, may be below or above stack 18. For example, multiple vertically alternating layers of conductive and insulating material of such circuitry may be below the lowermost conductive layer 22 and / or above the uppermost conductive layer 22. For example, one or more select gate layers (not shown) may be portions of the bottom of stack 18. The conductive layer 22 may not be conductive at this processing point, for example, if it is a "post-gate" / "replacement gate," and the insulating layer 20 may not be insulating at this processing point (but is insulating at least in the finished circuit system construction). In any case, in some embodiments, the conductive layer 22 is referred to as first layer 22, and the insulating layer 20 is referred to as second layer 20, and they have compositions different from each other. An exemplary insulating / second layer 20 includes an insulating material 24 (e.g., silicon dioxide and / or other materials that may have one or more components). An exemplary conductive / first layer 22 includes a sacrificial material 26 (e.g., silicon nitride) in an exemplary post-gate processing. This would include the conductive material (not shown) in a so-called pre-gate processing.

[0016] Channel material strings 53 extend through the first layer 22 and the second layer 20. The channel material strings 53 are arranged into sets 60, which are spaced apart from each other in the horizontal X and Y directions, which are orthogonal to each other. Within individual sets 60, the channel material strings 53 are arranged into groups 62, which are spaced apart from each other in the Y direction. Individual groups 62 comprise multiple rows 64 of channel material strings 53, which are spaced apart from each other in the Y direction. More or fewer sets, groups, and / or rows may be present in configuration 10 (not shown). The Y-direction distance (D2) between adjacent groups 62 is greater than the Y-direction distance (D1) between adjacent rows 64 within an individual group 62 (there are no groups or rows between those groups or rows that are respectively adjacent to each other). There is a space 67 between groups 62 that are adjacent to each other in the Y direction.

[0017] An exemplary channel material string 53 extends into conductor layer 16. In some embodiments, channel material string 53 may enter into conductor material 17 of conductor layer 16 as shown, or may terminate on top of it (not shown). Alternatively, as an example, channel material string 53 may terminate on top of or inside the lowermost insulating layer 20. The reason for making channel material string 53 extend at least into conductor material 17 of conductor layer 16 is to ensure direct electrical coupling of the channel material of channel material string 53 to conductor layer 16, without using alternative processes and structures to do so when such a connection is required and / or to provide an anchoring effect to channel material string 53. Etch-stop material (not shown) may be inside or on top of conductor material 17 of conductor layer 16 to facilitate processing during the formation of channel material string 53. Such etch-stop material may be sacrificial or non-sacrificial. As an example, but in some embodiments, row 64 individually has two and only two channel material strings 53, and individual sets 60 contain two and only two groups 62. Alternative arrangements and constructions can be used.

[0018] The channel material string 53 includes a channel material 36 that can be directly electrically coupled to the conductor material 17 in the conductor layer 16. Individual memory cells of the formed exemplary memory array may include a gate region (e.g., a control gate region) and a memory structure laterally positioned between the gate region and the channel material. In one such embodiment, the memory structure is formed to include a charge-blocking region, a storage material (e.g., a charge storage material), and an insulating charge-transfer material. The storage material of the individual memory cell (e.g., a floating gate material, such as doped or undoped silicon, or a charge-trapping material, such as silicon nitride, metal dots, etc.) may be vertically positioned along the individual charge-blocking region. The insulating charge-transfer material (e.g., a bandgap engineered structure having a nitrogen-containing material (e.g., silicon nitride) sandwiched between two insulating oxides (e.g., silicon dioxide) may be laterally positioned between the channel material and the storage material. The exemplary channel material 36 comprises a suitably doped crystalline semiconductor material, such as one or more silicon, germanium, and so-called III / V semiconductor materials (e.g., GaAs, InP, GaP, and GaN).

[0019] The figure illustrates an embodiment in which charge-blocking material 30, storage material 32, and charge-transfer material 34 are formed before the channel material 36 forming the channel material string 53, passing through insulating layer 20 and conductive layer 22. Materials 30, 32, 34, and 36 can be formed, for example, by depositing their respective thin layers above stack 18 and within the depicted trenches, and subsequently planarizing such thin layers to at least return to the top surface of stack 18, as shown. An exemplary thickness of each of materials 30, 32, 34, and 36 is 25 to 100 angstroms, and this is typically thinner than layers 20 and 22. This is not shown in the figure to emphasize the exemplary structural properties associated with materials 30, 32, 34, and 36. Additionally, the trenches containing materials 30, 32, 34, and 36 are shown as having vertical sidewalls, but such vertical sidewalls may gradually narrow (not shown) as they move deeper inward and / or outward into stack 18. Punch etching can be performed as shown to remove materials 30, 32, and 34 at their bottom to expose conductor layer 16, such that channel material 36 (channel material string 53) is directly electrically coupled to conductor material 17 of conductor layer 16. Such punch etching can occur individually for each of materials 30, 32, and 34 (as shown), or it can occur together for all materials after material 34 is deposited (not shown). Alternatively, and by way of example only, punch etching can be omitted, and channel material 36 can be directly electrically coupled to conductor material 17 of conductor layer 16 via separate conductive interconnects (not shown).

[0020] In some embodiments, as shown, a first trench 66 (e.g., formed of materials 34 and 36) extends through the stack 18 and elongates horizontally in the Y direction. Individual trenches 66 are located in one of individual sets 60 and extend horizontally through a group 62 between the channel material strings 53 and through a space 67 in an individual set 60. In some such embodiments, the sidewalls 68 of the first trench 66 include channel material 36 of the channel material strings 53 and barrier insulators 30, wherein the channel material 36 and the barrier insulators 30 alternate with each other along the Y direction.

[0021] refer to Figure 8 and 9In one embodiment, at least some of the barrier insulators 30 have been removed from the sidewalls 68 of the first trench 66 (e.g., by timed isotropic etching) to widen at least a portion of the first trench 66 in the X direction. In one such embodiment, and as shown, at least some of the storage material 32 have also been removed (e.g., by timed isotropic etching). In some embodiments, this removal may form one or more respective flat surfaces 69, 70, 71, and 72 of the tunnel insulator 34, the channel material 36, the storage material 32, and the barrier insulator 30. In some such embodiments, at least two, at least three, and all four (as shown, all four) of the flat surfaces 69, 70, 71, and 72 in different rows 64 of different groups 62 in individual sets 60 are coplanar in the Y direction. Alternatively, none, only one, only two, or only three of the surfaces 69, 70, 71, and 72 may be flat.

[0022] refer to Figure 10 and 11 The first trench 66 has been filled with insulating material 73 (e.g., silicon dioxide).

[0023] refer to Figures 12 to 14 The insulating material 73 has been masked in individual sets 60 (e.g., with sacrificial masking material 74) so ​​that at least some of the insulating material 73 in space 67 is exposed in those individual sets through which the trench will be formed, as described below. Figure 12 The diagram illustrates the position of the masking material 74 at the top of the structural outline (shown as a shading), but Figure 12 Is it so? Figure 13 and 14 The section line 12-12 indicates and corresponds to Figure 2 , 8 And the horizontal cross-section of such a cross-section of 10 taken in the middle of stack 18.

[0024] refer to Figures 15 to 17An opening 75 has been formed through the stack 18 in the space 67 between individual groups 62 in the individual sets 60, wherein the opening 75 extends individually in the X direction to expose the sacrificial material 26 to the opening 75. The opening 75 is formed in those individual sets 60 that will horizontally pass through to form the trench, as mentioned above and described below. During and / or after the formation of the opening 75, the sacrificial masking material 74 (not shown) has been removed. In one embodiment and as shown, the opening 75 has been formed through the exposed insulating material 73 (in use) in the space 67. In one such embodiment, the formation of the opening 75 includes dry etching of the exposed insulating material 73 in the space 67. In one embodiment and as shown, this formation of the opening 75 also includes dry etching of the barrier insulator 30 to (at least) expose the sacrificial material 26 to the opening 75. Those skilled in the art can select various anisotropic and / or isotropic etching chemicals to achieve the depicted profile depending on the composition of materials 30, 32, 34, and 36.

[0025] The embodiments described and illustrated above are merely one exemplary manner in which an opening 75 is formed through the stack 18 in the space 67 between individual groups 62 in an individual collection 60, wherein the individual opening 75 extends in the X direction to expose the sacrificial material 26 to the opening 75. Alternative manners may be used, and two examples of such manners are described below with respect to constructions 10a and 10b.

[0026] refer to Figures 18 to 21 The sacrificial material 26 (not shown) has been removed from the first layer 22 through the opening 75 (e.g., if it is silicon nitride, selective etching is performed using H3PO4). Figures 22 to 25 The conductive material 48 (conductive metallic material) is formed by passing through the opening 75 into the void space created by the removal of the sacrificial material 26. This is just one example of replacing the sacrificial material 26 with conductive material 48 that completely surrounds the individual groups 62 and individual sets 60 in the individual first layers 22 through the opening 75. The conductive material 48 extends along the X direction between the openings 75 adjacent to each other in the X direction.

[0027] refer to Figures 26 to 32 Conductive material 48 has been removed from opening 75 (e.g., by selective etching) and sufficiently removed in individual first layers 22 to form trenches 40 (referred to in some embodiments as second trenches 40) that extend horizontally through stack 18 in the X direction and form memory blocks 58 spaced apart from each other in the Y direction. Individual trenches 40 extend through multiple sets 60 and through spaces 67 between individual groups 62 within individual sets 60.

[0028] This removal of conductive material 48 to form trenches 40 forms individual conductive lines 29 (e.g., word lines) in the stack 18, and forms vertically extending strings 49 of individual transistors and / or memory cells 56 in the stack 18. After removing the sacrificial material 26 and before forming the conductive material 48, an insulating material (e.g., AlO) can be used. x (and not shown) is the first layer 22 as a liner, on which conductive material 48 is formed.

[0029] In some figures, brackets indicate the approximate location of transistors and / or memory cells 56, and dashed outlines indicate the approximate location of some of them. The conductive material 48 can be considered as a control gate region 52 having individual transistors and / or memory cells 56. In the depicted embodiment, the control gate region 52 includes individual portions of individual conductive lines 29.

[0030] A charge-blocking region (e.g., charge-blocking material 30) is located between the storage material 32 and the individual control gate region 52. The charge-blocking member in the memory cell may function to prevent charge carriers from flowing from the storage material (e.g., a floating gate material, a charge trapping material, etc.) to the control gate in programming mode, and to prevent charge carriers from flowing from the control gate into the storage material in erase mode. Therefore, the charge-blocking member can be used to block charge migration between the control gate region and the storage material of an individual memory cell. An exemplary charge-blocking region as shown includes an insulating material 30. As another example, the charge-blocking region may include a lateral (e.g., radial) outer portion of the storage material (e.g., material 32), wherein such storage material is insulating (e.g., in the absence of any different compositional material between the insulating storage material 32 and the conductive material 48). In any case, as an additional example, the interface between the storage material and the conductive material of the control gate may be sufficient to act as a charge-blocking region even in the absence of any separate component insulating material 30. Additionally, the interface between the conductive material 48 and the insulating material 30 (when present) can together act as a charge-blocking region, and alternatively or additionally, can act as a lateral outer region of an insulating storage material (e.g., silicon nitride material 32). Exemplary material 30 is one or more of hafnium oxide and silicon dioxide.

[0031] refer to Figures 33 to 35 Wall 57 is formed in individual trenches 40. Wall 57 can provide lateral electrical isolation (insulation) between adjacent memory blocks 58 in the Y direction. Exemplary insulating materials are one or more of SiO2, Si3N4, and Al2O3. Wall 57 may include through-array vias (not shown).

[0032] refer to Figures 36 to 38Alternative embodiments of the method and a construction 10a including a memory array 12a are described. The same designations from the embodiments described above have been used where appropriate, with some construction differences indicated by the suffix "a" or by different designations. Figure 36 The display is by Figure 10 Alternative processing methods are shown. For example, from... Figure 36 It is obvious, and in one embodiment, that no event has occurred before the insulating material 73 is formed in the first trench 66. Figure 8 and 9 Display processing. Figure 37 The display is similar to Figure 15 The subsequent processing shown in the figure, wherein in one embodiment, forming opening 75 includes from Figure 36 The exposed insulating material 73 in space 67 is wet-etched. In one such embodiment, forming the opening 75 also includes... Figure 36 Wet etching is performed on the barrier insulator 30, the storage material 32, and the tunnel insulator 34 to expose the sacrificial material 26 to the opening 75, such as... Figure 37 As shown in the figure. Again, those skilled in the art can select various anisotropic and / or isotropic etching chemicals to achieve the depicted profile, depending on the composition of the material being etched relative to the other exposed materials. Figure 38 The display corresponds to Figure 27 An exemplary obtained structure 10a is shown in the structure 10.

[0033] refer to Figures 39 to 41 Alternative embodiments of the method and a construction 10b including a memory array 12b are described. The same reference numerals as those used in the embodiments described above are used where appropriate, with some construction differences indicated by the suffix "b" or by different reference numerals. Figure 39 The display is by Figure 36 An alternative treatment to the demonstrated treatment. At least some of the spaces 67 in the first trench 66 have been masked (e.g., with a sacrificial masking material, not shown), while the remainder of the first trench 66 is exposed. Thereafter, as... Figure 39 As shown, the exposed portion of the first trench 66 is filled with insulating material 73, thereby forming a radially inner portion of the opening 75 through the space 67 and the stack 18 (e.g., the sacrificial masking material is subsequently removed).

[0034] refer to Figure 40In one embodiment, the barrier insulator 30 (no longer shown relative to opening 75), the storage material 32 (no longer shown relative to opening 75), and the tunnel insulator 34 (no longer shown relative to opening 75) have been etched (e.g., wet or dry) to expose the sacrificial material 26 to opening 75. During such etching, some of the storage material 32 may be etched in the Y direction within space 67 (not shown). Alternatively, it may initially be as follows Figure 40 As shown (not displayed), it forms as Figure 39 The opening 75 shown is designed to minimize any etching of the storage material 32, for example, in the Y direction in space 67 and later when the sacrificial material 26 is etched (if it has the same composition as the storage material 32). Figure 41 The display corresponds to Figure 27 An exemplary obtained structure 10b is shown in the structure 10.

[0035] Any other attributes or aspects shown and / or described herein with reference to other embodiments may be used in the embodiments shown and described above.

[0036] In one embodiment, a method for forming a memory circuit system (e.g., 10, 10a, 10b) includes forming a stack (e.g., 18) comprising vertically alternating first layers (e.g., 22) and second layers (e.g., 20). In the finished circuit system configuration, the first layer is conductive and the second layer is insulating. Channel material strings (e.g., 53) extend through the first and second layers. The channel material strings are arranged into sets (e.g., 60) that are spaced apart from each other in horizontal X and Y directions orthogonal to each other. Individual channels within the sets are arranged into groups (e.g., 62) that are spaced apart from each other in the Y direction. Individual groups comprise multiple rows of channel material strings (e.g., 64) that are spaced apart from each other in the Y direction. The Y-direction distance between adjacent groups (e.g., D2) is greater than the Y-direction distance between adjacent rows within an individual group (e.g., D1). The stack is divided into memory block regions (e.g., 58) that are spaced apart from each other in the Y direction. Walls (e.g., 57) are formed between adjacent memory block regions. The walls extend through the stack and are horizontally elongated in the X direction, passing through the multiples in the set and through the spaces between individual groups in the individual sets.

[0037] In one such embodiment, the formed memory circuit system includes memory cells (e.g., 56), which individually include a tunnel insulator (e.g., 34), a channel material (e.g., 36) of one of a string of channel materials, a storage material (e.g., 32), and a barrier insulator (e.g., 30). At least two of the tunnel insulators, channel materials, storage materials, and barrier insulators in different rows of different groups in individual sets include flat surfaces coplanar in the Y direction (e.g., any two of 69, 70, 71, and 72). In one such embodiment, at least three of the tunnel insulators, channel materials, storage materials, and barrier insulators in different rows of different groups in individual sets, and in one embodiment all four, have flat surfaces coplanar in the Y direction.

[0038] Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0039] Alternative embodiments may be constructed from the method embodiments described above or otherwise. In any case, embodiments of the invention cover memory arrays independent of manufacturing methods. Nevertheless, such memory arrays may have any of the properties described herein in the method embodiments. Similarly, the method embodiments described above may incorporate having, forming, and / or having any of the properties described relative to the device embodiments.

[0040] In one embodiment, the memory array (e.g., 12, 12a, 12b) includes a stack (e.g., 18) comprising vertically alternating insulating layers (e.g., 20) and conductive layers (e.g., 22). Channel material strings (e.g., 53) extend through the insulating and conductive layers. The channel material strings are arranged in sets (e.g., 60) spaced apart from each other in horizontal X and Y directions, which are orthogonal to each other. Individual channels within the sets are arranged in groups (e.g., 62) spaced apart from each other in the Y direction. Individual groups comprise multiple rows (e.g., 64) of channel material strings, spaced apart from each other in the Y direction. The Y-direction distance between adjacent groups (e.g., D2) is greater than the Y-direction distance between adjacent rows within an individual group (e.g., D1). The stack includes memory blocks (e.g., 58) spaced apart from each other in the Y direction. There are walls (e.g., 57) between adjacent memory blocks that extend through the stack and horizontally in the X direction, through the many in the set and through the space between individual groups in the individual set (e.g., 67).

[0041] In some embodiments, the memory array (e.g., 12) includes memory cells (e.g., 56), which individually include a tunnel insulator (e.g., 34), a channel material (e.g., 36) of one of a series of channel materials, a storage material (e.g., 32), and a barrier insulator (e.g., 30). In one of such embodiments, the tunnel insulators and storage materials in different rows of different groups in a particular set include flat surfaces coplanar in the Y direction (e.g., 69 and 71, respectively). In one of such embodiments, the channel material and tunnel insulators in different rows of different groups in a particular set include flat surfaces coplanar in the Y direction (e.g., 70 and 69, respectively). In one of such embodiments, the channel material and storage materials in different rows of different groups in a particular set include flat surfaces coplanar in the Y direction (e.g., 70 and 71, respectively). In one of such embodiments, the tunnel insulators, storage materials, and barrier insulators in different rows of different groups in a particular set include flat surfaces coplanar in the Y direction (e.g., 69, 71, and 72, respectively). In one of these embodiments, the tunnel insulators, trench materials, storage materials, and barrier insulators in different rows of different groups in individual sets include flat surfaces that are coplanar in the Y direction (e.g., 69, 70, 71, and 72, respectively).

[0042] Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0043] The prior art construction of this invention forms walls between the sets in the trench, rather than forming walls through the space within the sets. Embodiments of this invention can achieve increased circuit density and / or reduced cost.

[0044] The memory circuitry described herein (e.g., its conductive vias) can be connected to circuitry on the top or bottom of a stack (i.e., either z-axis side), regardless of the orientation of the construction in three-dimensional space, and this is not important to aspects of the invention disclosed herein. For example, and only as an example, a conductive via can be connected to a peripheral control circuitry oriented below the stack relative to the orientation shown in the figures. As an alternative example, and only as an example, a conductive via can be connected to a peripheral control circuitry oriented above the stack relative to the shown orientation, for example, to another substrate having such circuitry and engaging with the top of the stack relative to the shown orientation. In such an alternative example, the construction can be reversed from the shown orientation and then engaged with another substrate. Additionally, in such an alternative example, source lines or plates can be fabricated relative to the bottom of the stack relative to the shown orientation, but reversed from them during processing. Such source lines or plates can be connected to conductive vias extending through the stack to an engagement with a substrate on the other side having such peripheral control circuitry. In any case, the construction shown and described herein can be handled, encapsulated and / or mounted in any three-dimensional spatial orientation.

[0045] The above-described processing or construction can be viewed as an array of components formed as a single stack or group of such components, or within a single stack or group, which is above or part of an underlying substrate (but a single stack / group may have multiple layers). Control circuitry and / or other peripheral circuitry for operating or accessing such components within the array may also be formed as part of the finished product construction at any location, and in some embodiments may be located below the array (e.g., under-array CMOS). In any case, one or more additional such stacks / groups may be provided or fabricated above and / or below the stacks / groups shown in the diagram or described above. Furthermore, the arrays of components in different stacks / groups may be identical or different relative to each other, and the different stacks / groups may have the same or different thicknesses relative to each other. Intervention structures (e.g., additional circuitry and / or dielectric layers) may be disposed between vertically adjacent stacks / groups. And, the different stacks / groups may be electrically coupled relative to each other. Multiple stacks / groups can be manufactured individually and sequentially (e.g., one on top of another), or two or more stacks / groups can be manufactured substantially simultaneously.

[0046] The assemblies and structures discussed above can be used in integrated circuit / circuit systems and incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can comprise multi-layered, multi-chip modules. Electronic systems can be any of the following wide range of systems: cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting systems, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, and so on.

[0047] In this document, unless otherwise indicated, “vertical,” “higher,” “upper,” “lower,” “top,” “above,” “bottom,” “above,” “below,” “under,” “upward,” and “downward” generally refer to the vertical direction. “Horizontal” means a generally relative direction (i.e., within 10 degrees) along the surface of the main substrate, with vertical being generally orthogonal to it. The reference to “fully horizontal” means a direction along the surface of the main substrate (i.e., not forming degrees with said surface) that the substrate can be relative to during manufacturing and as shown in the figures herein (if present). Furthermore, as used herein, “vertical” and “horizontal” are directions generally perpendicular to each other and are independent of the orientation of the substrate in three-dimensional space during manufacturing and / or in the finished product structure. Additionally, “vertically extending” and “vertically extending” mean a direction inclined at least 45° from fully horizontal. Additionally, for field-effect transistors, terms like "vertically extending," "vertically extending," "horizontally extending," and "horizontally extending" refer to the orientation of the transistor's channel length, along which current flows between the source and drain regions during operation. For bipolar junction transistors, "vertically extending," "vertically extending," "horizontally extending," and "horizontally extending" refer to the orientation of the substrate length, along which current flows between the emitter and collector during operation. In some embodiments, any vertically extending component, feature, and / or region extends vertically or within a vertical 10° range.

[0048] Furthermore, "directly above," "directly below," and "directly below" require that the two stated areas / materials / components have at least some lateral overlap (i.e., horizontally) relative to each other. And, using "above" without the preceding "direct" only requires that a portion of the stated area / material / component above the other stated area / material / component extends vertically outward from the other stated area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components). Similarly, using "below" and "under" without the preceding "direct" only requires that a portion of the stated area / material / component below / under the other stated area / material / component extends vertically inward from the other stated area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components).

[0049] Any of the materials, regions, and structures described herein may be homogeneous or non-homogeneous, and in any event may be continuous or discontinuous over any material covering them. When one or more exemplary components are provided for any material, the material may include, consist primarily of, or be composed of such one or more components. Furthermore, unless otherwise stated, any suitable existing or future-developed techniques may be used to form each material, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0050] Additionally, the term “thickness” used alone (without a directional adjective) is defined as the average straight-line distance perpendicular to the nearest surface of adjacent materials or regions with different compositions, passing through a given material or region. Furthermore, the various materials or regions described herein may have substantially constant thickness or variable thickness. If variable thickness is present, then unless otherwise indicated, the thickness refers to the average thickness, and the material or region will have a minimum thickness and a maximum thickness due to the variable thickness. As used herein, “different compositions” requires only that the portions of two stated materials or regions that can directly contact each other are chemically and / or physically different, for example, in cases where such materials or regions are not homogeneous. If two stated materials or regions are not directly contacting each other, then in cases where such materials or regions are not homogeneous, “different compositions” requires only that the portions of the two stated materials or regions that are closest to each other are chemically and / or physically different. In this document, when a stated material, region, or structure is in at least some physical contact with each other, one material, region, or structure “directly contacts” another material, region, or structure. In contrast, the words "over," "on," "near," "along," and "against" without the preceding "positive" encompass "direct contact" and constructions in which the intervention of materials, areas, or structures results in no physical contact between the stated materials, areas, or structures relative to each other.

[0051] In this context, if, during normal operation, current can flow continuously from one zone-material-component to another, and this flow is primarily accomplished by the movement of said subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated, then the zone-material-components are “electrically coupled” relative to each other. Another electronic component may be between the zone-material-components and electrically coupled to them. In contrast, when zone-material-components are referred to as “directly electrically coupled,” there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between directly electrically coupled zone-material-components.

[0052] Any use of the terms "row" and "column" in this document is for the convenience of distinguishing one series or orientation of features from another series or orientation of features, and for which components have been or may be formed along said "row" and "column". "Row" and "column" are used synonymously with respect to any series of areas, components, and / or features, regardless of function. In any case, rows may be straight and / or curved and / or parallel and / or non-parallel relative to each other, and columns may be the same. Furthermore, rows and columns may intersect each other at 90° or at one or more other angles (i.e., other than straight angles).

[0053] The composition of any of the conductive / conductor / conductive materials mentioned herein may be a conductive metallic material and / or a conductive-doped semiconducting / semiconductor / semiconductive material. "Metallic material" means any elemental metal, any mixture or alloy of two or more elemental metals, and any one or more metallic compounds.

[0054] In this document, any use of "selective" in relation to etching, removal, deposition, forming, and / or formation is an action in which a stated material is performed relative to another stated material at a volume ratio of at least 2:1. Additionally, any use of selective deposition, selective growth, or selective formation is the deposition, growth, or formation of one material relative to one or more stated materials at a volume ratio of at least 2:1 for at least the first 75 angstroms of the deposition, growth, or formation.

[0055] Unless otherwise indicated, the use of "or" in this document covers either or both.

[0056] in conclusion

[0057] In some embodiments, a method for forming a memory circuit system includes forming a stack comprising a vertically alternating first layer and a second layer. In the finished circuit system configuration, the first layer is conductive and the second layer is insulating. Channel material strings extend through the first and second layers. The channel material strings are arranged in sets, the sets being spaced apart from each other in horizontal X and Y directions orthogonal to each other. Individuals in the sets are arranged in groups, the groups being spaced apart from each other in the Y direction. Individuals in the groups comprise multiple rows of channel material strings, which are spaced apart from each other in the Y direction. The Y-direction distance between adjacent groups is greater than the Y-direction distance between adjacent rows within the individual groups. The stack is divided into memory block regions spaced apart from each other in the Y direction. Walls are formed between adjacent memory block regions. The walls extend through the stack and extend horizontally in the X direction, passing through the sets and through the spaces between individual groups in the individual sets.

[0058] In some embodiments, a method for forming a memory circuit system includes forming a stack comprising vertically alternating first and second layers. The first layer comprises a sacrificial material, and the second layer comprises an insulating material having a composition different from that of the sacrificial material. Channel material strings extend through the first and second layers. The channel material strings are arranged in sets, the sets being spaced apart from each other in horizontal X and Y directions orthogonal to each other. Individuals within the sets are arranged in groups, the groups being spaced apart from each other in the Y direction. Individuals within the groups comprise multiple rows of channel material strings, spaced apart from each other in the Y direction. The Y-direction distance between adjacent groups is greater than the Y-direction distance between adjacent rows within an individual group. Openings are formed through the stack in the spaces between individual groups within the individual sets. The openings extend individually in the X direction to expose the sacrificial material. The openings are formed in those sets through which trenches will be formed. Through the openings, the sacrificial material is replaced with a conductive material that completely surrounds the individual groups and sets within the individuals of the first layer. The conductive material extends along the X direction between adjacent openings in the X direction. The conductive material is sufficiently removed from the openings and in each individual first layer to form trenches that extend horizontally in the X direction through the stack, and memory blocks spaced apart from each other in the Y direction. Individual trenches extend through multiple trenches in an assembly, and through the space between individual groups in an individual assembly. Walls are formed in the individual trenches.

[0059] In some embodiments, a memory array includes a stack comprising vertically alternating insulating and conductive layers. Channel material strings extend through the insulating and conductive layers. The channel material strings are arranged in sets spaced apart from each other in horizontal X and Y directions orthogonal to each other. Individual channels in the sets are arranged in groups spaced apart from each other in the Y direction. Individual groups comprise multiple rows of channel material strings spaced apart from each other in the Y direction. The Y-direction distance between adjacent groups is greater than the Y-direction distance between adjacent rows within an individual group. The stack includes memory blocks spaced apart from each other in the Y direction. A wall extends through the stack and horizontally in the X direction between adjacent memory blocks, passing through the sets and through the space between the individual groups within the individual sets.

[0060] As per the regulations, the subject matter disclosed herein has been described in more or less specific language regarding structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes exemplary embodiments. Therefore, the claims have the full scope as stated in the writings and should be properly interpreted in accordance with the principle of equivalence.

Claims

1. A method for forming a memory circuit system, comprising: A stack comprising vertically alternating first and second layers is formed. In the finished circuit system construction, the first layer is conductive and the second layer is insulating. Channel material strings extend through the first and second layers. The channel material strings are arranged in sets, which are spaced apart from each other in horizontal X and Y directions that are orthogonal to each other. The channel material strings in the individual sets are arranged in groups, which are spaced apart from each other in the Y direction. Each group includes multiple rows of channel material strings that are spaced apart from each other in the Y direction. The Y-direction distance between adjacent groups is greater than the Y-direction distance between adjacent rows within the individual group. The stack is divided into memory block regions spaced apart from each other in the Y direction; as well as A wall is formed between adjacent memory block regions, the wall extending through the stack and horizontally elongating in the X direction, through many of the sets and through the space between the individual groups in the individual sets.

2. The method of claim 1, wherein the formed memory circuit system comprises a memory cell, each memory cell individually comprising a tunnel insulator, a channel material of one of the channel material strings, a storage material, and a barrier insulator; at least two of the tunnel insulator, the channel material, the storage material, and the barrier insulator in different rows of different groups in the individual sets comprise flat surfaces coplanar in the Y direction.

3. The method of claim 2, wherein the flat surfaces of at least three of the tunnel insulator, the trench material, the storage material, and the barrier insulator in the different rows of the different groups in the individual sets are coplanar in the Y direction.

4. The method of claim 2, wherein the flat surfaces of all four of the tunnel insulator, the trench material, the storage material, and the barrier insulator in the different rows of the different groups in the individual sets are coplanar in the Y direction.

5. A method for forming a memory circuit system, comprising: A stack comprising vertically alternating first and second layers is formed. The first layer includes a sacrificial material, and the second layer includes an insulating material having a composition different from that of the sacrificial material. Channel material strings extend through the first and second layers and are arranged in sets that are spaced apart from each other in horizontal X and Y directions orthogonal to each other. Individual channels material strings in the sets are arranged in groups that are spaced apart from each other in the Y direction. Individual groups include multiple rows of channels material strings that are spaced apart from each other in the Y direction. The Y-direction distance between adjacent groups is greater than the Y-direction distance between adjacent rows within an individual group. An opening is formed through the stack in the space between the individual groups in the individual sets, the opening extending individually in the X direction to expose the sacrificial material to the opening, the opening being formed in those sets through which the trench will be formed horizontally; The sacrificial material is replaced through the opening with a conductive material that completely surrounds the individual groups and sets of individuals in the first layer; the conductive material extends along the X direction between the openings adjacent to each other in the X direction; The conductive material is sufficiently removed from the opening and in the individual first layer to form trenches that extend horizontally in the X direction through the stack and to form memory blocks spaced apart from each other in the Y direction, the individual trenches extending through the multiple ones in the set and through the space between the individual groups in the individual set; as well as Walls are formed in the individual trenches.

6. The method of claim 5, wherein the trench is a second trench, and the method further comprises: A first trench extends through the stack and is horizontally elongated in the Y direction, with each individual of the first trench being in one of the individual sets and extending horizontally through the group between the strings of channel material and across the space in the individual set; The first trench is filled with an insulating material; The insulating material in the individual sets is masked so that at least some of the insulating material in the space is exposed. as well as The opening is formed by passing through the exposed insulating material in the space.

7. The method of claim 6, wherein the sidewall of the first trench comprises channel material of the channel material string and barrier insulators of the memory cells of the formed memory circuit system, the channel material and the barrier insulators alternating with each other along the Y direction, and the method further comprises: Before filling the first trench with the insulating material, at least some of the blocking insulators are removed from the sidewalls of the first trench to widen at least a portion of the first trench in the X direction; and Forming the opening includes dry etching the exposed insulating material in the space.

8. The method of claim 7, wherein forming the opening comprises dry etching the barrier insulator to expose the sacrificial material to the opening.

9. The method of claim 6, wherein the sidewall of the first trench comprises channel material of the channel material string and barrier insulators of the memory cells of the formed memory circuit system, the channel material and the barrier insulators alternating with each other along the Y direction; and The formation of the opening includes wet etching of the exposed insulating material in the space.

10. The method of claim 9, wherein forming the opening comprises wet etching of the barrier insulator of the memory cell of the formed memory circuit system, wet etching of the storage material of the memory cell of the formed memory circuit system, and wet etching of the tunnel insulator of the memory cell of the formed memory circuit system to expose the sacrificial material to the opening.

11. The method of claim 5, wherein the trench is a second trench, and the method further comprises: A first trench extends through the stack and is horizontally elongated in the Y direction, with each individual of the first trench being in one of the individual sets and extending horizontally through the group between the strings of channel material and across the space in the individual set; At least some of the spaces in the first trench are covered, while the rest of the first trench is exposed. as well as The exposed portion of the first trench is filled with an insulating material, thereby passing through the space and stacking to form the radially inner portion of the opening.

12. The method according to claim 11, wherein, After forming the radially inner portion of the opening, the blocking insulator of the memory cell of the formed memory circuit system is wet-etched, the storage material of the memory cell of the formed memory circuit system is wet-etched, and the tunnel insulator of the memory cell of the formed memory circuit system is wet-etched to expose the sacrificial material to the opening.

13. A memory array comprising: Stacked, comprising vertically alternating insulating and conductive layers; Channel material strings extending through the insulating layer and the conductive layer are arranged in sets, the sets being spaced apart from each other in horizontal X and Y directions orthogonal to each other. Individual channels material strings within these sets are arranged in groups, the groups being spaced apart from each other in the Y direction. Individual groups comprise multiple rows of channels material strings, also spaced apart from each other in the Y direction. The Y-direction distance between adjacent groups is greater than the Y-direction distance between adjacent rows within an individual group. The stack includes memory blocks spaced apart from each other in the Y direction, with a wall between adjacent memory blocks extending through the stack and horizontally extending in the X direction, passing through many of the sets and through the space between the individual groups in the individual sets.

14. The memory array of claim 13, wherein each row individually has two and only two of the channel material strings.

15. The memory array of claim 13, wherein there are two and only two groups in the individual sets.

16. The memory array according to claim 13, wherein, Each row individually has two and only two strings of the channel material; and There are two and only two groups in each individual set.

17. The memory array of claim 13, wherein the memory array comprises memory cells, each memory cell individually comprising a tunnel insulator, a channel material of one of the strings of channel materials, a storage material, and a barrier insulator; the tunnel insulator and the storage material in different rows of different groups in the individual sets comprise flat surfaces coplanar in the Y direction.

18. The memory array of claim 13, wherein the memory array comprises memory cells, each memory cell individually comprising a tunnel insulator, a channel material of one of the strings of channel materials, a storage material, and a barrier insulator; the channel material and the tunnel insulator in different rows of different groups in the individual sets comprise flat surfaces coplanar in the Y direction.

19. The memory array of claim 13, wherein the memory array comprises memory cells, each memory cell individually comprising a tunnel insulator, a channel material of one of the strings of channel materials, a storage material, and a barrier insulator; the channel material and the storage material in different rows of different groups in the individual sets comprise flat surfaces coplanar in the Y direction.

20. The memory array of claim 13, wherein the memory array comprises memory cells, each memory cell individually comprising a tunnel insulator, a channel material of one of the strings of channel materials, a storage material, and a barrier insulator; the tunnel insulator, the storage material, and the barrier insulator in different rows of different groups in the individual sets comprise flat surfaces coplanar in the Y direction.

21. The memory array of claim 13, wherein the memory array comprises memory cells, each memory cell individually comprising a tunnel insulator, a channel material, a storage material, and a barrier insulator of one of the strings of channel materials; the tunnel insulator, the channel material, the storage material, and the barrier insulator in different rows of different groups in the individual sets comprise flat surfaces coplanar in the Y direction.

Images