Semiconductor device

Abstract

A semiconductor device may include: a substrate; conductive lines spaced apart from each other in a first horizontal direction, the conductive lines extending in a second horizontal direction intersecting the first horizontal direction; at least one gate electrode located between the conductive lines in a first horizontal direction, the at least one gate electrode extending in a vertical direction; channel layers surrounding the at least one gate electrode, the channel layers being spaced apart from each other in a vertical direction; a dielectric layer between the channel layer and the at least one gate electrode; the metal layer is positioned between the channel layer and the dielectric layer; the gate insulating layer is positioned between the channel layer and the metal layer; and at least one interface layer surrounding the at least one gate electrode, the at least one interface layer being located between the channel layer and the at least one gate electrode.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more particularly to a semiconductor device including a ferroelectric field-effect transistor. Background Technology

[0002] As electronic products become increasingly compact, multifunctional, and high-performance, there is a growing demand for high-capacity semiconductor memory devices. This necessitates increasing the integration density of memory devices. The integration density of two-dimensional semiconductor memory devices primarily depends on the area occupied by a single memory cell. Therefore, while the integration density of two-dimensional semiconductor memory devices is steadily increasing, it remains limited. Consequently, a semiconductor device incorporating a three-dimensional semiconductor memory device is proposed, which increases storage capacity by stacking multiple memory cells vertically on a substrate. Summary of the Invention

[0003] A semiconductor device is provided in which an interface layer comprising molybdenum oxide (MoOx), niobium oxide (NbOx), titanium oxide (TiOx), tantalum oxide (TaOx), or a combination thereof is disposed between a gate electrode and a dielectric layer.

[0004] According to aspects of this disclosure, a semiconductor device may include: a substrate; conductive lines spaced apart from each other in a first horizontal direction parallel to the top surface of the substrate, the conductive lines extending along a second horizontal direction intersecting the first horizontal direction; at least one gate electrode located between the conductive lines in the first horizontal direction, the at least one gate electrode extending along a vertical direction perpendicular to the substrate; a channel layer surrounding the at least one gate electrode, the channel layers being spaced apart from each other in the vertical direction; a dielectric layer located between the channel layers and the at least one gate electrode; a metal layer located between the channel layer and the dielectric layer; a gate insulating layer located between the channel layer and the metal layer; and at least one interface layer surrounding the at least one gate electrode, the at least one interface layer located between the channel layer and the at least one gate electrode.

[0005] According to aspects of this disclosure, a semiconductor device may include: a substrate; a gate electrode on the substrate extending in a vertical direction; a channel layer surrounding the gate electrode and spaced apart from each other in the vertical direction; a dielectric layer located between the channel layer and the gate electrode; a metal layer located between the channel layer and the dielectric layer; a gate insulating layer located between the channel layer and the metal layer; and at least one interface layer surrounding the gate electrode and located between the channel layer and the gate electrode, wherein the at least one interface layer comprises at least one of molybdenum oxide (MoOx), niobium oxide (NbOx), titanium oxide (TiOx), and tantalum oxide (TaOx).

[0006] According to aspects of this disclosure, a semiconductor device may include: a substrate; conductive lines spaced apart from each other in a first horizontal direction parallel to the top surface of the substrate and a vertical direction perpendicular to the top surface of the substrate, the conductive lines extending along a second horizontal direction intersecting the first horizontal direction; a gate electrode located between the conductive lines in the first horizontal direction and extending along the vertical direction; a channel layer surrounding the gate electrode, the gate electrodes being spaced apart from each other in the vertical direction; a dielectric layer located between the channel layer and the gate electrode; a metal layer located between the channel layer and the dielectric layer; a gate insulating layer located between the channel layer and the metal layer; and a first interface layer located between the gate electrode and the dielectric layer, the first interface layer extending along the vertical direction, and comprising at least one of molybdenum oxide (MoOx), niobium oxide (NbOx), titanium oxide (TiOx), and tantalum oxide (TaOx).

[0007] This disclosure is not limited to the aspects described above, and those skilled in the art will clearly understand other aspects of this disclosure not mentioned from the following description. Attached Figure Description

[0008] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic perspective view of a semiconductor device according to some embodiments; Figure 2a It is a plan view of a semiconductor device according to some embodiments; Figure 2b It is along Figure 1 A cross-sectional view taken from line A-A'; Figure 3 It is along Figure 2b A plan view intercepted by line B-B' in the middle; Figures 4a to 4c Is along with Figure 2b The plan view corresponding to the B-B' line in the diagram is used to illustrate a partial configuration of a semiconductor device according to some embodiments; Figures 5a to 11b This is a diagram illustrating a method for manufacturing a semiconductor device according to some embodiments, wherein Figure 5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a , Figure 10a and Figure 11a This is a plan view illustrating a method for manufacturing semiconductor devices, and the figure... Figure 5b , Figure 6b , Figure 7b , Figure 8b , Figure 9b , Figure 10b and Figure 11b Is along with Figure 1 A cross-sectional view of the line corresponding to line A-A' in the diagram, illustrating a method for manufacturing semiconductor devices; and Figure 12 This is a graph showing the correlation between the leakage current of a field-effect transistor and the thickness of the interface layer. Detailed Implementation

[0009] In the following, non-limiting exemplary embodiments are described in detail with reference to the accompanying drawings. The same reference numerals are used for the same parts in the drawings, and redundant descriptions may be omitted.

[0010] It should be understood that when a component or layer is referred to as being "on," "connected to," or "coupled to" other components or layers, the component or layer may be directly on, connected to, or coupled to other components or layers, or there may be intermediate components or layers. Conversely, when a component or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" other components or layers, there are no intermediate components or layers.

[0011] Figure 1 This is a schematic perspective view of a semiconductor device according to some embodiments.

[0012] Figure 2a It is a plan view of a semiconductor device according to some embodiments.

[0013] Figure 2b It is along Figure 1 A cross-sectional view taken from line A-A'.

[0014] Figure 3 It is along Figure 2b Plan view intercepted by line B-B'.

[0015] Reference Figures 1 to 3 According to an embodiment of the present invention, a semiconductor device 100 may include a substrate 101, an interlayer insulating film 103, an etch stop film 105, and a stacked structure SS. The interlayer insulating film 103 and the etch stop film 105 may be sequentially disposed on the substrate 101. The stacked structure SS may be disposed on the etch stop film 105.

[0016] In some embodiments, substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. For example, a group IV semiconductor may include silicon (Si), germanium (Ge), or silicon-germanium (Se-Ge). Substrate 101 may be configured as a bulk wafer or an epitaxial layer. In embodiments, substrate 101 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0017] In some embodiments, peripheral circuitry and wiring layers connected to the peripheral circuitry may be further formed on a portion of the substrate 101. For example, the peripheral circuitry may include, but is not limited to, planar metal-oxide-semiconductor field-effect transistors (MOSFETs) constituting sub-word line drivers, sense amplifiers, etc. Furthermore, a lower insulating layer may be further formed on the substrate 101, arranged to cover the peripheral circuitry and wiring layers.

[0018] In some embodiments, the interlayer insulating film 103 may include silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. The etch stop film 105 may include a metal oxide. For example, the etch stop film 105 may include silicon carbide (SiC), silicon nitride (SiN), nitrogen-doped silicon carbide (SiC:N), silicon oxynitride (SiOC), aluminum nitride (AlN), aluminum oxynitride (AlON), aluminum oxide (AlO), aluminum oxynitride (AlOC), or combinations thereof.

[0019] In some embodiments, the stacked structure SS may include a plurality of conductive lines 140. The plurality of conductive lines 140 may be spaced apart from each other in a vertical direction Z perpendicular to the substrate 101. Furthermore, the plurality of conductive lines 140 may be spaced apart from each other in a first horizontal direction X, and each may extend along a second horizontal direction Y. The first horizontal direction X and the second horizontal direction Y may be parallel to the substrate 101 and may intersect each other. Adjacent conductive lines of the conductive lines 140 may be spaced apart from each other in the first horizontal direction X, and a gate electrode 160 is located between adjacent conductive lines.

[0020] In some embodiments, the multiple conductive lines 140 may include conductive materials, and may include, for example, doped polycrystalline silicon, metals, conductive metal nitrides, conductive metal silicides, conductive metal oxides, or combinations thereof. The multiple conductive lines 140 may include, but are not limited to, doped polycrystalline silicon, aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), molybdenum (Mo), platinum (Pt), nickel (Ni), cobalt (Co), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), niobium nitride (NbN), titanium aluminum nitride (TiAl), titanium aluminum nitride (TiAlN), titanium silicide (TiSi), titanium silicon nitride (TiSiN), tantalum silicide (TaSi), tantalum silicon nitride (TaSiN), titanium ruthenium nitride (RuTiN), nickel silicide (NiSi), cobalt silicide (CoSi), iridium oxide (IrOx), ruthenium oxide (RuOx), or combinations thereof. The multiple conductive lines 140 may include two-dimensional semiconductor materials. For example, the two-dimensional semiconductor material of the multiple conductive lines 140 may include graphene, carbon nanotubes, or a combination thereof.

[0021] In some embodiments, on the substrate 101, a plurality of gate electrodes 160 may each extend longitudinally along the vertical direction Z. On the substrate 101, the plurality of gate electrodes 160 may be spaced apart from each other in a first horizontal direction X and a second horizontal direction Y. The plurality of gate electrodes 160 may be arranged between a plurality of conductive lines 140 in the first horizontal direction X.

[0022] In some embodiments, the stacked structure SS may further include a plurality of channel layers 121, each group surrounding a plurality of side surfaces of a plurality of gate electrodes 160. The plurality of channel layers 121 in each group may surround a plurality of gate electrodes 160. The plurality of channel layers 121 in the same group may each surround the same gate electrode 160 and may be spaced apart from each other in the vertical direction Z and may overlap each other in the vertical direction Z. The plurality of channel layers 121 may each have an annular shape surrounding the gate electrode 160 in a plan view. The plurality of channel layers 121 may be arranged between adjacent conductive lines of conductive lines 140 in a first horizontal direction X. Each conductive line 140 may be connected to a channel layer 121. In a plan view, the conductive lines 140 and their corresponding channel layers 121 may overlap each other in the first horizontal direction X.

[0023] In some embodiments, the plurality of channel layers 121 may each include a source / drain region. The source / drain region may include a semiconductor material doped with, for example, impurities.

[0024] In some embodiments, the plurality of channel layers 121 may each comprise Si (e.g., polycrystalline Si, doped Si, or single-crystal Si), Ge, Si-Ge, or an oxide semiconductor. In other embodiments, the plurality of channel layers 121 may each comprise an amorphous metal oxide, a polycrystalline metal oxide, or a combination thereof. For example, the plurality of channel layers 121 may comprise at least one of indium gallium (In-Ga)-based oxide (IGO), indium zinc (In-Zn)-based oxide (IZO), or indium gallium zinc (In-Ga-Zn)-based oxide (IGZO). For example, the channel layer 121 may include IGZO, tin (Sn)-IGZO, indium tungsten oxide (IWO) doped with tungsten, copper disulfide (CuS2), copper diselenide (CuSe2), tungsten diselenide (WSe2), indium gallium silicon oxide (InGaSiO), indium tin zinc oxide (InSnZnO), IZO, zinc oxide (ZnO), zinc titanium oxide (ZTO), yttrium doped zinc oxide (YZO), zinc tin oxide (ZnSnO), zinc oxynitride (ZnON), zirconium zinc tin oxide (ZrZnSnO), tin oxide (SnO), hafnium indium zinc oxide (HfInZnO), gallium zinc tin oxide (GaZnSnO), aluminum zinc tin oxide (AlZnSnO), ytterbium gallium zinc oxide (YbGaZnO), indium gallium oxide (InGaO), or combinations thereof. Furthermore, the channel layer 121 may include a two-dimensional semiconductor material. For example, two-dimensional semiconductor materials may include MoS2, MoSe2, WS2, graphene, carbon nanotubes, or combinations thereof.

[0025] In some embodiments, the stacked structure SS may further include a first interface layer 152, a dielectric layer 151, a metal layer 125, and a gate insulating layer 123, all disposed between the gate electrode 160 and the channel layer 121. For example, the dielectric layer 151 may be disposed between each of the plurality of channel layers 121 and a corresponding gate electrode 160. The metal layer 125 may be disposed between each of the plurality of channel layers 121 and the dielectric layer 151. The gate insulating layer 123 may be disposed between each of the plurality of channel layers 121 and the metal layer 125. The first interface layer 152 may be disposed between the gate electrode 160 and the dielectric layer 151.

[0026] In some embodiments, a plurality of first interface layers 152, a plurality of dielectric layers 151, a plurality of metal layers 125, and a plurality of gate insulating layers 123 may be provided, and each of the first interface layers 152 and dielectric layers 151, and each of the metal layers 125 and gate insulating layers 123, may be configured to correspond to a corresponding gate electrode 160 among a plurality of gate electrodes 160.

[0027] In some embodiments, a first interface layer 152 may surround a side surface of a corresponding gate electrode 160. A dielectric layer 151 may surround a side surface of a corresponding gate electrode 160 and may be spaced apart from the side surface of the corresponding gate electrode 160, with the first interface layer 152 situated between the dielectric layer 151 and the corresponding gate electrode 160. A metal layer 125 may surround a side surface of a corresponding gate electrode 160 and may be spaced apart from the side surface of the corresponding gate electrode 160, with the first interface layer 152 and the dielectric layer 151 situated between the metal layer 125 and the corresponding gate electrode 160. A gate insulating layer 123 may surround a side surface of a corresponding gate electrode 160 and may be spaced apart from the side surface of the corresponding gate electrode 160, with the first interface layer 152, the dielectric layer 151, and the metal layer 125 situated between the gate insulating layer 123 and the corresponding gate electrode 160.

[0028] In some embodiments, a first interface layer 152 may surround the side and bottom surfaces of the gate electrode 160. A dielectric layer 151 may surround the side and bottom surfaces of the gate electrode 160, and the first interface layer 152 is located between the dielectric layer 151 and a corresponding gate electrode 160. The bottom surface of the dielectric layer 151 may be in direct contact with the top surface of the etch stop film 105.

[0029] In some embodiments, dielectric layer 151 may include hafnium oxide (HfO2) having ferroelectric properties. Dielectric layer 151 may also include a dopant, wherein the dopant may include at least one selected from zirconium (Zr), silicon (Si), aluminum (Al), yttrium (Y), gadolinium (Gd), lanthanum (La), scandium (Sc), and strontium (Sr). Dielectric layer 151 may include, for example, HfO2, HfZnO, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or combinations thereof. For example, dielectric layer 151 may include HfO2 comprising a tetragonal phase, an orthorhombic phase, or a combination thereof.

[0030] In some embodiments, the metal layer 125 may surround the gate electrode 160 and at least a portion of the side surface of the dielectric layer 151. A gate electrode 160 may be surrounded by a plurality of metal layers 125. The plurality of metal layers 125 surrounding a gate electrode 160 may be spaced apart from each other in the vertical direction Z. The metal layer 125 may include at least one of, for example, a doped semiconductor material, a conductive metal nitride, a metal, a metal oxide, and a metal semiconductor compound.

[0031] In some embodiments, the gate insulating layer 123 may surround the gate electrode 160 in a manner that surrounds the outer surface of the metal layer 125. A gate electrode 160 may be surrounded by a plurality of gate insulating layers 123. The plurality of gate insulating layers 123 surrounding a gate electrode 160 may be spaced apart from each other in the vertical direction Z. The gate insulating layer 123 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. In other embodiments, the gate insulating layer 123 may each comprise a high-k material. The high-k material may have a dielectric constant of about 10 to about 25. The high-k material may include, but is not limited to, for example, HfO2, AlO, zirconium oxide (ZrO2), or combinations thereof.

[0032] In some embodiments, the first interface layer 152 may include molybdenum oxide (MoOx), niobium oxide (NbOx), titanium oxide (TiOx), tantalum oxide (TaOx), or a combination thereof.

[0033] In some embodiments, the gate electrode 160 may include doped polysilicon, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof. For example, the gate electrode 160 may include Mo, Nb, Ti, Ta, or a combination thereof.

[0034] In some embodiments, a gate electrode 160, a channel layer 121 surrounding a side surface of the gate electrode 160, and a first interface layer 152, a dielectric layer 151, a metal layer 125, and a gate insulating layer 123, each located between the channel layer 121 and a corresponding gate electrode 160, can constitute a ferroelectric field-effect transistor. Therefore, multiple ferroelectric field-effect transistors can be easily stacked in the vertical direction (e.g., vertical direction Z), thereby promoting high integration of semiconductor devices.

[0035] In semiconductor devices, according to a comparative example, the reliability of the semiconductor device decreases due to electric field concentration at the boundary between the gate electrode and the dielectric layer, while the electric field strength applied to the gate insulating layer decreases. Since the electric field is proportional to the curvature, the electric field strength applied to the boundary between the inner gate electrode and the dielectric layer may increase. Therefore, the robustness of the semiconductor device decreases.

[0036] The semiconductor device 100 of embodiments of the present invention can improve the durability and reliability of the semiconductor device by arranging a first interface layer 152 between the gate electrode 160 and the dielectric layer 151. In particular, by arranging the first interface layer 152 comprising MoOx, NbOx, TiOx, TaOx or combinations thereof, the dielectric constant K can be increased, thereby increasing the capacitance of the gate electrode 160. Furthermore, by reducing the electric field concentration at the boundary between the gate electrode 160 and the dielectric layer 151 and increasing the orthorhombic phase ratio of the dielectric layer 151, the polarization characteristics of the dielectric layer 151 can be improved without increasing the leakage current.

[0037] In another embodiment, the gate electrode 160 may include a first gate electrode and a second gate electrode. The outer surface of the first gate electrode may contact the interface layer, and the inner surface of the first gate electrode may contact the second gate electrode. That is, the second gate electrode may penetrate the first gate electrode. The first gate electrode may include Mo, Nb, or a combination thereof, and the second gate electrode may contain Ti.

[0038] In some embodiments, each of the plurality of conductive lines 140 can be electrically connected to adjacent channel layers 121 spaced apart from each other in the second horizontal direction Y. A corresponding gate electrode 160, a channel layer 121 surrounding the side surface of the corresponding gate electrode 160, and a first interface layer 152, a dielectric layer 151, a metal layer 125, and a gate insulating layer 123 respectively disposed between the channel layer 121 and the corresponding gate electrode 160 can constitute a ferroelectric field-effect transistor. For example, some of the conductive lines 140 can be used as bit lines, while other conductive lines 140 can be used as source lines.

[0039] In some embodiments, the stacked structure SS may further include a first insulating pattern 106, which is spaced apart from each other in the vertical direction Z and disposed between the plurality of channel layers 121. The first insulating pattern 106 and the plurality of channel layers 121 may be stacked alternately in the vertical direction Z. The plurality of channel layers 121 may be electrically separated (or insulated) from each other by the first insulating pattern 106. Each first insulating pattern 106 may surround a side surface of a corresponding gate electrode 160.

[0040] In some embodiments, the first insulating pattern 106 may extend in the vertical direction Z between adjacent gate insulating layers 123 and between adjacent metal layers 125. That is, the gate insulating layer 124 and the metal layer 125 may be arranged in the vertical direction Z between adjacent first insulating patterns 106. A dielectric layer 151 may extend between each first insulating pattern 106 and a corresponding gate electrode 160. The first insulating pattern 106 may contact the side surface of the dielectric layer 151. The first insulating pattern 106 may include, for example, silicon oxide.

[0041] In some embodiments, the sidewall insulating pattern 130 may be disposed on the etch stop film 105 and not located on the opposite side surface of the stacked structure SS. The sidewall insulating patterns 130 may be spaced apart from each other in a first horizontal direction X, with the stacked structure SS located between the sidewall insulating patterns 130. The sidewall insulating patterns 130 may extend in a vertical direction Z and a second horizontal direction Y. The sidewall insulating patterns 130 may extend in the vertical direction Z to cover the side surfaces of the plurality of conductive lines 140 and the first insulating pattern 106. The sidewall insulating pattern 130 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0042] Figures 4a to 4c Is along with Figure 2b The plan view corresponding to the B-B' line in the diagram is shown to illustrate a partial configuration of a semiconductor device according to some embodiments. Reference is made below. Figures 4a to 4c The components of the semiconductor devices 100a, 100b, and 100c described are similar to those in the reference reference. Figures 1 to 3 The components of the semiconductor device 100 are described. Therefore, the differences between them will be described primarily below.

[0043] Reference Figure 4a The stacked structure SS of the semiconductor device 100a in the embodiments of this disclosure (see Figure 1 The system may also include a second interface layer 252. The second interface layer 252 may be disposed between the dielectric layer 151 and the metal layer 125. The second interface layer 252 may surround a side surface of the dielectric layer 151. The second interface layer 252 may surround a side surface of a corresponding gate electrode 160 and may be spaced apart from the side surface of the corresponding gate electrode 160, with the first interface layer 152 and the dielectric layer 151 located between the second interface layer 252 and the corresponding gate electrode 160.

[0044] In some embodiments, the second interface layer 252 may include MoOx, NbOx, TiOx, TaOx, or a combination thereof.

[0045] In some embodiments, a plurality of second interface layers 252 may be provided to correspond to a plurality of gate electrodes 160 respectively.

[0046] Reference Figure 4b The stacked structure SS of the semiconductor device 100b in the embodiments of this disclosure (see Figure 1 The system may also include a third interface layer 352. The third interface layer 352 may be disposed between the metal layer 125 and the gate insulating layer 123. The third interface layer 352 may surround a side surface of the metal layer 125. The third interface layer 352 may surround a side surface of a corresponding gate electrode 160 and may be spaced apart from the side surface of the corresponding gate electrode 160, with the first interface layer 152, dielectric layer 151, and metal layer 125 located between the third interface layer 352 and the corresponding gate electrode 160.

[0047] In some embodiments, the third interface layer 352 may include MoOx, NbOx, TiOx, TaOx, or a combination thereof.

[0048] In some embodiments, a plurality of third interface layers 352 may be provided to correspond to a plurality of gate electrodes 160 respectively.

[0049] Reference Figure 4c The stacked structure SS of the semiconductor device 100c in the embodiments of this disclosure (see Figure 1 The system may also include a fourth interface layer 452. The fourth interface layer 452 may be disposed between the gate insulating layer 123 and the channel layer 121. The fourth interface layer 452 may surround a side surface of the gate insulating layer 123. The fourth interface layer 452 may surround a side surface of a corresponding gate electrode 160 and may be spaced apart from the side surface of the corresponding gate electrode 160, with the first interface layer 152, dielectric layer 151, metal layer 125, and gate insulating layer 123 located between the fourth interface layer 452 and the corresponding gate electrode 160.

[0050] In some embodiments, the fourth interface layer 452 may include MoOx, NbOx, TiOx, TaOx, or a combination thereof.

[0051] In some embodiments, a plurality of fourth interface layers 452 may be provided to correspond to a plurality of gate electrodes 160 respectively.

[0052] Reference Figures 4a to 4cSemiconductor devices 100a, 100b, and 100c are shown as including an interface layer (e.g., a second interface layer 252, a third interface layer 352, or a fourth interface layer 452) in addition to the first interface layer 152, but are not limited thereto. Semiconductor devices 100a, 100b, and 100c of embodiments of this disclosure may also include one or more interface layers in addition to the first interface layer 152. For example, semiconductor devices 100a, 100b, and 100c may together include the first interface layer 152, the second interface layer 252, and the third interface layer 352. Alternatively, semiconductor devices 100a, 100b, and 100c may together include the first interface layer 152, the second interface layer 252, the third interface layer 352, and the fourth interface layer 452.

[0053] The semiconductor devices 100a, 100b, and 100c of the embodiments of this disclosure can further improve their durability and reliability by providing a second interface layer 252, a third interface layer 352, and a fourth interface layer 452 therein. In particular, by arranging the second interface layer 252, the third interface layer 352, and the fourth interface layer 452, which include MoOx, NbOx, TiOx, TaOx, or combinations thereof, the electric field concentration at the boundary between the gate electrode 160 and the dielectric layer 151 can be reduced, and the orthorhombic crystal ratio of the dielectric layer 150 can be increased, thereby improving the polarization characteristics of the dielectric layer 152 without increasing the leakage current.

[0054] Figures 5a to 11b This is a diagram illustrating a method for manufacturing a semiconductor device according to some embodiments, wherein Figure 5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a , Figure 10a and Figure 11a It is a plan view illustrating a method for manufacturing semiconductor devices, and Figure 5b , Figure 6b , Figure 7b , Figure 8b , Figure 9b , Figure 10b and Figure 11b Is along with Figure 1 The line corresponding to A-A' in the diagram represents a cross-sectional view illustrating a method for manufacturing semiconductor devices. In the description... Figures 5a to 11b When referring to the above text, the reference can be omitted. Figures 1 to 3 The given descriptions are basically the same.

[0055] Reference Figure 5a and Figure 5bAn interlayer insulating film 103 and an etch stop film 105 can be sequentially formed on a substrate 101. A first insulating film and a second insulating film can be alternately stacked on the etch stop film 105. The first insulating film and the second insulating film can be alternately stacked in a vertical direction Z perpendicular to the top surface of the substrate 101. The first insulating film may include silicon oxide. The second insulating film may include a material that has etch selectivity relative to the first insulating film. For example, the second insulating film may include silicon nitride.

[0056] In some embodiments, a plurality of first trenches T1 may be formed in the first insulating film and the second insulating film. The first insulating film and the second insulating film may be anisotropically etched to form the first trenches T1. The first trenches T1 may penetrate the first insulating film and the second insulating film in the vertical direction Z and may expose the top surface of the etch stop film 105. When the first trenches T1 are formed, the first insulating film and the second insulating film may respectively form a first insulating pattern 106 and a second insulating pattern 108.

[0057] In some embodiments, the first trenches T1 may be spaced apart from each other in a first horizontal direction X parallel to the top surface of the substrate 101, and may extend in a second horizontal direction Y parallel to the top surface of the substrate 101. The second horizontal direction Y may intersect with the first horizontal direction X.

[0058] In some embodiments, a molding structure MS may be defined by a first trench T1. The molding structure MS may include a first insulating pattern 106 and a second insulating pattern 108 alternately stacked in the vertical direction Z. The first trenches T1 may be spaced apart from each other in a first horizontal direction X, the molding structure MS is located between the first trenches T1, and the first trenches T1 may extend along a second horizontal direction Y. The molding structure MS may extend along the second horizontal direction Y between the first trenches T1.

[0059] In some embodiments, first holes H1 may be formed within a molded structure MS. Each first hole H1 may extend in the vertical direction Z to pass through the molded structure MS and expose the top surface of the etch stop film 105. The first holes H1 may be spaced apart from each other in the second horizontal direction Y between the first trenches T1.

[0060] Reference Figure 6a and Figure 6bFirst sacrificial patterns 110 can be formed in the first trench T1. The first sacrificial patterns 110 can be formed to fill the first trench T1. The first sacrificial patterns 110 can be spaced apart from each other in a first horizontal direction X, with the molded structure MS located between the first sacrificial patterns 110, and the first sacrificial patterns 110 can extend along a second horizontal direction Y. The first sacrificial patterns 110 can cover both sides of the molded structure MS. The first sacrificial patterns 110 can include a material with etch selectivity for the second insulating pattern 108.

[0061] In some embodiments, the first hole H1 may expose the side surfaces of the first insulating pattern 106 and the second insulating pattern 108 of the molded structure MS. The exposed side surfaces of the second insulating pattern 108 may be selectively recessed. Thus, a first recessed region R1 may be formed in the molded structure MS. An etching process with etch selectivity may be performed on the second insulating pattern 108 to remove a portion of the exposed side surfaces of the second insulating pattern 108, thereby forming the first recessed region R1. The first recessed regions R1 may be spaced apart from each other in the vertical direction Z and may each be located between the first insulating patterns 106. Each first recessed region R1 may be formed to surround the first hole H1 in a planar view (e.g., in the horizontal direction).

[0062] Reference Figure 7a and Figure 7b A channel layer 121, a gate insulating layer 123, and a metal layer 125 can be sequentially formed in the first recessed region R1. The channel layer 121, gate insulating layer 123, and metal layer 125 can fill a portion of the first recessed region R1. For example, the channel layer 121 can be formed to cover the side surface of the second insulating pattern 108 and fill the first recessed region R1. The gate insulating layer 123 can be formed to cover the side surface of the channel layer 121 and fill the first recessed region R1. The metal layer 125 can be formed to cover the side surface of the gate insulating layer 123 and fill the first recessed region R1.

[0063] Reference Figure 8a and Figure 8b A second sacrificial pattern 120 can be formed in the first hole H1. The second sacrificial pattern 120 can be formed to fill the first hole H1. The second sacrificial patterns 120 can be spaced apart from each other in the second horizontal direction Y within the molded structure MS. The second sacrificial pattern 120 can include a material that has etch selectivity relative to the second insulating pattern 108.

[0064] The first sacrificial pattern 110 can then be removed from the first trench T1. With the removal of the first sacrificial pattern 110, the first trench T1 can expose the side surfaces of the first insulating pattern 106 and the second insulating pattern 108 of the molded structure MS. The exposed side surfaces of the second insulating pattern 108 can be selectively recessed. Therefore, a second recessed region R2 can be formed in the molded structure MS. An etching process with etch selectivity can be performed on the second insulating pattern 108 to remove a portion of the exposed side surfaces of the second insulating pattern 108, thereby forming the second recessed region R2. The second recessed region R2 can expose the side surfaces of the channel layer 121. The second recessed regions R2 can be spaced apart from each other in the vertical direction Z and can each be located between the first insulating patterns 106. Each second recessed region R2 can have a linear shape extending along the second horizontal direction Y.

[0065] Reference Figure 9a and Figure 9b Conductive lines 140 can be formed in the second recessed region R2. Multiple conductive lines 140 can each be formed in a corresponding second recessed region R2. The conductive lines 140 can fill the second recessed region R2 and contact the side surface of the channel layer 121.

[0066] In some embodiments, the conductive lines 140 may be spaced apart from each other in the vertical direction Z. First insulating patterns 106 may each be located between the conductive lines 140. Multiple conductive lines 140 may be spaced apart from each other in the first horizontal direction X and may extend along the second horizontal direction Y.

[0067] Then, sidewall insulating patterns 130 can be formed in the first trench T1. The sidewall insulating patterns 130 can be formed to fill the first trench T1 respectively. The sidewall insulating patterns 130 can be spaced apart from each other in the first horizontal direction X, with the molded structure MS located between the sidewall insulating patterns 130. The sidewall insulating patterns 130 can extend in the vertical direction Z to cover the side surface of the conductive line 140. The sidewall insulating patterns 130 can have a linear shape extending in the second horizontal direction Y. The second sacrificial pattern 120 can then be removed from the first hole H1.

[0068] Reference Figure 10a and Figure 10b A dielectric layer 151 can be formed in each first hole H1. The dielectric layer 151 can conformally cover the inner surface of the first hole H1. The dielectric layer 151 can cover the side surface of the metal layer 125, the side surface of the first insulating pattern 106, and the top surface of the etch stop film 105.

[0069] Reference Figure 11a and Figure 11bA first interface layer 152 can be formed in each first hole H1. The first interface layer 152 can conformally cover the inner and bottom surfaces of the dielectric layer 151 while filling the first hole H1. The process for forming the first interface layer 152 can include, but is not limited to, atomic layer deposition (ALD). After forming the first interface layer 152, an additional heat treatment process can be performed. The heat treatment process can increase the formation of the ferroelectric phase in the dielectric layer 151.

[0070] Refer again Figure 2a and Figure 2b A gate electrode 160 can be formed in the first hole H1. The gate electrode 160 can cover the first interface layer 152 while filling the first hole H1. Even after the gate electrode 160 is formed, an additional heat treatment process can be performed. Therefore, the gate electrode 160, the first interface layer 152, the dielectric layer 151, the metal layer 125, the gate insulating layer 123, the channel layer 121, the conductive line 140, and the first insulating pattern 106 can constitute a stacked structure SS.

[0071] Figure 12 This is a graph showing the correlation between the leakage current of a field-effect transistor and the thickness of the interface layer.

[0072] Reference Figure 12 The semiconductor device 100 of the present disclosure has a larger capacitance than the semiconductor device according to the comparative example at the same leakage current. Therefore, it can be seen that the equivalent oxide thickness (Tox) of the first interface layer 152 is reduced. In this case, the semiconductor device according to the comparative example includes a gate electrode comprising Ti and an interface layer comprising TiOx, while the semiconductor device 100 of the present disclosure may include a gate electrode 160 comprising Mo and a first interface layer 152 comprising MoOx. That is, in the case where the field-effect transistor includes a gate electrode 160 comprising Mo and a first interface layer 152 comprising MoOx, the dielectric constant K can be increased, thereby increasing the capacitance of the gate electrode 160.

[0073] While non-limiting exemplary embodiments of the invention have been described above with reference to the accompanying drawings, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device, the semiconductor device comprising: Substrate; The conductive lines are spaced apart from each other in a first horizontal direction parallel to the top surface of the substrate, and the conductive lines extend along a second horizontal direction intersecting the first horizontal direction. At least one gate electrode, the at least one gate electrode being located between the conductive lines in the first horizontal direction, the at least one gate electrode extending in a vertical direction perpendicular to the substrate; A channel layer surrounding the at least one gate electrode and spaced apart from each other in the vertical direction; A dielectric layer located between the channel layer and the at least one gate electrode; A metal layer located between the channel layer and the dielectric layer; A gate insulating layer, wherein the gate insulating layer is located between the channel layer and the metal layer; as well as At least one interface layer surrounding the at least one gate electrode, the at least one interface layer being located between the channel layer and the at least one gate electrode.

2. The semiconductor device according to claim 1, wherein, The at least one interface layer includes a first interface layer located between the at least one gate electrode and the dielectric layer, and extending along the vertical direction.

3. The semiconductor device according to claim 2, wherein, The at least one interface layer further includes a second interface layer, which is located between the dielectric layer and the metal layer.

4. The semiconductor device according to claim 2, wherein, The at least one interface layer further includes a second interface layer, which is located between the metal layer and the gate insulating layer.

5. The semiconductor device according to claim 2, wherein, The at least one interface layer further includes a second interface layer, which is located between the gate insulating layer and the channel layer.

6. The semiconductor device according to claim 1, wherein, The at least one interface layer includes at least one of molybdenum oxide (MoOx), niobium oxide (NbOx), titanium oxide (TiOx), and tantalum oxide (TaOx).

7. The semiconductor device according to claim 1, wherein, The at least one gate electrode comprises at least one of molybdenum (Mo), niobium (Nb), titanium (Ti), and tantalum (Ta).

8. The semiconductor device according to claim 7, wherein, The at least one gate electrode is a plurality of gate electrodes, the plurality of gate electrodes including: A first gate electrode, the first gate electrode contacting the at least one interface layer; and The second gate electrode passes through the first gate electrode.

9. The semiconductor device according to claim 8, wherein, The first gate electrode comprises Mo or Nb, and the second gate electrode comprises Ti.

10. The semiconductor device according to claim 1, wherein, The dielectric layer comprises a ferroelectric material.

11. A semiconductor device, the semiconductor device comprising: Substrate; A gate electrode located on the substrate, the gate electrode extending in a vertical direction; A channel layer surrounding the gate electrode and spaced apart from each other in the vertical direction; A dielectric layer located between the channel layer and the gate electrode; A metal layer located between the channel layer and the dielectric layer; A gate insulating layer, wherein the gate insulating layer is located between the channel layer and the metal layer; as well as At least one interface layer surrounds the gate electrode and is located between the channel layer and the gate electrode. The at least one interface layer includes at least one of molybdenum oxide (MoOx), niobium oxide (NbOx), titanium oxide (TiOx), and tantalum oxide (TaOx).

12. The semiconductor device according to claim 11, wherein, The at least one interface layer includes a first interface layer located between the gate electrode and the dielectric layer, the first interface layer extending along the vertical direction.

13. The semiconductor device according to claim 12, wherein, The first interface layer surrounds the side and bottom surfaces of the gate electrode.

14. The semiconductor device according to claim 12, wherein, The at least one interface layer further includes at least one of the following second interface layers: A second interface layer located between the dielectric layer and the metal layer; or A second interface layer located between the metal layer and the gate insulating layer; or A second interface layer located between the gate insulating layer and at least one of the channel layers.

15. The semiconductor device according to claim 14, wherein, The at least one second interface layer surrounds the gate electrode.

16. The semiconductor device according to claim 11, wherein, The gate electrode comprises at least one of molybdenum (Mo), niobium (Nb), titanium (Ti), and tantalum (Ta).

17. A semiconductor device, the semiconductor device comprising: Substrate; The conductive lines are spaced apart from each other in a first horizontal direction parallel to the top surface of the substrate and in a vertical direction perpendicular to the top surface of the substrate, and the conductive lines extend along a second horizontal direction intersecting the first horizontal direction. A gate electrode, wherein the gate electrode is located between the conductive lines in the first horizontal direction and extends along the vertical direction; A channel layer surrounding the gate electrode and spaced apart from each other in the vertical direction; A dielectric layer located between the channel layer and the gate electrode; A metal layer located between the channel layer and the dielectric layer; A gate insulating layer, wherein the gate insulating layer is located between the channel layer and the metal layer; as well as A first interface layer is located between the gate electrode and the dielectric layer and extends along the vertical direction. The first interface layer includes at least one of molybdenum oxide (MoOx), niobium oxide (NbOx), titanium oxide (TiOx), and tantalum oxide (TaOx).

18. The semiconductor device of claim 17, further comprising at least one second interface layer selected from the following second interface layers: A second interface layer located between the dielectric layer and the metal layer; or A second interface layer located between the metal layer and the gate insulating layer; or A second interface layer located between the gate insulating layer and at least one of the channel layers.

19. The semiconductor device according to claim 18, wherein, The at least one second interface layer includes at least one of molybdenum oxide (MoOx), niobium oxide (NbOx), titanium oxide (TiOx), and tantalum oxide (TaOx).

20. The semiconductor device according to claim 17, wherein, The gate electrode comprises at least one of molybdenum (Mo), niobium (Nb), titanium (Ti), and tantalum (Ta).

Images