Memory and preparation method thereof

Abstract

The invention provides a memory and a preparation method thereof, and the method comprises the steps: S1, providing a substrate which comprises a substrate, a first stacking layer and a second stacking layer, the first stacking layer comprises a plurality of stacked first sacrificial layers and first isolation layers located between two adjacent first sacrificial layers, the second stack layer comprises two stacked second isolation layers and a second sacrificial layer located between the two second isolation layers; s2, a first through hole is formed through the first side, the first through hole penetrates through the first stacking layer and the second stacking layer, a conductive column and a semiconductor material layer are formed in the first through hole, the conductive column penetrates through the first stacking layer, and the semiconductor material layer penetrates through the second sacrificial layer; the conductive column is connected with the semiconductor material layer, and the connected surface is located between the second sacrificial layer and the first stacking layer; and S3, replacing the first sacrificial layer with a storage film layer and a conductive wire coated by the storage film layer, and replacing the second sacrificial layer with a grid selection line. The memory density of the memory can be improved.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and in particular to a memory and a method for fabricating the same. Background Technology

[0002] Currently, MRAM (Magnetoresistive Random Access Memory) is mainly a planar structure, with one transistor controlling one memory cell, resulting in extremely low storage density and making it impossible to achieve ultra-large-scale integration. Summary of the Invention

[0003] One objective of this disclosure is to propose a memory and a method for fabricating the same, which improves storage density to achieve ultra-large-scale integration of memory.

[0004] The first aspect of this disclosure provides a method for fabricating a memory, comprising: Step S1: Provide a substrate having opposing first and second sides, the substrate including a substrate, a first stacked layer and a second stacked layer; The first stacked layer and the second stacked layer are stacked on a first side of the substrate. The first stacked layer includes multiple stacked first sacrificial layers and a first isolation layer located between two adjacent first sacrificial layers. The second stacked layer includes two stacked second isolation layers and a second sacrificial layer located between two second isolation layers. Step S2: A first through-hole is formed through the first side. The first through-hole penetrates the first stacked layer and the second stacked layer. A conductive pillar and a semiconductor material layer are formed in the first through-hole. The conductive pillar penetrates the first stacked layer, and the semiconductor material layer penetrates the second sacrificial layer. The conductive pillar is in contact with the semiconductor material layer, and the surface of the contact is located between the second sacrificial layer and the first stacked layer. Step S3: Replace the first sacrificial layer with a storage film layer and a conductive line covered by the storage film layer, wherein the storage film layer is located at least between the conductive line and the conductive pillar, and replace the second sacrificial layer with a gate select line.

[0005] A first aspect of this disclosure provides a memory, comprising: A substrate, and a storage block located on the substrate; The memory block includes a first stacked layer and a second stacked layer. The first stacked layer includes multiple layers of conductive lines and a first isolation layer located between two adjacent conductive lines. The second stacked layer includes two layers of second isolation layers and a gate select line located between the two layers of second isolation layers. A first via is formed through the memory block, and a conductive pillar and a semiconductor structure are formed in the first via. The conductive pillar penetrates the first stacked layer, and the semiconductor structure penetrates the gate select line. The surface of the conductive pillar in contact with the semiconductor structure is located between the gate select line and the first stacked layer. The semiconductor structure includes a semiconductor material layer, and the memory block also includes a gate dielectric layer located between the semiconductor material layer and the gate select line. The first stacked layer further includes a storage film layer comprising a first portion located between the conductive pillar and the conductive line, and a second portion extending from the first portion along the first isolation layer in a direction parallel to the substrate.

[0006] The technical solution provided in this disclosure can achieve the following beneficial effects: By first fabricating two stacked layers in step S1, and then forming the first via through a vertical via etching in step S2, compared to separately etching the first stacked layer to form a conductive via filling the conductive pillars, and separately etching the second stacked layer to form a channel via for the semiconductor material layer, one less photolithography step can be achieved, and alignment can be ensured without needing to align the vias. Furthermore, fabricating the storage film layer from the horizontal slot reduces mutual interference between storage film layers and minimizes damage to the storage module when the first sacrificial layer is removed. In the memory, storage cells can be arranged in a 3D vertical direction, and one transistor can control a row of storage cells in the vertical direction, thereby increasing the storage density of storage cells and enabling ultra-large-scale integration of the memory.

[0007] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this disclosure. Attached Figure Description

[0008] The above and other objects, features and advantages of this disclosure will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0009] Figures 1 to 22 These are schematic diagrams of the structures formed after different preparation steps in some embodiments of this disclosure.

[0010] The attached figures are labeled as follows: 10. Memory block; 100. Substrate; 101. First stacked layer; 1011. First sacrificial layer; 1012. First isolation layer; 102. Second stacked layer; 1021. Second sacrificial layer; 1022. Second isolation layer; 103. First via; 104. Conductive pillar; 105. Semiconductor material layer; 106. Mask structure layer; 107. Gate select line; 108. Memory film layer; 109. Conductive line; 110. Conductive material; 111. Polysilicon; 112. Insulating protective layer; 113. First opening; 114. First receiving trench; 115. First conductive material layer; 116. Second opening; 117. Second receiving trench; 118. Gate dielectric layer; 119. Insulating dielectric layer; 120. Second conductive material layer. Detailed Implementation

[0011] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art.

[0012] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0013] The present disclosure will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present disclosure described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0014] RAM (Random Access Memory) is a commonly used type of memory, which can include non-volatile RAMs such as MRAM, ReRAM (Resistive Random Access Memory), and FeRAM (Ferroelectric Random Access Memory).

[0015] MRAM combines the high-speed read / write capabilities of SRAM (Static Random Access Memory) with the high integration density of DRAM (Dynamic Random Access Memory). It can be rewritten virtually an unlimited number of times, meaning MRAM has the potential to become a general-purpose memory, combining the density of DRAM with the speed of SRAM while maintaining non-volatility and high energy efficiency. Furthermore, MRAM is resistant to high radiation, can operate under extreme temperature conditions, and is tamper-proof.

[0016] In MRAM, data is stored using magnetic storage cells, which can consist of two magnetic plates separated by a thin insulating layer. Each plate remains magnetized; this structure is called a magnetic tunnel junction (MTJ). One of the magnetic plates is a permanent magnet with a specific polarity set during manufacturing; the magnetic susceptibility of the other plate can change depending on the data being stored; this is called a free layer. When an external electric field magnetizes the free layer, different magnetization directions result in significant differences in its tunneling current. When the magnetization directions are the same, its resistance is lowest, representing a low-resistance state, allowing for the storage of 0. When the magnetization directions are opposite, its tunneling current is highest, allowing for the storage of the digit 1.

[0017] However, since MRAM is mainly designed as a planar structure and there is a strong self-coupling between adjacent magnetic particles, a large distance is required between memory cells. This makes it impossible to achieve ultra-large-scale integration and limits its application in the memory field.

[0018] Based on this, this disclosure provides a method for fabricating a memory, which can be used to fabricate MRAM, but is not limited thereto, and can also be used to fabricate ReRAM and FeRAM, etc. Specifically, in the embodiments of this disclosure, the method for fabricating the memory may include steps S1, S2 and S3, and the details of steps S1, S2 and S3 are as follows.

[0019] In step S1: A substrate is provided. The substrate has opposing first and second sides. The first and second sides may be opposing sides of the substrate in the thickness direction. (Referring to...) Figure 1 As shown, the substrate may include a substrate 100, a first stacked layer 101 and a second stacked layer 102, wherein the first stacked layer 101 and the second stacked layer 102 may be stacked on a first side of the substrate 100.

[0020] In a memory device, the substrate 100 is the basic material layer constituting the entire device, providing physical support for subsequent process steps and having a significant impact on the overall performance of the device. Details will not be elaborated here. For example, the substrate 100 in this embodiment can be a silicon substrate, on which silicon dioxide or other materials can be deposited or thermally grown. However, it is not limited to this; the substrate 100 can also be a single-layer structure or a multi-layer stacked structure of other materials, depending on the specific requirements of the memory. The specific structure of the substrate 100 will not be described in detail here.

[0021] refer to Figure 1 As shown, the first stacked layer 101 may include multiple layers of first sacrificial layers 1011 and a first isolation layer 1012 located between two adjacent first sacrificial layers 1011. The first sacrificial layer 1011 may be subsequently etched laterally and replaced with conductive lines, while the first isolation layer 1012 may be retained when the first sacrificial layer 1011 is subsequently etched laterally and used as a subsequent insulating layer to prevent short circuits between conductive lines.

[0022] In some embodiments, the material of the first isolation layer 1012 may include silicon oxide, that is, the first isolation layer 1012 may be made of silicon oxide material; the material of the first sacrificial layer 1011 may include silicon nitride, that is, the first sacrificial layer 1011 may be made of silicon nitride material.

[0023] refer to Figure 1 As shown, the second stacked layer 102 includes two stacked second isolation layers 1022 and a second sacrificial layer 1021 located between the two second isolation layers 1022. This second sacrificial layer 1021 can be subsequently etched laterally and replaced as a gate select line, while the second isolation layer 1022 can be retained during the subsequent lateral etching of the second sacrificial layer 1021 and used as a subsequent insulating layer. In some embodiments, the material of the second isolation layer 1022 may include silicon oxide, that is, the second isolation layer 1022 may be made of silicon oxide material; the material of the second sacrificial layer 1021 may include silicon germanium, that is, the first sacrificial layer 1011 may be made of silicon germanium material.

[0024] The first sacrificial layer and the second sacrificial layer are made of different materials. Therefore, the steps of replacing the first sacrificial layer with a storage film layer and the conductive line covered by the storage film layer, and replacing the second sacrificial layer with a gate select line can be achieved by a simple process. For example, the first sacrificial layer can be removed first to replace it with a storage film layer and the conductive line covered by the storage film layer, and then the second sacrificial layer can be removed to replace it with a gate select line.

[0025] The materials of the first sacrificial layer and the second sacrificial layer are different from those of the first isolation layer and the second isolation layer, so that the first isolation layer and the second isolation layer can be removed without damage or with reduced damage when removing the first sacrificial layer and removing the second sacrificial layer to perform the corresponding replacement steps.

[0026] The materials for the first sacrificial layer, the second sacrificial layer, the first isolation layer, and the second isolation layer can be set according to actual needs.

[0027] In step S2, a structure such as can be formed on the first side of the substrate. Figure 3 The first through-hole 103 shown penetrates the first stacked layer 101 and the second stacked layer 102, as shown in the reference. Figure 7 As shown, a conductive pillar 104 and a semiconductor material layer 105 are formed in the first via 103. The conductive pillar 104 penetrates the first stacked layer 101, and the semiconductor material layer 105 penetrates the second sacrificial layer 1021. The conductive pillar 104 and the semiconductor material layer 105 are in contact, and the contacting surfaces are located between the second sacrificial layer 1021 and the first stacked layer 101.

[0028] In this embodiment, the first side of the substrate may refer to the upper surface of the substrate, i.e., the fabrication side of the device. For example, in step S2, the method for fabricating the first via 103 may include: first forming a mask structure layer 106 on the first side of the substrate, referring to... Figure 2 The mask structure layer 106 may include a sequentially stacked amorphous carbon hard mask layer (APF, Advanced Patterning Film), a silicon oxynitride (SiON) layer, and an organic photoresist layer (PR). Then, the organic photoresist layer is exposed and developed to form an initial pattern. A first etching is then performed, for example using oxygen (O2) / carbon tetrafluoride (CF4) gas, to transfer the pattern from the organic photoresist layer to the silicon oxynitride layer. A second etching is then performed, for example using oxygen plasma to transfer the pattern to the amorphous carbon hard mask layer. A third etching is then performed, for example using fluorine-based gases such as C4F8 (octafluoro-2-butene) or CF4, utilizing the high selectivity of the amorphous carbon hard mask layer to precisely etch the underlying stacked structure, forming a first via 103 penetrating the first stacked layer 101 and the second stacked layer 102. (Refer to...) Figure 3 Since the stacked structure includes multiple material layers of different materials, the etching gas can be dynamically switched for different material layers during etching. The corresponding etching gas can be used to etch and form the first via 103 according to the materials of the first sacrificial layer, the second sacrificial layer, the first isolation layer, and the second isolation layer.

[0029] In step S2, after forming the first via 103, the remaining material of the mask structure layer 106 can be removed first, and then a conductive pillar 104 penetrating the first stacked layer 101 and a semiconductor material layer 105 penetrating the second sacrificial layer 1021 can be formed within the first via 103. Subsequently, the second sacrificial layer 1021 is replaced with a gate select line 107 (see reference). Figure 22 Afterwards, the semiconductor material layer 105 can serve as the channel of the transistor to realize the switching function of the transistor under the control of the gate select line 107. This semiconductor material layer 105 may include materials such as polysilicon. Subsequently, the first sacrificial layer 1011 is replaced by the storage film layer 108 and the conductive line 109 covered by the storage film layer 108 (see reference). Figure 22 Afterwards, the conductive post 104 can serve as an interconnect structure and reliably connect to the semiconductor material layer 105. The conductive post 104 may include a highly conductive material such as tungsten to reduce resistance. The contact surface between the conductive post 104 and the semiconductor material layer 105 may be located between the second sacrificial layer 1021 and the first stacked layer 101. The contact between the two between the second sacrificial layer 1021 and the first stacked layer 101 can reduce long-distance high-resistance paths, significantly reduce contact resistance and RC (Resistance-Capacitance) delay, and also prevent the channel from extending to the first stacked layer 101, reducing leakage current and interference.

[0030] In some embodiments, the first stacked layer 101 may be located between the substrate 100 and the second stacked layer 102. That is, during the fabrication process, the first stacked layer 101 is first formed on the substrate 100, and then the second stacked layer 102 is fabricated. The second stacked layer 102 is located on top of the first stacked layer 101. In this way, the conductive pillar 104 fabricated subsequently is also formed in the first via 103 before the semiconductor material layer 105. That is, the semiconductor material layer 105 is formed on top of the conductive pillar 104. Since the semiconductor material layer 105 is used to form the channel of the transistor, in this embodiment, the transistor is formed on top of the first via 103. Compared with the solution of forming the transistor at the bottom of the first via 103, it is not necessary to operate deep into the high aspect ratio hole. The fabrication is simple, uniform, has a high yield, and low cost. It also helps to protect the semiconductor material layer 105 from the process of fabricating the electrode pillar structure, thereby improving the reliability of the transistor.

[0031] For example, after fabricating the first via 103 and removing the remaining mask structure layer 106: (See reference...) Figure 4As shown, a conductive material 110 can be deposited first, filling the first via 103 and covering the surface of the second stacked layer 102 away from the first stacked layer 101. Then, CMP (Chemical Mechanical Polishing) technology can be used to remove the conductive material 110 covering the surface of the second stacked layer 102. Next, the conductive material 110 within the first via 103 is etched back to the position between the second sacrificial layer 1021 and the first stacked layer 101 to form a conductive pillar 104. (Refer to...) Figure 5 As shown, the top surface of the conductive pillar 104 can be located between the second sacrificial layer 1021 and the first stacked layer 101. Then, polysilicon 111 is deposited, filling the area in the first via 103 not filled by the conductive pillar 104 and covering the surface of the second stacked layer 102 away from the first stacked layer 101. Afterwards, CMP (Chemical Mechanical Polishing) technology can be used to remove the polysilicon 111 covering the surface of the second stacked layer 102 to form a semiconductor material layer 105 filling the first via 103. (Refer to...) Figure 7 As shown.

[0032] The conductive material 110 mentioned above can be a single conductive material or multiple conductive materials 110. For example, titanium nitride (TiN) can be deposited first, followed by the deposition of metallic tungsten to complete the deposition of conductive material 110. By depositing titanium nitride before metallic tungsten, the conductivity can be guaranteed, and the mutual diffusion between metallic tungsten and the materials in the first stacked layer 101 and the second stacked layer 102 can be effectively prevented. It can also improve the adhesion between metallic tungsten and the first stacked layer 101 and the second stacked layer 102, and reduce the risk of metallic tungsten falling off in chemical polishing or thermal cycling technology. In addition, titanium nitride has a high surface energy, which can provide excellent nucleation sites for metallic tungsten, ensuring seamless and void-free conformal filling.

[0033] In some embodiments, in order to reduce the impact of subsequent processes on the semiconductor material layer 105 and conductive pillar 104 within the first via 103, after the semiconductor material layer 105 is fabricated and before the subsequent step S3 is performed, refer to Figure 8 As shown, an insulating protective layer 112 can be formed first, which can cover the top surface of the second stacked layer 102 and encapsulate the semiconductor material layer 105 and the conductive pillar 104 in the first through hole 103.

[0034] The insulating protective layer 112 can be made of silicon dioxide, but it is not limited to this. It can also be made of other insulating materials, as long as it is not severely etched in subsequent process steps and can protect the semiconductor material layer 105 and the conductive pillar 104.

[0035] In step S3, refer to Figure 22 As shown, the first sacrificial layer 1011 is replaced by a storage film layer 108 and a conductive line 109 covered by the storage film layer 108, with the storage film layer 108 located at least between the conductive line 109 and the conductive pillar 104. The second sacrificial layer 1021 is replaced by a gate select line 107. After replacing the first sacrificial layer 1011 with the storage film layer 108 and the conductive line 109 covered by the storage film layer 108, this first stacked layer 101 can be formed into a storage stacked structure. The region in the storage film layer 108 located between the conductive line 109 and the conductive pillar 104 can be a storage region. After replacing the second sacrificial layer 1021 with the gate select line 107, the gate select line 107 can connect the semiconductor material layers 105 of a plurality of transistors arranged in the extension direction of the second stacked layer 102.

[0036] In some embodiments, the materials of the first sacrificial layer 1011 and the second sacrificial layer 1021 are different. Step S3 may include steps S31 and S32. For details of steps S31 and S32, please refer to the following content.

[0037] In step S31, refer to Figures 9 to 11 As shown, a first opening 113 is formed from a first side of the substrate, penetrating the first stacked layer 101 and the second stacked layer 102. A first sacrificial layer 1011 is removed through the first opening 113 to form a first receiving groove 114 between adjacent first isolation layers 1012 in the stacking direction. Subsequently, a storage film material layer and a conductive line 109 are formed sequentially. The storage film material layer is conformally formed on the surfaces of the first receiving groove 114 and the first opening 113. The storage film material layer includes a plurality of storage film layers 108. The conductive line 109 is formed in the first receiving groove 114 and located on the side of the storage film layer 108 away from the surface of the first receiving groove 114. The storage film layer 108 may include a first portion located between the conductive line 109 and the conductive post 104, and a second portion extending from the first portion along the surface of the first isolation layer 1012.

[0038] It should be noted that, in this embodiment, the storage film material layer conformally formed on the surfaces of the first receiving groove 114 and the first opening 113 means that the storage film material layer can cover the upper surface of the first receiving groove 114 (i.e., the lower surface of the upper first isolation layer 1012 in two adjacent first isolation layers 1012), cover the lower surface of the first receiving groove 114 (i.e., the upper surface of the lower first isolation layer 1012 in two adjacent first isolation layers 1012), cover the surface of the conductive post 104 surrounded by the first receiving groove 114, and cover the surface of the first opening 113 (i.e., the opening sidewall formed after the first opening 113 is opened).

[0039] The storage membrane material layer includes a storage membrane layer 108, which corresponds one-to-one with the first receiving groove 114.

[0040] The first part of the storage film layer 108 covers the portion of the conductive post 104 surrounded by the first receiving groove 114, and this first part is located between the conductive line 109 and the conductive post 104. The second part of the storage film layer 108 includes the portion of the storage film layer 108 covering the upper surface of the first receiving groove 114 and the portion covering the lower surface of the first receiving groove 114. The portion of the storage film layer 108 covering the upper surface of the first receiving groove 114 also covers the surface of the conductive line 109 away from the substrate 100, and the portion of the storage film layer 108 covering the lower surface of the first receiving groove 114 also covers the surface of the conductive line 109 close to the substrate 100.

[0041] In this embodiment, the first portion of the storage film layer 108 is located within the first receiving groove 114, sandwiched between the conductive line 109 and the conductive post 104, serving as the core of the storage unit for data storage. In other words, the first portion of the storage film layer 108 can be a storage section. The second portion of the storage film layer 108 is located within the first receiving groove 114 and extends laterally from the first portion, covering the horizontal surface of the first isolation layer 1012. Located in the dielectric region between adjacent conductive lines 109, it does not participate in charge storage. The second portion is used to ensure film continuity and improve deposition defects.

[0042] It should be understood that, as mentioned in this disclosure, the upper surface or top surface refers to the surface of the structure or tank away from the substrate 100, the lower surface or bottom surface refers to the surface of the structure or tank close to the substrate 100, the upper layer refers to the structural layer away from the substrate 100, and the lower layer refers to the structural layer close to the substrate 100.

[0043] For example, in step S31, the method for preparing the first opening 113 may include: referring to... Figure 12 As shown, a mask structure layer 106 is first formed on the surface of the insulating protective layer 112 away from the substrate, and then the first stacked layer 101 and the second stacked layer 102 are etched to form a first opening 113. The preparation method of the first opening 113 can refer to the preparation method of the first through hole 103 described above, and will not be repeated here.

[0044] It should be understood that in this embodiment of the present disclosure, the location of the first opening 113 is different from the location of the first through hole 103.

[0045] For example, when the first sacrificial layer 1011 is made of silicon nitride and the first isolation layer 1012 is made of silicon oxide, the method for forming the first accommodating trench 114 in step S31 may include: introducing an etchant, such as H3PO4 (phosphoric acid), through the first opening 113 to selectively remove silicon nitride and retain silicon oxide, that is: selectively removing the first sacrificial layer 1011 and retaining the first isolation layer 1012 to form a gap between each pair of first isolation layers 1012, that is: the first accommodating trench 114.

[0046] It should be understood that since this step is for forming the first receiving groove 114, in order to avoid affecting the second sacrificial layer 1021, the material design of the second sacrificial layer 1021 needs to be different from that of the first sacrificial layer 1011. For example, when the first sacrificial layer 1011 is silicon nitride, the second sacrificial layer 1021 can be silicon germanium, but it is not limited to this. The first sacrificial layer 1011 and the second sacrificial layer 1021 can also be other combinations.

[0047] After the first opening 113 is made and before the first receiving groove 114 is made, the remaining mask structure layer 106 on the upper surface of the insulating protective layer 112 can be removed.

[0048] For example, in step S31, the method for forming the storage film layer 108 may include: conformally forming a storage film material layer on the surface of the first receiving groove 114 and the surface of the first opening 113 through the first opening 113, the storage film material layer including the storage film layer 108, as shown in the reference. Figure 13 As shown. For example, atomic layer deposition (ALD) technology can be used to diffuse the reaction precursor inward from the first opening 113 to achieve conformal coverage. It should be noted that conformal coverage is a key term in thin film deposition, used to describe the ability of a thin film to uniformly, continuously, and conformally cover the surface of a complex three-dimensional structure.

[0049] In the process of forming the storage film layer 108, the storage film material layer is not only conformally formed on the surfaces of the first receiving groove 114 and the first opening 113, but also formed on the surface of the insulating protective layer 112 away from the substrate 100.

[0050] In some embodiments, the storage film layer 108 may include one of a magnetic tunnel junction, a ferroelectric storage layer, and a resistive switching storage layer. That is, the memory mentioned in this embodiment may correspond to one of MRAM, FeRAM, and ReRAM. However, it is not limited to this. In addition to the magnetic tunnel junction, ferroelectric storage layer, and resistive switching storage layer mentioned above, the storage film layer 108 may also be a phase-change storage layer. When the storage film layer 108 is a phase-change storage layer, the memory may be a phase-change memory (PRAM).

[0051] It should be noted that the storage film layer 108 may include one of a magnetic tunnel junction, a ferroelectric storage layer, a resistive switching storage layer, and a phase change storage layer. Correspondingly, the storage film material layer may include one of a magnetic tunnel junction, a ferroelectric storage layer, a resistive switching storage layer, and a phase change storage layer.

[0052] It should also be noted that a storage film material layer is conformally formed on the surface of the first receiving groove 114 and the surface of the first opening 113. The storage film material layer includes a magnetic tunnel junction, which means that a permanent magnet layer, an insulating layer and a free layer are conformally formed sequentially on the surface of the first receiving groove 114 and the surface of the first opening 113, or a free layer, an insulating layer and a permanent magnet layer are conformally formed sequentially on the surface of the first receiving groove 114 and the surface of the first opening 113; wherein, the magnetic tunnel junction includes a permanent magnet layer, an insulating layer and a free layer.

[0053] For example, in step S31, after a storage film material layer is conformally formed on the surface of the first receiving groove 114 and the surface of the first opening 113 through the first opening 113, the method for forming the conductive line 109 may include: referring to Figure 14 As shown, the remaining space between the first opening 113 and the first receiving groove 114 is first filled with a first conductive material layer 115; then, the first conductive material layer 115 is etched back to form a conductive line 109.

[0054] In some embodiments, reference Figure 11 As shown, the end of the conductive line 109 near the first opening 113 is recessed between adjacent first isolation layers 1012 to avoid the risk of subsequent process operations causing adjacent conductive lines 109 to connect at the first opening 113. Furthermore, this also reduces the etching difficulty of subsequently forming a second opening through the first stacked layer 101, as well as the process difficulty of fabricating the gate select line.

[0055] For example, the first conductive material layer 115 may include a single conductive material or multiple conductive materials. For instance, titanium nitride (TiN) may be deposited first, followed by the deposition of tungsten metal to complete the deposition of conductive materials. By depositing titanium nitride before tungsten metal, the conductivity is ensured, and the material diffusion between tungsten metal and the storage film layer 108 is effectively prevented. The adhesion between tungsten metal and the storage film layer 108 is also improved, reducing the risk of tungsten metal falling off during chemical polishing or thermal cycling. In addition, titanium nitride has a high surface energy, which can provide excellent nucleation sites for tungsten metal, ensuring seamless and void-free conformal filling.

[0056] In one embodiment, the first conductive material layer 115, while filling the remaining space of the first opening 113 and the first receiving groove 114, can also cover the surface of the insulating protective layer 112. Furthermore, during the back etching of the first conductive material layer 115 to form the conductive line 109: the first conductive material layer 115 filled in the first opening 113 is completely etched, and the portion of the first conductive material layer 115 filled in the remaining space of the first receiving groove 114 that is etched—that is, the portion of the first conductive material layer 115 filled in the remaining space of the first receiving groove 114 near the first opening 113—is etched to form a conductive line 109 with its end recessed relative to the first insulating layer 1012. (Refer to...) Figure 11 As shown.

[0057] In step S32, refer to Figure 16 As shown, a second opening 116 is formed from the first side of the substrate. On the orthographic projection of the substrate 100, the second opening 116 overlaps with the first opening 113. The second opening 116 penetrates the second sacrificial layer 1021. (Refer to...) Figure 18 As shown, the second sacrificial layer 1021 is removed through the second opening 116 to form the second receiving groove 117, see reference. Figure 19 As shown, a gate dielectric layer 118 is formed on the surface of the semiconductor material layer 105 exposed by the second accommodating trench 117. Then, referring to... Figure 20 As shown, a gate selection line 107 is then formed in the second receiving groove 117.

[0058] In some embodiments, after etching back the first conductive material layer 115 to form the conductive line 109, that is, after step S31 and before step S32, the fabrication method further includes: referencing Figure 15 As shown, an insulating dielectric layer 119 is prepared to fill the remaining space of the first opening 113 and the first receiving groove 114 to protect the conductive wire 109 and reduce the possibility of damage to the conductive wire 109 in subsequent processes. It also facilitates the process of forming the second opening 116.

[0059] In some embodiments, in step S32, reference Figure 16 As shown, the second opening 116 penetrates the insulating dielectric layer 119, the first stacked layer 101, and the second stacked layer 102. When forming the second opening 116, the storage film material layer on the opening sidewall of the first opening 113 is also removed. This exposes the second sacrificial layer 1021 at the second opening 116, facilitating subsequent replacement processes. It should be understood that because the conductive line 109 is recessed near the end of the first opening 113, it can still be protected by the insulating dielectric layer 119 filling the first receiving groove 114.

[0060] During the formation of the conductive line 109, the etching process of the conductive material layer 115 often struggles to etch the memory film material layer, resulting in residual memory film material on the sidewall of the first opening 113, affecting memory performance. The residual memory film material on the sidewall of the first opening 113 can be removed during the formation of the second opening 116, which penetrates the insulating dielectric layer 119, the first stacked layer 101, and the second stacked layer 102. This improves memory performance, reduces process complexity, and does not add any process steps. However, this is not the only method; other methods can be used to remove the residual memory film material on the sidewall of the first opening 113. This application does not impose specific limitations. As an example, before forming the second opening 116, other openings penetrating the insulating dielectric layer 119 and the first stacked layer 101 can be formed to remove the residual memory film material on the sidewall of the first opening 113.

[0061] For example, the second opening 116 can completely overlap with the first opening 113. This ensures that subsequent processes can proceed normally while avoiding damage to the conductive wire 109. Furthermore, the opening position parameters of the second opening 116 are the same as those of the first opening 113, reducing manufacturing complexity. After removing the storage film layer 108 from the sidewall of the first opening 113, the remaining storage film material layers located in the adjacent first receiving grooves 114 are disconnected at the second opening 116, meaning that the storage film layers 108 are not connected by a portion of the storage film material layer. At this time, the storage film layer 108 can include any one of a magnetic tunnel junction, a ferroelectric storage layer, or a resistive switching storage layer. When the storage film layer 108 is a magnetic tunnel junction, it reduces the mutual interference between vertically adjacent storage units caused by spin coupling between adjacent magnetic particles. When the storage film layer 108 is a ferroelectric storage layer or a resistive switching storage layer, it reduces leakage current between vertically adjacent storage units.

[0062] In some other embodiments, in step S32, reference is made to Figure 17 As shown, the second opening 116 penetrates the second sacrificial layer 1021 in the second stacked layer 102. When forming the second opening 116, the storage film material layer on the sidewall of the second sacrificial layer 1021 is also removed, so that the second sacrificial layer 1021 can be exposed for subsequent replacement processes. In this embodiment, the storage film material layer is formed continuously on the surface of the portion of the first opening 113 located within the first stacked layer 101; that is, in this embodiment, the depth of the second opening 116 penetrates the second sacrificial layer 1021 but does not penetrate to the first stacked layer 101. This reduces the processing difficulty of the second opening 116 and saves subsequent filling material, thus reducing costs.

[0063] When the storage film material layer is formed continuously on the surface of the first opening 113, the storage film layer 108 includes a phase change storage layer. However, it is not limited to this. The storage film layer 108 may also include a magnetic tunnel junction. When the storage film layer 108 is a magnetic tunnel junction, the continuous extension length of the magnetic tunnel junction located between two adjacent first portions in a direction perpendicular to the substrate 100 and close to the side of the first opening 113 is greater than 50 nm. In this way, when the storage film layer 108 is a magnetic tunnel junction, the mutual interference between storage units caused by the spin coupling effect between adjacent magnetic particles can be reduced.

[0064] For example, when the second sacrificial layer 1021 is made of silicon-germanium material and the second isolation layer 1022 is made of silicon oxide, the method for preparing the second receiving trench 117 in step S32 may include: introducing an etchant through the second opening 116, such as: using a solution containing an oxidant and hydrofluoric acid (HF) to selectively remove silicon-germanium (SiGe) and retain silicon oxide, that is: selectively removing the second sacrificial layer 1021 and retaining the second isolation layer 1022, so as to form a gap between each pair of second isolation layers 1022, that is: the second receiving trench 117.

[0065] For example, in step S32, the method for forming the gate dielectric layer 118 may include: conformally forming the gate dielectric layer 118 on the surface of the second accommodating trench 117 and the surface of the second opening 116 through the second opening 116. For example, atomic layer deposition technology can be used to diffuse the reactive precursor from the second opening 116 inward to achieve conformal coverage.

[0066] For example, the semiconductor material layer 105 includes polycrystalline silicon, such as... Figure 19 As shown, the method for forming the gate dielectric layer 118 may include: oxidizing the surface of the semiconductor material layer 105 to form the gate dielectric layer 105. However, it is not limited to this, and the material of the semiconductor material layer 105 may be used according to actual needs, as long as it can realize the conversion of the surface portion of the semiconductor material layer 105 into the gate dielectric layer 118.

[0067] In some embodiments, the gate dielectric layer 118 may be made of the same material as the first isolation layer 1012, the second isolation layer 1022 and the insulating protective layer 112, for example, all of which are made of silicon oxide, but it is not limited thereto and may also be other insulating materials.

[0068] For example, in step S32, after forming the gate dielectric layer 118, the method for forming the gate select line 107 includes: referring to... Figure 21 As shown, the remaining space of the second opening 116 and the second receiving groove 117 is first filled with a second conductive material layer 120; then, the second conductive material layer 120 is etched back to form the gate select line 107, as shown in the reference. Figure 20 As shown.

[0069] In some embodiments, reference Figure 20 As shown, the end of the gate select line 107 near the second opening 116 is recessed between adjacent second isolation layers 1022 to prevent the second conductive material layer 120 from remaining in the second opening and affecting the reliability of the memory.

[0070] In some embodiments, the material of the gate select line 107 may be different from the material of the conductive line 109. For example, the material of the gate select line 107 may be selected according to the electrical requirements of the transistor. As an example, the material of the gate select line 107 may be selected based on the threshold voltage regulation requirements of the transistor. However, this is not a limitation; the material of the gate select line 107 may also be the same as the material of the conductive line 109, depending on the specific circumstances.

[0071] For example, the second conductive material layer 120 may include a single conductive material or multiple conductive materials. For instance, titanium nitride (TiN) may be deposited first, followed by tungsten metal to complete the deposition of the conductive material. By depositing titanium nitride before tungsten metal, the conductivity is guaranteed, and the material diffusion between tungsten metal and gate dielectric layer 118 can be effectively prevented. It can also improve the adhesion between tungsten metal and gate dielectric layer 118 and reduce the risk of tungsten metal falling off in chemical polishing or thermal cycling techniques. In addition, titanium nitride has a high surface energy, which can provide excellent nucleation sites for tungsten metal, ensuring seamless and void-free conformal filling.

[0072] In one embodiment, during the etching back of the second conductive material layer 120 to form the gate select line 107: the second conductive material layer 120 filling the second opening 116 is completely etched, and the portion of the second conductive material layer 120 filling the remaining space of the second receiving trench 117 that has been etched is referenced. Figure 20 As shown, the portion of the second conductive material layer 120 near the second opening 116, which fills the remaining space in the second accommodating groove 117, is etched to form a gate select line 107 with its end recessed relative to the second isolation layer 1022. During the back etching of the second conductive material layer 120, the insulating dielectric layer 119 covers the recessed end of the conductive line 109 to protect it, especially when the second conductive material layer 120 and the conductive line 109 are made of the same material.

[0073] In some embodiments, the fabrication method further includes, after etching back the second conductive material layer 120 to form the gate select line 107, referencing Figure 22 As shown, an insulating dielectric layer 119 is prepared to fill the remaining space of the second opening 116 and the second receiving groove 117 to protect the gate select line 107 and reduce the possibility of the gate select line 107 being damaged in subsequent processes.

[0074] In some embodiments of this disclosure, two stacked layers are fabricated in step S1, and then a first via 103 is formed through a vertical via etching in step S2. Compared to separately etching the first stacked layer 101 to form a conductive hole filling the conductive pillar 104, and etching the second stacked layer 102 to form a channel hole for the semiconductor material layer 105, one less photolithography step is achieved, and alignment is not required to ensure connection. Furthermore, the storage film layer 108 is fabricated from a horizontal slot, which reduces mutual interference between the storage film layers 108 and reduces damage to the storage unit when the first sacrificial layer is removed. In the memory provided by this application, the storage cells can be arranged in a 3D vertical direction, and one transistor can control a column of storage cells in the vertical direction, thereby increasing the storage density of the storage cells and realizing ultra-large-scale integration of the memory.

[0075] This disclosure also provides a memory, combined with Figures 1 to 22 As shown, the storage block 10 may include a substrate 100 and a storage block located on the substrate 100. The storage block 10 includes a first stacked layer 101 and a second stacked layer 102. The first stacked layer 101 includes multiple layers of stacked conductive lines 109 and a first isolation layer 1012 located between two adjacent conductive lines 109. The second stacked layer 102 includes two stacked second isolation layers 1022 and a gate select line 107 located between the two second isolation layers 1022. A first via 103 is formed in the storage block 10, and a conductive pillar 104 and a semiconductor structure are formed in the first via 103. The conductive pillar 104 penetrates the storage block 10. The first stacked layer 101 has a semiconductor structure extending through the gate select line 107. The surface of the conductive pillar 104 in contact with the semiconductor structure is located between the gate select line 107 and the first stacked layer 101. The semiconductor structure includes a semiconductor material layer 105. The memory block 10 also includes a gate dielectric layer 118 located between the semiconductor material layer 105 and the gate select line 107. The first stacked layer 101 also includes a memory film layer 108, which includes a first portion located between the conductive pillar 104 and the conductive line 109, and a second portion extending from the first portion along the first isolation layer 1012 in a direction parallel to the substrate 100.

[0076] In some embodiments, on the orthographic projection of the substrate 100, the outer contour of the storage film layer 108 overlaps with the edge of the storage block 10, and the outer contour of the gate select line 107 lies within the outer contour of the storage film layer 108. Wherein, reference... Figure 16 As shown, in a direction perpendicular to the substrate 100, the storage film layer 108 in contact with two adjacent conductive lines 109 is disconnected from each other at the edge of the storage block 10; the storage film layer 108 includes any one of a magnetic tunnel junction, a ferroelectric storage layer, and a resistive switching storage layer.

[0077] In some embodiments, the storage film layer 108 includes a phase change storage layer, or the storage film layer 108 includes a magnetic tunnel junction, wherein the continuous extension length of the magnetic tunnel junction located between two adjacent first portions in a direction perpendicular to the substrate 100 and near the edge of the storage block 10 is greater than 50 nm.

[0078] In some embodiments, on the orthographic projection of the substrate 100, the outer contour of the conductive line 109 lies within the outer contour of the storage film layer 108.

[0079] This disclosure also provides a memory, combined with Figures 1 to 22 As shown, the storage block 10 may include a substrate 100 and a storage block located on the substrate 100. The storage block 10 includes a first stacked layer 101, which includes multiple layers of conductive lines 109 and a first isolation layer 1012 located between adjacent conductive lines 109. A first through-hole 103 is formed in the storage block 10, and a conductive post 104 is formed in the first through-hole 103, which penetrates the first stacked layer 101. The first stacked layer 101 also includes a storage film layer 108, which includes a first portion located between the conductive post 104 and the conductive lines 109, and a portion extending from the first portion along the first isolation layer 1012. The second portion extends in a direction parallel to the substrate 100; on the orthographic projection of the substrate 100, the outer contour of the conductive line 109 is located within the outer contour of the storage film layer 108; wherein: in a direction perpendicular to the substrate 100, between two adjacent conductive lines 109, the storage film layer 108 in contact with them is disconnected from each other at the edge of the storage block 10, and the storage film layer 108 includes any one of a magnetic tunnel junction, a ferroelectric storage layer, and a resistive switching storage layer; or, the storage film layer 108 includes a magnetic tunnel junction, and the continuous extension length of the magnetic tunnel junction located between two adjacent first portions in a direction perpendicular to the substrate 100 and near the edge of the storage block 10 is greater than 50 nm.

[0080] It should be understood that the memory in the embodiments of this disclosure can be manufactured using the corresponding preparation methods mentioned above. Since the specific structure and effects have been limited in the preparation methods, they will not be repeated here.

[0081] Although this disclosure has been described with reference to several typical embodiments, it should be understood that the terminology used is descriptive and exemplary, and not restrictive. Because this disclosure can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A method for fabricating a memory, characterized in that, include: Step S1: Provide a substrate having opposing first and second sides, the substrate including a substrate, a first stacked layer and a second stacked layer; The first stacked layer and the second stacked layer are stacked on a first side of the substrate. The first stacked layer includes multiple stacked first sacrificial layers and a first isolation layer located between two adjacent first sacrificial layers. The second stacked layer includes two stacked second isolation layers and a second sacrificial layer located between two second isolation layers. Step S2: A first through-hole is formed through the first side. The first through-hole penetrates the first stacked layer and the second stacked layer. A conductive pillar and a semiconductor material layer are formed in the first through-hole. The conductive pillar penetrates the first stacked layer, and the semiconductor material layer penetrates the second sacrificial layer. The conductive pillar is in contact with the semiconductor material layer, and the surface of the contact is located between the second sacrificial layer and the first stacked layer. Step S3: Replace the first sacrificial layer with a storage film layer and a conductive line covered by the storage film layer, wherein the storage film layer is located at least between the conductive line and the conductive pillar, and replace the second sacrificial layer with a gate select line.

2. The preparation method according to claim 1, characterized in that, The first stacked layer is located between the substrate and the second stacked layer.

3. The preparation method according to claim 2, characterized in that, The first sacrificial layer and the second sacrificial layer are made of different materials, and step S3 includes: Step S31: A first opening is formed from the first side, penetrating the first stacked layer and the second stacked layer. The first sacrificial layer is removed through the first opening to form a first receiving groove between adjacent first isolation layers in the stacking direction. Then, a storage film material layer and a conductive line are formed sequentially. The storage film material layer is conformally formed on the surface of the first receiving groove and the first opening. The storage film material layer includes the storage film layer. The conductive line is formed in the first receiving groove and located on the side of the storage film layer away from the surface of the first receiving groove. The storage film layer includes a first portion located between the conductive line and the conductive post, and a second portion extending from the first portion along the surface of the first isolation layer. Step S32: A second opening is formed from the first side. The second opening overlaps with the first opening on the orthographic projection of the substrate. The second opening penetrates the second sacrificial layer. The second sacrificial layer is removed through the second opening to form a second accommodating trench. A gate dielectric layer is formed on the surface of the semiconductor material layer exposed by the second accommodating trench. Then, a gate select line is formed in the second accommodating trench.

4. The preparation method according to claim 3, characterized in that, The steps of forming the storage film and conductive lines include: A storage film material layer is conformally formed on the surface of the first receiving groove and the surface of the first opening through the first opening; A first conductive material layer is filled into the remaining space between the first opening and the first receiving groove; The first conductive material layer is etched back to form the conductive line, wherein the end of the conductive line near the first opening is recessed between adjacent first insulating layers.

5. The preparation method according to claim 4, characterized in that, The method further includes the following steps after step S31 and before step S32: An insulating dielectric layer is prepared to fill the remaining space of the first opening and the first receiving groove; In step S32, the second opening penetrates the insulating dielectric layer, the first stacked layer, and the second stacked layer, and when the second opening is formed, the storage film material layer on the opening sidewall of the first opening is also removed.

6. The preparation method according to claim 5, characterized in that, The storage film layer includes any one of a magnetic tunnel junction, a ferroelectric storage layer, and a resistive switching storage layer.

7. The preparation method according to claim 4, characterized in that, The method further includes the following steps after step S31 and before step S32: An insulating dielectric layer is prepared to fill the remaining space of the first opening and the first receiving groove; In step S32, the second opening penetrates the second sacrificial layer in the second stacked layer, and when the second opening is formed, the storage film material layer on the sidewall of the second sacrificial layer is also removed. The storage film material layer is formed continuously on the surface of the portion of the first opening located within the first stacked layer; The storage film layer includes a phase change storage layer, or the storage film layer includes a magnetic tunnel junction, wherein the continuous extension length of the magnetic tunnel junction located between two adjacent first portions in a direction perpendicular to the substrate and near the first opening side is greater than 50 nm.

8. The preparation method according to claim 1, characterized in that, The material of the conductive line is different from the material of the gate select line; and / or The first sacrificial layer and the second sacrificial layer are made of different materials; and / or The materials of the first isolation layer and the second isolation layer include silicon oxide, the material of the first sacrificial layer includes silicon nitride, and the material of the second sacrificial layer includes silicon germanium.

9. A memory, characterized in that, include: A substrate, and a storage block located on the substrate; The memory block includes a first stacked layer and a second stacked layer. The first stacked layer includes multiple layers of conductive lines and a first isolation layer located between two adjacent conductive lines. The second stacked layer includes two layers of second isolation layers and a gate select line located between the two layers of second isolation layers. A first via is formed through the memory block, and a conductive pillar and a semiconductor structure are formed in the first via. The conductive pillar penetrates the first stacked layer, and the semiconductor structure penetrates the gate select line. The surface of the conductive pillar in contact with the semiconductor structure is located between the gate select line and the first stacked layer. The semiconductor structure includes a semiconductor material layer, and the memory block also includes a gate dielectric layer located between the semiconductor material layer and the gate select line. The first stacked layer further includes a storage film layer comprising a first portion located between the conductive pillar and the conductive line, and a second portion extending from the first portion along the first isolation layer in a direction parallel to the substrate.

10. The memory as claimed in claim 9, characterized in that, The material of the conductive line is different from the material of the gate select line.

11. The memory as claimed in claim 9, characterized in that, The first stacked layer is located between the substrate and the second stacked layer.

12. The memory as claimed in claim 11, characterized in that, On the orthographic projection of the substrate, the outer contour of the storage film layer overlaps with the edge of the storage block, and the outer contour of the gate select line is located within the outer contour of the storage film layer.

Images