Electrochemical random access memory

Abstract

The invention relates to the field of memories, and provides an electrochemical random access memory, which comprises a plurality of memory units, the plurality of memory units are communicated with a read word line and a write word line; each memory unit comprises an NV-FET (Non-Volume Field Effect Transistor) and an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and the NV-FET and the MOSFET are connected in series; the NV-FET transistor includes: a first substrate layer; a channel layer; a first source layer; a first drain layer; the first source electrode layer and the first drain electrode layer are respectively arranged at two ends of the channel layer; a first gate dielectric layer; and a first gate layer. The invention discloses an electrochemical random access memory and a manufacturing method thereof, and aims to overcome the defects that information stored in the electrochemical random access memory is easy to lose and the risk of data security exists due to power failure of the electrochemical random access memory in the related technology. The brand new metal oxide semiconductor transistor is applied to the electrochemical random access memory provided by the scheme of the invention, and the transistor has non-volatility; and thus, the electrochemical random access memory also has non-volatility.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and more particularly to an electrochemical random access memory. Background Technology

[0002] Electrochemical random-access memory (ECRAM) is a novel memory technology based on electrochemical principles. It works similarly to the charging and discharging process of a battery, using an electric field to drive the reversible movement of ions in a material to store and manipulate data.

[0003] Most electrochemical random access memories in related technologies are volatile, and the information stored in them can be easily lost when power is turned off, posing a risk to data security. Summary of the Invention

[0004] This invention provides an electrochemical random access memory (RAM) to address the shortcomings of most electrochemical RAMs in related technologies, which are volatile and prone to data loss when power is off, posing a risk to data security. The electrochemical RAM provided in this application uses a novel metal-oxide-semiconductor transistor (MOST), which is non-volatile, thereby making the electrochemical RAM non-volatile as well.

[0005] This invention provides an electrochemical random access memory, comprising a plurality of memory cells; Each of the aforementioned memory cells is connected to both the read word line and the write word line; Each memory cell includes an NV-FET transistor and a MOSFET transistor, wherein the NV-FET transistor and the MOSFET transistor are connected in series; The NV-FET transistor includes: First substrate layer; A channel layer is disposed on top of the substrate layer; The first source layer is used for current input; The first drain layer is used for current output; The first source layer and the first drain layer are respectively disposed at both ends of the channel layer; The first gate dielectric layer is disposed at the center of the top of the channel layer; The first gate layer is disposed on one side of the top center position of the gate layer.

[0006] According to the electrochemical random access memory provided by the present invention, the first source layer of the NV-FET transistor is connected in series with the source layer of the MOSFET transistor, and the series connection method includes: The channel layer of the NV-FET transistor and the channel layer of the MOSFET transistor are doped to form the source and drain. The first source layer of the NV-FET transistor and the source layer of the MOSFET transistor are connected in series through the source and drain. And / or, The first source layer of the NV-FET transistor forms a conductive connection with the source layer of the MOSFET transistor; The source and drain materials include any one or more of boron, phosphorus, arsenic, neodymium, aluminum, and platinum.

[0007] In the electrochemical random access memory provided by the present invention, the first gate layer of the NV-FET transistor is connected to the write word line; The gate layer of the MOSFET transistor is connected to the word line.

[0008] According to the electrochemical random access memory provided by the present invention, the first source layer of the NV-FET transistor is connected to the source line; The source layer of the MOSFET transistor is connected to the bit line.

[0009] According to the electrochemical random access memory provided by the present invention, the first source layer and the first drain layer are disposed on the top of the channel layer, and the bottom of the first source layer and the first drain layer are in contact with the channel layer.

[0010] According to the electrochemical random access memory provided by the present invention, the first source layer and the first drain layer are disposed on the side of the channel layer, and the side edges of the first source layer and the first drain layer are in contact with the side edges of the channel layer.

[0011] The electrochemical random access memory provided by the present invention further includes a back gate layer; The back gate layer is disposed between the channel layer and the first substrate layer, and is used to adjust the electric field distribution of the channel layer; An insulating dielectric layer is provided between the back grid layer and the channel layer.

[0012] According to the electrochemical random access memory provided by the present invention, the channel layer is made of aluminum scandium nitride, or any one or more mixed materials selected from aluminum, gallium, indium, germanium, tin, zinc, silicon, nitrogen, phosphorus, arsenic, scandium, oxygen and yttrium.

[0013] According to the electrochemical random access memory provided by the present invention, the material of the gate dielectric layer includes, but is not limited to, any one or more of silicon oxide, aluminum oxide, silicon nitride, aluminum nitride, hafnium oxide, zirconium oxide, hafnium nitride, and zirconium nitride; The material of the gate layer includes, but is not limited to, any one or more of polysilicon, titanium nitride, tungsten, tantalum, molybdenum, platinum, and aluminum.

[0014] According to the electrochemical random access memory provided by the present invention, the materials of the source layer and the drain layer include, but are not limited to, any one or more of titanium nitride, tungsten, tantalum, molybdenum, platinum, ruthenium, nickel and cobalt.

[0015] The electrochemical random access memory provided by this invention uses non-volatile NV-FET transistors connected in series with conventional MOSFET transistors, making the electrochemical random access memory as a whole non-volatile. At the same time, the memory cells of the electrochemical random access memory are all connected to the read word line and the write word line, realizing read-write separation and eliminating the risk of read-write crosstalk. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of the electrochemical random access memory provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a memory cell provided in an embodiment of the present invention; Figure 3 This is one of the structural schematic diagrams of the metal-oxide-semiconductor transistor provided in the embodiments of the present invention; Figure 4 This is a second schematic diagram of the structure of a metal-oxide-semiconductor transistor provided in an embodiment of the present invention; Figure 5 This is the third schematic diagram of the structure of the metal-oxide-semiconductor transistor provided in the embodiments of the present invention; Figure 6 This is one of the performance evaluation diagrams provided in the embodiments of the present invention; Figure 7 This is the second performance evaluation diagram provided in the embodiments of the present invention.

[0018] in: 1-Memory cell; 2-NV-FET transistor; 3-MOSFET transistor; 4-First substrate layer; 5-Channel layer; 6-First source layer; 7-First drain layer; 8-First gate dielectric layer; 9-First gate layer; 10-Back gate layer. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0020] Figure 1 This is a schematic diagram of the structure of the electrochemical random access memory provided in an embodiment of the present invention.

[0021] Figure 2 This is a schematic diagram of the structure of a memory unit provided in an embodiment of the present invention.

[0022] like Figure 1 As shown, this embodiment provides an electrochemical random access memory, including a plurality of memory cells; Each of the aforementioned memory cells is connected to both the read word line and the write word line; like Figure 2 As shown, each memory cell includes an NV-FET transistor and a MOSFET transistor, wherein the NV-FET transistor and the MOSFET transistor are connected in series; In practical applications, the first source layer of the NV-FET transistor is connected in series with the source layer of the MOSFET transistor, thereby realizing the series connection of the NV-FET transistor and the MOSFET transistor. Specifically, the series connection methods include: The channel layer of the NV-FET transistor and the channel layer of the MOSFET transistor are doped to form the source and drain. The first source layer of the NV-FET transistor and the source layer of the MOSFET transistor are connected in series through the source and drain. And / or, The first source layer of the NV-FET transistor forms a conductive connection with the source layer of the MOSFET transistor; The source and drain materials include any one or more of boron, phosphorus, arsenic, neodymium, aluminum, and platinum; In practice, the methods by which the channel layer of the NV-FET transistor and the channel layer of the MOSFET transistor are doped to form source and drain electrodes include, but are not limited to, ion implantation, ion diffusion, and co-sputtering deposition.

[0023] Furthermore, such as Figure 1As shown, the first gate layer of the NV-FET transistor is connected to the write word line; the gate layer of the MOSFET transistor is connected to the read word line. In this way, read and write separation of the electrochemical random access memory is realized. Specifically, the NV-FET transistor is only responsible for writing information, and the MOSFET transistor is only responsible for selection and reading. By separating read and write, the risk of read-write crosstalk is reduced and the security of data storage is improved. On the other hand, the memory usage time can also be increased, that is, the endurance is improved. This beneficial effect has a significant performance improvement for memory applications in various application scenarios, such as AI training and other fields with frequent read and write operations.

[0024] Figure 3 This is one of the structural schematic diagrams of a metal-oxide-semiconductor transistor provided in an embodiment of the present invention.

[0025] Figure 4 This is the second schematic diagram of the structure of the metal-oxide-semiconductor transistor provided in the embodiment of the present invention.

[0026] like Figure 3 and Figure 4 As shown, the NV-FET transistor includes: First substrate layer; A channel layer is disposed on top of the substrate layer; in practical applications, the material of the channel layer can be aluminum scandium nitride, or any one or more mixed materials selected from aluminum, gallium, indium, germanium, tin, zinc, silicon, nitrogen, phosphorus, arsenic, scandium, oxygen and yttrium. The first source layer is used for current input; The first drain layer is used for current output; The first source layer and the first drain layer are respectively disposed at both ends of the channel layer. The materials of the source layer and the drain layer can be any one or more of titanium nitride, tungsten, tantalum, molybdenum, platinum, ruthenium, nickel and cobalt. The first gate dielectric layer is disposed at the center of the top of the channel layer. The material of the gate dielectric layer may be any one or more of silicon suboxide, aluminum oxide, silicon nitride, aluminum nitride, hafnium oxide, zirconium oxide, hafnium nitride, and zirconium nitride. The first gate layer is disposed on one side of the top center position of the gate layer. The material of the gate layer may be any one or more of polysilicon, titanium nitride, tungsten, tantalum, molybdenum, platinum and aluminum, including but not limited to polysilicon, titanium nitride, tungsten, tantalum, molybdenum, platinum and aluminum.

[0027] In practical applications, the field-induced phase transition effect of AlScN (aluminum scandium nitride) can be utilized (a phase transition occurs when an electric field is applied, thereby changing the resistance state). Referring to the conventional metal-oxide-semiconductor transistor structure in the prior art, that is, referring to the MOSFET, an NV (non-volatile)-FET can be constructed, which is the metal-oxide-semiconductor transistor provided by the solution of this application. The core difference between the NV-FET provided by the solution of this application and the MOSFET in the related technology is that its channel material is different from that of traditional semiconductors. It is a non-volatile field-induced phase transition material. In addition, other thin film materials can be superimposed on the upper and lower surfaces of the channel material as needed to improve the interface characteristics.

[0028] in Figure 3 and Figure 4 Two specific implementations of NV-FET transistors are illustrated, both of which result in non-volatile NV-FET transistors. Figure 3 As shown, the first source layer and the first drain layer are disposed on the top of the channel layer, and the bottom of the first source layer and the first drain layer are in contact with the channel layer.

[0029] like Figure 4 As shown, the first source layer and the first drain layer are disposed on the side of the channel layer, the side edges of the first source layer and the first drain layer are in contact with the side edge of the channel layer, and a back gate layer is also included. The back gate layer is disposed between the channel layer and the first substrate layer, and is used to adjust the electric field distribution of the channel layer; An insulating dielectric layer is provided between the back grid layer and the channel layer.

[0030] Figure 5 This is the third schematic diagram of the structure of a metal-oxide-semiconductor transistor provided in an embodiment of the present invention. Figure 5 This is a top view of a transistor. As can be seen from the top view angle, Figure 3 and Figure 4 The two corresponding implementations are identical.

[0031] The metal-oxide-semiconductor transistor provided in this application can also refer to the P / N type MOSFET in the prior art to construct various logic devices and memory devices. In principle, it can completely replace them and bring performance improvements such as non-volatility.

[0032] The metal-oxide-semiconductor transistor provided in this application can perform normal write and read operations during application. Specifically, during data writing, it can... In a write operation, if a write voltage exceeding the forward threshold voltage is applied, after successful programming, the NV-NFET exhibits a low-resistance state (high current), and the NV-PFET exhibits a high-resistance state (low current). After the voltage is removed, the written state remains unchanged, indicating non-volatility. Similarly, if a write voltage exceeding the reverse threshold voltage is applied, after successful programming, the NV-NFET exhibits a high-resistance state (low current), and the NV-PFET exhibits a low-resistance state (high current). After the voltage is removed, the written state remains unchanged, indicating non-volatility. Here, NV-NFET refers to an N-type NV-FET, and NV-PFET refers to a P-type NV-FET.

[0033] When performing data readout operations, NV-NFET and NV-PFET operate in the same way, and both can apply a readout voltage less than the threshold voltage. Preferably, it can be less than 50% of the threshold voltage. Furthermore, it can identify the high-resistance state (off, logic 0) and the low-resistance state (on, logic 1) based on the current magnitude. In practical applications, the threshold voltage can be 0.1 to 1 volt.

[0034] Figure 6 This is one of the performance evaluation diagrams provided in the embodiments of the present invention.

[0035] Figure 7 This is the second performance evaluation diagram provided in the embodiments of the present invention.

[0036] like Figure 6 and Figure 7 As shown, the performance of the metal-oxide-semiconductor transistor provided in this application can also be tested. In this embodiment, an ID-VG test was performed on the metal-oxide-semiconductor transistor. The ID-VG curve can show the variation of the drain-source current (ID) with the gate-source voltage (VGS) under a fixed drain-source voltage (VDS). Figure 6 The ID-VG curve obtained from the ID-VG experiment of NV-NFET. Figure 7 To obtain the ID-VG curve from the ID-VG test of the NV-PFET, from Figure 6 and Figure 7 As can be seen, the NV-FET provided in this embodiment can perform data writing and data reading operations normally.

[0037] In addition, the solution proposed in this application has the following beneficial effects: The principle of electric field-controlled phase transition means that the performance is only related to the electric field, and it has good consistency and temperature stability, making it suitable for special scenarios such as ultra-low temperature environments.

[0038] Its non-volatile nature allows it to be directly used to create storage devices, enabling 0 / 1 or even polymorphic storage.

[0039] The channel requires no doping, the process is simple and reliable, and the cost is low.

[0040] It facilitates process miniaturization and can replace traditional MOSFETs at advanced nodes.

[0041] It is compatible with traditional semiconductor processes and can be easily replaced or upgraded.

[0042] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An electrochemical random access memory, characterized in that, Includes several memory units; Each of the aforementioned memory cells is connected to both the read word line and the write word line; Each memory cell includes an NV-FET transistor and a MOSFET transistor, wherein the NV-FET transistor and the MOSFET transistor are connected in series; The NV-FET transistor includes: First substrate layer; A channel layer is disposed on top of the substrate layer; The first source layer is used for current input; The first drain layer is used for current output; The first source layer and the first drain layer are respectively disposed at both ends of the channel layer; The first gate dielectric layer is disposed at the center of the top of the channel layer; The first gate layer is disposed on one side of the top center position of the gate layer.

2. The electrochemical random access memory according to claim 1, characterized in that, The first source layer of the NV-FET transistor is connected in series with the source layer of the MOSFET transistor, and the series connection method includes: The channel layer of the NV-FET transistor and the channel layer of the MOSFET transistor are doped to form the source and drain. The first source layer of the NV-FET transistor and the source layer of the MOSFET transistor are connected in series through the source and drain. And / or, The first source layer of the NV-FET transistor forms a conductive connection with the source layer of the MOSFET transistor; The source and drain materials include any one or more of boron, phosphorus, arsenic, neodymium, aluminum, and platinum.

3. The electrochemical random access memory according to claim 1, characterized in that, The first gate layer of the NV-FET transistor is connected to the write line; The gate layer of the MOSFET transistor is connected to the word line.

4. The electrochemical random access memory according to claim 1, characterized in that, The first source layer of the NV-FET transistor is connected to the source line; The source layer of the MOSFET transistor is connected to the bit line.

5. The electrochemical random access memory according to claim 1, characterized in that, The first source layer and the first drain layer are disposed on the top of the channel layer, and the bottom of the first source layer and the first drain layer are in contact with the channel layer.

6. The electrochemical random access memory according to claim 1, characterized in that, The first source layer and the first drain layer are disposed on the side of the channel layer, and the side edges of the first source layer and the first drain layer are in contact with the side edge of the channel layer.

7. The electrochemical random access memory according to claim 6, characterized in that, It also includes the back gate layer; The back gate layer is disposed between the channel layer and the first substrate layer, and is used to adjust the electric field distribution of the channel layer; An insulating dielectric layer is provided between the back grid layer and the channel layer.

8. The electrochemical random access memory according to claim 1, characterized in that, The channel layer is made of aluminum scandium nitride, or a mixture of one or more of the elements aluminum, gallium, indium, germanium, tin, zinc, silicon, nitrogen, phosphorus, arsenic, scandium, oxygen, and yttrium.

9. The electrochemical random access memory according to claim 1, characterized in that, The material of the gate dielectric layer includes, but is not limited to, any one or more of silicon oxide, aluminum oxide, silicon nitride, aluminum nitride, hafnium oxide, zirconium oxide, hafnium nitride, and zirconium nitride; The material of the gate layer includes, but is not limited to, any one or more of polysilicon, titanium nitride, tungsten, tantalum, molybdenum, platinum, and aluminum.

10. The electrochemical random access memory according to claim 1, characterized in that, The source layer and the drain layer are made of materials including, but not limited to, any one or more of titanium nitride, tungsten, tantalum, molybdenum, platinum, ruthenium, nickel, and cobalt.

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