Semiconductor device
By creating recesses on the wiring substrate and filling and sealing them with insulating material and resin, the problem of bonding material protrusion during semiconductor chip stacking is solved, improving the reliability and stability of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-13
- Publication Date
- 2026-03-13
AI Technical Summary
In existing technologies, during semiconductor chip stacking, bonding materials are prone to accidental protrusion, leading to reduced reliability.
Recesses are formed on the wiring substrate, and the semiconductor chip is filled and covered with insulating material to prevent bonding material leakage. The reliability of chip stacking is improved by flip-chip bonding or gap filling sealing resin.
It effectively prevents accidental protrusion of bonding materials, improves the reliability of semiconductor devices, prevents cracks caused by moisture infiltration, and enhances the stability of chip stacking.
Smart Images
Figure CN121665587A_ABST
Abstract
Description
Technical Field
[0001] The implementation scheme described in this article generally relates to a semiconductor device. Background Technology
[0002] In semiconductor devices such as NAND flash memory, multiple semiconductor chips can be stacked on the same wiring substrate from the viewpoint of miniaturization and high speed. In this case, a film overdie (FOD) structure is known, in which multiple semiconductor chips are bonded to each other using a dieattach film (DAF) disposed between and stacked.
[0003] A semiconductor device is provided to prevent accidental protrusion of bonding material used for stacking multiple semiconductor chips and to provide high reliability.
[0004] According to one embodiment, a semiconductor device includes a wiring substrate having a recess on a first surface. A first semiconductor chip is disposed on the bottom surface of the recess. A first insulating material fills the recess and is disposed around the first semiconductor chip. At least one second semiconductor chip is stacked on top of the first semiconductor chip. Attached Figure Description
[0005] Figure 1 This is a top view showing an example configuration of a semiconductor device according to a first embodiment.
[0006] Figure 2 This is a cross-sectional view showing an example configuration of a semiconductor device according to the first embodiment.
[0007] Figure 3 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to a first embodiment.
[0008] Figure 4 From Figure 3 Continuing, a cross-sectional view of an example of a semiconductor device manufacturing method is shown.
[0009] Figure 5 From Figure 4 Continuing, a cross-sectional view of an example of a semiconductor device manufacturing method is shown.
[0010] Figure 6 From Figure 5 Continuing, a cross-sectional view of an example of a semiconductor device manufacturing method is shown.
[0011] Figure 7 This is a top view showing an example configuration of a semiconductor device according to the second embodiment.
[0012] Figure 8 This is a cross-sectional view showing an example configuration of a semiconductor device according to the second embodiment.
[0013] Figure 9 This is a cross-sectional view showing an example configuration of a semiconductor device according to the second embodiment.
[0014] Figure 10 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to a second embodiment.
[0015] Figure 11 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to a second embodiment.
[0016] Figure 12 This is a top view showing an example configuration of a semiconductor device according to a third embodiment.
[0017] Figure 13 This is a cross-sectional view showing an example configuration of a semiconductor device according to a third embodiment.
[0018] Figure 14 This is a cross-sectional view illustrating an example of a method for manufacturing a package of a semiconductor device according to a third embodiment.
[0019] Figure 15 From Figure 14 Continuing, a cross-sectional view of an example of a semiconductor device manufacturing method is shown.
[0020] Figure 16 From Figure 15 Continuing, a cross-sectional view of an example of a semiconductor device manufacturing method is shown.
[0021] Figure 17 From Figure 16 Continuing, a cross-sectional view of an example of a semiconductor device manufacturing method is shown. Detailed Implementation
[0022] The implementation provides a semiconductor device with high reliability, wherein accidental protrusion of bonding material used to stack multiple semiconductor chips is prevented.
[0023] In the following description, embodiments of the present disclosure will be illustrated with reference to the accompanying drawings. These embodiments do not limit the scope of the disclosure. The drawings are schematic or conceptual. In both the description and the drawings, the same elements are indicated by the same reference numerals.
[0024] (First Implementation Plan)
[0025] Figure 1 This is a top view showing an example configuration of a semiconductor device 1 according to a first embodiment. Figure 2This is a cross-sectional view showing an example configuration of the semiconductor device 1 according to the first embodiment.
[0026] like Figure 2 As shown, the semiconductor device 1 according to this embodiment is a semiconductor package including a wiring substrate SUB1, semiconductor chips CH1 to CH3, insulating materials D1 to D3, bonding wires BW, and sealing resin MR.
[0027] Wiring substrate SUB1 includes resin material 10, solder resist 11a and 11b, wiring 12, and electrode pads 13a and 13b. Wiring substrate SUB1 is a substrate including a wiring layer with wiring 12 disposed thereon. Wiring substrate SUB1 electrically connects semiconductor chips CH1 to CH3 to each other via wiring 12, or electrically connects semiconductor chips CH1 to CH3 and external devices to each other. Wiring substrate SUB1 includes a first surface F1 and a second surface F2 opposite to the first surface F1.
[0028] The resin material 10 is, for example, glass epoxy resin. The resin material 10 is disposed around the wiring 12 and electrically isolates the wiring 12 from each other.
[0029] Solder resist 11a is applied to the first surface F1 side of the wiring substrate SUB1. Solder resist 11a exposes a portion of the front surface of the electrode pad 13a.
[0030] Solder resist 11b is applied to the second surface F2 side of the wiring substrate SUB1. Solder resist 11b exposes a portion of the front surface of the electrode pad 13b.
[0031] Wiring 12 is disposed in resin material 10 or solder resist 11a and 11b. Wiring 12 may include, for example, metallic materials such as copper, tungsten or aluminum.
[0032] The electrode pad 13a, serving as the second electrode, is disposed on the first surface F1 side of the wiring substrate SUB1 and is exposed from the solder resist 11a. The electrode pad 13a functions as a bonding pad for connecting the bonding wire BW. A portion of the electrode pad 13a is disposed on the bottom of the recess CAV.
[0033] Electrode pads 13b are disposed on the second surface F2 side of the wiring substrate SUB1 and exposed from the solder resist 11b. Electrode pads 13b serve as pads or bumps for electrical connection to external devices.
[0034] The wiring substrate SUB1 includes a recess CAV located on the first surface F1 side. The recess CAV has dimensions capable of accommodating a semiconductor chip CH1 and is filled with an insulating material D2. The recess CAV extends to the resin material 10 and is formed by pressing down the resin material 10. Electrode pads 13a are provided on the bottom surface of the recess CAV. Furthermore, the semiconductor chip CH1 is disposed on the bottom surface of the recess CAV.
[0035] The depth of the recess CAV is greater than the thickness of the semiconductor chip CH1. Furthermore, in the top view (viewed from the Z direction) taken from the first surface F1, as shown... Figure 1 As shown, the outer edge of the opening OP1 of the recess CAV is outside the outer edge of the semiconductor chip CH1. As a result, the semiconductor chip CH1 can be accommodated in the recess CAV, and the semiconductor chip CH1 can be arranged in the bottom surface of the recess CAV.
[0036] like Figure 1 As shown, in the top view viewed from the Z direction, the recess CAV is essentially located at the center of the wiring substrate SUB1. However, the planar position of the recess CAV relative to the wiring substrate SUB1 is freely selectable and can be offset in the X and / or Y directions.
[0037] Semiconductor chip CH1 is bonded to the bottom surface of recess CAV using insulating material D1. Semiconductor chip CH1 can be a controller chip that controls semiconductor chips CH2 and CH3, which are memory chips. Semiconductor chip CH1 is electrically connected to electrode pads 13a disposed on the bottom surface of recess CAV via bonding wire BW. Semiconductor chip CH1 is an example of a first semiconductor chip. Semiconductor chips CH2 and CH3 are examples of second semiconductor chips.
[0038] The thickness of the semiconductor chip CH1 is less than the depth of the recess CAV. Furthermore, the outer edge of the semiconductor chip CH1 is smaller than the outer edge of the opening OP1 of the recess CAV. Therefore, as described above, the semiconductor chip CH1 can be accommodated within the recess CAV.
[0039] Insulating material D1 is pre-attached to the back surface of semiconductor chip CH1. During the chip bonding process, insulating material D1 is disposed together with semiconductor chip CH1 on the bottom surface of recess CAV and cured. As a result, insulating material D1 bonds semiconductor chip CH1 to the bottom surface of recess CAV.
[0040] Insulating material D2 fills the recess CAV and is disposed around the semiconductor chip CH1. As a result, insulating material D2 protects the semiconductor chip CH1 and the bonding wire BW. Furthermore, the thickness of the cured insulating material D2 is substantially the same as the depth of the recess CAV. Consequently, the front surface of the semiconductor chip CH2 disposed on the insulating material D2 is located above the first surface F1 (in the +Z direction).
[0041] Insulating material D2 is pre-attached to the back surface of semiconductor chip CH2. During the chip bonding process, insulating material D2 is arranged to cover semiconductor chip CH1 in the recess CAV together with semiconductor chip CH2 and is cured. As a result, insulating material D2 can cover semiconductor chip CH1 and bonding wire BW, and can bond semiconductor chip CH2 to the area above semiconductor chip CH1. Furthermore, insulating material D2 can fill the recess CAV. In a top view viewed from the Z direction, insulating material D2 has substantially the same dimensions as the back surface of semiconductor chip CH2 before curing, but has substantially the same dimensions as the opening OP1 of the recess CAV after curing. The volume of insulating material D2 is substantially the same as the capacity of the recess CAV.
[0042] Semiconductor chip CH2 is disposed on insulating material D2 and stacked on top of semiconductor chip CH1. Semiconductor chip CH2 is, for example, a memory chip including a memory cell array of NAND flash memory. Semiconductor chip CH2 is electrically connected to electrode pads 13a disposed on the first surface F1 of wiring substrate SUB1 via bonding wire BW.
[0043] The outer edge of the semiconductor chip CH2 is slightly smaller than the outer edge of the opening OP1 of the recess CAV. That is, in a top view viewed from the Z direction, the outer edge of the opening OP1 of the recess CAV is outside the outer edge of the semiconductor chip CH2. Therefore, as described above, the uncured insulating material D2 attached to the semiconductor chip CH2 can be accommodated in the recess CAV. Preferably, the sum of the volumes of the semiconductor chip CH1, the insulating material D1, the bonding wire BW connected to the semiconductor chip CH1, and the insulating material D2 is the same as the volume of the recess CAV. Therefore, the thickness of the uncured insulating material D2 attached to the semiconductor chip CH2 is slightly greater than the depth of the recess CAV. As a result, the volume of the insulating material D2 can be substantially the same as the capacity of the recess CAV, and the recess CAV can be embedded with the insulating material D2.
[0044] Semiconductor chip CH3 is bonded to the front surface of semiconductor chip CH2 via insulating material D3. Semiconductor chip CH3 is, for example, a NAND flash memory chip, the same as that in semiconductor chip CH2. Semiconductor chip CH3 is electrically connected to electrode pads 13a disposed on the first surface F1 of wiring substrate SUB1 via bonding wire BW.
[0045] Semiconductor chip CH3 is stacked and shifted so that the electrode pads of semiconductor chip CH2 are exposed above semiconductor chip CH1. As a result, semiconductor chip CH3 and electrode pads 13a can be connected to each other via bonding wires BW. Another semiconductor chip (not shown) can be stacked on top of semiconductor chip CH3.
[0046] Insulating material D3 is pre-attached to the back surface of semiconductor chip CH3. During the chip bonding process, insulating material D3 is disposed together with semiconductor chip CH3 on semiconductor chip CH2 and cured. As a result, insulating material D3 bonds semiconductor chip CH3 to semiconductor chip CH2.
[0047] A sealing resin MR is disposed on the first surface F1 of the wiring substrate SUB1, and covers the semiconductor chips CH2 and CH3 as well as the bonding wires BW. As a result, the sealing resin MR can protect the semiconductor chips CH2 and CH3 as well as the bonding wires BW.
[0048] Insulating materials D1 to D3 are, for example, insulating bonding materials such as DAF. In this embodiment, insulating material D2 is embedded in the semiconductor chip CH1. That is, the thickness of insulating material D2 is greater than the thickness of insulating materials D1 and D3.
[0049] In the FOD structure according to the comparative example, the DAF attached to the rear surface of the underlying semiconductor chip can flow from the rear surface of the semiconductor chip through the side surface to the front surface during curing. In this case, the upper semiconductor chip stacked on top of the semiconductor chip may unintentionally float due to the DAF, or the bonding wires may come into contact with the DAF. Furthermore, the DAF may protrude in the planar direction of the wiring substrate to reach the electrode pads on the wiring substrate. Such protrusions may reduce the reliability of the semiconductor device.
[0050] In this embodiment, a recess CAV is disposed within a wiring substrate SUB1, and a semiconductor chip CH1 is disposed within the recess CAV. An insulating material D2 covers the semiconductor chip CH1 and fills the recess CAV. The insulating material D2 has a volume substantially the same as the capacity of the recess CAV. Therefore, the insulating material D2 will not leak from the recess CAV during chip bonding and can prevent it from flowing from the side surface of the semiconductor chip CH2 to the front surface. Thus, accidental floating of the semiconductor chip CH3 from the front surface of the semiconductor chip CH2 or accidental contact between the insulating material D2 and the bonding wire BW can be prevented.
[0051] Furthermore, the recess CAV is filled with insulating material D2, thus eliminating gaps. As a result, cracks that can form when moisture seeps into gaps are prevented, and the reliability of the semiconductor device is improved.
[0052] Next, a method for manufacturing the semiconductor device 1 according to the first embodiment will be described.
[0053] Figures 3 to 6 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device 1 according to a first embodiment.
[0054] like Figure 3 As shown, a wiring substrate SUB1, including a recess CAV, is formed on the first surface F1. The thickness of the wiring substrate SUB1 in the Z direction is, for example, about 195 μm in the region excluding the recess CAV, and about 90 μm in the region of the recess CAV. Therefore, the depth of the recess CAV is, for example, about 105 μm.
[0055] Next, as Figure 4 As shown, a semiconductor chip CH1 and an insulating material D1 are arranged on the bottom surface of a recess CAV. The insulating material D1 is pre-attached to the back surface of the semiconductor chip CH1. Therefore, by curing the insulating material D1, the semiconductor chip CH1 is bonded to the bottom of the recess CAV. Next, the electrode pads of the semiconductor chip CH1 and the electrode pads 13a on the bottom surface of the recess CAV are connected to each other by bonding wires BW.
[0056] Next, as Figure 5As shown, semiconductor chip CH2 and insulating material D2 are arranged to cover semiconductor chip CH1 in a recess CAV. Insulating material D2 is pre-attached to the back surface of semiconductor chip CH2. Therefore, by curing insulating material D2, semiconductor chip CH1 and semiconductor chip CH2 in the recess CAV are bonded to each other. Furthermore, insulating material D2 is filled in the recess CAV and supports the back surface of semiconductor chip CH2 at approximately the same height level as the solder resist 11a on the first surface F1. Then, the electrode pads of semiconductor chip CH2 and the electrode pads 13a on the first surface F1 are connected to each other by bonding wires BW.
[0057] Next, as Figure 6 As shown, semiconductor chip CH3 and insulating material D3 are disposed on semiconductor chip CH2. Insulating material D3 is pre-attached to the back surface of semiconductor chip CH3. Therefore, by curing insulating material D3, semiconductor chip CH2 and semiconductor chip CH3 are bonded to each other. Next, the electrode pads of semiconductor chip CH3 and semiconductor chip CH2 are connected to each other by bonding wires BW.
[0058] Next, optionally, another semiconductor chip is stacked on semiconductor chip CH3 for wire bonding. Then, a sealing resin MR is formed on the first surface F1 to cover the stack of the semiconductor chip and the bonding wire BW. Furthermore, to improve efficiency, the bonding process of the bonding wire BW can be performed in batches after all the semiconductor chips have been stacked.
[0059] As a result, the work was completed according to... Figure 2 The semiconductor device 1 of the first embodiment shown.
[0060] In this embodiment, insulating material D2 covers the semiconductor chip CH1 and fills the recess CAV. Insulating material D2 has a volume substantially the same as the capacity of the recess CAV, thus preventing leakage from the recess CAV during the curing process. Therefore, insulating material D2 will not flow onto the front surface of the semiconductor chip CH2, and semiconductor chip CH3 will not float from the front surface of the semiconductor chip CH2. Furthermore, insulating material D2 is also prevented from leaking onto the electrode pads 13a on the first surface F1.
[0061] (Second Implementation Plan)
[0062] Figure 7 This is a top view showing an example configuration of the semiconductor device 1 according to the second embodiment.
[0063] Figure 8 and Figure 9 This is a cross-sectional view showing an example configuration of the semiconductor device 1 according to the second embodiment.
[0064] Figure 8 Show along Figure 7 The cross section intercepted by line AA. Figure 9 Show along Figure 7 The cross section cut by line BB.
[0065] like Figure 7 As shown, in the second embodiment, the planar shape of the opening OP1 of the recess CAV differs from that of the first embodiment in the top view viewed from the Z direction. Furthermore, the second embodiment differs from the first embodiment in that the material filling the recess CAV is a sealing resin MR.
[0066] In the planar shape of the opening OP1, four protrusions OP10 protruding in the X and Y directions are provided on each side of the generally rectangular opening OP5. In the top view viewed from the Z direction, the outer edge of the opening OP5 is larger than the outer edge of the semiconductor chip CH1 and is outside of it, and smaller than the outer edge of the semiconductor chip CH2 and is inside it.
[0067] On the other hand, the protrusion OP10 protrudes to the outer side of the outer edge of the semiconductor chip CH2. Therefore, as Figure 8 As shown, in the AA section of the region of the protrusion OP10, there is a gap GP between the semiconductor chip CH2 and the wiring substrate SUB1. The sealing resin MR penetrates from the gap GP into the recess CAV and fills the recess CAV.
[0068] In the top view viewed from the Z direction, the protrusions OP10 protrude approximately equally from both sides of the opening OP5. Furthermore, the protrusions OP10 have substantially the same width and length. As a result, the sealing resin MR is able to penetrate and fill the recess CAV substantially uniformly.
[0069] The outer edge of the opening OP5 is smaller than the outer edge of the semiconductor chip CH2 and is inside the outer edge of the semiconductor chip CH2. Therefore, as Figure 9 As shown, in the BB section of the opening OP5 region, the semiconductor chip CH2 is bonded to the solder resist 11a of the wiring substrate SUB1 through the insulating material D2.
[0070] Thus, in the second embodiment, the planar shape of the opening OP1 of the recess CAV has a protrusion OP10, and the gap GP is formed between the semiconductor chip CH2 and the wiring substrate SUB1, as shown. Figure 8As shown, after semiconductor chips CH2 and CH3 are stacked on semiconductor chip CH1, sealing resin MR can be filled in the space formed between semiconductor chip CH2 and recess CAV via gap GP. Sealing resin MR is also disposed on semiconductor chips CH2 and CH3 and formed on the first surface F1. Therefore, sealing resin MR is filled in recess CAV and covers the periphery of semiconductor chips CH2 and CH3 and bonding line BW. Sealing resin MR is integrally formed from the inside of recess CAV to the region above semiconductor chips CH2 and CH3 and is continuous in gap GP.
[0071] In the second embodiment, insulating material D2 can have the same thickness as insulating materials D1 and D3. Therefore, the recess CAV cannot be embedded with insulating material D2. Therefore, by providing the protrusion OP10, sealing resin MR can penetrate from the gap GP into the recess CAV and can be filled into the recess CAV.
[0072] Furthermore, the opening OP5 is smaller than the outer edge of the semiconductor chip CH2. Therefore, as... Figure 9 As shown, the wiring substrate SUB1 can support semiconductor chips CH2 and CH3.
[0073] The remaining configurations of the second implementation scheme can be the same as those of the first implementation scheme. Therefore, the second implementation scheme can achieve the same effect as the first implementation scheme.
[0074] Next, a method for manufacturing the semiconductor device 1 according to the second embodiment will be described.
[0075] Figure 10 and Figure 11 This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device 1 according to a second embodiment. Figure 10 This corresponds to the section cut along line AA. Figure 11 This corresponds to the section cut along line BB.
[0076] refer to Figure 3 and Figure 4 The described process is performed. Although the planar shape of the concave CAV is different, the cross-section at this time can be the same as... Figure 3 and Figure 4 The cross-sections shown are the same.
[0077] Next, as Figure 10 and Figure 11As shown, a semiconductor chip CH2 is stacked on a wiring substrate SUB1. An insulating material D2 is pre-attached to the back surface of the semiconductor chip CH2. The thickness of the insulating material D2 is less than that of the first embodiment, and can be the same as the thickness of the insulating materials D1 and D3. By curing the insulating material D2, the insulating material D2 bonds the semiconductor chip CH2 to the solder resist 11a of the wiring substrate SUB1.
[0078] Here, as Figure 10 As shown, in the region of the protrusion OP10, a gap GP is formed between the semiconductor chip CH2 and the wiring substrate SUB1. Additionally, as... Figure 11 As shown, in the region of the opening OP5, the semiconductor chip CH2 is bonded to the solder resist 11a of the wiring substrate SUB1 via the insulating material D2. A space SP is formed between the semiconductor chip CH2 and the wiring substrate SUB1.
[0079] Next, the electrode pads of the semiconductor chip CH2 and the electrode pads 13a on the first surface F1 are connected to each other by bonding wire BW.
[0080] Next, as Figure 8 and Figure 9 As shown, semiconductor chip CH3 and insulating material D3 are disposed on semiconductor chip CH2. Insulating material D3 is pre-attached to the back surface of semiconductor chip CH3. Therefore, by curing insulating material D3, semiconductor chip CH2 and semiconductor chip CH3 are bonded to each other. Next, the electrode pads of semiconductor chip CH3 and semiconductor chip CH2 are connected to each other by bonding wires BW.
[0081] Next, optionally, another semiconductor chip is stacked on top of semiconductor chip CH3 for wire bonding. Furthermore, to improve efficiency, the bonding process of the bonding wire BW can be performed in batches after all the semiconductor chips have been stacked.
[0082] Next, a sealing resin MR is formed on the first surface F1 to cover the stack of the semiconductor chip and bonding wires BW. At this time, the sealing resin MR is also filled in the space SP via the gap GP. As a result, a... Figure 8 and Figure 9 The structure shown.
[0083] In the second embodiment, the sealing resin MR fills the recess CAV and covers the semiconductor chips CH2 and CH3. Therefore, the sealing resin MR is integrally formed on the inner sides of the recess CAV and the semiconductor chips CH2 and CH3. As a result, the same type of insulating material as insulating materials D1 and D3 can be used as the insulating material D2, leading to a reduction in cost.
[0084] The remainder of the manufacturing process in the second embodiment can be the same as that in the first embodiment. Therefore, the second embodiment can achieve the same effects as the first embodiment.
[0085] (Third Implementation Plan)
[0086] Figure 12 This is a top view showing an example configuration of semiconductor device 1 according to a third embodiment. Figure 13 This is a cross-sectional view showing an example configuration of the semiconductor device 1 according to the third embodiment.
[0087] like Figure 12 As shown, in the third embodiment, in the top view viewed from the Z direction, the outer edge of the opening OP1 of the recess CAV is smaller than the outer edge of the semiconductor chip CH2 and is inside the outer edge of the semiconductor chip CH2. Therefore, the semiconductor chip CH2 is configured to cover the opening OP1 of the recess CAV and is also disposed on the wiring substrate SUB1.
[0088] In addition, such as Figure 13 As shown, in the third embodiment, a plurality of metal bumps BMP are provided as first electrodes on the rear surface of the bottom surface of the semiconductor chip CH1 facing the recess CAV. The wiring substrate SUB1 includes a plurality of second electrodes 14 corresponding to the metal bumps BMP on the bottom surface of the recess CAV. As a result, during chip bonding, the plurality of metal bumps BMP are respectively connected to the plurality of second electrodes 14. That is, the semiconductor chip CH1 is flip-chip bonded to the plurality of second electrodes 14 of the wiring substrate SUB1. As a result, the bonding wire BW does not need to be connected between the semiconductor chip CH1 and the wiring substrate SUB1.
[0089] Material A1 is provided around the metal bumps BMP and the second electrode 14. Material A1 is, for example, an anisotropic conductive film (ACF) in which conductive particles are dispersed in a thermosetting resin. Material A1 is conductive in the direction (Z direction) of bonding the semiconductor chip CH1 and has insulating properties in the X and Y directions. That is, due to thermocompression bonding when the semiconductor chip CH1 is bonded to the bottom surface of the recess CAV, the conductive particles in material A1 come into contact with the metal bumps BMP and the second electrode 14, and a conductive path is formed between the metal bumps BMP and the second electrode 14. On the other hand, the conductive particles are dispersed in the thermosetting resin between adjacent metal bumps BMP or between adjacent second electrodes 14, thereby continuously maintaining the insulating properties. As a result, electrical connection between the metal bumps BMP and the corresponding second electrodes 14 is ensured, and electrical insulation between adjacent metal bumps BMP or between adjacent second electrodes 14 is maintained.
[0090] Furthermore, during the bonding of the chip to the inside of the recess CAV, the semiconductor chip CH1 has a thickness at which the front surface of the semiconductor chip CH1 is substantially at the same height level as the front surface of the first surface F1 of the wiring substrate SUB1. That is, the front surface of the semiconductor chip CH1 is preferably substantially flush with the first surface F1. As a result, the recess CAV does not require the embedding of insulating material D2. Insulating material D2 can have the same thickness as insulating material D3.
[0091] An insulating material P1 is disposed between the side surface of the semiconductor chip CH1 and the inner wall of the recess CAV. The insulating material P1 is, for example, a potting resin used for embedding gaps. The potting resin is typically liquid and is cured by heat treatment or ultraviolet treatment. Furthermore, a material with a relatively low coefficient of thermal expansion is used as the potting resin. As a result, stress can be reduced, and cracks in the wiring substrate SUB1, etc., can be prevented. The semiconductor chip CH1 is fixed within the recess CAV by the aforementioned material P1 and the insulating material P1. Furthermore, the gaps in the recess CAV can be reduced, and the reliability of the semiconductor device 1 can be improved.
[0092] Semiconductor chip CH2 is stacked on wiring substrate SUB1 and the first surface F1 of semiconductor chip CH1. Furthermore, semiconductor chip CH3 is stacked on semiconductor chip CH2. Additionally, other semiconductor chips can be stacked on semiconductor chip CH3.
[0093] The remaining configurations of the third implementation scheme can be the same as those of the first implementation scheme. Therefore, the third implementation scheme can achieve the same effect as the first implementation scheme.
[0094] Next, a method for manufacturing the semiconductor device 1 according to the third embodiment will be described.
[0095] Figures 14 to 17 This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device 1 according to a third embodiment.
[0096] like Figure 14 As shown, a plurality of second electrodes 14 are disposed on the bottom surface of the recess CAV. The second electrodes 14 are electrically connected to any one of the wirings 12. The second electrodes 14 protrude from the bottom surface of the recess CAV. The remaining configuration of the wiring substrate SUB1 according to the third embodiment can be the same as the configuration of the wiring substrate SUB1 according to the first embodiment.
[0097] Subsequently, as Figure 15As shown, a semiconductor chip CH1 is disposed on the bottom surface of the recess CAV. Metal bumps BMP are disposed on the rear surface of the semiconductor chip CH1. Additionally, material A1 is pre-deposited around the second electrode 14. Therefore, by bonding the semiconductor chip CH1 to the bottom of the recess CAV, the metal bumps BMP on the rear surface of the semiconductor chip CH1 are connected to the corresponding second electrode 14. Furthermore, by curing material A1, the bottom of the recess CAV and the semiconductor chip CH1 are bonded together.
[0098] Next, as Figure 16 As shown, insulating material P1 flows into the gap between the side surface of the semiconductor chip CH1 and the sidewall of the recess CAV. Then, insulating material P1 is cured by heat treatment or ultraviolet treatment. As a result, the recess CAV is filled with semiconductor chip CH1 and insulating material P1.
[0099] Next, as Figure 17 As shown, a semiconductor chip CH2 is stacked on a wiring substrate SUB1 and on the first surface F1 of the semiconductor chip CH2. An insulating material D2 is pre-attached to the rear surface of the semiconductor chip CH2. The insulating material D2 can have the same thickness as the insulating material D3. Therefore, by curing the insulating material D2, the insulating material D2 bonds the solder resist 11a, the insulating material P1, and the semiconductor chip CH1 to the semiconductor chip CH2. Then, the electrode pads of the semiconductor chip CH2 and the electrode pads 13a on the first surface F1 are connected to each other via bonding wires BW.
[0100] Next, as Figure 13 As shown, semiconductor chip CH3 and insulating material D3 are disposed on semiconductor chip CH2. Insulating material D3 is pre-attached to the back surface of semiconductor chip CH3. Therefore, by curing insulating material D3, semiconductor chip CH2 and semiconductor chip CH3 are bonded to each other. Next, the electrode pads of semiconductor chip CH3 and semiconductor chip CH2 are connected to each other by bonding wires BW.
[0101] Next, optionally, another semiconductor chip is stacked on top of semiconductor chip CH3 for wire bonding. Furthermore, to improve efficiency, the bonding process of the bonding wire BW can be performed in batches after all the semiconductor chips have been stacked.
[0102] Next, a sealing resin MR is formed on the first surface F1 to cover the stack of the semiconductor chip and bonding wires BW. As a result, the following is obtained: Figure 13 The structure shown.
[0103] In the third embodiment, the semiconductor chip CH1 is flip-bonded to the inside of the recess CAV. Therefore, in the recess CAV, the semiconductor chip CH1 and the second electrode 14 do not need to be wire-bonded to each other. This facilitates the fabrication of the semiconductor device 1.
[0104] Furthermore, the front surface of the semiconductor chip CH1 is substantially at the same height level as the first surface F1 of the wiring substrate SUB1. As a result, the semiconductor chip CH2 can be bonded to both the semiconductor chip CH1 and the wiring substrate SUB1.
[0105] The remainder of the manufacturing process in the third embodiment can be the same as that in the first embodiment. Therefore, the third embodiment can achieve the same effects as the first embodiment.
[0106] Furthermore, insulating material P1 can be present between the front surface of semiconductor chip CH1 and the rear surface of semiconductor chip CH2 or insulating material D2. Even in this case, semiconductor chip CH2 can be stacked on top of semiconductor chip CH1 as long as the front surface of insulating material P1 is substantially at the same height level as the first surface F1 of wiring substrate SUB1.
[0107] While certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of this disclosure. In fact, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions, and changes may be made to the form of the embodiments described herein without departing from the spirit of this disclosure. Unless otherwise expressly stated, references to the terms “approximate,” “about,” “substantially,” or other terms of degree include variations of + / - 10% from a given measurement, unit, or range. The appended claims and their equivalents are intended to cover these forms or modifications that fall within the scope and spirit of this disclosure.
[0108] Explanation of reference numerals in the attached figures
[0109] 1 Semiconductor device
[0110] SUB1 Wiring Board
[0111] CH1~CH3 semiconductor chips
[0112] D1~D3 Insulation Materials
[0113] BW bond wire
[0114] MR sealing resin
[0115] 10 Resin Materials
[0116] 11a, 11b solder resist
[0117] 12 wiring
[0118] 13a, 13b electrode pads
Claims
1. A semiconductor device, comprising: A substrate, comprising a first surface and a recess in the first surface; A first semiconductor chip is disposed on the bottom surface of the recess; A first insulating material fills the recess and covers at least one surface of the first semiconductor chip; as well as At least one second semiconductor chip is stacked on top of the first semiconductor chip.
2. The semiconductor device according to claim 1, wherein, The depth of the recess is greater than the thickness of the first semiconductor chip.
3. The semiconductor device according to claim 1, wherein, The depth of the recess is the same as the thickness of the first insulating material.
4. The semiconductor device according to claim 1, wherein, The first insulating material covers the periphery of the at least one second semiconductor chip.
5. The semiconductor device according to claim 4, wherein, When viewed from a top view in the depth direction, the entire outer edge of the opening of the recess is outside the outer edge of the first semiconductor chip, a first portion of the outer edge of the opening of the recess is outside the outer edge of at least one second semiconductor chip, and a second portion of the outer edge of the opening of the recess is inside the outer edge of at least one second semiconductor chip.
6. The semiconductor device according to claim 1, wherein, The at least one second semiconductor chip includes a plurality of second semiconductor chips stacked on top of the first semiconductor chip.
7. The semiconductor device according to claim 1, wherein, The substrate includes a second electrode disposed on the bottom surface of the recess, and the first semiconductor chip is electrically connected to the second electrode via bonding wires.
8. A semiconductor device, comprising: A substrate, comprising a first surface and a recess in the first surface; A first semiconductor chip is disposed on the bottom surface of the recess and includes a front surface flush with the first surface; A first insulating material covering the front surface of the first semiconductor chip; and At least one second semiconductor chip is stacked on top of the first semiconductor chip.
9. The semiconductor device according to claim 1 or 8, wherein, When viewed from a top view in the depth direction, the outer edge of the opening of the recess is outside the outer edge of the first semiconductor chip.
10. The semiconductor device according to claim 1 or 8, wherein, The at least one second semiconductor chip is disposed on the first insulating material.
11. The semiconductor device according to claim 9, wherein, When viewed from a top view in the depth direction, the outer edge of the opening of the recess is outside the outer edge of the outer edge of at least one second semiconductor chip.
12. The semiconductor device according to claim 1 or 8, wherein, The at least one second semiconductor chip is disposed above the first semiconductor chip and the first surface of the substrate.
13. The semiconductor device according to claim 1 or 8, wherein, The at least one second semiconductor chip is a memory chip including an array of memory cells, and the first semiconductor chip is a controller chip including control circuitry for controlling the memory chip.
14. The semiconductor device according to claim 8, wherein, The first semiconductor chip includes a plurality of first electrodes on a surface facing the bottom surface of the recess, and the plurality of first electrodes are respectively connected to a plurality of second electrodes disposed on the bottom surface of the recess.
15. The semiconductor device according to claim 12, wherein, The at least one second semiconductor chip is disposed on the first insulating material, and The first insulating material is disposed on the first surface of the first semiconductor chip and the first surface of the substrate.
16. The semiconductor device according to claim 8, wherein, The at least one second semiconductor includes a plurality of second semiconductor chips stacked on the first semiconductor chip.