Capacitor structure and capacitor array and electronic device including same

Abstract

The invention provides a capacitor structure, a capacitor array and an electronic device. The capacitor structure includes a semiconductor substrate, a first well, a second well, a first electrode, a second electrode, a first choke impedance element, and a second choke impedance element. The semiconductor substrate includes an outer well having a first conductivity type. The first well is disposed in the outer well and has a second conductivity type. The second well is disposed in the first well and has the first conductivity type. At least portions of the first electrode and the second electrode contact the second well. A first choke impedance element is connected between the second well and a ground voltage. A second choke impedance element is connected between the first well and the supply voltage.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0116672, filed on August 29, 2024, and Korean Patent Application No. 10-2024-0177302, filed on December 3, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The example embodiments generally relate to semiconductor integrated circuits, and more specifically, to capacitor structures, switching structures, and capacitor arrays and electronic devices including capacitor structures and / or switching structures. Background Technology

[0003] As package prices increase, the chip size of radio frequency integrated circuits (RFICs) used in wireless mobile communications has become increasingly smaller. Furthermore, for RFICs used in wireless mobile communications, producing the desired output at low power is advantageous. Recently, with the evolution of mobile communications from third-generation (3G) to Long Term Evolution (LTE) and then to fifth-generation (5G), RFICs used in wireless mobile communications increasingly need to support modulation such as radio detection and ranging (RADAR), and the operating frequencies of RFICs used in wireless mobile communications are also increasing. However, problems exist in the design of impedance matching networks for RFICs used in wireless mobile communications, as well as in the design of RFICs with low-noise characteristics.

[0004] In RFICs used in wireless mobile communications and transportation for ultra-wideband (UWB) RADARs, there is an increasing demand for supporting wide bandwidth and also for high output power. Therefore, research is underway to address these issues. Summary of the Invention

[0005] One or more example embodiments provide capacitor and switching structures that can have relatively low parasitic capacitance.

[0006] In addition, one or more example embodiments provide capacitor arrays including capacitor structures and / or switching structures, which may have improved reliability and improved performance.

[0007] In addition, one or more example embodiments provide electronic devices including capacitor structures, switching structures, and / or capacitor arrays.

[0008] According to one aspect of an example embodiment, a capacitor structure includes: a semiconductor substrate including an outer well having a first conductivity type; a first well in the outer well and having a second conductivity type; a second well in the first well and having a first conductivity type; a first electrode and a second electrode, at least portions of the first electrode and the second electrode being in the second well; a first choke impedance element connected between the second well and a ground voltage; and a second choke impedance element connected between the first well and a power supply voltage.

[0009] According to one aspect of an example embodiment, a capacitor array includes: a plurality of capacitors connected between a first terminal and a second terminal; and at least one switch between two adjacent capacitors among the plurality of capacitors, wherein each of the plurality of capacitors includes: an outer well having a first conductivity type; a first well in the outer well and having a second conductivity type; a second well in the first well and having a first conductivity type; and a first electrode and a second electrode, at least a portion of the first electrode and the second electrode being in the second well, and wherein the second well of each of the plurality of capacitors is electrically isolated from other second wells of the other capacitors among the plurality of capacitors.

[0010] According to one aspect of an example embodiment, a capacitor array includes: a plurality of capacitors connected between a first terminal and a second terminal; and at least one switch between two adjacent capacitors among the plurality of capacitors, wherein the at least one switch includes: a plurality of transistors connected in series between a third terminal and a fourth terminal, each of the plurality of transistors including a gate electrode receiving a first switch control signal, the third terminal and the fourth terminal being between the two adjacent capacitors; a plurality of first resistors, each of the plurality of first resistors being connected to a node between the third terminal, the fourth terminal, or two adjacent transistors among the plurality of transistors, a second switch control signal being applied to each of the plurality of first resistors; a plurality of second resistors, each of the plurality of second resistors being connected between a gate electrode of one of the plurality of transistors and the first switch control signal; and a plurality of choke impedance elements, each of the plurality of choke impedance elements being connected between the body of the transistor among the plurality of transistors and ground voltage.

[0011] According to one aspect of an example embodiment, an electronic device includes: at least one capacitor, wherein the at least one capacitor includes: a semiconductor substrate including an outer well having a first conductivity type; a first well in the outer well and having a second conductivity type; a second well in the first well and having the first conductivity type; a first electrode and a second electrode, at least partially contacting the second well; a first choke impedance element connected between the second well and a ground voltage; and a second choke impedance element connected between the first well and a power supply voltage.

[0012] According to one aspect of an example embodiment, a switching structure configured to control an electrical connection between a first terminal and a second terminal includes: a plurality of transistors connected in series between the first terminal and the second terminal, each of the plurality of transistors including a gate electrode for receiving a first switch control signal; a plurality of first resistors, each of the plurality of first resistors connected to a node between the first terminal, the second terminal, or two adjacent transistors among the plurality of transistors, a second switch control signal being applied to each of the plurality of first resistors; a plurality of second resistors, each of the plurality of second resistors connected between the gate electrode of a transistor among the plurality of transistors and the first switch control signal; and a plurality of choke impedance elements, each of the plurality of choke impedance elements connected between the body of a transistor among the plurality of transistors and ground voltage.

[0013] The main bodies of the multiple transistors can be electrically isolated or electrically separated by multiple choke impedance elements.

[0014] The plurality of choke impedance elements can be configured to reduce the parasitic capacitance of the switching structure.

[0015] Each of the plurality of choke impedance elements may include a choke resistor.

[0016] The plurality of transistors may include a first transistor, a second transistor, and a third transistor connected in series between the first terminal and the second terminal.

[0017] The plurality of first resistors may include: a first first resistor connected between a first terminal and a second switch control signal; a first second resistor connected between a first node and a second switch control signal, the first node being between a first transistor and a second transistor; a first third resistor connected between a second node and a second switch control signal, the second node being between a second transistor and a third transistor; and a first fourth resistor connected between a second terminal and a second switch control signal.

[0018] The plurality of second resistors may include: a second first resistor connected between the gate electrode of the first transistor and the first switch control signal; a second second resistor connected between the gate electrode of the second transistor and the first switch control signal; and a second third resistor connected between the gate electrode of the third transistor and the first switch control signal.

[0019] The plurality of choke impedance elements may include: a first choke resistor connected between the body of the first transistor and ground voltage; a second choke resistor connected between the body of the second transistor and ground voltage; and a third choke resistor connected between the body of the third transistor and ground voltage.

[0020] The thickness of the insulating layer between the gate electrode and the semiconductor substrate of each of the plurality of transistors may be smaller than a reference thickness.

[0021] Each of the plurality of transistors may be an n-type metal-oxide-semiconductor transistor.

[0022] The capacitor structure according to the example embodiment can be implemented using a triple-well structure, and may include a first choke impedance element connected between the second well (e.g., the first impurity region and the second impurity region) and ground voltage, and may include a second choke impedance element connected between the first well (e.g., the fourth impurity region) and the power supply voltage. Therefore, parasitic capacitance can be reduced, and operating performance and characteristics can be improved.

[0023] The switching structure according to the example embodiment can be implemented using a stacked transistor structure and can include multiple choke impedance elements connected between the multiple transistors and ground voltage. Therefore, parasitic capacitance can be reduced, and operating performance and characteristics can be improved.

[0024] The capacitor array and electronic device according to the example embodiments may include capacitor structures and / or switching structures, thereby reducing parasitic capacitance and achieving a wide frequency tuning range. Consequently, insertion loss can be reduced, a wide frequency range can be supported, and reliability can be improved. Attached Figure Description

[0025] The illustrative and non-limiting exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0026] Figure 1 This is a diagram illustrating a capacitor structure according to an example embodiment.

[0027] Figure 2 It is shown Figure 1 An example diagram of a capacitor structure.

[0028] Figure 3 and Figure 4 It is used to describe Figure 2 A diagram illustrating the structure of a capacitor.

[0029] Figure 5A , Figure 5B and Figure 5C It is used to describe Figure 2 A diagram illustrating the characteristics of the capacitor structure.

[0030] Figure 6A , Figure 6B and Figure 6C It is shown that it includes Figure 2A diagram illustrating an example of the first and second electrodes in a capacitor structure.

[0031] Figure 7 It is shown Figure 1 An example diagram of a capacitor structure.

[0032] Figure 8 This is a diagram illustrating a switch structure according to an example embodiment.

[0033] Figure 9 It is shown Figure 8 A circuit diagram illustrating an example of a switch structure.

[0034] Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E , Figure 11A and Figure 11B It is used to describe Figure 9 A diagram illustrating the switch structure.

[0035] Figure 12A and Figure 12B It is shown that it includes Figure 9 An example diagram of a transistor in a switching structure.

[0036] Figure 13 , Figure 14 and Figure 15 This is a block diagram illustrating a capacitor array according to an example embodiment.

[0037] Figure 16 It is shown Figure 15 A circuit diagram of an example capacitor array.

[0038] Figure 17A , Figure 17B , Figure 17C and Figure 17D It is used to describe Figure 16 A diagram illustrating the operation of the capacitor array.

[0039] Figure 18 , Figure 19 and Figure 20 This is a block diagram illustrating an electronic device according to an example embodiment.

[0040] Figure 21 and Figure 22 It is shown Figure 20 A block diagram of an example electronic device.

[0041] Figure 23 This is a block diagram illustrating an electronic device in a network environment according to an example embodiment. Detailed Implementation

[0042] Various exemplary embodiments will be described more fully with reference to the accompanying drawings, in which embodiments are illustrated. However, this disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Throughout this application, the same reference numerals refer to the same elements.

[0043] Figure 1 This is a diagram illustrating a capacitor structure according to an example embodiment.

[0044] Reference Figure 1 The capacitor structure 10 includes a capacitor element C. UNIT The first choke impedance element is CIMP1, and the second choke impedance element is CIMP2. The choke impedance element may include discrete inductor elements (such as wires wound on a core), or it may be a planar circuit construction using a radial stub design.

[0045] In some example embodiments, capacitor structure 10 can be fabricated using semiconductor processes, and in addition to capacitor element C UNIT In addition to the first choke impedance element CIMP1 and the second choke impedance element CIMP2, the capacitor structure 10 may also include various components disposed (or arranged) and / or formed in and / or on the semiconductor substrate. (Refer to...) Figures 2 to 7 An example construction of capacitor structure 10 is described.

[0046] Capacitor element C UNIT Connected between the first terminal T11 and the second terminal T21. Capacitor element C UNIT It may include a first plate connected to the first terminal T11 and a second plate connected to the second terminal T21. Capacitor element C UNIT It may also include a dielectric material disposed and / or formed between the first plate and the second plate.

[0047] Capacitor structure 10 can be manufactured and / or modeled to include a first parasitic capacitor C. PAR1 Second parasitic capacitor C PAR2 For example, the first parasitic capacitor C PAR1 It can be connected between the first terminal T11 and node N11, and the second parasitic capacitor C PAR2 It can be connected between the second terminal T21 and node N11. First parasitic capacitor C PAR1 Second parasitic capacitor C PAR2 It may not be included in the actual product (e.g., it may not actually exist as a unit component in the actual product), and it may be or represent a parasitic component. Figure 1In the subsequent figures, the components corresponding to the parasitic components are shown by dashed lines.

[0048] In some example embodiments, when capacitor structure 10 is manufactured using a semiconductor process, the first parasitic capacitor C PAR1 Second parasitic capacitor C PAR2 It can be formed on the semiconductor substrate and the capacitor element C UNIT Between at least one of the first and second plates.

[0049] The first choke impedance element CIMP1 is connected between node N11 and ground voltage GND, and the second choke impedance element CIMP2 is connected between node N11 and power supply voltage VDD. Figure 1 In the accompanying diagram, three parallel straight lines of different lengths can represent the ground voltage GND.

[0050] When the first choke impedance element CIMP1 and the second choke impedance element CIMP2 are included in and connected to the capacitor structure 10, the parasitic capacitance of the capacitor structure 10 can be reduced, which will refer to Figure 5A , Figure 5B and Figure 5C describe.

[0051] In some example embodiments, each of the first choke impedance element CIMP1 and the second choke impedance element CIMP2 can be implemented to have a relatively high impedance.

[0052] In some example embodiments, capacitor structure 10 may be included in various electronic devices operating at relatively high operating frequencies, and for example, may be included in electronic devices that perform frequency tuning operations by adjusting capacitance. For example, capacitor structure 10 may be included in a capacitor array for performing and supporting frequency tuning operations and for obtaining a relatively wide frequency tuning range. (Refer to...) Figures 13 to 17D Describe the capacitor array, and refer to Figures 18 to 23 Describe an electronic device.

[0053] Figure 2 It is shown Figure 1 An example diagram of a capacitor structure.

[0054] Reference Figure 2The capacitor structure 100a includes a semiconductor substrate 101, an outer well 103, first wells 111, 112 and 113, a second well 121, a first electrode 141, a second electrode 142, a first choke impedance element 151, and a second choke impedance element 152. The capacitor structure 100a may also include a first impurity region 131, a second impurity region 132, a third impurity region 133, a fourth impurity region 134, a fifth impurity region 135, and a sixth impurity region 136.

[0055] exist Figure 2 In the accompanying figures, the direction perpendicular or substantially perpendicular to the first surface (e.g., the upper surface or top surface) of the semiconductor substrate 101 is referred to as the first direction DR1 (e.g., the Z-axis direction). Furthermore, two directions, each parallel or substantially parallel to the first surface of the semiconductor substrate 101 and intersecting each other, are referred to as the second direction DR2 (e.g., the X-axis direction) and the third direction DR3 (e.g., the Y-axis direction). For example, the second direction DR2 and the third direction DR3 may be perpendicular or substantially perpendicular to each other. Additionally, the first direction DR1 may be perpendicular or substantially perpendicular to both the second direction DR2 and the third direction DR3. Furthermore, the direction indicated by the arrows in the figures and the opposite direction are considered to be the same direction.

[0056] Semiconductor substrate 101 has a first conductivity type. An outer well 103 is disposed and / or formed in semiconductor substrate 101 and has a first conductivity type. First wells 111, 112, and 113 are disposed and / or formed in outer well 103 and have a second conductivity type different from the first conductivity type. A second well 121 is disposed and / or formed in first wells 111, 112, and 113 and has a first conductivity type.

[0057] In some example embodiments, the first conductivity type may be p-type conductivity, and the second conductivity type may be n-type conductivity. In this example, the semiconductor substrate 101 may correspond to the p-type substrate PSUB, the outer well 103 may correspond to the p-well PW, the first wells 111, 112, and 113 may correspond to the n-wells NW and DNW, and the second well 121 may correspond to the p-well PW.

[0058] In some example embodiments, the triple-well structure can be implemented by an outer well 103, first wells 111, 112, and 113, and a second well 121. For example, a PNP triple-well structure can be formed when the outer well 103 corresponds to the p-well PW, when the first wells 111, 112, and 113 correspond to the n-wells NW and DNW, and when the second well 121 corresponds to the p-well PW, but the example embodiments are not limited thereto.

[0059] In the following description, example embodiments will be based on the premise that the first conductivity type is p-type conductivity and the second conductivity type is n-type conductivity. However, the example embodiments are not limited thereto. In some example embodiments, the first conductivity type may be n-type conductivity and the second conductivity type may be p-type conductivity.

[0060] The first impurity region 131 and the second impurity region 132 may be disposed and / or formed in the second well 121, and may have a first conductivity type. For example, in a cross-sectional view, the first impurity region 131 and the second impurity region 132 may be spaced apart from each other along a second direction DR2 in the second well 121.

[0061] In some example embodiments, the impurity concentrations of the first impurity region 131 and the second impurity region 132 may be higher than the impurity concentration of the second well 121. For example, when the second well 121 corresponds to the p-well PW, each of the first impurity region 131 and the second impurity region 132 may correspond to the P+ region.

[0062] The third impurity region 133 and the fourth impurity region 134 may be disposed and / or formed in the first wells 111, 112 and 113, and may have a second conductivity type. For example, in a cross-sectional view, the third impurity region 133 and the fourth impurity region 134 may be spaced apart from each other along a second direction DR2 in the first wells 111, 112 and 113.

[0063] In some example embodiments, the impurity concentrations of the third impurity region 133 and the fourth impurity region 134 may be higher than the impurity concentrations of the first wells 111, 112, and 113. For example, when the first wells 111, 112, and 113 correspond to n-wells NW and DNW, each of the third impurity region 133 and the fourth impurity region 134 may correspond to an N+ region.

[0064] In some example embodiments, the first wells 111, 112, and 113 may include a first well region 111, a second well region 112, and a third well region 113. The first well region 111 may surround the third impurity region 133 and may contact a first side surface of the second well 121. The second well region 112 may surround the fourth impurity region 134 and may contact a second side surface of the second well 121. The third well region 113 may contact the lower surface of the second well 121. The outer well 103 and the second well 121 may be separated or isolated by the first wells 111, 112, and 113.

[0065] In some example embodiments, the first well region 111 and the second well region 112 may be in contact with the upper surface of the semiconductor substrate 101, and the third well region 113 may be spaced apart from the upper surface of the semiconductor substrate 101. For example, when the first wells 111, 112, and 113 correspond to n-wells (NWs) and DNWs, the first well region 111 and the second well region 112 may correspond to a normal n-well (NW), and the third well region 113 may correspond to a deep n-well (DNW) that is different from a normal n-well (NW).

[0066] Although the first well region 111 and the second well region 112 are shown as separate components for ease of illustration, the exemplary embodiment is not limited thereto. For example, the first well region 111 and the second well region 112 may be integrally formed to surround the second well 121 in a plan view (or on a plane).

[0067] The fifth impurity region 135 and the sixth impurity region 136 may be disposed and / or formed in the outer well 103, may have a first conductivity type, and may be connected to ground voltage. For example, in a cross-sectional view, the fifth impurity region 135 and the sixth impurity region 136 may be spaced apart from each other in the outer well 103 along a second direction DR2.

[0068] In some example embodiments, the impurity concentrations of the fifth impurity region 135 and the sixth impurity region 136 may be higher than the impurity concentration of the outer well 103. For example, when the outer well 103 corresponds to the p-well PW, each of the fifth impurity region 135 and the sixth impurity region 136 may correspond to the P+ region.

[0069] The first electrode 141 and the second electrode 142 are disposed and / or formed on the semiconductor substrate 101. For example, at least a portion of the first electrode 141 and the second electrode 142 may be disposed and / or formed on the second well 121 between the first impurity region 131 and the second impurity region 132. The first electrode 141 and the second electrode 142 may be respectively disposed with respect to the semiconductor substrate 101. Figure 1 Capacitor element C UNIT The first plate and the second plate in the semiconductor substrate 101 correspond to each other. For example, the first electrode 141 and the second electrode 142 can be formed using a conductive layer (e.g., a metal layer) on the semiconductor substrate 101.

[0070] Although the first electrode 141 and the second electrode 142 are shown stacked on the first direction DR1 for ease of illustration, the exemplary embodiment is not limited thereto. Reference will be made later. Figure 6A , Figure 6B and Figure 6C An example construction of the first electrode 141 and the second electrode 142 is described.

[0071] The first choke impedance element 151 is connected between the second well 121 and the ground voltage. For example, the first choke impedance element 151 can be connected between the first impurity region 131 and the second impurity region 132 in the second well 121 and the ground voltage. Therefore, unlike the fifth impurity region 135 and the sixth impurity region 136 which are directly connected to the ground voltage, the first impurity region 131 and the second impurity region 132 can be connected to the ground voltage through the first choke impedance element 151.

[0072] The second choke impedance element 152 is connected between the first wells 111, 112, and 113 and the power supply voltage VDD. For example, the second choke impedance element 152 may be connected between the fourth impurity region 134 in the first wells 111, 112, and 113 and the power supply voltage VDD. Therefore, the fourth impurity region 134 can be connected to the power supply voltage VDD through the second choke impedance element 152. For example, the third impurity region 133 may be electrically floated, but the example embodiment is not limited thereto.

[0073] In some example embodiments, each of the first choke impedance element 151 and the second choke impedance element 152 may include a choke resistor. For example, the first choke impedance element 151 may include a first choke resistor R connected between the first impurity region 131 and the second impurity region 132 and the ground voltage. BSUB Furthermore, the second choke impedance element 152 may include a second choke resistor R connected between the fourth impurity region 134 and the power supply voltage VDD. BNW For example, the first choke impedance element 151 and the second choke impedance element 152 can be achieved by using the first choke resistor R. BSUB Second choke resistor R BNW It has relatively high impedance, but the example embodiments are not limited to this.

[0074] In some example embodiments, when the first impurity region 131 and the second impurity region 132 correspond to the P+ region, and when the fourth impurity region 134 corresponds to the N+ region, the first choke impedance element 151 connected to the P+ region and the second choke impedance element 152 connected to the N+ region can be implemented separately.

[0075] In some exemplary embodiments, the first choke impedance element 151 and the second choke impedance element 152 may be disposed on the semiconductor substrate 101 and may be arranged in a plan view outside the first wells 111, 112 and 113 and the second well 121. However, the exemplary embodiments are not limited thereto.

[0076] although Figure 2A capacitor structure 100a is shown formed in and / or on a semiconductor substrate, but the example embodiment is not limited thereto, and multiple capacitor structures may be formed in and / or on the semiconductor substrate 101. For example, when multiple capacitor structures are formed in and / or on the semiconductor substrate 101, the multiple capacitor structures may share an outer well 103. For example, the multiple capacitor structures may be implemented by forming a plurality of first wells in one outer well and by forming each of a plurality of second wells in a corresponding one of the plurality of first wells.

[0077] Figure 3 and Figure 4 It is used to describe Figure 2 A diagram illustrating the structure of a capacitor.

[0078] Reference Figure 3 An example of a parasitic component generated by a component in capacitor structure 100a is shown.

[0079] Reference Figure 1 The parasitic capacitor C described PAR1 and C PAR2 It can be formed between the second well 121 and at least one of the first electrode 141 and the second electrode 142.

[0080] Parasitic diode D PWTW1 and D PWTW2 It can be formed by a PN junction between the second well 121 and the third well region 113 among the first wells 111, 112 and 113.

[0081] Parasitic diode D NW1 It can be formed by a PN junction between the fifth impurity region 135 and the first well region 111 among the first wells 111, 112, and 113. Parasitic diode D TW1 It can be formed by a PN junction between the fifth impurity region 135 and the third well region 113 among the first wells 111, 112 and 113.

[0082] Parasitic diode D NW2 It can be formed by a PN junction between the sixth impurity region 136 and the second well region 112 among the first wells 111, 112, and 113. Parasitic diode D TW2 It can be formed by a PN junction between the sixth impurity region 136 and the third well region 113 among the first wells 111, 112 and 113.

[0083] Reference Figure 4 An example of an equivalent circuit is shown, which includes a capacitor element C formed by a first electrode 141 and a second electrode 142. UNITThe first choke resistor R, included in the first choke impedance element 151 and the second choke impedance element 152 BSUB Second choke resistor R BNW as well as Figure 3 Parasitic components in.

[0084] Capacitor element C UNIT and parasitic capacitor C PAR1 and C PAR2 The connection can be with the reference Figure 1 The connections described are basically the same.

[0085] First choke resistor R BSUB It can be connected between node N11 and ground. Parasitic diode D PWTW It can be with Figure 3 Parasitic diode D in PWTW1 and D PWTW2 The corresponding parasitic component can be connected between nodes N11 and N21. Parasitic diode D TW It can be with Figure 3 Parasitic diode D in TW1 and D TW2 The corresponding parasitic component can be connected between node N21 and ground voltage. Parasitic diode D NW It can be with Figure 3 Parasitic diode D in NW1 and D NW2 The corresponding parasitic component, and can be connected between node N21 and ground voltage and parasitic diode D. TW Parallel connection. Second choke resistor R BNW It can be connected between node N21 and the power supply voltage VDD.

[0086] When capacitor structure 100a has Figure 4 When constructing the equivalent circuit shown, the parasitic capacitance of capacitor structure 100a can be reduced. For example, the parasitic capacitance of capacitor structure 100a can be determined based on the second choke resistor R. BNW The resistance decreases.

[0087] Figure 5A , Figure 5B and Figure 5C It is used to describe Figure 2 A diagram illustrating the characteristics of the capacitor structure.

[0088] Reference Figure 5A The left side includes Figure 4 The second choke resistor R BNW and parasitic diode D PWTW D TW and DNW The circuit is modeled as including the second choke resistor R on the right side. BNW and parasitic capacitor C PWTW and C NWTW An example of the circuit is shown.

[0089] For example, parasitic capacitor C PWTW Can be used with parasitic diode D PWTW The capacitor assembly corresponds to, and the parasitic capacitor C NWTW Can be used with parasitic diode D TW and D NW The parallel connection of capacitor components corresponds to this. For example, parasitic capacitor C PWTW It can be connected between node N11 and node N21, and the second choke resistor R BNW and parasitic capacitor C NWTW It can be connected in parallel between node N21 and the ground voltage.

[0090] Reference Figure 5B , Figure 4 The equivalent circuit includes the first choke resistor R. BSUB Second choke resistor R BNW and parasitic diode D PWTW D TW and D NW Partial use Figure 5A The modeling circuit on the right (e.g., including the second choke resistor R) BNW and parasitic capacitor C PWTW and C NWTW An example of a circuit replacement is shown.

[0091] Reference Figure 5C ,exist Figure 5B An example of reduced parasitic capacitance in a circuit is shown.

[0092] exist Figure 5C In the curve graph, the horizontal axis represents the second choke resistor R. BNW The resistance is shown, and the vertical axis represents the parasitic capacitance of the capacitor structure. Furthermore, CASE1 indicates that the first choke resistor R is not included. BSUB Second choke resistor R BNW The conventional capacitor structure, and CASE2 represents the first choke resistor R according to the example embodiment. BSUB Second choke resistor R BNW The capacitor structure is 100a. In the following description, the capacitor and its corresponding capacitance will be described using the same reference numerals.

[0093] Excluding the first choke resistor R BSUBSecond choke resistor R BNW In a conventional capacitor structure, the parasitic capacitor C PWTW and C NWTW The effect of parasitic capacitance can be ignored; therefore, parasitic capacitance can be determined solely by parasitic capacitor C. PAR1 and C PAR2 Determined. For example, in CASE1, capacitor C1 can have the same capacitance as the parasitic capacitor C. PAR1 and C PAR2 The values ​​corresponding to the parallel connection (e.g., C1=C) PAR1 +C PAR2 For example, when C PAR1 =C PAR2 At that time, C1 = 2 × C PAR1 =2×C PAR2 Furthermore, since conventional capacitor structures do not include a first choke resistor R... BSUB Second choke resistor R BNW Therefore, the parasitic capacitance can be constant, while the second choke resistor R... BNW The resistance is irrelevant.

[0094] According to the example embodiment, the first choke resistor R is included. BSUB Second choke resistor R BNW In capacitor structure 100a, the parasitic capacitor C PWTW and C NWTW The effect can be seen through the second choke resistor R BNW Let's consider it.

[0095] For example, even the second choke resistor R BNW The resistance is very small, and the parasitic capacitance C PWTW The effects of parasitic capacitance are also considered, and the parasitic capacitance can be determined by the parasitic capacitor C. PAR1 and C PAR2 and parasitic capacitor C PWTW Determined. For example, in CASE2, when the second choke resistor R... BNW When the resistance is very small, capacitor C2 can have the same resistance as capacitor C1 and parasitic capacitor C. PWTW The values ​​corresponding to the series connection (e.g., 1 / C2 = 1 / C1 + 1 / C) PWTW ).

[0096] For example, with the second choke resistor R BNW The increased resistance not only affects the parasitic capacitor C PWTW Moreover, the parasitic capacitor C NWTW The effects can be considered together, and the parasitic capacitance can be determined by the parasitic capacitor C. PAR1 and C PAR2 Parasitic capacitor CPWTW and parasitic capacitor C NWTW Determined. For example, in CASE2, when the second choke resistor R... BNW When the resistance is very high, capacitor C3 can have the same characteristics as capacitor C2 and parasitic capacitor C. NWTW The values ​​corresponding to the series connection (e.g., 1 / C3 = 1 / C2 + 1 / C) NWTW ).

[0097] As can be seen from the above, compared with the conventional capacitor structure, the example embodiment includes a first choke resistor R. BSUB Second choke resistor R BNW The parasitic capacitance of capacitor structure 100a is reduced. For example, with the second choke resistor R... BNW As the resistance increases, the parasitic capacitance of the 100A capacitor structure can be reduced.

[0098] Figure 6A , Figure 6B and Figure 6C It is shown that it includes Figure 2 A diagram illustrating an example of the first and second electrodes in a capacitor structure.

[0099] Reference Figure 6A The first electrode 141a and the second electrode 142a can be stacked in a direction perpendicular to the upper surface of the semiconductor substrate 101 (e.g., in the first direction DR1).

[0100] For example, a first conductive layer and a second conductive layer stacked on the first direction DR1 can be formed in an insulating layer 143. For example, the insulating layer 143 may include multiple insulating layers. Among the first conductive layer and the second conductive layer, the first conductive layer, as the lower conductive layer, may include a first electrode 141a, and the second conductive layer, as the upper conductive layer, may include a second electrode 142a. For example, the first electrode 141a, the second electrode 142a, and the insulating layer 143 may be disposed and / or formed on the semiconductor substrate 101.

[0101] In some example embodiments, when the first electrode 141a and the second electrode 142a are stacked in the first direction DR1, the parasitic capacitor C PAR1 and C PAR2 It can be formed between the second well 121 and the first electrode 141a, where the first electrode 141a is the lower electrode between the first electrode 141a and the second electrode 142a.

[0102] Reference Figure 6B The first electrode 141b and the second electrode 142b may be spaced apart from each other in a direction parallel to the upper surface of the semiconductor substrate 101 (e.g., the second direction DR2).

[0103] For example, the first electrode 141b and the second electrode 142b may be disposed and / or formed in the same conductive layer within an insulating layer (not shown). For example, in the same conductive layer, the first electrode 141b may extend in a third direction DR3, and the second electrode 142b may extend in a third direction DR3, while being spaced apart from the first electrode 141b in a second direction DR2. For example, the first electrode 141b, the second electrode 142b, and the insulating layer may be disposed and / or formed on a semiconductor substrate 101.

[0104] In some example embodiments, when the first electrode 141b and the second electrode 142b are spaced apart in the same conductive layer along the second direction DR2, the parasitic capacitor C PAR1 and C PAR2 It can be formed between the second well 121 and the first electrode 141b and the second electrode 142b.

[0105] Reference Figure 6C The first electrode 141c and the second electrode 142c may be spaced apart from each other in a direction parallel to the upper surface of the semiconductor substrate 101 (e.g., in the second direction DR2 and the third direction DR3). For simplicity, the terms "and" will be omitted. Figure 6B The description is repetitive or overlapping.

[0106] For example, the first electrode 141c and the second electrode 142c can be disposed and / or formed in the same conductive layer within an insulating layer (not shown). The first electrode 141c may include a first main electrode 145 extending in a third direction DR3 and a first sub-electrode 146 extending from the first main electrode 145 and arranged along the third direction DR3 in a second direction DR2. The second electrode 142c may include a second main electrode 147 extending in a third direction DR3 and a second sub-electrode 148 extending from the second main electrode 147 and arranged along the third direction DR3 in a second direction DR2. The first sub-electrode 146 and the second sub-electrode 148 may be arranged alternately along the third direction DR3, thereby improving capacitance.

[0107] However, the example embodiments are not limited to this, and are used to form capacitor element C. UNIT The construction and arrangement of the first electrode 141 and the second electrode 142 can be implemented differently according to the example embodiment.

[0108] Figure 7 It is shown Figure 1 An example diagram of a capacitor structure is shown. For brevity, symbols and symbols are omitted. Figure 2 The description is repetitive or overlapping.

[0109] Reference Figure 7The capacitor structure 100b includes a semiconductor substrate 101, an outer well 103, a first well 111b, a second well 121, a first electrode 141, a second electrode 142, a first choke impedance element 151, and a second choke impedance element 152. The capacitor structure 100b may also include a first impurity region 131, a second impurity region 132, a third impurity region 133, a fourth impurity region 134, a fifth impurity region 135, and a sixth impurity region 136.

[0110] Apart from the structural changes to the first well 111b, the capacitor structure 100b can be combined with... Figure 2 The capacitor structure is basically the same as that of the 100a capacitor.

[0111] The first well 111b can be integrally formed to surround the second well 121. In other words, with Figure 2 The first wells 111, 112 and 113 are divided into a first well region 111, a second well region 112 and a third well region 113, respectively. The first well 111b can be formed integrally.

[0112] The capacitor structure according to the example embodiment can be implemented as a three-well structure, and may include a first choke impedance element 151 connected between the second well 121 (e.g., the first impurity region 131 and the second impurity region 132) and ground voltage, and may include a second choke impedance element 152 connected between the first wells 111, 112, 113 and 111b (e.g., the fourth impurity region 134) and the power supply voltage VDD. Therefore, parasitic capacitance can be reduced, and operating performance and characteristics can be improved.

[0113] Figure 8 This is a diagram illustrating a switch structure according to an example embodiment.

[0114] Reference Figure 8 The switch structure 20 controls the electrical connection between the first terminal T12 and the second terminal T22, and includes multiple transistors TR, multiple first resistors R1, multiple second resistors R2, and multiple choke impedance elements CIMP.

[0115] In some example embodiments, the switch structure 20 may be fabricated using semiconductor processes and may also include various components disposed (or arranged) and / or formed in and / or on a semiconductor substrate. Reference will be made to... Figures 9 to 12B Describe an example construction of switch structure 20.

[0116] Multiple transistors TR are connected in series between the first terminal T12 and the second terminal T22. Each of the multiple transistors TR has a gate electrode that receives a first switch control signal SC1. For example, each of the multiple transistors TR may be an n-type metal-oxide-semiconductor (NMOS) transistor, but the example embodiment is not limited thereto.

[0117] In some example embodiments, each of the plurality of transistors TR can be a thin gate oxide transistor. For example, the thickness of the insulating layer disposed between the gate electrode and the semiconductor substrate of each of the plurality of transistors TR can be smaller than a reference thickness, but the example embodiments are not limited thereto.

[0118] Each of the plurality of first resistors R1 is connected to a node between two adjacent transistors of the first terminal T12, the second terminal T22, or the plurality of transistors TR. A second switch control signal SC2 is applied to each of the plurality of first resistors R1. For example, one end of each of the plurality of first resistors R1 may be connected to a node between two adjacent transistors of the first terminal T12, the second terminal T22, or the plurality of transistors TR. For example, the second switch control signal SC2 may be applied to the other end of each of the plurality of first resistors R1.

[0119] like Figure 8 As shown, multiple first resistors R1 and multiple transistors TR can be alternately arranged between the first terminal T12 and the second terminal T22. Therefore, the number of multiple first resistors R1 can be one more than the number of multiple transistors TR.

[0120] In some example embodiments, the switching on and off of the switch structure 20 (e.g., the electrical connection and disconnection between the first terminal T12 and the second terminal T22) can be controlled based on the first switch control signal SC1 and the second switch control signal SC2, which will refer to Figure 11A and Figure 11B describe.

[0121] Each of the plurality of second resistors R2 is connected between the gate electrode of one of the plurality of transistors TR and the first switch control signal SC1. For example, one end of each of the plurality of second resistors R2 may be connected to the gate electrode of the corresponding one of the plurality of transistors TR. For example, the first switch control signal SC1 may be applied to the other end of the corresponding one of the plurality of second resistors R2. For example, a transistor TR and a second resistor R2 may be connected, and therefore the number of the plurality of second resistors R2 may be equal to the number of the plurality of transistors TR.

[0122] Each of the multiple choke impedance elements CIMP is connected between the body of one of the multiple transistor TRs and ground voltage GND. For example, one end of each of the multiple choke impedance elements CIMP can be connected to the body of the corresponding one of the multiple transistor TRs. For example, the other end of each of the multiple choke impedance elements CIMP can be connected to ground voltage GND. For example, a transistor TR and a choke impedance element CIMP can be connected, so the number of multiple choke impedance elements CIMP can be equal to the number of multiple transistor TRs.

[0123] In some example embodiments, the plurality of transistors TR may have a body separation structure in which the bodies of the plurality of transistors TR are electrically isolated and / or electrically separated by a plurality of choke impedance elements CIMP.

[0124] When multiple choke impedance elements CIMP are included in and connected to the switching structure 20, the parasitic capacitance of the switching structure 20 can be reduced, which will refer to Figure 10A , Figure 10B , Figure 10C , Figure 10D and Figure 10E describe.

[0125] In some example embodiments, each of the multiple choke impedance elements CIMP can be implemented to have a relatively high impedance.

[0126] In some example embodiments, the switch structure 20 may be included in various electronic devices that operate at relatively high operating frequencies, and for example, may be included in electronic devices that perform frequency tuning operations by adjusting a capacitor. For example, the switch structure 20 may be included in a capacitor array for performing and supporting frequency tuning operations and for obtaining a relatively wide frequency tuning range.

[0127] Figure 9 It is shown Figure 8 A circuit diagram illustrating an example of a switch structure.

[0128] Reference Figure 9 The switching structure 200a includes multiple transistors TR1, TR2 and TR3, multiple first resistors R11, R12, R13 and R14, multiple second resistors R21, R22 and R23, and multiple choke impedance elements.

[0129] The multiple transistors TR1, TR2, and TR3 may include a first transistor TR1, a second transistor TR2, and a third transistor TR3. The first transistor TR1, the second transistor TR2, and the third transistor TR3 may be connected in series between the first terminal T12 and the second terminal T22.

[0130] In some example embodiments, the stacked transistor structure can be implemented by connecting multiple transistors TR1, TR2, and TR3 in series. For example, a triple-stacked transistor structure can be formed when three transistors TR1, TR2, and TR3 are connected in series, but the example embodiments are not limited to this.

[0131] The plurality of first resistors R11, R12, R13, and R14 may include a first first resistor R11, a first second resistor R12, a first third resistor R13, and a first fourth resistor R14. The first first resistor R11 may be connected between the first terminal T12 and the second switch control signal SC2. The first second resistor R12 may be connected between node N12 and the second switch control signal SC2, with node N12 located between the first transistor TR1 and the second transistor TR2. The first third resistor R13 may be connected between node N22 and the second switch control signal SC2, with node N22 located between the second transistor TR2 and the third transistor TR3. The first fourth resistor R14 may be connected between the second terminal T22 and the second switch control signal SC2.

[0132] The plurality of second resistors R21, R22, and R23 may include a second first resistor R21, a second second resistor R22, and a second third resistor R23. The second first resistor R21 may be connected between the gate electrode of the first transistor TR1 and the first switch control signal SC1. The second second resistor R22 may be connected between the gate electrode of the second transistor TR2 and the first switch control signal SC1. The second third resistor R23 may be connected between the gate electrode of the third transistor TR3 and the first switch control signal SC1.

[0133] In some example embodiments, the plurality of choke impedance elements may include a plurality of choke resistors RCHK1, RCHK2, and RCHK3, wherein the plurality of choke resistors RCHK1, RCHK2, and RCHK3 include a first choke resistor RCHK1, a second choke resistor RCHK2, and a third choke resistor RCHK3. For example, the first choke resistor RCHK1 may be connected between the body of the first transistor TR1 and ground. The second choke resistor RCHK2 may be connected between the body of the second transistor TR2 and ground. The third choke resistor RCHK3 may be connected between the body of the third transistor TR3 and ground. For example, the plurality of choke impedance elements may have relatively high impedance by using a plurality of choke resistors RCHK1, RCHK2, and RCHK3, but the example embodiments are not limited thereto.

[0134] Figure 10A , Figure 10B , Figure 10C , Figure 10D, Figure 10E , Figure 11A and Figure 11B It is used to describe Figure 9 A diagram illustrating the switch structure.

[0135] Reference Figure 10A An example of a parasitic component generated by a component in switch structure 200a is shown.

[0136] Parasitic capacitor C PAR3 It can be formed between node NA corresponding to the first terminal T12 and node NB corresponding to the body of the first transistor TR1. Similarly, the parasitic capacitor C PAR4 It can be formed between node NC corresponding to the second terminal T22 and node ND corresponding to the body of the third transistor TR3.

[0137] Reference Figure 10B and Figure 10C An example of a signal in a switching structure 200a comprising multiple choke resistors RCHK1, RCHK2 and RCHK3 according to an example embodiment is shown. Figure 10B The voltage level of the signal at node NA is shown, and Figure 10C Showing response to Figure 10B The voltage level of the signal at node NB.

[0138] like Figure 10B and Figure 10C As shown, when the switching structure 200a includes multiple choke resistors RCHK1, RCHK2, and RCHK3, the difference between the signal swing width VSWA at node NA and the signal swing width VSWB at node NB can be relatively small. Therefore, the parasitic capacitance can be reduced through the parasitic capacitor C. PAR3 Reduced. Similarly, although not shown in detail, the signal at node NC can be substantially the same as the signal at node NA, and the signal at node ND can be substantially the same as the signal at node NB. Therefore, the parasitic capacitance can be reduced through the parasitic capacitor C. PAR4 Decrease.

[0139] Reference Figure 10D and Figure 10E An example of a signal in a conventional switching structure excluding multiple choke resistors RCHK1, RCHK2 and RCHK3 is shown.

[0140] like Figure 10D and Figure 10EAs shown, when the conventional switching structure does not include multiple choke resistors RCHK1, RCHK2, and RCHK3, the difference between the signal swing width VSWA' at node NA and the signal swing width VSWB' at node NB may be relatively large. Therefore, due to the parasitic capacitor C PAR3 The resulting parasitic capacitance may increase. Similarly, due to the parasitic capacitance C... PAR4 The resulting parasitic capacitance may also increase.

[0141] As can be seen from the above, compared with conventional switching structures, the parasitic capacitance of the switching structure 200a, which includes multiple choke resistors RCHK1, RCHK2 and RCHK3 according to the example embodiment, is reduced.

[0142] Reference Figure 11A An example of the switching structure 200a being turned on (e.g., an example where the first terminal T12 and the second terminal T22 are electrically connected to each other via the switching structure 200a) is shown. For example, the switching structure 200a can be turned on when the first switch control signal SC1 has a first voltage level VH and when the second switch control signal SC2 has a second voltage level VL, and the first terminal T12 and the second terminal T22 can be electrically connected to each other. For example, the first voltage level VH can be higher than the second voltage level VL.

[0143] Reference Figure 11B An example of the switch structure 200a being turned off (e.g., an example where the first terminal T12 and the second terminal T22 are electrically disconnected from each other via the switch structure 200a) is shown. For example, when the first switch control signal SC1 has a second voltage level VL, and when the second switch control signal SC2 has a first voltage level VH, the switch structure 200a can be turned off, and the first terminal T12 and the second terminal T22 can be electrically disconnected from each other.

[0144] As described above, the switch structure 200a according to the example embodiment can be implemented using a stacked transistor structure. The turning on and turning off of the switch structure 200a can be controlled using the same voltage levels VH and VL, and reliability issues will not occur even if the same voltage levels VH and VL are used.

[0145] Figure 12A and Figure 12B It is shown that it includes Figure 9 An example diagram of a transistor in a switching structure.

[0146] Reference Figure 12A The transistor 250a may include a semiconductor substrate 251, a first well 261, a first impurity region 271, a second impurity region 272, an insulating layer 281a, and a gate electrode 282.

[0147] The semiconductor substrate 251 may have a first conductivity type. The first well 261 may also have a first conductivity type. For example, the first conductivity type may be p-type conductivity. In this example, the semiconductor substrate 251 may correspond to a p-type substrate PSUB, and the first well 261 may correspond to a p-well PW.

[0148] The first impurity region 271 and the second impurity region 272 may be disposed and / or formed in the first well 261, and may have a second conductivity type different from the first conductivity type. For example, in a cross-sectional view, the first impurity region 271 and the second impurity region 272 may be spaced apart from each other along a second direction DR2 in the first well 261. For example, the second conductivity type may be n-type conductivity. In this example, each of the first impurity region 271 and the second impurity region 272 may be an N+ region. The first impurity region 271 and the second impurity region 272 may correspond to the source region and drain region of the transistor 250a.

[0149] The insulating layer 281a and the gate electrode 282 may be disposed and / or formed on the semiconductor substrate 251 between the first impurity region 271 and the second impurity region 272 (e.g., on the first well 261). The insulating layer 281a may have a thickness TK1.

[0150] In some example embodiments, the thickness TK1 of the insulating layer 281a can be smaller than the reference thickness. In other words, transistor 250a can be a thin gate oxide transistor. When a stacked transistor structure including multiple transistors TR1, TR2, and TR3 is implemented, and when each transistor is implemented with a thin gate oxide transistor, parasitic capacitance can be reduced and reliability issues can be resolved.

[0151] Reference Figure 12B Transistor 250b may include a semiconductor substrate 251, a first well 261, a first impurity region 271, a second impurity region 272, an insulating layer 281b, and a gate electrode 282. For simplicity, the components mentioned above will be omitted. Figure 12A The description is repetitive or overlapping.

[0152] The insulating layer 281b can have a thickness TK2. Besides the change in the thickness TK2 of the insulating layer 281b, the transistor 250b can be... Figure 12A The transistor 250a is basically the same.

[0153] In some example embodiments, the thickness TK2 of the insulating layer 281b may be greater than a reference thickness. In other words, transistor 250b may be a thick gate oxide transistor. The plurality of transistors TR1, TR2 and TR3 included in the switch structure 200a according to the example embodiment may not be limited to thin gate oxide transistors and may be implemented as thick gate oxide transistors.

[0154] Although the switching structure according to the example embodiment is described based on a specific number of transistors, a specific number of first resistors, a specific number of second resistors, and a specific number of choke resistors, the example embodiment is not limited thereto.

[0155] The switching structure according to the example embodiment can be implemented as a stacked transistor structure and can include multiple choke impedance elements (CIMPs) connected between multiple transistors (TRs) and ground voltage. Therefore, parasitic capacitance can be reduced, and operating performance and characteristics can be improved.

[0156] Figure 13 , Figure 14 and Figure 15 This is a block diagram illustrating a capacitor array according to an example embodiment.

[0157] Reference Figure 13 The capacitor array 30 includes multiple capacitors 31 and 33 and at least one switch 35. The capacitor array may be referred to as a capacitor bank.

[0158] Multiple capacitors 31 and 33 are connected between the first terminal T13 and the second terminal T23. For example, the multiple capacitors 31 and 33 may include the first capacitor 31 to the Nth capacitor 33 (where N is a positive integer greater than or equal to 2).

[0159] At least one switch 35 is disposed between two adjacent capacitors among a plurality of capacitors 31, 33. For example, at least one switch 35 may include a first switch 35.

[0160] like Figure 13 As shown, multiple capacitors 31 and 33 and at least one switch 35 can be alternately arranged between the first terminal T13 and the second terminal T23. Therefore, the number of capacitors 31 and 33 can be one more than the number of switches 35. For example, when N=2, the first capacitor 31, the first switch 35, and the second capacitor can be arranged in this order between the first terminal T13 and the second terminal T23. For example, when N=3, the first capacitor 31, the first switch 35, the second capacitor, the second switch, and the third capacitor can be arranged in sequence between the first terminal T13 and the second terminal T23.

[0161] In some example embodiments, the capacitor array 30 can perform frequency tuning operations by turning on and off at least one switch 35. For example, the capacitor array 30 can be included in a transceiver performing wireless communication, and the transceiver can perform frequency tuning operations by controlling the operating frequency using a combination of the inductance of an inductor and the capacitance of a capacitor. In this example, the frequency tuning operation can be performed by controlling the capacitance of the capacitor array 30 via turning on and off at least one switch 35.

[0162] In some exemplary embodiments, each of the plurality of capacitors 31 and 33 may correspond to a capacitor structure according to an exemplary embodiment. For example, the plurality of capacitors 31 and 33 may have a structure in which the second well 121 of capacitors 31 and 33 are electrically isolated and / or electrically separated from each other. For example, each of the plurality of capacitors 31 and 33 may include a first choke impedance element CIMP1 and a second choke impedance element CIMP2. For example, as referenced Figures 1 to 7 As described, each of the plurality of capacitors 31 and 33 can be implemented with a triple-well structure, and may include a first choke impedance element 151 connected between the second well 121 (e.g., the first impurity region 131 and the second impurity region 132) and ground voltage, and may include a second choke impedance element 152 connected between the first wells 111, 112, 113 and 111b (e.g., the fourth impurity region 134) and the power supply voltage VDD. The second wells 121 of the plurality of capacitors 31 and 33 can be electrically isolated and / or electrically decoupled from each other through the triple-well structure and the first choke impedance element CIMP1. Therefore, the parasitic capacitance of the plurality of capacitors 31 and 33 can be reduced, and the capacitor array 30 can have a relatively wide frequency tuning range.

[0163] In some example embodiments, multiple capacitors 31 and 33 may be formed in and / or on the same semiconductor substrate, and at least some of the multiple capacitors 31 and 33 may share the outer well 103. In other words, at least some of the multiple capacitors 31 and 33 may be formed in the same outer well.

[0164] Reference Figure 14 The capacitor array 40 includes multiple capacitors 41 and 43 and at least one switch 45. For brevity, the symbols 41 and 43 will be omitted. Figure 13 The description is repetitive or overlapping.

[0165] Multiple capacitors 41 and 43 are connected between a first terminal T14 and a second terminal T24. At least one switch 45 is provided between two adjacent capacitors among the multiple capacitors 41 and 43.

[0166] In some example embodiments, at least one switch 45 may correspond to a switch structure according to an example embodiment. For example, at least one switch 45 may include a plurality of choke impedance elements (CIMPs). For example, as referenced... Figures 8 to 12B As described, at least one switch 45 can be implemented in a stacked transistor structure and can include multiple choke impedance elements CIMP connected between multiple transistors TR and ground voltage. Therefore, the parasitic capacitance of at least one switch 45 can be reduced, and the capacitor array 40 can have a relatively wide frequency tuning range.

[0167] Reference Figure 15 The capacitor array 50 includes multiple capacitors 51 and 53 and at least one switch 55. For brevity, the symbols 51 and 53 will be omitted. Figure 13 and Figure 14 The description is repetitive or overlapping.

[0168] Multiple capacitors 51 and 53 are connected between a first terminal T15 and a second terminal T25. At least one switch 55 is provided between two adjacent capacitors among the multiple capacitors 51 and 53.

[0169] In some exemplary embodiments, each of the plurality of capacitors 51 and 53 may correspond to a capacitor structure according to an exemplary embodiment, and at least one switch 55 may correspond to a switch structure according to an exemplary embodiment. For example, the plurality of capacitors 51 and 53 may have a structure in which the second wells 121 of the capacitors 51 and 53 are electrically isolated and / or electrically separated from each other, and each of the plurality of capacitors 51 and 53 may include a first choke impedance element CIMP1 and a second choke impedance element CIMP2. For example, at least one switch 55 may include a plurality of choke impedance elements CIMP. The second wells 121 of the plurality of capacitors 51 and 53 may be electrically isolated and / or electrically separated from each other by a triple-well structure and the first choke impedance element CIMP1. Therefore, the parasitic capacitance of the plurality of capacitors 51 and 53 can be reduced, the parasitic capacitance of at least one switch 55 can be reduced, and the capacitor array 50 can have a relatively wide frequency tuning range.

[0170] Figure 16 It is shown Figure 15 A circuit diagram of an example capacitor array.

[0171] Reference Figure 16 The capacitor array 500a may include a first capacitor 510, a first switch 550, and a second capacitor 530 connected between a first terminal T15 and a second terminal T25. Figure 16 Showing in Figure 15 An example of N=2 in capacitor array 50.

[0172] The first capacitor 510 can be connected between the first terminal T15 and the third terminal T35. The first capacitor 510 can correspond to a capacitor structure according to the example embodiment and can include component C. UNIT1 C PAR11 C PAR21 D PWTW1 D TW1 D NW1 R BSUB1 and R BNW1 Component C included in the first capacitor 510 UNIT1 C PAR11 C PAR21 D PWTW1 D TW1 D NW1 R BSUB1 and R BNW1 Can be included separately with Figure 4 Component C in the equivalent circuit UNIT1 C PAR1 C PAR2 D PWTW D TW D NW R BSUB and R BNW They are basically the same.

[0173] The second capacitor 530 can be connected between the fourth terminal T45 and the second terminal T25. The second capacitor 530 can correspond to the capacitor structure according to the example embodiment and can include component C. UNIT2 C PAR12 C PAR22 D PWTW2 D TW2 D NW2 R BSUB2 and R BNW2 Component C included in the second capacitor 530 UNIT2 C PAR12 C PAR22 D PWTW2 D TW2 D NW2 R BSUB2 and R BNW2 Can be included separately with Figure 4 Component C in the equivalent circuit UNIT1 C PAR1 C PAR2 D PWTW D TW D NW R BSUB and R BNW They are basically the same.

[0174] The first switch 550 can be connected between the third terminal T35 and the fourth terminal T45. The first switch 550 can correspond to a switch structure according to the example embodiment and can include components TR1, TR2, TR3, R11, R12, R13, R14, R21, R22, R23, RCHK1, RCHK2, and RCHK3. Components TR1, TR2, TR3, R11, R12, R13, R14, R21, R22, R23, RCHK1, RCHK2, and RCHK3 included in the first switch 550 can respectively connect to components included in the example embodiment. Figure 9 The components TR1, TR2, TR3, R11, R12, R13, R14, R21, R22, R23, RCHK1, RCHK2 and RCHK3 in the switch structure 200a are basically the same.

[0175] Figure 17A , Figure 17B , Figure 17C and Figure 17D It is used to describe Figure 16 A diagram illustrating the operation of the capacitor array.

[0176] Reference Figure 17A The signals at the first terminal T15 and the second terminal T25 can have a swing width VSW1.

[0177] Reference Figure 17B The signals at the third terminal T35 and the fourth terminal T45 can have a swing width VSW2. For example, the swing width VSW2 can be substantially the same as the swing width VSW1.

[0178] Reference Figure 17C The signal near the second resistors R21 and R23 can have a swing width VSW3. For example, the swing width VSW3 can be smaller than the swing widths VSW1 and VSW2.

[0179] Reference Figure 17D The signal near the choke resistors RCHK1, RCHK2, and RCHK3 can have a swing width VSW4. For example, the swing width VSW4 can be smaller than the swing widths VSW1, VSW2, and VSW3.

[0180] Figure 18 , Figure 19 and Figure 20 This is a block diagram illustrating an electronic device according to an example embodiment.

[0181] Reference Figure 18 The electronic device 60 includes at least one capacitor 61.

[0182] At least one capacitor 61 may correspond to a capacitor structure according to an example embodiment. For example, at least one capacitor 61 may have a structure in which the second wells 121 are electrically isolated and / or electrically separated from each other, and may include a first choke impedance element CIMP1 and a second choke impedance element CIMP2. Therefore, the parasitic capacitance of at least one capacitor 61 can be reduced.

[0183] Reference Figure 19 The electronic device 70 includes at least one switch 71.

[0184] At least one switch 71 may correspond to a switch structure according to an example embodiment. For example, at least one switch 71 may include a plurality of choke impedance elements (CIMP). Therefore, the parasitic capacitance of at least one switch 71 can be reduced.

[0185] Although not shown in detail, the electronic device according to the example embodiment may include both a capacitor corresponding to the capacitor structure according to the example embodiment and a switch corresponding to the switch structure according to the example embodiment.

[0186] Reference Figure 20 The electronic device 80 includes a capacitor array 81.

[0187] The capacitor array 81 may include multiple capacitors CAP and at least one switch SW. The capacitor array 81 may be configured according to reference... Figures 13 to 17D The capacitor array described is an example embodiment. For example, each of the plurality of capacitors CAP can correspond to a capacitor structure according to an example embodiment that includes a first choke impedance element CIMP1 and a second choke impedance element CIMP2. For example, at least one switch SW can correspond to a switch structure according to an example embodiment that includes a plurality of choke impedance elements CIMP. For example, both the plurality of capacitors CAP and at least one switch SW can correspond to the capacitor structure and the switch structure according to an example embodiment.

[0188] Figure 21 and Figure 22 It is shown Figure 20 A block diagram of an example electronic device.

[0189] Reference Figure 21 The transceiver 800a may include a transmit (TX) circuit 810, a first amplifier 820, an output circuit 830, an input circuit 840, a second amplifier 850, a receive (RX) circuit 860, and an input / output (I / O) port PT. The transceiver 800a may be connected to an antenna 801 located outside the transceiver 800a. Figure 21 An example of an electronic device implemented in the form of a transceiver 800a is shown.

[0190] The transmitting circuit 810 can generate a first signal (or transmit signal) TS based on the first data TDAT. For example, the first data TDAT can be provided from a processor located outside the transceiver 800a. For example, although not shown in detail, the transmitting circuit 810 may include a mixer, an analog filter, etc.

[0191] The first amplifier 820 can amplify the first signal TS and generate the amplified first signal ATS. For example, the first amplifier 820 can be or includes a power amplifier (PA).

[0192] The output circuit 830 can output the amplified first signal ATS to an external device (e.g., another electronic device and / or another transceiver). For example, although not shown in detail, the output circuit 830 may include impedance matching circuitry, filters, etc.

[0193] The transmitting circuit 810, the first amplifier 820, and the output circuit 830 can form a transmitter and / or a transmitting path.

[0194] Input circuit 840 can receive a second signal (or receive signal) RS from an external device. For example, although not shown in detail, input circuit 840 may include impedance matching circuitry, filters, etc.

[0195] The second amplifier 850 can amplify the second signal RS and generate an amplified second signal ARS. For example, the second amplifier 850 can be or include a low-noise amplifier (LNA).

[0196] The receiving circuit 860 can generate second data RDAT based on the amplified second signal ARS. For example, the second data RDAT can be output externally from the transceiver 800a and can be sent to a processor. For example, although not shown in detail, the receiving circuit 860 may include a mixer, an analog filter, etc.

[0197] The input circuit 840, the second amplifier 850, and the receiving circuit 860 can form a receiver and / or a receiving path.

[0198] I / O port PT can be connected to a transmitter or transmit path and a receiver or receive path, and can be shared by the transmitter and receiver. For example, I / O port PT can be connected together by output circuit 830 and input circuit 840. I / O port PT can be connected to antenna 801, and can output an amplified first signal ATS or receive a second signal RS through antenna 801. For example, the amplified first signal ATS can be output to the outside of transceiver 800a, and can be transmitted to another electronic device and / or another transceiver. For example, the second signal RS can be provided from another electronic device and / or another transceiver.

[0199] In some example embodiments, transceiver 800a can operate in transmit mode and receive mode. For example, in transmit mode, the transmitter can be enabled or activated, can receive first data TDAT, and can generate and output a first signal TS, and at this time, the receiver can be disabled or deactivated. For example, in receive mode, the receiver can be enabled or activated, can receive a second signal RS, and can generate and output second data RDAT, and at this time, the transmitter can be disabled or deactivated.

[0200] In some example embodiments, transceiver 800a can operate in an operating mode in which the transmitter and receiver are enabled or activated together. For example, to support high output power and wide bandwidth, and to support radio detection and ranging (RADAR) functionality, transceiver 800a can be implemented with an I / O port PT shared by the transmitter and receiver. For example, transceiver 800a for RADAR functionality can operate with the transmitter and receiver enabled substantially simultaneously or concurrently.

[0201] In some example embodiments, the transmitting circuit 810 may include a capacitor array (CAP_ARY) 812, and the output circuit 830 may include a capacitor array 832. Each of the capacitor arrays 812 and 832 may be a capacitor array according to the example embodiment, and frequency tuning can be performed by adjusting the capacitance. Furthermore, the parasitic capacitance of the internal components can be reduced, and a relatively wide frequency tuning range can be achieved.

[0202] Although not in Figure 21 As shown, however, only one of the transmitting circuit 810 and the output circuit 830 may include a capacitor array according to the example embodiment. Furthermore, at least one of the input circuit 840 and the receiving circuit 860 may also include a capacitor array according to the example embodiment.

[0203] Reference Figure 22 The semiconductor chip 800b may include a processor 870 and a transceiver 880. Figure 22 An example of an electronic device implemented in the form of a semiconductor chip 800b is shown.

[0204] In some example embodiments, the processor 870 and transceiver 880 may be implemented as a single integrated circuit (IC) (or chip or module).

[0205] Processor 870 can generate the first data TDAT to be sent to an external device. For example, processor 870 can perform various signal processing operations (such as modulation / demodulation, encoding / decoding, channel estimation, etc.). Processor 870 can be referred to as a communication processor, modem, etc. Furthermore, processor 870 can exchange baseband signals with transceiver 880 and can be referred to as a baseband processor.

[0206] Transceiver 880 can generate a first signal to be transmitted to an external device based on the first data TDAT. Transceiver 880 can be based on a reference... Figure 21 The transceiver described is an example embodiment. For example, transceiver 880 may include transmitter 882, receiver 884, and I / O port PT, and transmitter 882 may include capacitor array (CAP_ARY) 883. Capacitor array 883 may be a capacitor array according to an example embodiment.

[0207] Furthermore, transceiver 880 can receive a second signal from an external device and can generate second data RDAT based on the second signal. Processor 870 can receive the second data RDAT and perform data processing on the second data RDAT.

[0208] The capacitor structure, switching structure, and / or capacitor array according to the example embodiments can be applied to or employed in transceivers that operate across multiple frequency bands, support wide bandwidth, and require high output power. For example, when the capacitor structure according to the example embodiments is applied or employed, choke coil impedance elements CIMP1 and CIMP2 can be used to reduce parasitic capacitance, thereby reducing insertion loss and supporting a wide frequency range. For example, when the switching structure according to the example embodiments is applied or employed, choke coil impedance element CIMP can be used to reduce parasitic capacitance, thereby addressing reliability issues.

[0209] Figure 23 This is a block diagram illustrating an electronic device in a network environment according to an example embodiment.

[0210] Reference Figure 23In network environment 1300, electronic device 1301 can communicate with electronic device 1302 via a first network 1398 (e.g., a short-range wireless communication network), or with electronic device 1304 or server 1308 via a second network 1399 (e.g., a long-range wireless communication network). For example, electronic device 1301 can communicate with electronic device 1304 via server 1308. For example, electronic device 1301 may include processor 1320, memory 1330, input device 1350, sound output device 1355, display device 1360, audio module 1370, sensor module 1376, interface 1377, haptic module 1379, camera module 1380, power management module 1388, battery 1389, communication module 1390, subscriber identification module (SIM) 1396, and / or antenna module 1397. In some example embodiments, at least one of the components (e.g., display device 1360 or camera module 1380) may be omitted from electronic device 1301, or one or more other components may be added to electronic device 1301. In some example embodiments, a portion of the components may be implemented as a single integrated circuit. For example, sensor module 1376 (e.g., fingerprint sensor, iris sensor, or illuminance sensor) may be implemented as embedded in display device 1360 (e.g., display).

[0211] Processor 1320 can execute, for example, software (e.g., program 1340) to control at least one other component (e.g., hardware or software component) of electronic device 1301 associated with processor 1320, and can perform various data processing or calculations. For example, as at least part of data processing or calculation, processor 1320 can load commands or data received from another component (e.g., sensor module 1376 or communication module 1390) into volatile memory 1332, process the commands or data stored in volatile memory 1332, and store the resulting data in non-volatile memory 1334. In some example embodiments, processor 1320 may include a main processor 1321 (e.g., central processing unit (CPU) or application processor (AP)) and an auxiliary processor 1323 (e.g., graphics processing unit (GPU), image signal processor (ISP), sensor hub processor, or communication processor (CP)) that can operate independently of or in conjunction with main processor 1321. Additionally or optionally, the auxiliary processor 1323 may be adapted to consume less power than the main processor 1321, or be specific to a particular function. The auxiliary processor 1323 may be implemented separately from the main processor 1321, or may be implemented as part of the main processor 1321.

[0212] When the main processor 1321 is inactive (e.g., in sleep mode), the auxiliary processor 1323 may take over from the main processor 1321 to control at least some of the functions or states associated with at least one component of the electronic device 1301 (e.g., display device 1360, sensor module 1376, or communication module 1390). Alternatively, when the main processor 1321 is active (e.g., executing an application), the auxiliary processor 1323 may work with the main processor 1321 to control at least some of the functions or states associated with at least one component of the electronic device 1301 (e.g., display device 1360, sensor module 1376, or communication module 1390). In some example embodiments, the auxiliary processor 1323 (e.g., an image signal processor or a communication processor) may be implemented as part of another component (e.g., camera module 1380 or communication module 1390) functionally associated with the auxiliary processor 1323.

[0213] Memory 1330 may store various data used by at least one component of electronic device 1301 (e.g., processor 1320 or sensor module 1376). The various data may include, for example, software (e.g., program 1340) and input or output data for commands associated with, for example, software (e.g., program 1340). Memory 1330 may include volatile memory 1332 and / or non-volatile memory 1334. Memory 1330 may include internal memory 1336 and external memory 1338.

[0214] Program 1340 may be stored as software in memory 1330 and may include, for example, an operating system (OS) 1342, middleware 1344 and / or application 1346.

[0215] Input device 1350 can receive commands or data from outside electronic device 1301 (e.g., a user) that will be used by another component of electronic device 1301 (e.g., processor 1320). Input device 1350 may include, for example, a microphone, mouse, keyboard, or digital pen (e.g., stylus).

[0216] The sound output device 1355 can output sound signals to the outside of the electronic device 1301. The sound output device 1355 may include, for example, a speaker or a receiver. The speaker may be used for general purposes (such as playing multimedia or playing recordings), and the receiver may be used for incoming calls. In some example embodiments, the receiver may be implemented separately from the speaker or may be implemented as part of the speaker.

[0217] Display device 1360 can visually provide information to the outside of electronic device 1301 (e.g., to a user). Display device 1360 may include, for example, a display, a holographic device, or a projector, and control circuitry for controlling a corresponding one of the display, holographic device, and projector. In some example embodiments, display device 1360 may include touch circuitry adapted to detect touch or sensor circuitry adapted to measure the intensity of the force caused by touch (e.g., a pressure sensor).

[0218] Audio module 1370 can convert sound into electrical signals and vice versa. In some example embodiments, audio module 1370 can obtain sound via input device 1350, or output sound via sound output device 1355 or headphones of an external electronic device (e.g., electronic device 1302) directly (e.g., wired) or wirelessly connected to electronic device 1301.

[0219] Sensor module 1376 can detect the operating state of electronic device 1301 (e.g., power or temperature) or the environmental state outside electronic device 1301 (e.g., user state), and then generate an electrical signal or data value corresponding to the detected state. In some example embodiments, sensor module 1376 may include, for example, a gesture sensor, a gyroscope sensor, an atmospheric pressure sensor, a magnetic sensor, an accelerometer, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, and / or an illuminance sensor, but the example embodiments are not limited thereto.

[0220] Interface 1377 may support one or more specified protocols for direct (e.g., wired) or wireless connection between electronic device 1301 and external electronic device (e.g., electronic device 1302). In some example embodiments, interface 1377 may include, for example, a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, a Secure Digital Card (SD) interface, and / or an audio interface, but the example embodiments are not limited thereto.

[0221] Connection terminal 1378 may include a connector via which electronic device 1301 can be physically connected to an external electronic device (e.g., electronic device 1302). In some example embodiments, connection terminal 1378 may include, for example, an HDMI connector, a USB connector, an SD card connector, and / or an audio connector (e.g., a headphone connector), but the example embodiments are not limited thereto.

[0222] The haptic module 1379 can convert electrical signals into mechanical stimuli (e.g., vibration or movement) or electrical stimuli that can be recognized by a user through his tactile or kinesthetic senses. In some example embodiments, the haptic module 1379 may include, for example, a motor, a piezoelectric element, and / or an electrical stimulator.

[0223] Camera module 1380 can capture still or moving images. In some example embodiments, camera module 1380 may include one or more lenses, an image sensor, an image signal processor, and / or a flash.

[0224] The power management module 1388 can manage the power supplied to the electronic device 1301. In some example embodiments, the power management module 1388 can be implemented as at least part of, for example, a power management integrated circuit (PMIC).

[0225] Battery 1389 can supply power to at least one component of electronic device 1301. In some example embodiments, battery 1389 may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0226] Communication module 1390 can support the establishment of a direct (e.g., wired) or wireless communication channel between electronic device 1301 and external electronic devices (e.g., electronic device 1302, electronic device 1304, or server 1308), and perform communication via the established communication channel. Communication module 1390 may include one or more communication processors capable of operating independently of processor 1320 (e.g., application processor (AP)) and supports direct (e.g., wired) or wireless communication. In some example embodiments, communication module 1390 may include wireless communication module 1392 (e.g., cellular communication module, short-range wireless communication module, or Global Navigation Satellite System (GNSS) communication module) and / or wired communication module 1394 (e.g., local area network (LAN) communication module or power line communication (PLC) module). A corresponding one of these communication modules can communicate via a first network 1398 (e.g., a short-range communication network such as Bluetooth). TMThe communication module 1392 communicates with external electronic devices via a Wi-Fi Direct or Infrared Data Association (IrDA) network or a second network 1399 (e.g., a long-range communication network, such as a cellular network, the Internet, or a computer network such as a LAN or a wide area network (WAN)). These various types of communication modules can be implemented as a single component (e.g., a single chip) or as multiple components that are separate from each other (e.g., multiple chips). The wireless communication module 1392 can use user information (e.g., the International Mobile Subscriber Identity (IMSI)) stored in the user identification module 1396 to identify and authenticate electronic devices 1301 in the communication network (e.g., a first network 1398 or a second network 1399).

[0227] Antenna module 1397 can transmit or receive signals or power to or from the exterior of electronic device 1301 (e.g., external electronic device). In some example embodiments, antenna module 1397 may include an antenna comprising a radiating element made of conductive material or conductive pattern formed in or on a substrate (e.g., PCB). In some example embodiments, antenna module 1397 may include multiple antennas. In some example embodiments, at least one antenna suitable for a communication scheme used in a communication network (such as a first network 1398 or a second network 1399) may be selected from multiple antennas, for example, by communication module 1390 (e.g., wireless communication module 1392). Signals or power can then be transmitted or received between communication module 1390 and external electronic device via the selected at least one antenna. In some example embodiments, another component besides the radiating element (e.g., a radio frequency integrated circuit (RFIC)) may be additionally incorporated into antenna module 1397.

[0228] In some example embodiments, communication module 1390 may include a transceiver TRX according to an example embodiment. Part or all of processor 1320 may be a processor included in a semiconductor chip according to an example embodiment. In some example embodiments, transceiver TRX and part or all of processor 1320 may be implemented as separate chips or a single chip. Antenna module 1397 may include an antenna connected to transceiver TRX. Similarly, according to example embodiments, other electronic devices 1302 and 1304 may also include transceivers, processors, antennas, etc. For example, each electronic device may be a user equipment (UE) or a base station.

[0229] The exemplary embodiments can be applied to a variety of communication devices and systems, as well as electronic devices and systems that include communication devices and systems. For example, the exemplary embodiments can be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smartphones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, camcorders, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, automobiles, and the like.

[0230] The foregoing is illustrative of exemplary embodiments and should not be construed as limiting them. Although some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the exemplary embodiments without substantially departing from the novel teachings and advantages of the exemplary embodiments. Therefore, all such modifications are intended to be included within the scope of the exemplary embodiments as defined in the claims. It will thus be understood that the foregoing is illustrative of various exemplary embodiments and should not be construed as limiting to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of the appended claims.

Claims

1. A capacitor structure, comprising: A semiconductor substrate, including an outer well having a first conductivity type; The first well is located in the outer well and has a second type of conductivity. The second well is located within the first well and has the first conductivity type; A first electrode and a second electrode, at least a portion of the first electrode and the second electrode being in a second well; The first choke impedance element is connected between the second sink and the ground voltage; as well as The second choke impedance element is connected between the first sink and the power supply voltage.

2. The capacitor structure according to claim 1 further includes: In the second well, each of the first impurity region and the second impurity region has a first conductivity type; The third impurity region and the fourth impurity region, in the first well, each of the third impurity region and the fourth impurity region has a second conductivity type; as well as The fifth and sixth impurity regions, in the outer well, each of the fifth and sixth impurity regions has a first conductivity type.

3. The capacitor structure according to claim 2, wherein, The first and second impurity regions in the second well are connected to ground voltage through the first choke impedance element, and Among them, the fifth and sixth impurity regions in the outer well are directly connected to the ground voltage.

4. The capacitor structure according to claim 1, wherein, The first choke impedance element and the second choke impedance element are configured to reduce the parasitic capacitance of the capacitor structure.

5. The capacitor structure according to claim 4, wherein, Each of the first choke impedance element and the second choke impedance element includes a choke resistor.

6. The capacitor structure according to claim 1, wherein, The second electrode is stacked on top of the first electrode in a direction perpendicular to the upper surface of the semiconductor substrate.

7. The capacitor structure according to claim 1, wherein, The first electrode and the second electrode are spaced apart from each other in a direction parallel to the upper surface of the semiconductor substrate.

8. The capacitor structure according to claim 2, wherein, The first impurity region and the second impurity region are spaced apart from each other in the second well. The third and fourth impurity regions are spaced apart from each other in the first well, and The fifth and sixth impurity regions are spaced apart from each other in the outer trap.

9. The capacitor structure according to claim 2, wherein, The impurity concentration in the first impurity region and the impurity concentration in the second impurity region are higher than the impurity concentration in the second well. Among them, the impurity concentrations in the third and fourth impurity regions are higher than those in the first well, and The impurity concentrations in the fifth and sixth impurity regions are higher than those in the outer well.

10. The capacitor structure according to claim 1, wherein, The first conductivity type is p-type conductivity, and the second conductivity type is n-type conductivity.

11. A capacitor array, comprising: Multiple capacitors are connected between the first terminal and the second terminal; as well as At least one switch is located between two adjacent capacitors among the plurality of capacitors. Each of the plurality of capacitors includes: The outer well has the first type of conductivity; The first well is located in the outer well and has a second type of conductivity. A second well, located within the first well and having a first conductivity type; and A first electrode and a second electrode, at least a portion of the first electrode and the second electrode being in the second well, and The second well of each of the plurality of capacitors is electrically isolated from the second wells of the other capacitors in the plurality of capacitors.

12. The capacitor array according to claim 11, wherein, Each of the plurality of capacitors further includes: The first choke impedance element is connected between the second sink and ground voltage; and The second choke impedance element is connected between the first sink and the power supply voltage.

13. The capacitor array according to claim 11, wherein, The at least one switch includes: Multiple transistors are connected in series between a third terminal and a fourth terminal, each of the multiple transistors including a gate electrode for receiving a first switch control signal, the third terminal and the fourth terminal being between two adjacent capacitors; A plurality of first resistors, each of the plurality of first resistors being connected to a third terminal, a fourth terminal or a node, the node being between two adjacent transistors among the plurality of transistors, and a second switch control signal being applied to each of the plurality of first resistors; A plurality of second resistors, each of which is connected between the gate electrode of one of the plurality of transistors and a first switching control signal; and A plurality of choke impedance elements, each of the plurality of choke impedance elements being connected between the body of one of the plurality of transistors and ground voltage.

14. The capacitor array according to claim 11, wherein, Frequency tuning is performed by turning the at least one switch on and off.

15. An electronic device comprising: At least one capacitor, Wherein, the at least one capacitor includes: A semiconductor substrate, including an outer well having a first conductivity type; The first well is located in the outer well and has a second type of conductivity. The second well is located within the first well and has the first conductivity type; A first electrode and a second electrode, at least a portion of which are in contact with a second well; The first choke impedance element is connected between the second sink and ground voltage; and The second choke impedance element is connected between the first sink and the power supply voltage.

16. The electronic device according to claim 15, wherein, The electronic device also includes a transceiver configured to perform wireless communication.

17. The electronic device according to claim 16, wherein, The transceiver includes: The transmitting circuit is configured to generate a first signal based on the first data; The first amplifier is configured to amplify the first signal; The output circuit is configured to output the amplified first signal to an external device. The input circuit is configured to receive a second signal from an external device; The second amplifier is configured to amplify the second signal; The receiving circuit is configured to generate second data based on the amplified second signal; as well as The input / output port is connected by both the output and input circuits.

18. The electronic device of claim 17, further comprising: At least one switch, Wherein, the at least one capacitor and the at least one switch form a capacitor array, and The capacitor array is included in at least one of the transmitting circuit and the output circuit.

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