Semiconductor device
By setting finger-shaped wiring and upper and lower electrode contact points in trenches on the semiconductor substrate, the gate signal delay problem caused by increased wiring resistance in semiconductor devices is solved, and more efficient signal transmission is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-08
- Publication Date
- 2026-03-13
AI Technical Summary
In existing semiconductor devices, the increased wiring resistance caused by the vertical segmentation of electrodes within the trench leads to gate signal delay.
Finger wiring is formed on a semiconductor substrate, and upper and lower electrodes are arranged in trenches and connected by an insulating film to form multiple contact points to reduce wiring resistance and suppress gate signal delay.
By increasing contact points and using finger-like wiring design, wiring resistance is effectively reduced, gate signal delay is suppressed, and chip performance is improved.
Smart Images
Figure CN121665593A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to semiconductor devices. Background Technology
[0002] Patent Document 1 discloses a semiconductor device comprising: a gate insulating film disposed along a trench of a semiconductor substrate; and an active trench having an active portion configured to contact the gate insulating film and connect to a gate electrode. The active portion is divided into upper and lower parts by an intermediate insulating film.
[0003] Patent Document 1: Japanese Patent Application Publication No. 2024-45595
[0004] In a semiconductor device like that in Patent Document 1, the electrodes within the trench are divided vertically. Therefore, there is a concern that the smaller area of the electrodes within the trench leads to increased wiring resistance, potentially causing delays in the gate signal. Summary of the Invention
[0005] This disclosure was made to solve the above-mentioned problems, and its purpose is to provide a semiconductor device capable of suppressing the delay of the gate signal.
[0006] The semiconductor device disclosed in the first disclosure includes: a semiconductor substrate having a first trench formed thereon; a gate pad disposed on the semiconductor substrate; a first gate wiring disposed on the semiconductor substrate and electrically connected to the gate pad; a second gate wiring disposed on the semiconductor substrate and electrically connected to the gate pad; a finger wiring disposed on the semiconductor substrate between the first gate wiring and the second gate wiring and electrically connected to the gate pad; and a first main electrode disposed on the semiconductor substrate. Between the first gate wiring and the aforementioned finger wiring; a second main electrode, disposed on the semiconductor substrate between the second gate wiring and the aforementioned finger wiring; a first lower electrode, disposed inside the aforementioned first trench; and a first upper electrode, disposed inside the aforementioned first trench via an insulating film on the aforementioned first lower electrode, wherein the aforementioned first lower electrode is in contact with the aforementioned first gate wiring or the aforementioned second gate wiring and the aforementioned finger wiring, and the aforementioned first upper electrode is in contact with the aforementioned first gate wiring or the aforementioned second gate wiring and the aforementioned finger wiring.
[0007] The semiconductor device disclosed in the second disclosure includes: a semiconductor substrate having a first trench formed thereon; an upper gate pad disposed on the semiconductor substrate; a lower gate pad disposed on the semiconductor substrate; a first lower gate wiring disposed on the semiconductor substrate and electrically connected to the lower gate pad; a second lower gate wiring disposed on the semiconductor substrate and electrically connected to the lower gate pad; a finger wiring disposed on the semiconductor substrate between the first lower gate wiring and the second lower gate wiring and electrically connected to the lower gate pad; and a first main electrode disposed on the semiconductor substrate between the first lower gate wiring and the second lower gate wiring. Between the finger-shaped wirings; a second main electrode, disposed on the semiconductor substrate between the second lower-level gate wiring and the finger-shaped wirings; an upper-level gate wiring, disposed on the semiconductor substrate between the first lower-level gate wiring or the second lower-level gate wiring and the finger-shaped wirings, and electrically connected to the upper-level gate pad; a first lower-level electrode, disposed inside the first trench; and a first upper-level electrode, disposed inside the first trench via an insulating film on the first lower-level electrode, wherein the first lower-level electrode contacts the first lower-level gate wiring or the second lower-level gate wiring and the finger-shaped wirings, and the first upper-level electrode contacts the upper-level gate wiring.
[0008] In the semiconductor device disclosed in the first disclosure, the first lower electrode and the first upper electrode are in contact with the first gate wiring or the second gate wiring and the finger wiring, respectively. This suppresses wiring resistance and gate signal delay.
[0009] In the semiconductor device disclosed in the second disclosure, the first lower electrode is in contact with the first lower gate wiring or the second lower gate wiring, as well as the finger wiring. This suppresses wiring resistance and gate signal delay. Attached Figure Description
[0010] Figure 1 This is a top view of the semiconductor device according to Embodiment 1.
[0011] Figure 2 This is a cross-sectional view of the semiconductor device according to Embodiment 1 in a direction perpendicular to the trench extension direction.
[0012] Figure 3 This is a cross-sectional view of the semiconductor device according to Embodiment 1 along the trench direction.
[0013] Figure 4 This is a cross-sectional view of the semiconductor device according to Embodiment 2 along the trench direction.
[0014] Figure 5This is a top view of the semiconductor device involved in Embodiment 3.
[0015] Figure 6 This is a cross-sectional view of the semiconductor device according to Embodiment 4 in a direction perpendicular to the trench extension direction.
[0016] Figure 7 This is a cross-sectional view of the semiconductor device according to Embodiment 4 along the trench direction.
[0017] Figure 8 This is a top view of the semiconductor device according to Embodiment 5.
[0018] Figure 9 This is a cross-sectional view of the semiconductor device according to Embodiment 5 in a direction perpendicular to the trench extension direction.
[0019] Figure 10 This is a cross-sectional view of the semiconductor device according to Embodiment 5 along the trench direction.
[0020] Figure 11 This is a top view of the semiconductor device involved in Embodiment 6.
[0021] Figure 12 This is a top view of the semiconductor device according to Embodiment 7.
[0022] Figure 13 This is a top view of the semiconductor device according to Embodiment 8.
[0023] Figure 14 This is a cross-sectional view of the semiconductor device according to Embodiment 9 in a direction perpendicular to the trench extension direction.
[0024] Figure 15 This is a cross-sectional view of the semiconductor device according to Embodiment 9 along the trench direction.
[0025] Figure 16 This is a cross-sectional view of the semiconductor device according to Embodiment 10 in a direction perpendicular to the trench extension direction.
[0026] Figure 17 This is a top view of the semiconductor device according to Embodiment 10.
[0027] Explanation of reference numerals in the attached figures
[0028] 10... Gate pad; 11, 11a, 11b... Gate wiring; 12, 12a, 12b... Finger wiring; 20, 20a-20e... Trench; 30... Upper electrode; 31... Lower electrode; 32... Upper electrode; 35... Insulating film; 40a... Upper contact; 40b... Lower contact; 41... Lower lift region; 50, 50a-50c... Main electrode; 60... Semiconductor substrate; 100, 200, 300, 400, 500... Semiconductor device; 513... Upper gate pad; 514, 514a-514d... Upper-level gate wiring; 515... Lower-level gate pad; 516, 516a, 516b... Lower-level gate wiring; 530... Upper-level electrode; 531... Lower-level electrode; 532... Upper-level electrode; 600, 700... Semiconductor device; 714, 714a-714f... Upper-level gate wiring; 716, 716a, 716b... Lower-level gate wiring; 800... Semiconductor device; 870... Diode region; 900, 1000... Semiconductor device; 1032... Upper-level electrode. Detailed Implementation
[0029] The semiconductor device according to this embodiment will be described with reference to the accompanying drawings. The same or corresponding components are labeled with the same reference numerals, and repeated descriptions are sometimes omitted.
[0030] Implementation Method 1
[0031] Figure 1 This is a top view of the semiconductor device 100 according to Embodiment 1. Figure 2 This is a cross-sectional view of the semiconductor device 100 according to Embodiment 1, in a direction perpendicular to the direction in which the trench 20 extends. Figure 3 This is a cross-sectional view of the semiconductor device 100 according to Embodiment 1 along the direction of the trench 20. That is, Figure 3 yes Figure 1 The A-B cross-sectional view shows the semiconductor device 100, for example, an IGBT (Insulated Gate Bipolar Transistor). The semiconductor device 100 includes a semiconductor substrate 60. Furthermore, in the cross-sectional view, the semiconductor layer formed on the semiconductor substrate 60 and the collector electrode disposed on the back side of the semiconductor substrate 60 are omitted.
[0032] The semiconductor substrate 60 is, for example, a silicon substrate. A plurality of trenches 20 are formed on the semiconductor substrate 60. The plurality of trenches 20 extend along... Figure 1A straight line A-B extends from the image. A gate pad 10 is provided on the semiconductor substrate 60. Gate signals are input to the gate pad 10 from the outside. Gate wirings 11a and 11b and finger wirings 12, which are electrically connected to the gate pad 10, are provided on the semiconductor substrate 60. The finger wirings 12 are disposed between the gate wirings 11a and 11b. The gate wirings 11a and 11b and the finger wirings 12 constitute the gate wirings 11. The gate wirings 11 can also be metal wirings, such as those formed of aluminum.
[0033] A main electrode 50a is disposed on the semiconductor substrate 60 between the gate wiring 11a and the finger wiring 12. Additionally, a main electrode 50b is disposed on the semiconductor substrate 60 between the gate wiring 11b and the finger wiring 12. Figure 2 In the diagram, either main electrode 50a or main electrode 50b is shown as main electrode 50. Main electrodes 50a and 50b are emitter electrodes and are electrically connected to emitter pads (not shown). In top view, main electrodes 50a and 50b are surrounded by gate wiring 11, which includes gate wirings 11a and 11b and finger wirings 12. The finger wirings 12 are configured to divide the main electrodes 50.
[0034] An upper electrode 30 and a lower electrode 31, serving as gate electrodes, are disposed inside the trench 20. The upper electrode 30 and the lower electrode 31 are formed, for example, of polysilicon. The upper electrode 30 is disposed on top of the lower electrode 31 via an insulating film 35. That is, the insulating film 35 separates the upper electrode 30 and the lower electrode 31. Figure 2 As shown, the insulating film 35 is configured to surround the lower electrode 31 and the upper electrode 30 on both sides and above and below. The insulating film 35 is formed, for example, from SiO2.
[0035] like Figure 3 As shown, the upper electrode 30 is in contact with the gate wiring 11a, the gate wiring 11b, and the finger wiring 12. Specifically, an upper contact portion 40a is formed by forming an opening in the insulating film 35. In the upper contact portion 40a, the upper electrode 30 is in contact with the gate wiring 11. Similarly, the lower electrode 31 is in contact with the gate wiring 11a, the gate wiring 11b, and the finger wiring 12. Specifically, a lower contact portion 40b is formed by forming an opening in the insulating film 35. In the lower contact portion 40b, the lower electrode 31 is in contact with the gate wiring 11.
[0036] Furthermore, the trench 20 extending along the A-B direction is divided directly below the finger wiring 12. In this embodiment and the following embodiments, the multiple portions divided in the A-B direction are sometimes considered as a single trench 20.
[0037] Next, the effects of this embodiment will be explained. In this embodiment, the main electrode 50 is divided at the finger wiring 12. The upper electrode 30 and the lower electrode 31 are in contact with the gate wirings 11a, 11b and the finger wiring 12, respectively, thereby being electrically connected to the gate wiring 11. At this time, compared with the case where the finger wiring 12 is not provided, the length of the trench 20 in the A-B direction is shortened by providing the finger wiring 12. In addition, generally speaking, the wiring resistance of the gate wiring 11 is smaller than that of the electrodes in the trench 20. Therefore, in this embodiment, the wiring resistance can be suppressed, and the delay of the gate signal can be suppressed. In particular, even when the gate electrode is divided into the upper electrode 30 and the lower electrode 31, and the area of the gate electrode is reduced, the delay of the gate signal can still be suppressed. In addition, by suppressing the delay of the gate signal, for example, the chip size can be increased.
[0038] Furthermore, in this embodiment, the trench 20 is divided directly below the finger wiring 12 in the direction from the gate wiring 11a toward the gate wiring 11b. Therefore, the trench 20 is further shortened, which can suppress the delay of the gate signal.
[0039] The upper electrode 30 may also contact only one of the gate wiring 11a and the gate wiring 11b. Similarly, the lower electrode 31 may also contact only one of the gate wiring 11a and the gate wiring 11b. Figure 3 In this example, the gate electrode of the left portion of the trench 20, which is divided into left and right sides, contacts the gate wiring 11a and the finger wiring 12, while the gate electrode of the right portion contacts the gate wiring 11b and the finger wiring 12. Even in this case, the effect of suppressing the delay of the gate signal can be achieved.
[0040] The shape of the gate wiring 11 is not limited to Figure 1 The shape shown is correct. Alternatively, the semiconductor substrate 60 can also be formed of a wide-bandgap semiconductor. Examples of wide-bandgap semiconductors include silicon carbide, gallium nitride-based materials, or diamond.
[0041] The above-described modifications can be appropriately applied to the semiconductor device involved in the following embodiments. Furthermore, since the semiconductor device involved in the following embodiments shares many similarities with Embodiment 1, the differences from Embodiment 1 will be described.
[0042] Implementation Method 2
[0043] Figure 4 This is a cross-sectional view of the semiconductor device 200 according to Embodiment 2, along the direction of the trench 20. In the semiconductor device 200, the trench 20 is not divided directly below the finger wiring 12. Even in this configuration, as in Embodiment 1, wiring resistance and gate signal delay can be suppressed.
[0044] Implementation Method 3
[0045] Figure 5 This is a top view of the semiconductor device 300 according to Embodiment 3. The semiconductor device 300 differs from the semiconductor device 100 of Embodiment 1 in that it has a plurality of finger-shaped wirings 12a, 12b. Other structures are the same as those of the semiconductor device 100. Figure 5 In this example, the main electrode 50 is divided into three parts: main electrode 50a, 50b, and 50c, by finger wiring 12a and 12b. The number of finger wiring 12 is not limited.
[0046] Similar to Embodiment 1, the trench 20 can also be divided directly below the finger wirings 12a and 12b. When there are two finger wirings 12, the trench 20 is divided into three parts in the A-B direction. According to this embodiment, the trench 20 can be further shortened, and the gate signal delay can be suppressed compared to Embodiment 1. Furthermore, similar to Embodiment 2, the trench 20 may not be divided directly below the finger wirings 12a and 12b.
[0047] Implementation Method 4
[0048] Figure 6 This is a cross-sectional view of the semiconductor device 400 according to Embodiment 4, in a direction perpendicular to the direction in which the trench 20 extends. Figure 7 This is a cross-sectional view of the semiconductor device 400 according to Embodiment 4 along the direction of the trench 20. In this embodiment, two types of trenches 20a and 20b are formed on the semiconductor substrate 60. The structure of trench 20a is the same as that of trench 20 in Embodiment 1. A lower electrode 31 and an upper electrode 32 disposed on the lower electrode 31 via an insulating film 35 are disposed inside the trench 20b. Other structures are the same as those in Embodiment 1.
[0049] like Figure 7 As shown, the lower electrode 31 of trench 20b is in contact with gate wiring 11a, gate wiring 11b, and finger wiring 12. The upper electrode 32 of trench 20b is in contact with main electrode 50a and main electrode 50b. That is, the upper electrode 30 and lower electrode 31 of trench 20a and the lower electrode 31 of trench 20b are active electrodes electrically connected to the gate pad 10. In addition, the upper electrode 32 of trench 20b is a dummy electrode.
[0050] In this embodiment, the input capacitance can be adjusted via the upper electrode 32 connected to the main electrode 50.
[0051] The lower electrode 31 of trench 20b may also contact only one of gate wiring 11a and gate wiring 11b. Similarly, the upper electrode 32 of trench 20b may also contact only one of main electrode 50a and main electrode 50b. Figure 7 In this example, the lower electrode 31 of the left portion of the trench 20b, which is divided into left and right sides, contacts the gate wiring 11a and the finger wiring 12, while the lower electrode 31 of the right portion contacts the gate wiring 11b and the finger wiring 12. Additionally, the upper electrode 32 of the left portion of the trench 20b, which is divided into left and right sides, contacts the main electrode 50a, while the upper electrode 32 of the right portion contacts the main electrode 50b.
[0052] There are no restrictions on the configuration of trench 20b. For example, trenches 20a and 20b can also be set alternately. Figure 1 A portion of the multiple trenches 20 shown can also be replaced by trench 20b.
[0053] Implementation Method 5
[0054] Figure 8 This is a top view of the semiconductor device 500 according to Embodiment 5. Figure 9 This is a cross-sectional view of the semiconductor device 500 according to Embodiment 5, in a direction perpendicular to the direction in which the trench 20 extends. Figure 10 This is a cross-sectional view of the semiconductor device 500 according to Embodiment 5 along the direction of the trench 20. That is, Figure 10 yes Figure 8 The C-D cross-sectional view shows that the semiconductor device 500 is, for example, an IGBT. The semiconductor device 500 includes a semiconductor substrate 60. Furthermore, in the cross-sectional view, the semiconductor layer formed on the semiconductor substrate 60 and the collector electrode disposed on the back side of the semiconductor substrate 60 are omitted.
[0055] An upper-level gate pad 513, a lower-level gate pad 515, an upper-level gate wiring 514 electrically connected to the upper-level gate pad 513, and a lower-level gate wiring 516 electrically connected to the lower-level gate pad 515 are disposed on a semiconductor substrate 60. Gate signals are input from the outside to the upper-level gate pad 513 and the lower-level gate pad 515. The upper-level gate pad 513 and the lower-level gate pad 515 are, for example, adjacent to each other.
[0056] The lower-level gate wiring 516 includes lower-level gate wirings 516a and 516b electrically connected to the lower-level gate pad 515. On the semiconductor substrate 60, a finger wiring 12 electrically connected to the lower-level gate pad 515 is provided between the lower-level gate wirings 516a and 516b.
[0057] A main electrode 50a is disposed on the semiconductor substrate 60 between the lower-level gate wiring 516a and the finger wiring 12. A main electrode 50b is disposed on the semiconductor substrate 60 between the lower-level gate wiring 516b and the finger wiring 12. Figure 9 In the diagram, main electrode 50a or main electrode 50b is shown as main electrode 50. Main electrodes 50a and 50b are emitter electrodes and are electrically connected to emitter pads (not shown).
[0058] The upper-level gate wiring 514 includes upper-level gate wirings 514a to 514d electrically connected to the upper-level gate pad 513. Upper-level gate wiring 514a is disposed between lower-level gate wiring 516a and the main electrode 50a. Upper-level gate wiring 514b is disposed between lower-level gate wiring 516b and the main electrode 50b. Upper-level gate wiring 514c is disposed between the finger wiring 12 and the main electrode 50a. Upper-level gate wiring 514d is disposed between the finger wiring 12 and the main electrode 50b. When viewed from above, the main electrode 50a and the main electrode 50b are surrounded by the upper-level gate wiring 514.
[0059] Semiconductor device 500 includes: a lower electrode 531 disposed inside a trench 20; and an upper electrode 530 disposed on the lower electrode 531 inside the trench 20 via an insulating film 35. The upper electrode 530 is in contact with upper gate wirings 514a, 514b, 514c, and 514d. Specifically, an upper contact portion 40a is formed by forming an opening in the insulating film 35. In the upper contact portion 40a, the upper electrode 530 is in contact with the upper gate wiring 514. The lower electrode 531 is in contact with lower gate wirings 516a, 516b, and finger wirings 12. Specifically, a lower contact portion 40b is formed by forming an opening in the insulating film 35. In the lower contact portion 40b, the lower electrode 531 is in contact with the lower gate wiring 516.
[0060] exist Figure 10 In this example, the upper electrode 530 on the left side of the trench 20, which is divided into left and right sections, contacts the upper gate wirings 514a and 514c, while the upper electrode 530 on the right side contacts the upper gate wirings 514b and 514d. Additionally, the lower electrode 531 on the left side of the trench 20 contacts the lower gate wiring 516a and the finger wiring 12, while the lower electrode 531 on the right side contacts the lower gate wiring 516b and the finger wiring 12.
[0061] Even in this embodiment, wiring resistance and gate signal delay can be suppressed. Furthermore, by connecting the lower gate pad 515 to the upper gate pad 513, the upper electrode 530 and the lower electrode 531 can be set to the same potential. For example, wires can be used for the connection. And by connecting the lower gate pad 515 to the main electrode 50, the lower electrode 531 can be set to the emitter potential. Thus, multiple states can be achieved for the electrodes within the trench 20. Additionally, the potential of the lower electrode 531 can be changed according to the connection configuration, and capacitance adjustment can be easily implemented.
[0062] Furthermore, gate signals can be input to the upper electrode 530 and the lower electrode 531 respectively. For example, the timing of the gate signal can be changed by using the upper electrode 530 and the lower electrode 531. As a result, the adjustment of charge carriers near the trench 20 becomes easier, and losses during switching operations can be reduced.
[0063] The shapes of the upper gate wiring 514 and the lower gate wiring 516 are not limited to Figure 8 The shape is shown. The upper gate wiring 514 only needs to be disposed on the semiconductor substrate 60 between the lower gate wiring 516a or 516b and the finger wiring 12. Furthermore, the upper electrode 530 only needs to contact any portion of the upper gate wiring 514. For example, the upper electrode 530 may contact one or more of the upper gate wirings 514a, 514b, 514c, and 514d. The lower electrode 531 may also contact only one of the lower gate wirings 516a and 516b.
[0064] In this embodiment, the trench 20 is segmented directly below the finger wiring 12 in the direction from the lower gate wiring 516a toward the lower gate wiring 516b. Similarly to embodiment 2, the trench 20 may not be segmented.
[0065] Implementation Method 6
[0066] Figure 11 This is a top view of the semiconductor device 600 according to Embodiment 6. In this embodiment, the upper gate pad 513 and the lower gate pad 515 are respectively disposed on one side and the other side of the semiconductor substrate 60. A finger-shaped wiring 12 is provided between the upper gate pad 513 and the lower gate pad 515. Other structures are the same as those in Embodiment 5.
[0067] Implementation Method 7
[0068] Figure 12This is a top view of the semiconductor device 700 according to Embodiment 7. The semiconductor device 700 has a plurality of finger wirings 12a, 12b. Other structures are the same as those in Embodiment 5.
[0069] The lower-level gate wiring 716 includes lower-level gate wirings 716a and 716b electrically connected to the lower-level gate pad 515. On the semiconductor substrate 60, finger wirings 12a and 12b electrically connected to the lower-level gate pad 515 are disposed between the lower-level gate wirings 716a and 716b.
[0070] On the semiconductor substrate 60, a main electrode 50a is disposed between the lower-level gate wiring 716a and the finger wiring 12a. On the semiconductor substrate 60, a main electrode 50b is disposed between the lower-level gate wiring 716b and the finger wiring 12b. On the semiconductor substrate 60, a main electrode 50c is disposed between the finger wirings 12a and 12b.
[0071] The upper-level gate wiring 714 includes upper-level gate wirings 714a to 714f electrically connected to the upper-level gate pad 513. Upper-level gate wiring 714a is disposed between the lower-level gate wiring 716a and the main electrode 50a. Upper-level gate wiring 714b is disposed between the lower-level gate wiring 716b and the main electrode 50b. Upper-level gate wiring 714c is disposed between the finger wiring 12a and the main electrode 50a. Upper-level gate wiring 714d is disposed between the finger wiring 12b and the main electrode 50b. Upper-level gate wiring 714e is disposed between the finger wiring 12a and the main electrode 50c. Upper-level gate wiring 714f is disposed between the finger wiring 12b and the main electrode 50c.
[0072] exist Figure 12 In this example, the main electrode 50 is divided into three parts: main electrode 50a, 50b, and 50c, by finger wirings 12a and 12b. The number of finger wirings 12 is not limited. Alternatively, similar to Embodiment 1, the trench 20 may be divided directly below the finger wirings 12a and 12b. Alternatively, similar to Embodiment 2, the trench 20 may not be divided directly below the finger wirings 12a and 12b.
[0073] Implementation Method 8
[0074] Figure 13 This is a top view of the semiconductor device 800 according to Embodiment 8. The semiconductor device 800 differs from Embodiment 5 in that it also has a diode region 870 formed on the semiconductor substrate 60 in addition to the IGBT region. The other structures are the same as in Embodiment 5. That is, the semiconductor device 800 can also be an RC (Reverse Conducting) IGBT. Furthermore, the semiconductor device 100 of Embodiment 1 can also be configured as an RC-IGBT.
[0075] Implementation Method 9
[0076] Figure 14 This is a cross-sectional view of the semiconductor device 900 according to Embodiment 9, in a direction perpendicular to the direction in which the trench 20 extends. Figure 15 This is a cross-sectional view of the semiconductor device 900 according to Embodiment 9 along the direction of the trench 20. In this embodiment, two types of trenches 20c and 20d are formed on the semiconductor substrate 60. The structure of trench 20c is the same as that of trench 20 in Embodiment 5. A lower electrode 531 and an upper electrode 532 disposed on the lower electrode 531 via an insulating film 35 are disposed inside the trench 20d. Other structures are the same as those in Embodiment 5.
[0077] like Figure 15 As shown, the lower electrode 531 of trench 20d contacts the lower gate wiring 516a, lower gate wiring 516b, and finger wiring 12. The upper electrode 532 of trench 20d contacts the main electrodes 50a and 50b. The upper electrode 530 of trench 20c is an active electrode electrically connected to the upper gate pad 513. Additionally, the upper electrode 532 of trench 20d is a dummy electrode.
[0078] exist Figure 15 In this example, the lower electrode 531 on the left side of the trench 20d, which is divided into left and right sections, contacts the lower gate wiring 516a and the finger wiring 12, while the lower electrode 531 on the right side contacts the lower gate wiring 516b and the finger wiring 12. Additionally, the upper electrode 532 on the left side of the trench 20d, which is divided into left and right sections, contacts the main electrode 50a, while the upper electrode 532 on the right side contacts the main electrode 50b.
[0079] In this embodiment, the capacitance can be adjusted via the upper electrode 532 connected to the main electrode 50. Furthermore, by changing the connection of the lower gate pad 515, the potential of the lower electrode 531 can be changed, thereby facilitating easy capacitance adjustment.
[0080] In this embodiment, the lower electrode 531 of trench 20d may also contact only one of the lower gate wiring 516a and the lower gate wiring 516b. Similarly, the upper electrode 532 of trench 20d may also contact only one of the main electrode 50a and the main electrode 50b.
[0081] Implementation Method 10
[0082] Figure 16 This is a cross-sectional view of the semiconductor device 1000 according to Embodiment 10, in a direction perpendicular to the direction in which the trench 20 extends. Figure 17This is a top view of the semiconductor device 1000 according to Embodiment 10. In this embodiment, it differs from Embodiment 9 in that a trench 20e is provided instead of a trench 20d. The other structures are the same as in Embodiment 9.
[0083] A lower-level electrode 531 and an upper-level electrode 1032 disposed on the lower-level electrode 531 via an insulating film 35 are disposed inside the trench 20e. The lower-level electrode 531 of the trench 20e is in contact with the lower-level gate wiring 516a, the lower-level gate wiring 516b, and the finger wiring 12. The upper-level electrode 1032 of the trench 20e is in contact with the lower-level gate wiring 516a, the lower-level gate wiring 516b, and the finger wiring 12.
[0084] like Figure 17 As shown, the lower electrode 531 of trench 20c is electrically connected to the lower gate wiring 516 via the lower contact portion 40b in the lower rise region 41. The upper electrode 530 of trench 20c is electrically connected to the upper gate wiring 514 via the upper contact portion 40a. Additionally, the upper electrode 1032 of trench 20e is electrically connected to the lower gate wiring 516 via the upper contact portion 40a. The lower electrode 531 of trench 20e is electrically connected to the lower gate wiring 516 via the lower contact portion 40b in the lower rise region 41.
[0085] In this embodiment, by changing the connection of the gate pad, the potentials of the lower electrode 531 and the upper electrode 1032 can also be changed, and capacitance adjustment can be easily implemented.
[0086] In addition, the lower electrode 531 and the upper electrode 1032 can be in contact with one of the lower gate wiring 516a and the lower gate wiring 516b, respectively.
[0087] The various forms disclosed herein will be recorded hereafter as appendices.
[0088] (Note 1) A semiconductor device, characterized in that,
[0089] The aforementioned semiconductor device includes:
[0090] A semiconductor substrate having a first trench formed thereon;
[0091] Gate pads are disposed on the aforementioned semiconductor substrate;
[0092] The first gate wiring is disposed on the semiconductor substrate and electrically connected to the gate pad.
[0093] The second gate wiring is disposed on the semiconductor substrate and electrically connected to the gate pad.
[0094] Finger-shaped wiring is disposed on the semiconductor substrate between the first gate wiring and the second gate wiring, and is electrically connected to the gate pad.
[0095] The first main electrode is disposed on the semiconductor substrate between the first gate wiring and the finger wiring;
[0096] The second main electrode is disposed on the semiconductor substrate between the second gate wiring and the finger wiring;
[0097] The first lower electrode is disposed inside the aforementioned first trench; and
[0098] The first upper electrode is disposed on top of the first lower electrode via an insulating film inside the first trench.
[0099] The first lower electrode is in contact with the first gate wiring or the second gate wiring, and the finger wiring.
[0100] The first upper electrode is in contact with the first gate wiring or the second gate wiring and the finger wiring.
[0101] (Note 2) The semiconductor device according to Note 1 is characterized in that,
[0102] When viewed from above, the first main electrode and the second main electrode are surrounded by a gate wiring including the first gate wiring, the second gate wiring and the finger wiring.
[0103] (Note 3) The semiconductor device according to Note 1 or 2 is characterized in that,
[0104] The first trench is divided directly below the finger wiring in the direction from the first gate wiring toward the second gate wiring.
[0105] (Appendix 4) The semiconductor device according to any one of Appendices 1 to 3, characterized in that,
[0106] It has multiple of the above-mentioned finger-shaped wirings.
[0107] (Appendix 5) The semiconductor device according to any one of Appendices 1 to 4, characterized in that,
[0108] The aforementioned semiconductor device includes:
[0109] The second lower electrode is disposed inside the second trench formed in the semiconductor substrate; and
[0110] The second upper electrode is disposed on top of the second lower electrode via an insulating film inside the second trench.
[0111] The second lower electrode is in contact with the first gate wiring or the second gate wiring, and the finger wiring.
[0112] The second upper electrode is in contact with either the first main electrode or the second main electrode.
[0113] (Appendix 6) A semiconductor device, characterized in that,
[0114] The aforementioned semiconductor device includes:
[0115] A semiconductor substrate having a first trench formed thereon;
[0116] The upper gate pad is disposed on the semiconductor substrate mentioned above;
[0117] The lower-level gate pad is disposed on the aforementioned semiconductor substrate;
[0118] The first lower-level gate wiring is disposed on the semiconductor substrate and electrically connected to the lower-level gate pad.
[0119] The second lower-level gate wiring is disposed on the semiconductor substrate and electrically connected to the lower-level gate pad.
[0120] Finger-shaped wiring is disposed on the semiconductor substrate between the first lower-level gate wiring and the second lower-level gate wiring, and is electrically connected to the lower-level gate pad.
[0121] The first main electrode is disposed on the semiconductor substrate between the first lower-level gate wiring and the finger wiring.
[0122] The second main electrode is disposed on the semiconductor substrate between the second lower-level gate wiring and the finger wiring.
[0123] The upper-level gate wiring is disposed on the semiconductor substrate between the first lower-level gate wiring or the second lower-level gate wiring and the finger wiring, and is electrically connected to the upper-level gate pad.
[0124] The first lower electrode is disposed inside the aforementioned first trench; and
[0125] The first upper electrode is disposed on top of the first lower electrode via an insulating film inside the first trench.
[0126] The first lower-level electrode is in contact with the first lower-level gate wiring or the second lower-level gate wiring, as well as the finger wiring.
[0127] The first upper electrode mentioned above is in contact with the upper gate wiring mentioned above.
[0128] (Note 7) The semiconductor device according to Note 6 is characterized in that,
[0129] The aforementioned upper-level gate wiring includes:
[0130] The first upper-level gate wiring is disposed between the first lower-level gate wiring and the first main electrode, and is electrically connected to the upper-level gate pad.
[0131] The second upper-level gate wiring is disposed between the second lower-level gate wiring and the second main electrode, and is electrically connected to the upper-level gate pad.
[0132] The third upper-level gate wiring is disposed between the aforementioned finger wiring and the aforementioned first main electrode, and is electrically connected to the aforementioned upper-level gate pad; and
[0133] The fourth upper-level gate wiring is disposed between the aforementioned finger wiring and the aforementioned second main electrode, and is electrically connected to the aforementioned upper-level gate pad.
[0134] The first upper electrode is in contact with the first upper gate wiring, the second upper gate wiring, the third upper gate wiring, and the fourth upper gate wiring.
[0135] (Note 8) The semiconductor device according to Note 6 or 7 is characterized in that,
[0136] When viewed from above, the first main electrode and the second main electrode are surrounded by the upper gate wiring.
[0137] (Note 9) The semiconductor device according to any one of Notes 6 to 8, characterized in that,
[0138] The first trench is divided directly below the finger wiring in the direction from the first lower gate wiring toward the second lower gate wiring.
[0139] (Note 10) The semiconductor device according to any one of Notes 6 to 9, characterized in that,
[0140] The aforementioned upper-level gate pad is adjacent to the aforementioned lower-level gate pad.
[0141] (Note 11) The semiconductor device according to any one of Notes 6 to 9, characterized in that,
[0142] The aforementioned finger-shaped wiring is provided between the aforementioned upper-level gate pad and the aforementioned lower-level gate pad.
[0143] (Note 12) The semiconductor device according to any one of Notes 6 to 11, characterized in that,
[0144] It has multiple of the above-mentioned finger-shaped wirings.
[0145] (Note 13) The semiconductor device according to any one of Notes 6 to 12, characterized in that,
[0146] The aforementioned semiconductor device includes:
[0147] The second lower electrode is disposed inside the second trench formed in the semiconductor substrate; and
[0148] The second upper electrode is disposed on top of the second lower electrode via an insulating film inside the second trench.
[0149] The second lower-level electrode is in contact with the first lower-level gate wiring or the second lower-level gate wiring, as well as the finger wiring.
[0150] The second upper electrode is in contact with either the first main electrode or the second main electrode.
[0151] (Note 14) The semiconductor device according to any one of Notes 6 to 12, characterized in that,
[0152] The aforementioned semiconductor device includes:
[0153] The second lower electrode is disposed inside the second trench formed in the semiconductor substrate; and
[0154] The second upper electrode is disposed on top of the second lower electrode via an insulating film inside the second trench.
[0155] The second lower-level electrode is in contact with the first lower-level gate wiring or the second lower-level gate wiring, as well as the finger wiring.
[0156] The second upper electrode is in contact with the first lower gate wiring or the second lower gate wiring and the finger wiring.
[0157] (Note 15) The semiconductor device according to any one of Notes 1 to 14, characterized in that,
[0158] The aforementioned semiconductor substrate is formed from a wide-bandgap semiconductor.
[0159] (Note 16) The semiconductor device according to Note 15 is characterized in that,
[0160] The aforementioned wide-bandgap semiconductor is silicon carbide, gallium nitride-based material, or diamond.
Claims
1. A semiconductor device, characterized in that, The semiconductor device includes: A semiconductor substrate having a first trench formed thereon; Gate pads are disposed on the semiconductor substrate; The first gate wiring is disposed on the semiconductor substrate and electrically connected to the gate pad; The second gate wiring is disposed on the semiconductor substrate and electrically connected to the gate pad; Finger-shaped wiring is disposed on the semiconductor substrate between the first gate wiring and the second gate wiring, and is electrically connected to the gate pad; The first main electrode is disposed on the semiconductor substrate between the first gate wiring and the finger wiring; The second main electrode is disposed on the semiconductor substrate between the second gate wiring and the finger wiring; The first lower electrode is disposed inside the first trench; as well as The first upper electrode is disposed inside the first trench, above the first lower electrode, via an insulating film. The first lower electrode is in contact with the first gate wiring or the second gate wiring, and the finger wiring. The first upper electrode is in contact with the first gate wiring or the second gate wiring, as well as the finger wiring.
2. The semiconductor device according to claim 1, characterized in that, When viewed from above, the first main electrode and the second main electrode are surrounded by a gate wiring including the first gate wiring, the second gate wiring and the finger wiring.
3. The semiconductor device according to claim 1 or 2, characterized in that, The first trench is divided directly below the finger wiring in a direction from the first gate wiring toward the second gate wiring.
4. The semiconductor device according to claim 1 or 2, characterized in that, It has multiple of the aforementioned finger-shaped wirings.
5. The semiconductor device according to claim 1 or 2, characterized in that, The semiconductor device includes: The second lower electrode is disposed inside the second trench formed on the semiconductor substrate; and The second upper electrode is disposed inside the second trench, above the second lower electrode, via an insulating film. The second lower electrode is in contact with the first gate wiring or the second gate wiring, and the finger wiring. The second upper electrode is in contact with either the first main electrode or the second main electrode.
6. A semiconductor device, characterized in that, The semiconductor device includes: A semiconductor substrate having a first trench formed thereon; An upper-level gate pad is disposed on the semiconductor substrate; The lower-level gate pad is disposed on the semiconductor substrate; The first lower-level gate wiring is disposed on the semiconductor substrate and electrically connected to the lower-level gate pad; The second lower-level gate wiring is disposed on the semiconductor substrate and electrically connected to the lower-level gate pad; Finger-shaped wiring is disposed on the semiconductor substrate between the first lower-level gate wiring and the second lower-level gate wiring, and is electrically connected to the lower-level gate pad; The first main electrode is disposed on the semiconductor substrate between the first lower-level gate wiring and the finger wiring; The second main electrode is disposed on the semiconductor substrate between the second lower-level gate wiring and the finger wiring; An upper-level gate wiring is disposed on the semiconductor substrate between the first lower-level gate wiring or the second lower-level gate wiring and the finger wiring, and is electrically connected to the upper-level gate pad. The first lower electrode is disposed inside the first trench; as well as The first upper electrode is disposed inside the first trench, above the first lower electrode, via an insulating film. The first lower-level electrode is in contact with the first lower-level gate wiring or the second lower-level gate wiring, and the finger wiring. The first upper electrode is in contact with the upper gate wiring.
7. The semiconductor device according to claim 6, characterized in that, The upper-level gate wiring includes: The first upper-level gate wiring is disposed between the first lower-level gate wiring and the first main electrode, and is electrically connected to the upper-level gate pad; The second upper-level gate wiring is disposed between the second lower-level gate wiring and the second main electrode, and is electrically connected to the upper-level gate pad; The third upper-level gate wiring is disposed between the finger wiring and the first main electrode, and is electrically connected to the upper-level gate pad; as well as The fourth upper-level gate wiring is disposed between the finger wiring and the second main electrode, and is electrically connected to the upper-level gate pad. The first upper electrode is in contact with the first upper gate wiring, the second upper gate wiring, the third upper gate wiring, and the fourth upper gate wiring.
8. The semiconductor device according to claim 6 or 7, characterized in that, When viewed from above, the first main electrode and the second main electrode are surrounded by the upper gate wiring.
9. The semiconductor device according to claim 6 or 7, characterized in that, The first trench is divided directly below the finger wiring in the direction from the first lower gate wiring toward the second lower gate wiring.
10. The semiconductor device according to claim 6 or 7, characterized in that, The upper-level gate pad is adjacent to the lower-level gate pad.
11. The semiconductor device according to claim 6 or 7, characterized in that, The finger-shaped wiring is provided between the upper gate pad and the lower gate pad.
12. The semiconductor device according to claim 6 or 7, characterized in that, It has multiple of the aforementioned finger-shaped wirings.
13. The semiconductor device according to claim 6 or 7, characterized in that, The semiconductor device includes: The second lower electrode is disposed inside the second trench formed on the semiconductor substrate; and The second upper electrode is disposed inside the second trench, above the second lower electrode, via an insulating film. The second lower-level electrode is in contact with the first lower-level gate wiring or the second lower-level gate wiring, as well as the finger wiring. The second upper electrode is in contact with either the first main electrode or the second main electrode.
14. The semiconductor device according to claim 6 or 7, characterized in that, The semiconductor device includes: The second lower electrode is disposed inside the second trench formed on the semiconductor substrate; and The second upper electrode is disposed inside the second trench, above the second lower electrode, via an insulating film. The second lower-level electrode is in contact with the first lower-level gate wiring or the second lower-level gate wiring, as well as the finger wiring. The second upper electrode is in contact with the first lower gate wiring or the second lower gate wiring, as well as the finger wiring.
15. The semiconductor device according to claim 1 or 6, characterized in that, The semiconductor substrate is formed of a wide-bandgap semiconductor.
16. The semiconductor device according to claim 15, characterized in that, The wide-bandgap semiconductor is silicon carbide, gallium nitride-based materials, or diamond.
Citation Information
Patent Citations
Semiconductor element, semiconductor device
JP2024045595A