Power semiconductor device with terminal area integrated with temperature sensor

Abstract

The invention relates to a power semiconductor device with a terminal area integrated with a temperature sensor. According to the technical scheme provided by the invention, the power semiconductor device with the terminal area integrated with the temperature sensor comprises a semiconductor substrate of a first conduction type; the terminal area surrounds the active area surrounding the central area of the semiconductor substrate and at least comprises a cut-off ring and a temperature sensor integrated in the cut-off ring, the cut-off ring comprises a cut-off ring groove, and the temperature sensor is located in the cut-off ring groove. Under the condition that the area of an active region is not occupied, the terminal cut-off function can be achieved, and the real temperature can be effectively monitored.

Description

Technical Field

[0001] This invention relates to a power semiconductor device, and more particularly to a power semiconductor device with an integrated temperature sensor in the terminal area. Background Technology

[0002] Termination rings are indispensable "guardian boundaries" in the design of power semiconductor devices such as IGBTs. Although they do not participate in the switching control function at the device center, they cleverly manage the electric field at the chip edge, ensuring that the entire device can safely and stably withstand high voltages. This is one of the key technologies for achieving high voltage and high reliability. Currently, there are two main types of termination ring designs: N-type ring design and trench design. The trench design uses N-type polysilicon to achieve trench cutoff, while the trench design extends the termination ring from the device surface into the device interior.

[0003] Under normal operating conditions, power semiconductor devices generate power consumption, which causes their temperature to rise. If the ambient temperature is also high, the temperature of the power semiconductor device may exceed its maximum operating temperature, ultimately leading to its failure and burnout. Therefore, effective temperature control of power semiconductor devices is crucial to prevent malfunctions in equipment based on them, thereby avoiding equipment failure, losses, or accidents.

[0004] Currently, temperature monitoring is generally achieved by adding a packaged thermistor to the power semiconductor device module. This method is rather crude, as the power semiconductor device is the heat-generating center and is far from the thermistor, thus failing to accurately reflect the actual operating temperature.

[0005] In addition, temperature sensors can be integrated into power semiconductor devices. Generally, a region is set up in the active area of ​​the power semiconductor device to serve as a temperature sensor. This method occupies the area of ​​the active area and affects the function of the active area. Moreover, this structure is located on the surface of the power semiconductor device, but the heat generated by the power semiconductor device is generally located inside, which is still different from the actual temperature and cannot reflect the true operating temperature of the power semiconductor device. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a power semiconductor device with an integrated temperature sensor in the terminal area, which can realize the terminal cutoff function and effectively monitor the real temperature without occupying the area of ​​the active area.

[0007] According to the technical solution provided by the present invention, a power semiconductor device integrating a temperature sensor in a terminal area is provided, the power semiconductor device comprising: The semiconductor substrate exhibits a first conductivity type; The terminal region, surrounding the active region enclosing the central region of the semiconductor substrate, includes at least a stop-off ring and a temperature sensor integrated within the stop-off ring, wherein... The stop ring includes a stop ring groove, and the temperature sensor is located inside the stop ring groove.

[0008] The stop ring further includes stop-conductive polycrystalline silicon located within the stop ring trench and exhibiting a first conductivity type, wherein... The conductive polycrystalline silicon is cut off from the ohmic contact of the cutoff ring metal above the semiconductor substrate. The temperature sensor is located at least within a portion of the cutoff ring trench, wherein, when the temperature sensor is present within the cutoff ring trench, the cutoff conductive polysilicon is located above the temperature sensor body, and the temperature sensor and the cutoff conductive polysilicon are insulated from each other.

[0009] The temperature sensor comprises a first temperature-conductive polycrystalline silicon and a second temperature-conductive polycrystalline silicon, wherein... The first-temperature conductive polycrystalline silicon and the second-temperature conductive polycrystalline silicon have different conductivity types, and there is contact between the first-temperature conductive polycrystalline silicon and the second-temperature conductive polycrystalline silicon. The first temperature-conductive polysilicon is in ohmic contact with the first temperature-sensing pad, and the second temperature-conductive polysilicon is in ohmic contact with the second temperature-sensing pad.

[0010] An insulating oxide layer is provided on the inner wall of the stop ring trench. The stop conductive polysilicon, the first temperature conductive polysilicon, and the second temperature conductive polysilicon are insulated and isolated from the inner wall of the stop ring trench through the insulating oxide layer. Within the cutoff ring trench, the second temperature conductive polysilicon is located between the first temperature conductive polysilicon and the cutoff conductive polysilicon; The second conductive polysilicon at temperature is insulated from the cut-off conductive polysilicon through the first insulating isolation layer in the tank, and the second conductive polysilicon at temperature is isolated from the first conductive polysilicon at temperature through the second insulating isolation layer in the tank. The second conductive polysilicon at temperature is also in contact with the first conductive polysilicon at temperature through an isolation contact hole that penetrates the second insulating isolation layer in the tank.

[0011] Both the first insulating layer and the second insulating layer inside the tank are insulating oxide layers.

[0012] The depth of the stop ring trench is not greater than the junction depth of the main junction, or, when the cell in the active region adopts a trench structure, the depth of the stop ring trench is not greater than the depth of the cell trench.

[0013] When the cells in the active region adopt a trench structure, a trench grid is set in each cell trench, and the trench grid is insulated from the inner wall of the cell trench.

[0014] The terminal area also includes several field-limited loops, among which... When the terminal area includes multiple field limiting loops, all the field limiting loops surround the active area, and the field limiting loops are located between the active area and the cutoff loop. For any field limiting ring, the field limiting ring includes a second conductivity type doped region located in the terminal region, and the junction depth of the second conductivity type doped region of the field limiting ring gradually decreases along the direction from the active region to the cutoff ring.

[0015] The second conductivity type doped region of each field limiting ring is in ohmic contact with the field limiting ring metal layer, and the field limiting ring metal layer is connected to the conductive polysilicon and the connected second conductivity type doped region through the doped region.

[0016] A back electrode structure is provided on the back side of the semiconductor substrate, wherein the back electrode structure corresponds to the active region and the terminal region.

[0017] Advantages of this invention: A temperature sensor is integrated within the cutoff ring, and a first type of conductive polysilicon is provided within the cutoff ring groove. The cutoff function can be achieved using the first type of conductive polysilicon. When the temperature sensor is integrated within the cutoff ring, effective temperature monitoring can be achieved without occupying the area of ​​the active region, and the normal cutoff function of the cutoff ring can be maintained. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of one embodiment of the power semiconductor device of the present invention.

[0019] Figure 2 This is a cross-sectional view of an embodiment of the power semiconductor device of the present invention.

[0020] Figure 3 This is a schematic diagram of one embodiment of the temperature sensor of the present invention located in the cutoff ring groove.

[0021] Figure label explanation: 1-Emitter pad, 2-Gate pad, 3-Stop ring, 4-Temperature sensing first pad, 5-Temperature sensing second pad, 6-Temperature sensor, 7-Field limiting ring transition region, 6-Stop region, 8-Back electrode structure, 9-Cell trench, 10-Trench gate, 11-Cell insulating oxide layer, 12-Field limiting ring, 13-Insulating dielectric layer, 14-Passivation layer, 15-Field limiting ring metal layer, 16-Stop ring trench, 17-Temperature first conductive polysilicon 18 - Temperature-controlled second conductive polysilicon; 19 - Cut-off trench insulating oxide layer; 20 - Cut-off conductive polysilicon; 21 - Cut-off ring metal; 22 - First insulating isolation layer in the trench; 23 - N-type field cut-off layer; 24 - P+ collector layer; 25 - Collector metal layer; 26 - Doped region connecting conductive polysilicon; 27 - Temperature-controlled first lead-out; 28 - Second insulating isolation layer in the trench; 29 - Isolation contact hole; 30 - N+ substrate; 31 - Temperature-controlled second lead-out; 32 - Cut-off region. Detailed Implementation

[0022] The present invention will be further described below with reference to specific accompanying drawings and embodiments.

[0023] To achieve both termination cutoff functionality and effective real-time temperature monitoring without occupying the active area, this invention provides a power semiconductor device with an integrated temperature sensor 6 in the termination area. Specifically, taking N-type as an example, the power semiconductor device includes: The semiconductor substrate is of the N-type conductivity. The terminal region, surrounding the active region of the semiconductor substrate's central region, includes at least a stop-off ring 3 and a temperature sensor 6 integrated within the stop-off ring 3. The stop ring 3 includes a stop ring groove 16, and the temperature sensor 6 is located in the stop ring groove 16.

[0024] Similar to existing power semiconductor devices, the power semiconductor device of the present invention also includes a semiconductor substrate, an active region disposed in the central region of the semiconductor substrate, and a terminal region surrounding the active region. Figure 1 The diagram illustrates one embodiment of the distribution of the active region and the termination region on a semiconductor substrate. Similar to existing termination regions, the termination region of this invention also includes a stop ring 3, which is generally closer to the edge of the termination region. Furthermore, the stop ring 3 of this invention should include a stop ring trench 16. It is understood that the stop ring trench 16 is an annular trench, and it should also surround the active region. The area where the stop ring 3 is located can form a stop region 32. When the stop ring 3 and the stop ring trench 16 are used, the stop effect can be introduced from the surface of the device into the interior of the device.

[0025] To effectively monitor temperature, a temperature sensor 6 is integrated within the cutoff ring 3. When the temperature sensor 6 is integrated within the cutoff ring 3, it does not occupy the area of ​​the active region and does not affect the normal cutoff function of the cutoff ring 3. Figure 2 and Figure 3 It can be seen that when the temperature sensor 6 is integrated into the stop ring 3, specifically, the temperature sensor 6 is fabricated within the stop ring trench 16. When the temperature sensor 6 is located within the stop ring trench 16, that is, within the power semiconductor device, it can better address the heat generation location during the operation of the power semiconductor device, thereby effectively enabling temperature monitoring of the power semiconductor device during operation.

[0026] In one embodiment of the present invention, the cutoff ring 3 further includes a cutoff conductive polycrystalline silicon 20 located within the cutoff ring trench 16 and having an N-type conductivity, wherein, The conductive polycrystalline silicon 20 is in ohmic contact with the stop ring metal 21 above the semiconductor substrate; Temperature sensor 6 is located at least within a portion of the cutoff ring trench 16, wherein, when temperature sensor 6 is present within the cutoff ring trench 16, cutoff conductive polysilicon 20 is located above the body of temperature sensor 6, and temperature sensor 6 and cutoff conductive polysilicon 20 are insulated from each other.

[0027] Similar to existing methods for achieving the cutoff function, an N-type cutoff conductive polysilicon 20 is provided within the cutoff ring trench 16, such as... Figure 2 and Figure 3 As shown, the cutoff conductive polysilicon 20 extends from the control within the cutoff ring trench 16 towards the bottom of the trench 16. Since the cutoff ring trench 16 is annular, the cutoff conductive polysilicon 20 should fill the entire area of ​​the cutoff ring trench 16. Figure 2 and Figure 3 In the process, the cut-off conductive polycrystalline silicon 20 is in ohmic contact with the cut-off ring metal 21. During operation, the cut-off ring metal 21 is generally configured to be in a floating state, that is, the cut-off ring metal 21 does not need to be connected to external voltage, etc.

[0028] In practice, temperature sensors 6 can be installed within a portion of the stop ring groove 16. In this case, the temperature sensors 6 are only distributed in a part of the stop ring groove 16. Of course, the temperature sensors 6 can also be distributed throughout the area where the stop ring groove 16 is located; the specific distribution can be chosen according to the needs. Figure 1 The image shows an embodiment in which the temperature sensor 6 is distributed in a portion of the stop ring groove 16, that is... Figure 1 The image only shows a temperature sensor 6 integrated on one side inside the stop ring 3.

[0029] Figure 2 and Figure 3An embodiment of the temperature sensor 6 is shown in the cutoff ring groove 16. In order not to affect the normal cutoff function and to improve the effectiveness of temperature monitoring, the temperature sensor 6 should be located below the cutoff conductive polysilicon 20, and the temperature sensor 6 and the cutoff conductive polysilicon 20 should be insulated and isolated from each other, that is, the temperature sensor 6 and the cutoff conductive polysilicon 20 should not interfere with each other.

[0030] In one embodiment of the present invention, the temperature sensor 6 includes a first temperature-conductive polycrystalline silicon 17 and a second temperature-conductive polycrystalline silicon 18, wherein... The first-temperature conductive polycrystalline silicon 17 and the second-temperature conductive polycrystalline silicon 18 correspond to different conductivity types, and there is contact between the first-temperature conductive polycrystalline silicon 17 and the second-temperature conductive polycrystalline silicon 18. The first temperature conductive polysilicon 17 is in 4-ohm contact with the first temperature sensing pad, and the second temperature conductive polysilicon 18 is in 5-ohm contact with the second temperature sensing pad.

[0031] In order to achieve temperature monitoring, the temperature sensor 6 should include a first temperature conductive polycrystalline silicon 17 and a second temperature conductive polycrystalline silicon 18. The first temperature conductive polycrystalline silicon 17 and the second temperature conductive polycrystalline silicon 18 have different conductivity types. For example, the conductivity type of the first temperature conductive polycrystalline silicon 17 can be N-type or P-type, while the conductivity type of the second temperature conductive polycrystalline silicon 18 should be P-type or N-type. When the first temperature conductive polycrystalline silicon 17 and the second temperature conductive polycrystalline silicon 18 form a contact fit, a PN junction for temperature measurement can be formed.

[0032] To facilitate temperature measurement connection, the first conductive polysilicon 17 should be in 4-ohm contact with the first temperature sensing pad, and the second conductive polysilicon 18 should be in 5-ohm contact with the second temperature sensing pad. Figure 1 As shown, the first temperature sensing pad 4 and the second temperature sensing pad 5 can be located at the corner of the terminal area of ​​the semiconductor substrate, so as not to affect the entire power semiconductor device. During temperature measurement, the external circuit is electrically connected to the first temperature sensing pad 4 and the second temperature sensing pad 5, and temperature measurement can be achieved according to the conduction state of the formed PN junction. The specific temperature measurement method and principle can be consistent with the existing technology, and will not be described in detail here.

[0033] It should be noted that... Figure 1 The direction formed by the connection between the first temperature sensing pad 4 and the second temperature sensing pad 5 is configured as the first direction, and the connection is perpendicular to the first direction. Figure 1 When the active region and terminal region are viewed in cross-section, the following can be obtained: Figure 2 The diagram shows that when the area where the temperature sensor 6 is located is viewed in cross-section along the first direction, the following can be obtained: Figure 3 A sectional view.

[0034] In one embodiment of the present invention, a stop trench insulating oxide layer 19 is provided on the inner wall of the stop ring trench 16, and the stop conductive polysilicon 20, the first temperature conductive polysilicon 17 and the second temperature conductive polysilicon 18 are insulated and isolated from the inner wall of the stop ring trench 16 through the stop trench insulating oxide layer 19. Within the cutoff ring trench 16, the second temperature conductive polysilicon 18 is located between the first temperature conductive polysilicon 17 and the cutoff conductive polysilicon 20. The second conductive polysilicon 18 is insulated from the cut-off conductive polysilicon 20 through the first insulating isolation layer 22 in the tank. The second conductive polysilicon 18 is isolated from the first conductive polysilicon 17 through the second insulating isolation layer 28 in the tank. The second conductive polysilicon 18 is also in contact with the first conductive polysilicon 17 through the isolation contact hole 29 that penetrates the second insulating isolation layer 28 in the tank.

[0035] Specifically, the insulating oxide layer 19 of the stop trench is a silicon dioxide layer, and the insulating oxide layer 19 of the stop trench covers the inner wall of the stop ring trench 16. Figure 3 In this configuration, the second temperature-conductive polysilicon 18 is located between the first temperature-conductive polysilicon 17 and the cutoff-conductive polysilicon 20. The first temperature-conductive polysilicon 17 is closer to the bottom of the cutoff ring trench 16, while the second temperature-conductive polysilicon 18 is closer to the cutoff-conductive polysilicon 20. To enable the formation of a PN junction, contact holes 29 are provided in the second insulating layer 28 within the trench. This allows the second temperature-conductive polysilicon 18 to connect with the first temperature-conductive polysilicon 17 via the contact holes 29 during its fabrication.

[0036] In specific implementation, the first insulating isolation layer 22 and the second insulating isolation layer 28 in the tank are both insulating oxide layers, and the first insulating isolation layer 22 and the second insulating isolation layer 28 in the tank can be prepared by thermal oxidation. Figure 3 In the middle, the first temperature conductive polysilicon 17 and the second temperature conductive polysilicon 18 are both L-shaped so that the first temperature conductive polysilicon 17 and the second temperature conductive polysilicon 18 can be led out, and the first temperature lead 27 is in ohmic contact with the first temperature conductive polysilicon 17, and the second temperature lead 31 is in ohmic contact with the second temperature conductive polysilicon 18. Then, the first temperature lead 27 is electrically connected to the first temperature sensing pad 4, and the second temperature lead 27 is electrically connected to the second temperature sensing pad 5.

[0037] In one embodiment of the present invention, the depth of the cutoff ring trench 16 is not greater than the junction depth of the main junction, or, when the cell in the active region adopts a trench structure, the depth of the cutoff ring trench 16 is not greater than the depth of the cell trench 9.

[0038] Specifically, the depth of the stop ring trench 16 should generally not exceed the junction depth of the main junction. The meanings of the main junction and its junction depth are consistent with the prior art and will not be repeated here. In addition, when the cell in the active region adopts a trench structure, the depth of the stop ring trench 16 should not exceed the depth of the cell trench 9.

[0039] Furthermore, when the cells in the active region adopt a trench structure, a trench grid 10 is provided in each cell trench 9, and the trench grid 10 is insulated from the inner wall of the cell trench 9.

[0040] Figure 2 The image shows an embodiment in which the cells in the active region employ a trench structure; therefore, Figure 2 The figure only includes the active region and the terminal region. When the cell adopts a trench structure, it can be consistent with existing technology, such as setting a trench gate 10 within the cell trench 9. Furthermore, a cell insulating oxide layer 11 is set within the cell trench 9, and the trench gate 10 is insulated from the sidewall of the cell trench 9 through the cell insulating oxide layer 11. The trench gate 10 can adopt a commonly used existing form. It should be understood that... Figure 2 Other structures besides cell groove 9 are not shown. Other structures should be based on the ability to form effective cells, and will not be listed here.

[0041] In one embodiment of the present invention, the terminal area further includes a plurality of field limiting loops 12, wherein, When the terminal area includes multiple field limiting rings 12, all multiple field limiting rings 12 surround the active area, and the field limiting rings 12 are located between the active area and the cutoff ring 3. For any field limiting ring 12, the field limiting ring 12 includes a P-type doped region located in the terminal region, and the junction depth of the P-type doped region of the field limiting ring 12 gradually decreases along the direction from the active region to the cutoff ring 3.

[0042] Figure 2 The image shows an embodiment that also includes a field limiting loop 12 within the terminal area. Figure 2 The field limiting ring 12 and the cell trench 9 adjacent to the terminal region can form a field limiting ring transition region 7. The number of field limiting rings 12 in the terminal region can be selected as needed. Figure 2 The diagram illustrates one embodiment including four field confinement rings 12. When the conductivity type of the semiconductor substrate is N-type, the conductivity type of the field confinement rings 12 should be P-type, such as by forming a P-type doped region through impurity ion implantation.

[0043] Furthermore, the P-type doped region of each field limiting ring 12 is in ohmic contact with the field limiting ring metal layer 15, and the field limiting ring metal layer 15 is connected to the connected P-type doped region via the doped region connecting the conductive polysilicon 26.

[0044] In order to form the function of the field limiting ring, each field limiting ring 12 should also be in ohmic contact with the field limiting ring metal layer 15. In addition, the field limiting ring metal layer 15 should also be connected to the connected P-type doped region via the doped region to the conductive polysilicon 26. During operation, all field limiting ring metal layers 15 should be in a floating state. The floating state can be referred to the corresponding description above.

[0045] Figure 2 and Figure 3 In this design, an insulating dielectric layer 13 is also disposed on the semiconductor substrate, covering the front side of the semiconductor substrate. As shown in the figure, a field-limiting ring metal layer 15 covers the insulating dielectric layer 13, and the field-limiting ring metal layer 15 makes ohmic contact with the P-type doped region through a dielectric layer contact hole. Of course, other contact implementations also require contact holes penetrating the insulating dielectric layer 13; see the attached diagram for details. Figure 2 and Figure 3 The explanation is as follows. In addition, a passivation layer 14 is provided on the insulating dielectric layer 13, and the passivation layer 14 covers the insulating dielectric layer 13 and the field limiting ring metal layer 15, etc., to achieve passivation protection.

[0046] In one embodiment of the present invention, a back electrode structure 8 is provided on the back side of the semiconductor substrate, wherein the back electrode structure 8 corresponds to the active region and the terminal region.

[0047] Figure 2 and Figure 3 The diagram outputs one embodiment of the back electrode structure 8. The back electrode structure 8 should correspond to the type of power semiconductor device. For example, when the power semiconductor device is an IGBT type device, the back electrode structure 8 should include an N-type field cutoff layer 23, a P+ collector layer 24, and a collector metal layer 25. The N-type field cutoff layer 23 is disposed on the N+ substrate 30, the P+ collector layer 24 is disposed on the N-type field cutoff layer 23, and the collector metal layer 25 is disposed on the P+ collector layer 24 and is in ohmic contact with the P+ collector layer 24. When the power semiconductor device is of other types, the back electrode structure 8 can be determined accordingly. Examples will not be given here.

[0048] also, Figure 1 The diagram shows a top front view of a power semiconductor device. When the power semiconductor device is an IGBT type device, it should also include emitter pad 1, which allows all cells in the active region to be arranged side-by-side. In addition, a gate pad 2 is provided in the active region, through which the trench gate in the active region can be led out and connected.

Claims

1. A power semiconductor device with an integrated temperature sensor in the terminal area, characterized in that, The power semiconductor device includes: The semiconductor substrate exhibits a first type of conductivity. The terminal region, surrounding the active region enclosing the central region of the semiconductor substrate, includes at least a stop-off ring and a temperature sensor integrated within the stop-off ring, wherein... The stop ring includes a stop ring groove, and the temperature sensor is located inside the stop ring groove.

2. The power semiconductor device with an integrated temperature sensor in the terminal area according to claim 1, characterized in that: The stop ring further includes stop-conductive polycrystalline silicon located within the stop ring trench and exhibiting a first conductivity type, wherein... The conductive polycrystalline silicon is cut off from the ohmic contact of the cutoff ring metal above the semiconductor substrate. The temperature sensor is located at least within a portion of the cutoff ring trench, wherein, when the temperature sensor is present within the cutoff ring trench, the cutoff conductive polysilicon is located above the temperature sensor body, and the temperature sensor and the cutoff conductive polysilicon are insulated from each other.

3. The power semiconductor device with an integrated temperature sensor in the terminal area according to claim 2, characterized in that: The temperature sensor comprises a first temperature-conductive polycrystalline silicon and a second temperature-conductive polycrystalline silicon, wherein... The first-temperature conductive polycrystalline silicon and the second-temperature conductive polycrystalline silicon have different conductivity types, and there is contact between the first-temperature conductive polycrystalline silicon and the second-temperature conductive polycrystalline silicon. The first temperature-conductive polysilicon is in ohmic contact with the first temperature-sensing pad, and the second temperature-conductive polysilicon is in ohmic contact with the second temperature-sensing pad.

4. The power semiconductor device with an integrated temperature sensor in the terminal area according to claim 3, characterized in that: An insulating oxide layer is provided on the inner wall of the stop ring trench. The stop conductive polysilicon, the first temperature conductive polysilicon, and the second temperature conductive polysilicon are insulated and isolated from the inner wall of the stop ring trench through the insulating oxide layer. Within the cutoff ring trench, the second temperature conductive polysilicon is located between the first temperature conductive polysilicon and the cutoff conductive polysilicon; The second conductive polysilicon at temperature is insulated from the cut-off conductive polysilicon through the first insulating isolation layer in the tank, and the second conductive polysilicon at temperature is isolated from the first conductive polysilicon at temperature through the second insulating isolation layer in the tank. The second conductive polysilicon at temperature is also in contact with the first conductive polysilicon at temperature through an isolation contact hole that penetrates the second insulating isolation layer in the tank.

5. The power semiconductor device with an integrated temperature sensor in the terminal area according to claim 3, characterized in that: Both the first insulating layer and the second insulating layer inside the tank are insulating oxide layers.

6. The power semiconductor device with an integrated temperature sensor in the terminal area according to claim 2, characterized in that: The depth of the stop ring trench is not greater than the junction depth of the main junction, or, when the cell in the active region adopts a trench structure, the depth of the stop ring trench is not greater than the depth of the cell trench.

7. The power semiconductor device with an integrated temperature sensor in the terminal area according to claim 6, characterized in that: When the cells in the active region adopt a trench structure, a trench grid is set in each cell trench, and the trench grid is insulated from the inner wall of the cell trench.

8. The power semiconductor device with an integrated temperature sensor in the terminal area according to any one of claims 1 to 7, characterized in that: The terminal area also includes several field-limited loops, among which... When the terminal area includes multiple field limiting loops, all the field limiting loops surround the active area, and the field limiting loops are located between the active area and the cutoff loop. For any field limiting ring, the field limiting ring includes a second conductivity type doped region located in the terminal region, and the junction depth of the second conductivity type doped region of the field limiting ring gradually decreases along the direction from the active region to the cutoff ring.

9. The power semiconductor device with an integrated temperature sensor in the terminal area according to claim 8, characterized in that: The second conductivity type doped region of each field limiting ring is in ohmic contact with the field limiting ring metal layer, and the field limiting ring metal layer is connected to the conductive polysilicon and the connected second conductivity type doped region through the doped region.

10. The power semiconductor device with an integrated temperature sensor in the terminal area according to any one of claims 1 to 7, characterized in that: A back electrode structure is provided on the back side of the semiconductor substrate, wherein the back electrode structure corresponds to the active region and the terminal region.

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