Semiconductor device

Abstract

The purpose of the present disclosure is to provide a technique capable of accurately measuring the potential of a temperature sensing unit. The semiconductor device includes an emitter electrode, a temperature sensing portion provided adjacent to the emitter electrode, a sensing wiring, and a first lead bonding portion provided adjacent to a connection portion between the emitter electrode and the sensing wiring. The sensing wiring includes a first sensing wiring portion, a second sensing wiring portion, and a bent portion. The distance from the connecting portion to the first lead bonding portion is shorter than the distance from the bent portion to the connecting portion.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. Background Technology

[0002] A structure has been proposed that connects a wiring led out from either the anode or cathode of a temperature sensing unit disposed on a semiconductor chip to a main current electrode such as the emitter electrode of the semiconductor element (e.g., Patent Document 1). According to such a structure, a portion of the main current electrode can be used as an electrode pad for the temperature sensing unit, thereby reducing the area required for the electrode pad of the temperature sensing unit.

[0003] Patent Document 1: International Publication No. 2015 / 029159

[0004] In the above structure, sometimes the distance between the wiring leading from the temperature sensing unit and the connection point of the main current electrode, and the lead junction point in the main current electrode that connects to the lead for reading the potential of the temperature sensing unit, becomes longer. When this distance becomes longer, the potential of the temperature sensing unit read through the lead is strongly affected by the main current flowing in the main current electrode, thus causing a problem where the potential of the temperature sensing unit cannot be accurately measured (read). Summary of the Invention

[0005] Therefore, this disclosure was made in view of the aforementioned problems, and its object is to provide a technique that can accurately measure the potential of a temperature sensing element.

[0006] The semiconductor device disclosed herein includes: a semiconductor substrate having a first main surface; an emitter electrode selectively disposed on the first main surface; a temperature sensing unit disposed on the first main surface adjacent to the emitter electrode at a position closer to the end of the semiconductor substrate when viewed from above; a sensing wiring having one end connected to the temperature sensing unit and the other end connected to the emitter electrode at the end of the semiconductor substrate and disposed along the emitter electrode; and a first lead connection portion, and a connection between the emitter electrode and the sensing wiring. The sensing wiring is disposed adjacent to the emitter electrode and includes: a first sensing wiring portion that, when viewed from above, extends from the inside of the semiconductor substrate in a first direction to the terminal; a second sensing wiring portion that, at the terminal, extends from the first sensing wiring portion to the connection portion in a second direction different from the first direction of the first sensing wiring portion; and a bend portion located between the first sensing wiring portion and the second sensing wiring portion, wherein the distance from the connection portion to the first lead junction portion is shorter than the distance from the bend portion to the connection portion.

[0007] According to this disclosure, the distance from the connecting portion to the first lead joint is shorter than the distance from the bend to the connecting portion. With this structure, the potential of the temperature sensing portion can be accurately measured. Attached Figure Description

[0008] Figure 1 This is a top view showing the structure of the semiconductor device involved in Embodiment 1.

[0009] Figure 2 This is a top view showing another structure of the semiconductor device involved in Embodiment 1.

[0010] Figure 3 This is a partially enlarged top view showing the structure of the IGBT region of the semiconductor device according to Embodiment 1.

[0011] Figure 4 This is a cross-sectional view showing the structure of the IGBT region of the semiconductor device according to Embodiment 1.

[0012] Figure 5 This is a cross-sectional view showing the structure of the IGBT region of the semiconductor device according to Embodiment 1.

[0013] Figure 6 This is a partially enlarged top view showing the structure of the diode region of the semiconductor device according to Embodiment 1.

[0014] Figure 7 This is a cross-sectional view showing the structure of the diode region of the semiconductor device according to Embodiment 1.

[0015] Figure 8 This is a cross-sectional view showing the structure of the diode region of the semiconductor device according to Embodiment 1.

[0016] Figure 9 This is a cross-sectional view showing the structure of the boundary region between the IGBT region and the diode region of the semiconductor device involved in Embodiment 1.

[0017] Figure 10 This is a cross-sectional view showing the structure of the terminal region of the semiconductor device according to Embodiment 1.

[0018] Figure 11 This is a cross-sectional view showing the structure of the terminal region of the semiconductor device according to Embodiment 1.

[0019] Figure 12 (a) and (b) are cross-sectional views showing the manufacturing method of the semiconductor device according to Embodiment 1.

[0020] Figure 13(a) and (b) are cross-sectional views showing the manufacturing method of the semiconductor device according to Embodiment 1.

[0021] Figure 14 (a) and (b) are cross-sectional views showing the manufacturing method of the semiconductor device according to Embodiment 1.

[0022] Figure 15 (a) and (b) are cross-sectional views showing the manufacturing method of the semiconductor device according to Embodiment 1.

[0023] Figure 16 (a) and (b) are cross-sectional views showing the manufacturing method of the semiconductor device according to Embodiment 1.

[0024] Figure 17 (a) and (b) are cross-sectional views showing the manufacturing method of the semiconductor device according to Embodiment 1.

[0025] Figure 18 This is a cross-sectional view showing the structure of the semiconductor device involved in Embodiment 1.

[0026] Figure 19 This is a top view schematically illustrating the structure of the semiconductor device according to Embodiment 1.

[0027] Figure 20 It is a top view that schematically represents the structure of the relevant device.

[0028] Figure 21 This is a top view schematically illustrating the structure of the semiconductor device according to Embodiment 1.

[0029] Figure 22 This is a top view schematically illustrating the structure of the semiconductor device involved in Embodiment 2.

[0030] Figure 23 This is an enlarged top view schematically illustrating the structure of the semiconductor device involved in Embodiment 3.

[0031] Figure 24 This is an enlarged top view schematically illustrating the structure of the semiconductor device involved in Embodiment 4.

[0032] Figure 25 This is an enlarged top view schematically illustrating the structure of the semiconductor device according to Embodiment 5.

[0033] Figure 26 This is a top view schematically illustrating the structure of the semiconductor device according to Embodiment 6.

[0034] Figure 27This is a top view schematically illustrating the structure of the semiconductor device according to Embodiment 7.

[0035] Figure 28 This is a top view schematically illustrating the structure of the semiconductor device according to Embodiment 8.

[0036] Figure 29 This is a top view schematically illustrating the structure of the semiconductor device according to Embodiment 9.

[0037] Explanation of reference numerals in the attached figures

[0038] 6...Emitter electrode; 41c...Gate pad; 50...Temperature sensing section; 51...Semiconductor substrate; 51a...Surface; 62...Cathode wiring; 62a...First sensing wiring section; 62b...Second sensing wiring section; 62c...Bend; 63...Connection section; 64...Anode wiring; 67...First lead joint; 73...Second lead joint; 75...Line segment; 76...Line portion; 78...Insulating film; 80a...Long side. Detailed Implementation

[0039] <Implementation Method 1>

[0040] In the following description, n and p represent the conductivity type of the semiconductor. In this disclosure, the first conductivity type is described as n-type and the second conductivity type as p-type, but it is also possible to describe the first conductivity type as p-type and the second conductivity type as n-type. Furthermore, n － This indicates that the impurity concentration is below n, where n is the concentration of impurities. + This indicates that the impurity concentration is higher than n. Similarly, p － This indicates that the impurity concentration is below p, where p + This indicates that the impurity concentration is higher than p.

[0041] Figure 1 This is a top view showing a semiconductor device including an RC-IGBT (Reverse Conducting IGBT). Additionally, Figure 2 This is a top view showing another structure of the semiconductor device including RC-IGBT according to Embodiment 1. Figure 1 The semiconductor device 100 shown arranges the IGBT region 10 and the diode region 20 in a striped pattern, which will sometimes be referred to simply as "striped" in the following description. Figure 2 In the semiconductor device 100 shown, multiple diode regions 20 are arranged in the vertical and horizontal directions, and IGBT regions 10 are arranged around the diode regions 20, which are sometimes referred to as "island type" in the following description.

[0042] <Striped Overall Planar Construction>

[0043] exist Figure 1 In the semiconductor device 100, an IGBT region 10 and a diode region 20 are included within the semiconductor device 100. The IGBT region 10 and the diode region 20 extend from one end of the semiconductor device 100 to the other end, and are alternately arranged in a stripe pattern in a direction orthogonal to the extending direction of the IGBT region 10 and the diode region 20. Figure 1 The diagram shows three IGBT regions 10 and two diode regions 20, with all diode regions 20 sandwiched between IGBT regions 10. However, the number of IGBT regions 10 and diode regions 20 is not limited to this; the number of IGBT regions 10 can be more than three or less, and the number of diode regions 20 can be more than two or less.

[0044] Alternatively, diode region 20 can be omitted entirely, and only IGBT region 10 can be provided. Alternatively, instead of an IGBT, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) can be used, eliminating the area that functions as the collector of IGBT region 10. Furthermore, the diode in diode region 20 can be a FWD (Free Wheeling Diode), SBD (Schottky Barrier Diode), or PND (PN junction diode). Alternatively, the diodes can be interchanged. Figure 1 The arrangement of the IGBT region 10 and the diode region 20 can be either a structure in which all the IGBT regions 10 are sandwiched between the diode regions 20, or a structure in which the IGBT regions 10 and the diode regions 20 are arranged one after another adjacent to each other.

[0045] like Figure 1As shown, a pad region 40 is disposed adjacent to the IGBT region 10 on the lower side of the paper. The pad region 40 is the region where electrode pads 41 for controlling the semiconductor device 100 are disposed. In the following description, the IGBT region 10 and the diode region 20 are sometimes referred to together as the cell region. A termination region 30 is disposed around the region formed by combining the cell region and the pad region 40 to maintain the withstand voltage of the semiconductor device 100. A known withstand voltage maintenance structure may also be disposed in the termination region 30. As a withstand voltage maintenance structure, for example, an FLR (Field Limiting Ring) surrounded by a p-type terminal well layer of p-type semiconductor and a VLD (Variation of Lateral Doping) surrounded by a p-type well layer with a concentration gradient are disposed on the first main surface side of the surface side of the semiconductor device 100. Furthermore, the number of annular p-type terminal well layers for the FLR and the concentration distribution for the VLD can be appropriately selected according to the withstand voltage design of the semiconductor device 100. Alternatively, a p-type terminal well layer can be set over approximately the entire area of ​​the pad region 40, or IGBT units and diode units can be set in the pad region 40.

[0046] Electrode pads 41 include, for example, at least one of current sensing pads 41a, Kelvin emitter pads 41b, gate pads 41c, and temperature sensing diode pads 41d and 41e. Furthermore, in this specification, for example, at least one of A, B, C, ..., and Z means any one of all combinations obtained by selecting more than one from the group of A, B, C, ..., and Z.

[0047] The current sensing pad 41a is an electrode pad used to detect the current flowing in the cell region of the semiconductor device 100. The current sensing pad 41a is electrically connected to a portion of the cell region such that when current flows in the cell region of the semiconductor device 100, a fraction to a few ten-thousandths of the current flowing in the entire cell region flows to the IGBT cell or diode cell in the portion of the cell region.

[0048] Kelvin emitter pad 41b and gate pad 41c are electrode pads for applying a gate drive voltage to control the on / off state of the semiconductor device 100. Kelvin emitter pad 41b is electrically connected to the p-type base layer of the IGBT cell. Gate pad 41c is electrically connected to the gate trench electrode of the IGBT cell. Kelvin emitter pad 41b and the p-type base layer can also be connected via p... +The temperature sensing diode pads 41d and 41e are electrode pads electrically connected to the anode and cathode of the temperature sensing unit 50, i.e., the temperature sensing diode, which is disposed in the semiconductor device 100. The voltage between the anode and cathode of the temperature sensing diode (not shown) disposed in the cell area is measured via the temperature sensing diode pads 41d and 41e, and the temperature of the semiconductor device 100 is measured based on this voltage.

[0049] <Island-shaped overall planar structure>

[0050] exist Figure 2 In this semiconductor device 100, an IGBT region 10 and a diode region 20 are included within the semiconductor device 100. Multiple diode regions 20 are arranged longitudinally and laterally within the semiconductor device 100, and each diode region 20 is surrounded by the IGBT region 10. That is, multiple diode regions 20 are arranged in an island-like configuration within the IGBT region 10. Figure 2 The diagram shows a matrix structure where the diode regions 20 are arranged in four columns along the left-right direction and two rows along the top-bottom direction. However, the number and arrangement of the diode regions 20 are not limited to this; any structure in which one or more diode regions 20 are distributed within the IGBT region 10, and each diode region 20 is surrounded by the IGBT region 10, is acceptable.

[0051] like Figure 2 As shown, a pad region 40 is disposed adjacent to the lower side of the IGBT region 10. The pad region 40 is the region where electrode pads 41 for controlling the semiconductor device 100 are disposed. In this description, the IGBT region 10 and the diode region 20 are also referred to collectively as the cell region. A termination region 30 is disposed around the region formed by the combined cell region and the pad region 40 to maintain the withstand voltage of the semiconductor device 100. A known withstand voltage holding structure may also be disposed in the termination region 30. As a withstand voltage holding structure, for example, an FLR (fluidic rectifier) ​​surrounded by a p-type terminal well layer of p-type semiconductor surrounding the region formed by the combined cell region and the pad region 40, and a VLD (voltage-dependent voltage limiter) surrounded by a p-type well layer with a concentration gradient are disposed on the first main surface side of the surface side of the semiconductor device 100. Furthermore, the number of annular p-type terminal well layers for the FLR and the concentration distribution for the VLD can be appropriately selected according to the withstand voltage design of the semiconductor device 100. Alternatively, a p-type terminal well layer can be set over approximately the entire area of ​​the pad region 40, or IGBT units and diode units can be set in the pad region 40.

[0052] Electrode pads 41 include, for example, at least one of current sensing pads 41a, Kelvin emitter pads 41b, gate pads 41c, and temperature sensing diode pads 41d and 41e.

[0053] The current sensing pad 41a is an electrode pad used to detect the current flowing in the cell region of the semiconductor device 100. The current sensing pad 41a is electrically connected to a portion of the cell region such that when current flows in the cell region of the semiconductor device 100, a fraction to a few ten-thousandths of the current flowing in the entire cell region flows to the IGBT cell or diode cell in the portion of the cell region.

[0054] Kelvin emitter pad 41b and gate pad 41c are electrode pads for applying a gate drive voltage to control the on / off state of the semiconductor device 100. Kelvin emitter pad 41b is connected to the p-type base layer and n-type base layer of the IGBT cell. + The source layer is electrically connected. Gate pad 41c is electrically connected to the gate trench electrode of the IGBT cell. Kelvin emitter pad 41b can also be connected to the p-type base layer via p... + The temperature sensing diode pads 41d and 41e are electrode pads electrically connected to the anode and cathode of the temperature sensing unit 50, i.e., the temperature sensing diode, which is disposed in the semiconductor device 100. The voltage between the anode and cathode of the temperature sensing diode (not shown) disposed in the cell area is measured via the temperature sensing diode pads 41d and 41e, and the temperature of the semiconductor device 100 is measured based on this voltage.

[0055] <IGBT Area 10>

[0056] Figure 3 This is a partially enlarged top view showing the structure of the IGBT region 10, which is an RC-IGBT semiconductor device. Specifically, Figure 3 It is Figure 1 as well as Figure 2 An enlarged view of the area enclosed by the dashed line 82 in the semiconductor device 100 shown.

[0057] in addition, Figure 4 as well as Figure 5 This is a cross-sectional view showing the structure of the IGBT region 10, which is a semiconductor device used in RC-IGBT. Specifically, Figure 4 yes Figure 3 The cross-sectional view of the semiconductor device 100 shown at the dotted line AA. Figure 5 It means Figure 3 A cross-sectional view of the semiconductor device 100 shown at the dotted line BB.

[0058] like Figure 3 As shown, an active trench gate 11 and a dummy trench gate 12 are arranged in a stripe pattern in the IGBT region 10. Figure 1In the semiconductor device 100, the active trench gate 11 and the dummy trench gate 12 extend along the long side direction of the IGBT region 10, and the long side direction of the IGBT region 10 corresponds to the long side direction of the active trench gate 11 and the dummy trench gate 12. On the other hand, in Figure 2 In the semiconductor device 100, the IGBT region 10 does not particularly distinguish between the long side direction and the short side direction. It can be either the left-right direction on the paper corresponding to the long side direction of the active trench gate 11 and the dummy trench gate 12, or the up-down direction on the paper corresponding to the long side direction of the active trench gate 11 and the dummy trench gate 12.

[0059] An active trench gate 11 is formed by depositing a gate trench electrode 11a within a trench in a semiconductor substrate via a gate trench insulating film 11b. A dummy trench gate 12 is formed by depositing a dummy trench electrode 12a within a trench in a semiconductor substrate via a dummy trench insulating film 12b. The gate trench electrode 11a of the active trench gate 11 and... Figure 1 as well as Figure 2 The gate pad 41c is electrically connected. The dummy trench electrode 12a of the dummy trench gate 12 is electrically connected to the emitter electrode disposed on the first main surface of the semiconductor device 100.

[0060] like Figure 3 As shown, n + The source layer 13 and the gate trench insulating film 11b are disposed on both sides of the active trench gate 11 in the width direction. According to the semiconductor device, n + Type source layer 13 is also called n + Type-n emitter layer. + The source layer 13 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, with an n-type impurity concentration of, for example, 1.0E+17 / cm³. 3 ~1.0E+20 / cm 3 n + The source layer 13 extends along the direction of the active trench gate 11, and is adjacent to the p-type source layer 13. + Type contact layers 14 are alternately arranged. Additionally, p... + The contact layer 14 and the dummy trench insulating film 12b are disposed between two adjacent dummy trench gates 12. + The p-type contact layer 14 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is, for example, 1.0E+15 / cm³. 3 ~1.0E+20 / cm 3 .

[0061] like Figure 3As shown, in the IGBT region 10 of the semiconductor device 100, three dummy trench gates 12 are arranged next to three active trench gates 11. Thus, a structure is configured such that three different active trench gates 11 are arranged next to the three dummy trench gates 12. The IGBT region 10 becomes a structure in which groups of active trench gates 11 and groups of dummy trench gates 12 are arranged alternately. Although in Figure 3 In this configuration, a group of active trench gates 11 may contain three active trench gates 11, but any group containing one or more is acceptable. Conversely, a group of dummy trench gates 12 may contain one or more dummy trench gates 12, or the number of dummy trench gates 12 may be zero. That is, all trench gates located in the IGBT region 10 may be active trench gates 11.

[0062] Figure 4 It is semiconductor device 100 Figure 3 The cross-sectional view at the dashed line AA is shown, and it is a cross-sectional view of the IGBT region 10. The semiconductor device 100 has an n-shaped structure made of a semiconductor substrate. － Type 1 drift layer. － The n-type drift layer 1 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, with an n-type impurity concentration of, for example, 1.0E+12 / cm³. 3 ~1.0E+15 / cm 3 Furthermore, the aforementioned n + The concentration ratio of n-type impurities in source layer 13 to n － The concentration of n-type impurities in drift layer 1 is high.

[0063] The range of semiconductor substrates is Figure 4 The middle is from n + Type source layer 13 and p + The range extends from the p-type contact layer 14 to the p-type collector layer 16. Depending on the semiconductor device, the p-type collector layer 16 is also referred to as the p-type drain layer. Figure 4 In the middle, n + Type source layer 13 and p + The upper end of the p-type contact layer 14 on the paper surface is referred to as the first main surface of the semiconductor substrate, and the lower end of the p-type collector layer 16 on the paper surface is referred to as the second main surface of the semiconductor substrate. The first main surface of the semiconductor substrate is the main surface on the surface side of the semiconductor device 100, and the second main surface of the semiconductor substrate is the main surface on the back side of the semiconductor device 100. In the IGBT region 10 of the cell region of the semiconductor device 100, there is an n-type contact layer between the first main surface and the second main surface on the opposite side of the first main surface. －Type drift layer 1. Furthermore, the semiconductor substrate may also be composed of at least one of, for example, a wafer and an epitaxial growth layer. Additionally, the semiconductor substrate may also include a wide-bandgap semiconductor (silicon carbide (SiC), gallium nitride (GaN), and diamond) capable of stable operation at high temperatures.

[0064] like Figure 4 As shown, in IGBT region 10, at n － The first principal surface of the drift layer 1 is provided with a concentration ratio of n-type impurities to n － The n-type carrier accumulation layer 2 has a high n-type drift layer 1. The n-type carrier accumulation layer 2 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, with an n-type impurity concentration of, for example, 1.0E+13 / cm³. 3 ~1.0E+17 / cm 3 Furthermore, the semiconductor device 100 may also omit the n-type carrier accumulation layer 2, and instead... Figure 4 The region of the n-type carrier accumulation layer 2 shown also has n － The structure of the n-type drift layer 1. By setting the n-type carrier accumulation layer 2, the current loss when current flows in the IGBT region 10 can be reduced. Alternatively, the n-type carrier accumulation layer 2 and n... － The drift layers 1 are collectively referred to as drift layers.

[0065] n-type carrier accumulation layer 2, through the formation of n － The semiconductor substrate of the type drift layer 1 is ion-implanted with n-type impurities, and then annealed to allow the implanted n-type impurities to function as n-type drift layers. － The drift layer 1 is formed by diffusion within the semiconductor substrate.

[0066] A p-type base layer 15 is disposed on the first main surface side of the n-type carrier accumulation layer 2. The p-type base layer 15 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is, for example, 1.0E+12 / cm³. 3 ~1.0E+19 / cm 3 The p-type base layer 15 is in contact with the gate trench insulating film 11b of the active trench gate 11. Figure 4 In the example, the p-type base layer 15 is also in contact with the dummy trench insulating film 12b of the dummy trench gate 12.

[0067] A region on a portion of the first main surface side of the p-type base layer 15 is provided with an n-type base that contacts the gate trench insulating film 11b of the active trench gate 11. + The source layer 13 is selectively provided with p-type base layer 15 in the remaining region on the first main surface side. + Type contact layer 14. + Type source layer 13 and p +The p-type contact layer 14 constitutes the first main surface of the semiconductor substrate. Furthermore, p... + The p-type contact layer 14 is a region where the concentration of p-type impurities is higher than that of the p-type base layer 15. This is necessary when it is necessary to distinguish between p-type and p-type impurities. + In the case of p-type contact layer 14 and p-type base layer 15, these two are referred to separately. When no distinction is needed, p-type base layer 15 can also be referred to as p-type base layer 15. + The p-type contact layer 14 and the p-type base layer 15 are collectively referred to as the p-type base layer.

[0068] Additionally, in the n of the semiconductor device 100 － The second main surface of the drift layer 1 is provided with a concentration ratio of n-type impurities to n － The n-type buffer layer 3 is a high-density n-type drift layer 1. The n-type buffer layer 3 is provided to suppress depletion layer punch-through extending from the p-type base layer 15 towards the second main surface when the semiconductor device 100 is in the off state. The n-type buffer layer 3 can be implanted with, for example, phosphorus (P) or protons (H). + It can be formed by injecting phosphorus (P) and protons (H). + This is formed by these two factors. The concentration of n-type impurities in the n-type buffer layer 3 is, for example, 1.0E+12 / cm³. 3 ~1.0E+18 / cm 3 Furthermore, the semiconductor device 100 may also be configured without the n-type buffer layer 3, but instead... Figure 4 The region of the n-type buffer layer 3 shown has n － The structure of type n drift layer 1. Alternatively, type n buffer layer 3 and type n... － The drift layers 1 are collectively referred to as drift layers.

[0069] A p-type collector layer 16 is provided on the second main surface side of the n-type buffer layer 3 of the semiconductor device 100. That is, the p-type collector layer 16 is provided on the n-type buffer layer 3. － Between the p-type drift layer 1 and the second main surface. The p-type collector layer 16 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is, for example, 1.0E+16 / cm³. 3 ~1.0E+20 / cm 3 The p-type collector layer 16 constitutes the second main surface of the semiconductor substrate. The p-type collector layer 16 may also be disposed not only in the IGBT region 10 but also in the termination region 30, as described later as a p-type termination collector layer 16a. Alternatively, the p-type collector layer 16 may be configured to extend a portion from the IGBT region 10 towards the diode region 20.

[0070] like Figure 4 As shown, a p-type base layer 15 extending from the first main surface of the semiconductor substrate and reaching the n-type base layer 15 is disposed in the IGBT region 10 of the semiconductor device 100. －The trenches of the drift layer 1 are formed. An active trench gate 11 is constructed by providing gate trench electrodes 11a within some trenches via a gate trench insulating film 11b. The gate trench electrodes 11a are connected to the n-type drift layer via the gate trench insulating film 11b. － The drift layer 1 is opposite to the type. Furthermore, a dummy trench gate 12 is formed by providing dummy trench electrodes 12a within some trenches via a dummy trench insulating film 12b. The dummy trench electrodes 12a are connected to n via the dummy trench insulating film 12b. － Type drift layer 1 is opposite.

[0071] The gate trench insulating film 11b of the active trench gate 11 and the p-type base layer 15 and n + The p-type source layer 13 is in contact. When a gate drive voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15 that is in contact with the gate trench insulating film 11b of the active trench gate 11.

[0072] like Figure 4 As shown, an interlayer insulating film 4 is disposed on the gate trench electrode 11a of the active trench gate 11. A barrier metal 5 is disposed on the region of the first main surface of the semiconductor substrate where the interlayer insulating film 4 is not disposed, and also on the interlayer insulating film 4. The barrier metal 5 can be, for example, a conductor containing titanium (Ti), specifically titanium nitride, or TiSi alloyed with titanium and silicon (Si). Figure 4 As shown, the blocking metal 5 and n + Type source layer 13, p + The contact layer 14 and the dummy trench electrode 12a make ohmic contact with n. + Type source layer 13, p + The contact layer 14 and the dummy trench electrode 12a are electrically connected. On the other hand, the blocking metal 5 is electrically insulated from the gate trench electrode 11a through the interlayer insulating film 4.

[0073] An emitter electrode 6 is disposed on top of the barrier metal 5. The emitter electrode 6 may be formed of an aluminum alloy, such as an aluminum-silicon alloy (Al-Si alloy), or it may be an electrode composed of a multilayer metal film on which a coating has been formed by chemical plating or electroplating on an electrode formed of an aluminum alloy. The coating formed by chemical plating or electroplating may be, for example, a nickel (Ni) coating. In cases where there are small regions, such as between adjacent interlayer insulating films 4, and where good embedment in the emitter electrode 6 cannot be obtained, a tungsten film with better embedment than the emitter electrode 6 may be disposed in the small regions, and the emitter electrode 6 may be disposed on this tungsten film. Alternatively, the barrier metal 5 may be omitted, and instead... + Type source layer 13, p +An emitter electrode 6 is disposed on the contact layer 14 and the dummy trench electrode 12a. Alternatively, an emitter electrode 6 may be disposed only on n. + A barrier metal 5 is disposed on top of an n-type semiconductor layer such as the source layer 13. The barrier metal 5 and the emitter electrode 6 can also be referred to together as the emitter electrode.

[0074] In addition, although Figure 4 The diagram shows a structure in which no interlayer insulating film 4 is disposed on the dummy trench electrode 12a of the dummy trench gate 12, but... Figure 4 In the cross-sectional portion, the interlayer insulating film 4 can also be disposed on the dummy trench electrode 12a of the dummy trench gate 12. Figure 4 In the cross-sectional portion, when the interlayer insulating film 4 is disposed on the dummy trench electrode 12a of the dummy trench gate 12, it is sufficient that the emitter electrode 6 is electrically connected to the dummy trench electrode 12a in other cross-sectional portions.

[0075] A collector electrode 7 is provided on the second main surface side of the p-type collector layer 16. The collector electrode 7 may also be constructed of aluminum alloy, or a multilayer of aluminum alloy and a coated film, similar to the emitter electrode 6. The collector electrode 7 may also have a different structure than the emitter electrode 6. The collector electrode 7 makes an ohmic contact with the p-type collector layer 16 and is electrically connected to it. Furthermore, by omitting the p-type collector layer 16, a MOSFET can be used instead of an IGBT.

[0076] Figure 5 It is semiconductor device 100 Figure 3 The cross-sectional view at the dotted line BB in the diagram, specifically the cross-sectional view of IGBT region 10. (And...) Figure 4 The cross-section at point AA shown is different. Figure 5 In the cross-sectional portion at the dotted line BB, n is not in contact with the active trench gate 11 and is disposed on the first main surface side of the semiconductor substrate. + Type source electrode layer 13. That is, Figure 3 The n shown + The source layer 13 is selectively disposed on the first main surface side of the p-type base layer. Furthermore, the p-type base layer mentioned herein may also include a p-type base layer 15 and a p-type base layer 16. + Type 14 contact layer.

[0077] <Diode Region 20>

[0078] Figure 6 This is a partially enlarged top view showing the structure of the diode region 20, which is a semiconductor device of an RC-IGBT. Specifically, Figure 6 It is Figure 1 as well as Figure 2A magnified view of the area enclosed by the dashed line 83 in the semiconductor device 100 shown.

[0079] in addition, Figure 7 as well as Figure 8 This is a cross-sectional view showing the structure of the diode region 20, which is a semiconductor device of an RC-IGBT. Specifically, Figure 7 yes Figure 6 The cross-sectional view of the semiconductor device 100 shown at the dotted line CC. Figure 8 yes Figure 6 A cross-sectional view of the semiconductor device 100 shown at the dotted line DD.

[0080] The diode trench gate 21 extends along the first main surface of the semiconductor device 100 from one end of the diode region 20 of the unit region toward the opposite end. The diode trench gate 21 is formed by providing a diode trench electrode 21a within the trench of the diode region 20 via a diode trench insulating film 21b. The diode trench electrode 21a is connected to the diode region 20 via the diode trench insulating film 21b. － Type drift layer 1 is opposite.

[0081] A p is provided between the gates 21 of two adjacent diode trenches. + The concentrations of type 24 contact layer and p-type impurities are lower than those of p-type impurities. + The p-type anode layer 25 of the p-type contact layer 24. + The p-type contact layer 24 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is, for example, 1.0E+15 / cm³. 3 ~1.0E+20 / cm 3 The p-type anode layer 25 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, with a p-type impurity concentration of, for example, 1.0E+12 / cm³. 3 ~1.0E+19 / cm 3 p + The p-type contact layer 24 and the p-type anode layer 25 are alternately disposed along the long side of the diode trench gate 21.

[0082] Figure 7 It is semiconductor device 100 Figure 6 The cross-sectional view at the dotted line CC is shown, and it is a cross-sectional view of the diode region 20. The semiconductor device 100, in the diode region 20, also has an n-shaped structure made of a semiconductor substrate, similar to the IGBT region 10. － Type drift layer 1. Diode region 20 n － n-type drift layer 1 and IGBT region 10 － The drift layer 1 is integrally formed continuously on the same semiconductor substrate.

[0083] The range of semiconductor substrates is Figure 7 The middle is from p + Type contact layer 24 to n + The range up to cathode layer 26. Figure 7 In the middle, p + The upper end of the contact layer 24 on the paper is called the first main surface of the semiconductor substrate, and n + The lower end of the cathode layer 26 is referred to as the second main surface of the semiconductor substrate. The first main surface of the diode region 20 and the first main surface of the IGBT region 10 are contained in the same surface, and the second main surface of the diode region 20 and the second main surface of the IGBT region 10 are contained in the same surface.

[0084] like Figure 7 As shown, in diode region 20, similarly to IGBT region 10, in n － An n-type carrier accumulation layer 2 is disposed on the first main surface side of the n-type drift layer 1. － An n-type buffer layer 3 is provided on the second main surface side of the n-type drift layer 1. The n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the diode region 20 have the same structure as the n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the IGBT region 10. Furthermore, it is not necessary to provide the n-type carrier accumulation layer 2 in both the IGBT region 10 and the diode region 20; for example, the n-type carrier accumulation layer 2 can be provided in the IGBT region 10 but not in the diode region 20. Alternatively, the n-type carrier accumulation layer 3 can be provided in the same manner as in the IGBT region 10. － The n-type drift layer 1, the n-type carrier accumulation layer 2, and the n-type buffer layer 3 are collectively referred to as the drift layer.

[0085] A p-type anode layer 25 is disposed on the first main surface side of the n-type carrier storage layer 2. The p-type anode layer 25 is disposed on the n-type carrier storage layer 2. － Between the p-type drift layer 1 and the first main surface. Alternatively, the concentration of p-type impurities in the p-type anode layer 25 can be set to be the same as the concentration of p-type impurities in the p-type base layer 15 of the IGBT region 10, thus simultaneously forming the p-type anode layer 25 and the p-type base layer 15. Alternatively, the concentration of p-type impurities in the p-type anode layer 25 can be configured to be lower than the concentration of p-type impurities in the p-type base layer 15 of the IGBT region 10, thereby reducing the amount of holes injected into the diode region 20 during diode operation. By reducing the amount of holes injected during diode operation, the recovery loss during diode operation can be reduced.

[0086] A p-type anode layer 25 is provided on the first main surface side. + Type contact layer 24. p + The concentration of p-type impurities in the contact layer 24 can be compared with that in the IGBT region 10. + The concentration of p-type impurities in the contact layer 14 can be the same or different.+ The contact layer 24 forms the first main surface of the semiconductor substrate. Furthermore, p... + The p-type contact layer 24 is a region where the concentration of p-type impurities is higher than that of the p-type anode layer 25, where it is necessary to distinguish between p-type and p-type impurities. + In the case of p-type contact layer 24 and p-type anode layer 25, these two can be referred to separately. If no distinction is needed, p-type anode layer 25 can also be referred to as p-type anode layer 25. + The p-type contact layer 24 and the p-type anode layer 25 are collectively referred to as the p-type anode layer.

[0087] An n-type buffer layer 3 is provided on the second main surface side of the semiconductor device 100. + Type 26 cathode layer. That is, n + Type 26 cathode layer is disposed in n － Between drift layer 1 and the second principal surface. + The cathode layer 26 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, with an n-type impurity concentration of, for example, 1.0E+16 / cm³. 3 ~1.0E+21 / cm 3 n + The cathode layer 26 is disposed in part or all of the diode region 20. + The cathode layer 26 forms the second main surface of the semiconductor substrate. Furthermore, although not shown, it can also be formed with an n-type cathode layer. + A portion of the region of the p-type cathode layer 26 is further selectively implanted with p-type impurities to form a p-type cathode layer as a p-type semiconductor.

[0088] like Figure 7 As shown, a p-type anode layer 25 extending from the first main surface of the semiconductor substrate and reaching the n-type diode region 20 of the semiconductor device 100 is provided. － The trench of the type drift layer 1. A diode trench electrode 21a is formed by providing a diode trench electrode 21a within the trench of the diode region 20 via a diode trench insulating film 21b, thereby constituting the diode trench gate 21. The diode trench electrode 21a is connected to the n-type drift layer 1 via the diode trench insulating film 21b. － Type drift layer 1 is opposite.

[0089] like Figure 7 As shown, in the diode trench electrode 21a and p + A barrier metal 5 is disposed on the contact layer 24. The barrier metal 5 is connected to the diode trench electrode 21a and p. + The contact layer has a 24-ohm contact with the diode trench electrode 21a and p. + The contact layer 24 is electrically connected. The barrier metal 5 can also have the same structure as the barrier metal 5 of the IGBT region 10.

[0090] An emitter electrode 6 is disposed on the barrier metal 5. The emitter electrode 6 disposed in the diode region 20 is continuously disposed on the emitter electrode 6 disposed in the IGBT region 10. Alternatively, similar to the case of the IGBT region 10, the barrier metal 5 may be omitted, and the diode trench electrode 21a and p may be disposed on the diode trench electrode 21a. + The contact layer 24 makes an ohmic contact with the emitter electrode 6.

[0091] In addition, although Figure 7 The diagram shows that no electrode is provided on the diode trench electrode 21a of the diode trench gate 21. Figure 4 That kind of interlayer insulating film 4 structure, but Figure 7 In the cross-sectional portion, the interlayer insulating film 4 can also be disposed on the diode trench electrode 21a. Figure 7 In the cross-sectional portion, when the interlayer insulating film 4 is disposed on the diode trench electrode 21a of the diode trench gate 21, it is sufficient that the emitter electrode 6 is electrically connected to the diode trench electrode 21a in other cross-sectional portions.

[0092] In n + A collector electrode 7 is disposed on the second main surface side of the cathode layer 26. Similar to the emitter electrode 6, the collector electrode 7 of the diode region 20 is continuously formed with the collector electrode 7 disposed in the IGBT region 10. The collector electrode 7 and n + The cathode layer has a 26-ohm contact, while the n-type cathode layer has a 26-ohm contact. + Type 26 cathode layer is electrically connected.

[0093] Figure 8 It is semiconductor device 100 Figure 6 The cross-sectional view at the dotted line DD in the diagram is a cross-sectional view of diode region 20. (And...) Figure 7 The cross-section at the dotted line CC shown is different. Figure 8 In the cross-sectional portion at the dotted line DD, no p-type anode layer 25 is provided between the p-type anode layer 25 and the barrier metal 5. + The p-type contact layer 24 and the p-type anode layer 25 form the first main surface of the semiconductor substrate. That is, Figure 7 p shown + The p-type contact layer 24 is selectively disposed on the first main surface side of the p-type anode layer 25.

[0094] <Structure of the boundary region between IGBT region 10 and diode region 20>

[0095] Figure 9 This is a cross-sectional view showing the structure of the boundary region between the IGBT region 10 and the diode region 20, which is an RC-IGBT semiconductor device. Specifically, Figure 9 yes Figure 1 as well as Figure 2 A cross-sectional view of the semiconductor device 100 shown at the dotted line EE.

[0096] like Figure 9 As shown, the p-type collector layer 16 disposed on the second main surface side of the IGBT region 10 and the n-type collector layer disposed on the second main surface side of the diode region 20 are... + The p-type cathode layer 26 is adjacent to each other in the in-plane direction of the semiconductor substrate. Moreover, the p-type collector layer 16 is configured to extend a distance U1 from the boundary between the IGBT region 10 and the diode region 20 toward the diode region 20.

[0097] In this way, by configuring the p-type collector layer 16 to extend into the diode region 20, the n-type collector of the diode region 20 can be increased. + The distance between the cathode layer 26 and the active trench gate 11. Therefore, even when a gate drive voltage is applied to the gate trench electrode 11a during freewheeling diode operation, current can be suppressed from flowing from the channel formed adjacent to the active trench gate 11 of the IGBT region 10 to the n + The cathode layer 26 flows. The distance U1 can be, for example, 100 μm. Furthermore, depending on its application as an RC-IGBT semiconductor device 100, the distance U1 can also be zero or less than 100 μm.

[0098] <Terminal Area 30>

[0099] Figure 10 as well as Figure 11 This is a cross-sectional view showing the structure of the terminal region 30 of the semiconductor device 100, which is an RC-IGBT. Specifically, Figure 10 yes Figure 1 as well as Figure 2 The cross-sectional view shown is located at the dotted line FF, and is a cross-sectional view from IGBT region 10 to terminal region 30. Additionally, Figure 11 yes Figure 1 The cross-sectional view shown is at the dotted line GG, and is a cross-sectional view from diode region 20 to terminal region 30.

[0100] like Figure 10 as well as Figure 11 As shown, the terminal region 30 of the semiconductor device 100 has n regions between the first main surface and the second main surface of the semiconductor substrate. － Type Drift Layer 1. The first and second main surfaces of the terminal region 30 are respectively contained in the same surface as the first and second main surfaces of the IGBT region 10 and the diode region 20. Additionally, the n-type of the terminal region 30... － Type-type drift layer 1 is the n-type drift layer of the IGBT region 10 and the diode region 20 respectively. － The drift layer 1 has the same structure and is integrally formed continuously.

[0101] In n － The first main surface of the drift layer 1, i.e., the first main surface of the semiconductor substrate and n － A p-type terminal well layer 31 is selectively disposed between the p-type drift layers 1. The p-type terminal well layer 31 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is, for example, 1.0E+14 / cm³. 3 ~1.0E+19 / cm 3 The p-type terminal well layer 31 is configured to surround the unit region including the IGBT region 10 and the diode region 20. The p-type terminal well layers 31 are arranged in multiple rings, and the number of p-type terminal well layers 31 is appropriately selected according to the voltage withstand design of the semiconductor device 100. Furthermore, n-type terminal well layers 31 are provided on the outermost edge of the p-type terminal well layer 31. + Type 32 channel truss layer, when viewed from above, n + The p-type terminal trap layer 31 is surrounded by the p-type channel cut-off layer 32.

[0102] In terminal region 30, n － A p-type terminal collector layer 16a is disposed between the p-type drift layer 1 and the second main surface of the semiconductor substrate. The p-type terminal collector layer 16a is integrally formed with the p-type collector layer 16 disposed in the IGBT region 10 of the cell region. Therefore, the p-type terminal collector layer 16a can also be included in the p-type collector layer 16 and referred to as the p-type collector layer.

[0103] In such Figure 1 In the structure of the semiconductor device 100 shown, where the diode region 20 and the terminal region 30 are arranged adjacent to each other, such as... Figure 11 As shown, the p-type terminal collector layer 16a is configured such that its end on the diode region 20 side extends a distance U2 into the diode region 20. With this structure, the n-axis of the diode region 20 can be increased. + The distance between the p-type cathode layer 26 and the p-type terminal well layer 31 can suppress the p-type terminal well layer 31 from acting as the anode of the diode. The distance U2 can also be, for example, 100 μm.

[0104] A collector electrode 7 is disposed on the second main surface of the semiconductor substrate. The collector electrode 7 is integrally formed continuously from the unit region including the IGBT region 10 and the diode region 20 to the terminal region 30.

[0105] On the other hand, an emitter electrode 6, continuous from the cell region, and a terminal electrode 6a, structurally separated from the emitter electrode 6, are disposed on the first main surface of the semiconductor substrate in the terminal region 30. The emitter electrode 6 and the terminal electrode 6a are electrically connected via a semi-insulating film 33. The semi-insulating film 33 may, for example, be sinSiN (semi-insulating silicon nitride). The terminal electrode 6a is connected to the p-type terminal well layer 31 and the n-type terminal well layer 32. + The channel cut-off layers 32 are electrically connected via contact holes in the interlayer insulating film 4 disposed on the first main surface of the terminal region 30. Additionally, a terminal protective film 34 covering the emitter electrode 6, the terminal electrode 6a, and the semi-insulating film 33 is disposed in the terminal region 30. The terminal protective film 34 is, for example, polyimide.

[0106] <Manufacturing Method of RC-IGBT>

[0107] Figure 12 (a)~ Figure 17 (b) is a cross-sectional view showing a method of manufacturing a semiconductor device as an RC-IGBT. Figure 12 (a)~ Figure 15 (b) indicates that the semiconductor device 100 is mainly formed. Figure 9 A diagram of the process on the surface side of the boundary region. Figure 16 (a), (b) and Figure 17 (a) and (b) represent the main components forming the semiconductor device 100. Figure 9 A diagram of the process on the back side of the boundary region.

[0108] First, such as Figure 12 As shown in (a), n is prepared to be constructed. － The semiconductor substrate is a type-drift layer 1. For the semiconductor substrate, for example, an FZ wafer fabricated by the FZ (Floating Zone) method, or an MCZ wafer fabricated by the MCZ (Magnetic-field-applied Czochralski) method, or an n-type wafer containing n-type impurities can be used. The concentration of n-type impurities contained in the semiconductor substrate is appropriately selected according to the breakdown voltage of the semiconductor device being fabricated. For example, in a semiconductor device with a breakdown voltage of 1200V, the concentration of n-type impurities is adjusted so that the n-type impurities constituting the semiconductor substrate... － The resistivity of drift layer 1 is approximately 40–120 Ω·cm. For example... Figure 12 As shown in (a), in the process of preparing the semiconductor substrate, the entire semiconductor substrate becomes n. －Type drift layer 1. P-type or n-type impurity ions are implanted from the first main surface side or the second main surface side of such a semiconductor substrate, and then diffused into the semiconductor substrate by heat treatment or the like, thereby appropriately forming a p-type or n-type semiconductor layer and manufacturing a semiconductor device 100.

[0109] like Figure 12 As shown in (a), n constitutes － The semiconductor substrate of the drift layer 1 has regions that serve as IGBT regions 10 and diode regions 20. Additionally, although not shown, regions such as termination regions 30 are provided around the regions that serve as IGBT regions 10 and diode regions 20. Hereinafter, the manufacturing method of the structure of the IGBT regions 10 and diode regions 20 of the semiconductor device 100 will be mainly described, but the termination regions 30 of the semiconductor device 100 can also be manufactured using known manufacturing methods. For example, when the termination region 30 is formed as a voltage withstand holding structure to form an FLR with a p-type termination well layer 31, p-type impurity ions can be implanted before processing the IGBT regions 10 and diode regions 20 of the semiconductor device 100 to form the FLR. Alternatively, p-type impurity ions can be implanted simultaneously with the implantation of p-type impurities into the IGBT regions 10 or diode regions 20 of the semiconductor device 100 to form the FLR.

[0110] Next, as Figure 12 As shown in (b), an n-type carrier accumulation layer 2 is formed by implanting n-type impurities such as phosphorus (P) from the first main surface of the semiconductor substrate. Additionally, a p-type base layer 15 and a p-type anode layer 25 are formed by implanting p-type impurities such as boron (B) from the first main surface of the semiconductor substrate. The n-type carrier accumulation layer 2, the p-type base layer 15, and the p-type anode layer 25 are formed by implanting impurity ions into the semiconductor substrate and then diffusing the impurity ions through heat treatment. Since the ion implantation of the n-type and p-type impurities is performed after masking on the first main surface of the semiconductor substrate, each layer is selectively formed on the surface side of the semiconductor substrate. The n-type carrier accumulation layer 2, the p-type base layer 15, and the p-type anode layer 25 are formed in the IGBT region 10 and the diode region 20, and are connected to the p-type terminal well layer 31 in the terminal region 30. Masking refers to the process of forming a mask on a semiconductor substrate by coating a resist onto the substrate, creating openings in designated areas of the resist using photolithography, and then performing ion implantation or etching into designated areas of the semiconductor substrate through these openings. Through the masking process and ion implantation described above, an n-type carrier accumulation layer 2, a p-type base layer 15, and a p-type anode layer 25 are selectively formed on the first main surface side of the IGBT region 10 and the diode region 20. Similarly, a p-type terminal well layer 31 is selectively formed in the terminal region 30.

[0111] P-type impurities in both the p-type base layer 15 and the p-type anode layer 25 can be simultaneously ion implanted. In this case, the depths and p-type impurity concentrations of the p-type base layer 15 and the p-type anode layer 25 are the same. Alternatively, p-type impurities in the p-type base layer 15 and the p-type anode layer 25 can be ion implanted separately using a mask, thereby making the depths and p-type impurity concentrations of the p-type base layer 15 and the p-type anode layer 25 different.

[0112] Figure 12 In (b) not shown, p-type impurities in the p-type terminal well layer 31 and p-type anode layer 25 of the terminal region 30 can also be simultaneously ion implanted. In this case, the depths and p-type impurity concentrations of the p-type terminal well layer 31 and p-type anode layer 25 are the same. Alternatively, p-type impurities in the p-type terminal well layer 31 and p-type anode layer 25 can be ion implanted separately using masking, thereby making the depths and p-type impurity concentrations of the p-type terminal well layer 31 and p-type anode layer 25 different. Alternatively, p-type impurities in the p-type terminal well layer 31 and p-type anode layer 25 can be ion implanted simultaneously using masks with different aperture ratios, thereby making the p-type impurity concentrations of the p-type terminal well layer 31 and p-type anode layer 25 different. In this case, it is sufficient to make one or both masks into mesh masks, thereby making the aperture ratios of the masks different. Similarly, by using masks with different aperture ratios, p-type impurities can be simultaneously ion-implanted into the p-type terminal well layer 31, the p-type base layer 15, and the p-type anode layer 25, resulting in different p-type impurity concentrations in these layers. The p-type terminal well layer 31, the p-type base layer 15, and the p-type anode layer 25 can also be formed by simultaneously ion-implanting p-type impurities.

[0113] Next, as Figure 13 As shown in (a), n-type impurities are selectively formed on the first main surface side of the p-type base layer 15 in the IGBT region 10 using masking and n-type impurity implantation. + The source layer 13. The implanted n-type impurity can also be, for example, arsenic (As) or phosphorus (P). Additionally, by using masking and p-type impurity implantation, p-type impurities are selectively formed on the first main surface side of the p-type base layer 15 in the IGBT region 10. + Type contact layer 14, selectively forming p on the first main surface side of p-type anode layer 25 in diode region 20. + Type contact layer 24. The implanted p-type impurities may also be, for example, boron (B) or aluminum (Al).

[0114] Next, as Figure 13 As shown in (b), a p-type base layer 15 and a p-type anode layer 25 are formed that penetrate from the first main surface side of the semiconductor substrate and reach the n-type anode layer. －The trench 8 of the drift layer 1. In the IGBT region 10, n... + The sidewalls of the trench 8 of the source layer 13 include n + Part of the source electrode layer 13. In the IGBT region 10, the p-type electrode is connected. + The sidewalls of the groove 8 of the contact layer 14 include p + Part of the contact layer 14. In the diode region 20, the p-type contact layer is penetrated. + The sidewalls of the groove 8 of the contact layer 24 include p + Part of the contact layer 24.

[0115] For example, trench 8 is formed by depositing an oxide film such as SiO2 on a semiconductor substrate, then using a mask to create openings in the portion of the oxide film where trench 8 is to be formed, and finally using the oxide film with the openings as a mask to etch the semiconductor substrate. Although in Figure 13 In (b), the spacing of the trenches 8 is made the same in the IGBT region 10 and the diode region 20, but it is also possible to make the spacing of the trenches 8 different in the IGBT region 10 and the diode region 20. The spacing of the trenches 8 and the pattern when viewed from above can be appropriately changed according to the mask pattern of the masking process.

[0116] Next, as Figure 14 As shown in (a), an oxide film 9 is formed on the inner wall of the trench 8 and on the first main surface of the semiconductor substrate by heating the semiconductor substrate in an oxygen-containing atmosphere. The oxide film 9 formed in the trench 8 of the IGBT region 10 is the gate trench insulating film 11b of the active trench gate 11 and the dummy trench insulating film 12b of the dummy trench gate 12. In addition, the oxide film 9 formed in the trench 8 of the diode region 20 is the diode trench insulating film 21b. The oxide film 9 formed on the first main surface of the semiconductor substrate, except for the portion formed in the trench 8, is removed in subsequent processes.

[0117] Next, as Figure 14 As shown in (b), polysilicon doped with n-type or p-type impurities is deposited in an oxide film 9 in a trench 8 using methods such as CVD (chemical vapor deposition) to form a gate trench electrode 11a, a dummy trench electrode 12a, and a diode trench electrode 21a.

[0118] Next, as Figure 15 As shown in (a), an interlayer insulating film 4 is formed on the gate trench electrode 11a of the active trench gate 11 in the IGBT region 10. The interlayer insulating film 4 can, for example, be SiO2. By using a mask process, contact holes are formed on the insulating film that has become the deposited interlayer insulating film 4, and the oxide film 9 formed on the first main surface of the semiconductor substrate is removed, thereby forming… Figure 15 (a) Interlayer insulating film 4, etc. The contact holes of interlayer insulating film 4 are formed at n + Above the source electrode layer 13, p + Above the contact layer 14, p + Above the contact layer 24, above the dummy trench electrode 12a, and above the diode trench electrode 21a.

[0119] Next, as Figure 15 As shown in (b), a barrier metal 5 is formed on the first main surface of the semiconductor substrate and on the interlayer insulating film 4, and an emitter electrode 6 is further formed on the barrier metal 5. The barrier metal 5 is formed by forming a titanium nitride film using PVD (physical vapor deposition) and CVD.

[0120] The emitter electrode 6 can be formed, for example, by depositing an aluminum-silicon alloy (Al-Si alloy) onto the barrier metal 5 using PVD methods such as sputtering or evaporation. Alternatively, a nickel alloy (Ni alloy) can be further formed on the already formed aluminum-silicon alloy using electroless plating or electroplating to serve as the emitter electrode 6. If the emitter electrode 6 is formed by plating, a thick metal film can be easily formed as the emitter electrode 6, thereby increasing the heat capacity of the emitter electrode 6 and improving its heat resistance. Furthermore, if the emitter electrode 6 made of aluminum-silicon alloy is formed by PVD, and then a nickel alloy is further formed on the emitter electrode 6 using a plating process, the plating process for forming the nickel alloy can be performed after processing the second main surface side of the semiconductor substrate.

[0121] Next, as Figure 16 As shown in (a), the second main surface of the semiconductor substrate is ground to thin the semiconductor substrate to a predetermined thickness. The thickness of the ground semiconductor substrate can be, for example, 80 μm to 200 μm.

[0122] Next, as Figure 16 As shown in (b), an n-type buffer layer 3 is formed by implanting an n-type impurity from the second main surface of the semiconductor substrate. Then, a p-type collector layer 16 is formed by implanting a p-type impurity from the second main surface of the semiconductor substrate. The n-type buffer layer 3 can be formed in the IGBT region 10, the diode region 20, and the termination region 30, or it can be formed only in the IGBT region 10 or the diode region 20. The n-type buffer layer 3 can be formed, for example, by implanting phosphorus (P) ions, or by implanting protons (H) ions. +It can also be formed by injecting protons or phosphorus. Protons can be injected into deeper locations from the second main surface of the semiconductor substrate with relatively low acceleration energy. In addition, the depth of proton injection can be easily changed by changing the acceleration energy. Therefore, when forming the n-type buffer layer 3 with protons, if multiple injections are performed while changing the acceleration energy, an n-type buffer layer 3 that is thicker in the thickness direction of the semiconductor substrate than the case formed with phosphorus can be formed.

[0123] Furthermore, since phosphorus can increase the activation rate of n-type impurities compared to protons, if an n-type buffer layer 3 is formed from phosphorus, even in a thinned semiconductor substrate, the penetration of the depletion layer can be suppressed. To achieve further thinning of the semiconductor substrate, it is preferable to form the n-type buffer layer 3 by implanting both protons and phosphorus, in which case the protons are implanted from the second main surface to a depth greater than that of the phosphorus.

[0124] The p-type collector layer 16 can also be formed by implanting boron (B). The p-type collector layer 16 is also formed in the terminal region 30, and the p-type collector layer 16 in the terminal region 30 becomes the p-type terminal collector layer 16a. After ion implantation from the second main surface of the semiconductor substrate, laser annealing is performed by irradiating the second main surface with a laser, thereby activating the implanted boron and forming the p-type collector layer 16. At this time, phosphorus implanted from the second main surface of the semiconductor substrate to a relatively shallow position is also activated simultaneously. On the other hand, since protons are activated at a relatively low annealing temperature of 350°C to 500°C, after proton implantation, in addition to the proton activation process, it is necessary to ensure that the overall temperature of the semiconductor substrate does not exceed 350°C to 500°C. Since laser annealing can only make the area near the second main surface of the semiconductor substrate reach a high temperature, it can be used for the activation of n-type and p-type impurities even after proton implantation.

[0125] Next, as Figure 17 As shown in (a), n is formed on the second main surface side of diode region 20. + Type 26 cathode layer. + The cathode layer 26 can also be formed by implanting arsenic (As) or phosphorus (P), for example. Figure 17 As shown in (a), n-type impurities are selectively implanted from the second main surface side using a masking process, so that the p-type collector layer 16 and the n + The boundary of the cathode layer 26 is located at a separation distance U1 from the boundary between the IGBT region 10 and the diode region 20 towards the diode region 20. This is used to form n + The amount of n-type impurities implanted in the p-type cathode layer 26 is greater than the amount of p-type impurities implanted to form the p-type collector layer 16. Although in Figure 17 In (a), the p-type collector layer 16 and n +The depth of the cathode layer 26 from the second main surface is shown to be the same, but n + The depth of the p-type cathode layer 26 is above the depth of the p-type collector layer 16. In the formation of the n-type cathode layer... + In the region of the p-type cathode layer 26, n-type impurities need to be implanted into the region where p-type impurities were implanted to eventually become n-type. Therefore, the concentration of n-type impurities is higher than that in the region where n-type impurities are formed. + The concentration of p-type impurities injected into the entire region of the cathode layer 26.

[0126] Next, as Figure 17 As shown in (b), a collector electrode 7 is formed on the second main surface of the semiconductor substrate. The collector electrode 7 is formed over the entire surface of the second main surface, including the IGBT region 10, the diode region 20, and the terminal region 30. Alternatively, the collector electrode 7 may be formed over the entire surface of the second main surface of the n-type wafer, which is the semiconductor substrate. The collector electrode 7 can be formed by PVD deposition of aluminum-silicon alloy (Ai-Si alloy), titanium (Ti), etc., such as by sputtering or evaporation, or by stacking multiple metals such as aluminum-silicon alloy, titanium, nickel, or gold. Alternatively, the collector electrode 7 can be formed by further forming a metal film on a metal film formed by PVD through chemical plating or electroplating.

[0127] The semiconductor device 100 is manufactured through the above-described process. Multiple semiconductor devices 100 are integrated in a matrix on a single n-type wafer or other semiconductor substrate. Therefore, the semiconductor device 100 is individually divided using laser cutting or blade cutting.

[0128] <Temperature Sensing Unit 50>

[0129] Figure 18 This is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 1. The semiconductor device according to Embodiment 1 not only includes the RC-IGBT described above, but also, as a polysilicon element, includes... Figure 2 , Figure 3 as well as Figure 18 The temperature sensing unit 50 shown.

[0130] like Figure 18 As shown, the semiconductor device according to Embodiment 1 includes a temperature sensing unit 50, a semiconductor substrate 51, a lower insulating film 52, an upper insulating film 54, a cathode electrode 55, and an anode electrode 56.

[0131] The semiconductor substrate 51 is the aforementioned semiconductor substrate, having a surface 51a as its first main surface. A temperature sensing unit 50 is disposed on the surface 51a of the semiconductor substrate 51, excluding the main current-carrying area such as the IGBT region 10, via a lower insulating film 52, on a region other than the main current-carrying area. The temperature sensing unit 50 includes n +Type cathode regions 53a, p + Type anode region 53b and p － Type-dependent drift region 53c. + Type cathode regions 53a, p + Type anode region 53b and p － The drift region 53c is disposed on the lower insulating film 52.

[0132] n + Impurities in cathode region 53a can also be combined with Figure 9 n + The impurities in source layer 13 are the same. Additionally, p... + Impurities in the anode region 53b can also be... Figure 9 p + The impurities in contact layer 14 are the same. － Type drift region 53c is set at n + Type cathode regions 53a and p + Between type anode region 53b, p － The impurity concentration in the drift region 53c is lower than that in p. + Impurity concentration in anode region 53b.

[0133] The upper insulating film 54 covers the upper part and sides of the temperature sensing part 50, and has exposed n + Contact holes and exposed p in cathode region 53a + The contact hole in the anode region 53b. Furthermore, the lower insulating film 52 and the upper insulating film 54 can also be thermally oxidized films.

[0134] Cathode electrode 55 exposed n + The contact hole in cathode region 53a is connected to n + The cathode region 53a is electrically connected. The anode electrode 56 is exposed at p. + The contact hole in type anode region 53b is connected to p + The anode region 53b is electrically connected. The temperature sensing unit 50 described above functions as a temperature sensing diode.

[0135] In addition, although Figure 18 In the middle, n during sectional observation + The width of the cathode region 53a, i.e., its length in the in-plane direction, varies relative to the direction from the back side of the semiconductor substrate 51 toward the surface 51a, i.e., the upward direction, but is not limited thereto. Furthermore, although in Figure 18 In the example, n during sectional observation + The width of the cathode region 53a increases monotonically and continuously relative to the upward direction, but it can also vary in a step-like manner relative to the upward direction. (n during cross-sectional observation) +In a structure in which the width of the cathode region 53a varies relative to the direction from the back side of the semiconductor substrate 51 toward the surface 51a, the junction area of ​​the pn junction can be increased.

[0136] <Wiring of the temperature sensing unit>

[0137] Figure 19 This is a top view (top view) schematically showing the structure of the semiconductor device according to Embodiment 1. Figure 19 It is a schematic representation in Figure 2 as well as Figure 3 The diagram showing the structure in detail, Figure 19 Structure and Figure 2 as well as Figure 3 The structure is slightly different. Furthermore, in Figure 19 In the diagram, the shaded areas represent effective areas such as unit areas.

[0138] like Figure 19 As shown, selectively disposed on the surface of semiconductor substrate 51 are... Figure 4 The emitter electrode 6 is shown in the figure. In this embodiment 1, approximately one emitter electrode 6 is provided on each side of the semiconductor substrate 51. Furthermore, although in Figure 19 Not shown in the diagram, but multiple second lead connections are provided on the emitter electrode 6, which are connected to multiple leads for the emission current (i.e., the main current flowing through the IGBT channel and the emitter electrode 6). This structure increases the area of ​​the path through which the emission current flows.

[0139] The temperature sensing unit 50 is disposed adjacent to the emitter electrode 6 on the surface of the semiconductor substrate 51. In this embodiment 1, when viewed from above, the temperature sensing unit 50 is disposed at a position inside the end of the semiconductor substrate 51 and between the left and right emitter electrodes 6.

[0140] The shape of the emitter electrode 6 includes a protrusion 61b that protrudes from the main body portion 61a of the emitter electrode 6 toward the outside of the emitter electrode 6 when viewed from above. In this embodiment 1, the protrusion 61b is provided at the end of the semiconductor substrate 51 (i.e., the end region 30) when viewed from above, and protrudes in a direction opposite to the Y direction (the first direction).

[0141] A cathode wire 62, serving as a sensing wire, is disposed along the emitter electrode 6. One end of the cathode wire 62 is connected to the temperature sensing unit 50, and the other end of the cathode wire 62 is connected to the emitter electrode 6 (protrusion 61b). With this structure, a portion of the emitter electrode 6 can be used as a sensing wire. Figure 2 as well as Figure 3The electrode pad 41 is a cathode pad, so not only can the area required for the cathode pad be eliminated, but also the reduction of invalid areas and the improvement of assembly performance can be expected.

[0142] In this embodiment 1, the cathode wiring 62 includes a first sensing wiring portion 62a, a second sensing wiring portion 62b, and a bend portion 62c. When viewed from above, the first sensing wiring portion 62a extends from the inside of the semiconductor substrate 51 between the left and right emitter electrodes 6 in a direction opposite to the Y direction (a first direction) to its terminal. At the terminal of the semiconductor substrate 51, the second sensing wiring portion 62b extends from the first sensing wiring portion 62a to the connection portion 63 between the emitter electrode 6 and the cathode wiring 62 in an X direction (a second direction) different from the extending direction (a first direction) of the first sensing wiring portion 62a. The bend portion 62c is the portion between the first sensing wiring portion 62a and the second sensing wiring portion 62b.

[0143] Like the cathode wiring 62, the anode wiring 64 is disposed adjacent to the emitter electrode 6. One end of the anode wiring 64 is connected to the temperature sensing unit 50, and the other end of the anode wiring 64 is connected to the emitter electrode 6. Figure 2 as well as Figure 3 An anode pad 65 is connected to one of the electrode pads 41. A lead joint 66 (not shown) is provided on the anode pad 65 to connect to a lead (not shown) that reads the anode potential of the temperature sensing unit 50.

[0144] Furthermore, although in this embodiment 1, an anode wire 64, which is a type of wire with a different potential than the cathode wire 62, is provided in the region between the left and right emitter electrodes 6 where the first sensing wire portion 62a is provided, this is not a limitation. In this region, a wire with a different potential than the cathode wire 62, i.e., a wire with another potential, such as a gate wire, may also be provided. Additionally, in the region from the first sensing wire portion 62a to the connection portion 63 where the second sensing wire portion 62b is provided, a wire with a different potential than the cathode wire 62, i.e., a wire with another potential, such as a gate wire, may also be provided.

[0145] On the emitter electrode 6, a first lead joint 67 is provided adjacent to the connection portion 63 between the emitter electrode 6 (protrusion 61b) and the cathode wiring 62, and is connected to a lead (not shown) that reads the cathode potential of the temperature sensing unit 50. In this embodiment 1, the distance from the connection portion 63 to the first lead joint 67 is shorter than the distance from the bend portion 62c to the connection portion 63.

[0146] Separated from emitter electrode 6 Figure 2 as well as Figure 3The gate pad 41c is disposed on the side opposite to the cathode wiring 62, opposite to the connection portion 63. A lead joint portion 69 (not shown) is provided on the gate pad 41c for supplying gate drive voltage to the gate trench electrode 11a. Furthermore, as... Figure 2 as well as Figure 3 The electrode pads can also be provided with electrode pads other than the emitter electrode 6, anode pad 65, and gate pad 41c, which are used as cathode pads.

[0147] Figure 20 This is a top view schematically illustrating the structure of related devices associated with the semiconductor device according to Embodiment 1, and is related to... Figure 19 The corresponding top view. In Figure 20 In the relevant device, no protrusion 61b is provided on the emitter electrode 6. Therefore, Figure 20 The distance between the cathode wiring 62 and the connection portion 70 of the emitter electrode 6 and the first lead junction portion 67 is... Figure 19 The distance between the connecting portion 63 and the first lead junction 67 is long. In such a structure, the cathode potential of the temperature sensing unit 50 read from the lead of the first lead junction 67 is strongly affected by the emitter current flowing in the emitter electrode 6, so the cathode potential of the temperature sensing unit 50 cannot be accurately measured.

[0148] In contrast, in this embodiment 1, the distance from the connecting portion 63 to the first lead joint 67 is shorter than the distance from the bending portion 62c to the connecting portion 63. With this structure, the influence of the emitter current flowing in the emitter electrode 6 on the cathode potential of the temperature sensing unit 50 read from the lead of the first lead joint 67 can be reduced, thus enabling accurate measurement of the cathode potential of the temperature sensing unit 50.

[0149] Furthermore, in this embodiment 1, the gate pad 41c, which is separate from the emitter electrode 6, is disposed on the side opposite to the cathode wiring 62 relative to the connection portion 63. With this structure, emitter current flowing in the emitter electrode 6 in the region opposite to the cathode wiring 62 relative to the connection portion 63 can be suppressed. Therefore, the influence of the emitter current flowing in the emitter electrode 6 on the cathode potential of the temperature sensing unit 50 read from the lead of the first lead junction 67 can be further reduced, thus enabling more accurate measurement of the cathode potential of the temperature sensing unit 50.

[0150] Furthermore, although the emitter electrode 6 includes a protrusion 61b in the above description, as... Figure 21 Therefore, the emitter electrode 6 may not include the protrusion 61b. This is also true in Embodiment 2 and subsequent embodiments.

[0151] <Implementation Method 2>

[0152] Figure 22 This is a top view schematically illustrating the structure of the semiconductor device according to Embodiment 2, and is related to... Figure 19 The corresponding top view.

[0153] In Embodiment 1, the protrusion 61b protrudes in a direction opposite to the Y direction (first direction). In contrast, in Embodiment 2, the protrusion 61b protrudes in the X direction (second direction).

[0154] Furthermore, in Embodiment 1, the cathode wiring 62 extends in the direction opposite to the Y direction (first direction) and extends in the X direction (second direction) by bending midway. In contrast, in this Embodiment 2, the cathode wiring 62 does not bend midway, but extends from the inside of the semiconductor substrate 51 to the terminal protrusion 61b in the direction opposite to the Y direction (first direction) when viewed from above. Additionally, in this Embodiment 2, the distance from the connection portion 63 to the first lead junction portion 67 is shorter than the distance from the temperature sensing portion 50 to the connection portion 63. According to this Embodiment 2, similar to Embodiment 1, the cathode potential of the temperature sensing portion 50 can be accurately measured.

[0155] Furthermore, although in this embodiment 2, an anode wiring 64, which is a type of wiring with a different potential than the cathode wiring 62, is provided in the region between the left and right emitter electrodes 6 where the cathode wiring 62 is provided, this is not a limitation. In this region, wiring with a different potential than the cathode wiring 62, i.e., wiring with other potentials, such as gate wiring, may also be provided. Additionally, the cathode wiring 62 may be slightly bent as long as it extends from the inside of the semiconductor substrate 51 to the terminal emitter electrode 6 in a direction opposite to the Y direction (the first direction) when viewed from above.

[0156] <Implementation Method 3>

[0157] Figure 23 This is an enlarged top view schematically illustrating the structure of the semiconductor device according to Embodiment 3, and it is a view showing... Figure 19 An enlarged top view of the periphery of the connecting part 63. Furthermore, in Figure 23 The diagram shows a plurality of second lead joints 73 connected to leads (not shown) for the flow of emitter current. The plurality of second lead joints 73 are disposed on the side opposite to the first lead joint 67 on the emitter electrode 6.

[0158] In this embodiment 3, as Figure 23As shown by the dashed lines, the cathode wiring 62, the connecting portion 63, and the emitter electrode 6, when viewed from above, have an overall U-shape. An insulating component is provided in the slit-like portion 72 within the U-shape, and no gate electrode or other electrodes are present. With this structure, the area of ​​the emitter electrode 6 can be maximized. This effect can be improved by making the slit-like portion 72 as thin as possible. Furthermore, here, although for... Figure 19 The structure of Implementation 1 applies Implementation 3, but it can also be modified. Figure 22 The structure of implementation method 2 is applied to implementation method 3.

[0159] <Implementation Method 4>

[0160] Figure 24 This is an enlarged top view schematically illustrating the structure of the semiconductor device according to Embodiment 4, and is related to... Figure 23 The corresponding enlarged top view.

[0161] In this embodiment 4, the line segment 75 between the connecting portion 63 and the first lead bonding portion 67 on the semiconductor substrate 51 is used as the diagonal. Figure 24 The area within the quadrilateral shown by the dashed line is where active cells are located. An active cell, for example, corresponds to a portion of IGBT region 10.

[0162] The emitter current flowing in the active cell flows toward a plurality of leads (a plurality of main emitter wirings) not shown, which are connected by the emitter electrode 6 and a plurality of second lead junctions 73. At this time, within the quadrilateral in which the active cell is located, the cathode potential of the temperature sensing unit 50, which is read from the lead of the first lead junction 67, is strongly affected by the emitter current flowing in the emitter electrode 6.

[0163] Therefore, in this embodiment 4, the distance between the connecting portion 63 and the first lead junction 67 is shortened in such a way that ΔV = Is × ρ × L < 0.7 × N, thereby reducing the aforementioned effects. In the above formula, L is the length of the diagonal line segment 75, Is is the current density in the cross-sectional direction flowing between the connecting portion 63 and the first lead junction 67, ρ is the specific resistance of the emitter electrode 6, N is the number of diodes connected in series in the temperature sensing unit 50, and ΔV is the voltage between the connecting portion 63 and the first lead junction 67.

[0164] The 0.7 in the above formula represents the built-in potential of silicon. The temperature of the temperature sensing unit 50 is measured based on the difference between the built-in potentials of the temperature sensing unit 50 before and after a temperature change. In order to perform such a measurement, in this embodiment 4, the voltage ΔV is adjusted to a value within the built-in potential using the above formula. When the number of diodes included in the temperature sensing unit 50 is N, in this embodiment 4, the voltage ΔV is adjusted to a value within the sum of the built-in potentials corresponding to the number of diodes using the above formula. In this embodiment 4, such adjustment is achieved using the above formula, thus enabling appropriate measurement of the temperature of the temperature sensing unit 50.

[0165] Furthermore, although in this embodiment 4 the metal of the emitter electrode 6 is aluminum and the specific resistance ρ of the emitter electrode 6 is the specific resistance of aluminum, the specific resistance ρ can be changed according to the metal used in the emitter electrode 6.

[0166] <Implementation Method 5>

[0167] Figure 25 This is an enlarged top view schematically illustrating the structure of the semiconductor device according to Embodiment 5, and is related to... Figure 22 The corresponding enlarged top view.

[0168] exist Figure 25 The diagram shows a line portion 76 in a straight line from the second lead junction 73 through the first lead junction 67 to the end of the emitter electrode 6. In this embodiment 5, an active cell is provided on a semiconductor substrate within a generally triangular region surrounded by the line portion 76 and the end of the emitter electrode 6. Within this quadrilateral where the active cell is provided, similar to embodiment 4, the cathode potential of the temperature sensing unit 50 read from the lead of the first lead junction 67 is strongly influenced by the emitter current flowing in the emitter electrode 6.

[0169] Therefore, in this embodiment 5, the distance between the connecting portion 63 and the first lead junction portion 67 is shortened such that ΔV = Is × ρ × L < 0.7 × N, thereby reducing the aforementioned effects. In the above formula, L is the length of the line portion 76. Other than this, Is, ρ, N, and ΔV are the same as in embodiment 4. With this structure, since the voltage ΔV is adjusted to a value within the sum of the built-in potentials corresponding to the number of diodes included in the temperature sensing unit 50, the temperature of the temperature sensing unit 50 can be appropriately measured.

[0170] <Modifications of Implementation Methods 4 and 5>

[0171] The voltage ΔV can also be less than 50% of the upper and lower limits of the standard voltage of the temperature sensing unit 50. For example, when the upper and lower limits of the standard voltage of the temperature sensing unit 50 are 1.8V and 2.2V, respectively, the voltage ΔV can be 0.2V (=0.4V×50%). In such a structure, the temperature measurement accuracy of the temperature sensing unit 50 can be improved compared to a structure where the voltage ΔV exceeds 50% of the aforementioned amplitude of the temperature sensing unit 50. Furthermore, in a structure where the voltage ΔV is less than 30% of the aforementioned amplitude of the temperature sensing unit 50, the temperature measurement accuracy of the temperature sensing unit 50 can be improved compared to a structure where the voltage ΔV exceeds 30% of the aforementioned amplitude of the temperature sensing unit 50. Additionally, in a structure where the voltage ΔV is less than 10% of the aforementioned amplitude of the temperature sensing unit 50, the temperature measurement accuracy of the temperature sensing unit 50 can be improved compared to a structure where the voltage ΔV exceeds 10% of the aforementioned amplitude of the temperature sensing unit 50. Furthermore, in a structure where the voltage ΔV is less than 1% of the aforementioned amplitude of the temperature sensing unit 50, the accuracy of temperature measurement of the temperature sensing unit 50 can be improved compared to a structure where the voltage ΔV exceeds 1% of the aforementioned amplitude of the temperature sensing unit 50.

[0172] <Implementation Method 6>

[0173] Figure 26 This is a top view schematically illustrating the structure of the semiconductor device according to Embodiment 6, and is related to... Figure 19 The corresponding top view.

[0174] In this embodiment 6, an insulating film 78 is provided to cover the emitter electrode 6 and the surface 51a of the semiconductor substrate 51. Furthermore, in Figure 26 In the image, the emitter electrode 6, which is covered by the insulating film 78, is shown by a dashed line.

[0175] The insulating film 78 has openings 78a, 78b, 78c, and 78d. Opening 78a exposes... Figure 23 as well as Figure 24 The second lead joint 73 is shown in the figure. Opening 78b exposes the first lead joint 67. Opening 78c exposes the lead joint 66 of the anode pad 65. Opening 78d exposes the lead joint 69 of the gate pad 41c. With this structure, the insulating film 78 can be used to mitigate the effects of external factors.

[0176] Furthermore, the insulating film 78 can expose the first lead junction 67 while covering at least a portion of the emitter electrode 6 and surface 51a, excluding the area between the first lead junction 67 and the end (i.e., terminal) of the semiconductor substrate 51. With this structure, the first lead junction 67 can be moved away from the second lead junction 73 in accordance with the provision of the insulating film 78. Therefore, the influence of the emitter current flowing in the emitter electrode 6 on the cathode potential of the temperature sensing section 50 read from the lead of the first lead junction 67 can be reduced.

[0177] <Implementation Method 7>

[0178] Figure 27 This is a top view schematically illustrating the structure of the semiconductor device according to Embodiment 7, and is related to... Figure 19 The corresponding top view. Furthermore, although in Figure 27 The insulating film 78 described in Embodiment 6 is provided, but it is not necessary in this Embodiment 7.

[0179] In this embodiment 7, the region in the semiconductor substrate 51 where the first lead junction 67 is located is not dotted and becomes an ineffective region of the p-type terminal well layer 31, etc. With this structure, the influence of the emitter current flowing in the emitter electrode 6 on the cathode potential of the temperature sensing unit 50 read from the lead of the first lead junction 67 can be reduced.

[0180] <Implementation Method 8>

[0181] Figure 28 This is a top view schematically illustrating the structure of the semiconductor device according to Embodiment 8, and is related to... Figure 19 The corresponding top view. Furthermore, although in Figure 28 The insulating film 78 described in Embodiment 6 is provided, but it is not necessary in this Embodiment 8. Furthermore, although in Figure 28 Similar to Embodiment 7, the region in the semiconductor substrate 51 where the first lead bonding portion 67 is provided becomes an invalid region, but this is not necessary in this Embodiment 8.

[0182] In this embodiment 8, the anode wiring 64, when viewed from above, overlaps at least a portion of the cathode wiring 62. For example, in Figure 28 The overlapping portion 79, with the other one disposed above one of the cathode wiring 62 and the anode wiring 64 through an insulating film, the cathode wiring 62 and the anode wiring 64 being insulated from each other. Figure 28 The cathode wiring 62 and anode wiring 64 overlap in the Z direction. With this structure, the area of ​​the cathode wiring 62 and anode wiring 64 when viewed from above can be reduced, thus increasing the area of ​​active units, for example.

[0183] <Implementation Method 9>

[0184] Figure 29 This is a top view schematically illustrating the structure of the semiconductor device according to Embodiment 9, and is related to... Figure 19 The corresponding top view. Furthermore, although in Figure 29 The insulating film 78 described in Embodiment 6 is provided, but it is not necessary in this Embodiment 9.

[0185] In this embodiment 9, the semiconductor substrate 51 is rectangular when viewed from above, with its long side 80a extending along the X direction and its short side 80b extending along the Y direction. Furthermore, a first lead bonding portion 67 is provided on the long side 80a side of the semiconductor substrate 51. With this structure, compared to a structure where the first lead bonding portion 67 is provided on the short side 80b side of the semiconductor substrate 51, the lengths of the cathode wiring 62 and the anode wiring 64 can be shortened, thus increasing the area of, for example, active cells.

[0186] Furthermore, in this disclosure written in English, 'a' and 'an' mean more than one. Therefore, 'a', 'an', 'one or more', and 'at least one' can be used with the same meaning.

[0187] Furthermore, the various embodiments and variations can be freely combined, or appropriately modified, or the various embodiments and variations can be omitted.

[0188] The various forms disclosed herein will be recorded hereafter as appendices.

[0189] (Note 1) A semiconductor device, wherein,

[0190] The aforementioned semiconductor device includes:

[0191] A semiconductor substrate having a first main surface;

[0192] The emitter electrode is selectively disposed on the first main surface mentioned above;

[0193] The temperature sensing unit, when viewed from above, is disposed adjacent to the emitter electrode on the first main surface at a position closer to the end of the semiconductor substrate.

[0194] The sensing wiring has one end connected to the temperature sensing unit and the other end connected to the emitter electrode at the terminal of the semiconductor substrate, and is disposed along the emitter electrode; and

[0195] The first lead junction and the connection portion between the emitter electrode and the sensing wiring are disposed adjacent to the emitter electrode.

[0196] The aforementioned sensing wiring includes:

[0197] The first sensing wiring section, when viewed from above, extends from the inner side of the semiconductor substrate in the first direction to the terminal.

[0198] The second sensing wiring portion extends from the first sensing wiring portion to the connection portion at the aforementioned terminal along a second direction different from the first direction of the first sensing wiring portion; and

[0199] The curved portion is located between the first sensing wiring portion and the second sensing wiring portion.

[0200] The distance from the connecting portion to the first lead joint is shorter than the distance from the bend to the connecting portion.

[0201] (Note 2) A semiconductor device, wherein,

[0202] The aforementioned semiconductor device includes:

[0203] A semiconductor substrate having a first main surface;

[0204] The emitter electrode is selectively disposed on the first main surface mentioned above;

[0205] The temperature sensing unit, when viewed from above, is disposed adjacent to the emitter electrode on the first main surface at a position closer to the end of the semiconductor substrate.

[0206] The sensing wiring has one end connected to the temperature sensing unit and the other end connected to the emitter electrode at the terminal of the semiconductor substrate, and is disposed along the emitter electrode; and

[0207] The first lead junction and the connection portion between the emitter electrode and the sensing wiring are disposed adjacent to the emitter electrode.

[0208] When viewed from above, the aforementioned sensing wiring extends from the inner side of the aforementioned semiconductor substrate in the first direction to the aforementioned terminal.

[0209] The distance from the aforementioned connecting portion to the aforementioned first lead joint is shorter than the distance from the aforementioned temperature sensing portion to the aforementioned connecting portion.

[0210] (Note 3) A semiconductor device, wherein,

[0211] The aforementioned semiconductor device includes:

[0212] A semiconductor substrate having a first main surface;

[0213] The emitter electrode is selectively disposed on the first main surface mentioned above;

[0214] A temperature sensing unit is disposed adjacent to the emitter electrode on the first main surface.

[0215] The sensing wiring has one end connected to the temperature sensing unit and the other end connected to the emitter electrode, and is disposed along the emitter electrode; and

[0216] The first lead junction and the connection portion between the emitter electrode and the sensing wiring are disposed adjacent to the emitter electrode.

[0217] When viewed from above, the aforementioned sensing wiring, the aforementioned connection portion, and the aforementioned emitter electrode collectively form a U-shape.

[0218] There are no electrodes within the portion of the aforementioned U-shape.

[0219] (Note 4) A semiconductor device, wherein,

[0220] The aforementioned semiconductor device includes:

[0221] A semiconductor substrate having a first main surface;

[0222] The emitter electrode is selectively disposed on the first main surface mentioned above;

[0223] A temperature sensing unit is disposed on the aforementioned first main surface;

[0224] The sensing wiring has one end connected to the temperature sensing unit and the other end connected to the emitter electrode; and

[0225] The first lead junction and the connection portion between the emitter electrode and the sensing wiring are disposed adjacent to the emitter electrode.

[0226] An active unit is provided in the portion of the semiconductor substrate within a quadrilateral whose diagonal is the line segment between the aforementioned connecting portion and the aforementioned first lead junction portion.

[0227] When the length of the diagonal is set to L, the current density in the cross-sectional direction flowing between the connection part and the first lead junction is set to Is, the specific resistance of the emitter electrode is set to ρ, the number of diodes in series in the temperature sensing part is set to N, and the voltage between the connection part and the first lead junction is set to ΔV, ΔV=Is×ρ×L<0.7×N holds true.

[0228] (Appendix 5) A semiconductor device, wherein,

[0229] The aforementioned semiconductor device includes:

[0230] A semiconductor substrate having a first main surface;

[0231] The emitter electrode is selectively disposed on the first main surface mentioned above;

[0232] A temperature sensing unit is disposed on the aforementioned first main surface;

[0233] The sensing wiring is connected at one end to the temperature sensing unit and at the other end to the emitter electrode.

[0234] The first lead junction and the connection portion between the emitter electrode and the sensing wiring are disposed adjacent to the emitter electrode; and

[0235] The second lead junction is disposed on the emitter electrode, on the side opposite to the first lead junction, opposite to the connecting portion.

[0236] An active cell is provided in a portion of the semiconductor substrate within the region enclosed by the line portion from the first lead junction to the emitter electrode and the emitter electrode itself, which is a straight line extending from the second lead junction through the first lead junction to the emitter electrode.

[0237] When the length of the above-mentioned line portion is set to L, the current density in the cross-sectional direction flowing between the above-mentioned connection portion and the above-mentioned first lead junction portion is set to Is, the specific resistance of the above-mentioned emitter electrode is set to ρ, the number of diodes in series included in the above-mentioned temperature sensing portion is set to N, and the voltage between the above-mentioned connection portion and the above-mentioned first lead junction portion is set to ΔV, ΔV=Is×ρ×L<0.7×N holds true.

[0238] (Note 6) In the semiconductor device according to Note 4 or Note 5, wherein,

[0239] The aforementioned ΔV is less than 50% of the amplitude of the upper and lower limits of the standard voltage of the aforementioned temperature sensing unit.

[0240] (Note 7) The semiconductor device according to Note 4 or Note 5, wherein,

[0241] The aforementioned ΔV is less than 30% of the amplitude of the upper and lower limits of the standard voltage of the aforementioned temperature sensing unit.

[0242] (Note 8) The semiconductor device according to Note 4 or Note 5, wherein,

[0243] The aforementioned ΔV is less than 10% of the amplitude of the upper and lower limits of the standard voltage of the aforementioned temperature sensing unit.

[0244] (Note 9) The semiconductor device according to Note 4 or Note 5, wherein,

[0245] The aforementioned ΔV is less than 1% of the amplitude of the upper and lower limits of the standard voltage of the aforementioned temperature sensing unit.

[0246] (Note 10) The semiconductor device according to any one of Notes 1 to 9, wherein,

[0247] It also includes an electrode pad, which is disposed on the side opposite to the sensing wiring relative to the connection portion and is separate from the emitter electrode.

[0248] (Note 11) The semiconductor device according to any one of Notes 1 to 10, wherein,

[0249] It also has an insulating film that covers the emitter electrode and the first main surface and has an opening that exposes the first lead joint.

[0250] (Note 12) The semiconductor device according to any one of Notes 1 to 10, wherein,

[0251] It also includes an insulating film that exposes the first lead junction and covers at least a portion of the emitter electrode and the first main surface, excluding the area between the first lead junction and the end of the semiconductor substrate.

[0252] (Note 13) The semiconductor device according to any one of Notes 1 to 12, wherein,

[0253] The region in the semiconductor substrate where the first lead junction is located is an invalid region.

[0254] (Note 14) The semiconductor device according to any one of Notes 1 to 13, wherein,

[0255] It also includes wiring that is connected to the temperature sensing unit and overlaps with at least a portion of the sensing wiring when viewed from above.

[0256] (Note 15) The semiconductor device according to any one of Notes 1 to 14, wherein,

[0257] The aforementioned semiconductor substrate has a rectangular shape when viewed from above.

[0258] The first lead junction is provided on the long side of the semiconductor substrate.

Claims

1. A semiconductor device, wherein, The semiconductor device includes: A semiconductor substrate having a first main surface; The emitter electrode is selectively disposed on the first main surface; The temperature sensing unit, when viewed from above, is disposed adjacent to the emitter electrode on the first main surface at a position closer to the end of the semiconductor substrate. The sensing wiring has one end connected to the temperature sensing unit and the other end connected to the emitter electrode at the terminal of the semiconductor substrate, and is disposed along the emitter electrode; as well as The first lead junction and the connection portion between the emitter electrode and the sensing wiring are disposed adjacent to the emitter electrode. The sensing wiring includes: The first sensing wiring section, when viewed from above, extends from the inside of the semiconductor substrate in a first direction to the terminal; A second sensing wiring portion extends from the first sensing wiring portion to the connection portion at the terminal along a second direction different from the first direction of the first sensing wiring portion; and The curved portion is located between the first sensing wiring portion and the second sensing wiring portion. The distance from the connecting portion to the first lead joint is shorter than the distance from the bend to the connecting portion.

2. A semiconductor device, wherein, The semiconductor device includes: A semiconductor substrate having a first main surface; The emitter electrode is selectively disposed on the first main surface; The temperature sensing unit, when viewed from above, is disposed adjacent to the emitter electrode on the first main surface at a position closer to the end of the semiconductor substrate. The sensing wiring has one end connected to the temperature sensing unit and the other end connected to the emitter electrode at the terminal of the semiconductor substrate, and is disposed along the emitter electrode; as well as The first lead junction and the connection portion between the emitter electrode and the sensing wiring are disposed adjacent to the emitter electrode. The sensing wiring extends from the inside of the semiconductor substrate in a first direction to the terminal when viewed from above. The distance from the connecting portion to the first lead joint is shorter than the distance from the temperature sensing portion to the connecting portion.

3. A semiconductor device, wherein, The semiconductor device includes: A semiconductor substrate having a first main surface; The emitter electrode is selectively disposed on the first main surface; A temperature sensing unit is disposed adjacent to the emitter electrode on the first main surface; The sensing wiring has one end connected to the temperature sensing unit and the other end connected to the emitter electrode, and is arranged along the emitter electrode; as well as The first lead junction and the connection portion between the emitter electrode and the sensing wiring are disposed adjacent to the emitter electrode. When viewed from above, the sensing wiring, the connecting portion, and the emitter electrode as a whole have a U-shaped configuration. There are no electrodes within the portion of the U-shape.

4. A semiconductor device, wherein, The semiconductor device includes: A semiconductor substrate having a first main surface; The emitter electrode is selectively disposed on the first main surface; A temperature sensing unit is disposed on the first main surface; The sensing wiring is connected at one end to the temperature sensing unit and at the other end to the emitter electrode; as well as The first lead junction and the connection portion between the emitter electrode and the sensing wiring are disposed adjacent to the emitter electrode. An active unit is disposed in the portion of the semiconductor substrate within a quadrilateral whose diagonal is the line segment between the connecting portion and the first lead junction portion. When the length of the diagonal is set to L, the current density in the cross-sectional direction flowing between the connection part and the first lead junction is set to Is, the specific resistance of the emitter electrode is set to ρ, the number of diodes in series in the temperature sensing part is set to N, and the voltage between the connection part and the first lead junction is set to ΔV, ΔV=Is×ρ×L<0.7×N holds true.

5. A semiconductor device, wherein, The semiconductor device includes: A semiconductor substrate having a first main surface; The emitter electrode is selectively disposed on the first main surface; A temperature sensing unit is disposed on the first main surface; The sensing wiring is connected at one end to the temperature sensing unit and at the other end to the emitter electrode; The first lead junction and the connection portion between the emitter electrode and the sensing wiring are disposed adjacent to the emitter electrode; and The second lead junction is located on the emitter electrode, opposite to the first lead junction on the side opposite to the connection portion. An active cell is disposed in a portion of the semiconductor substrate within a region enclosed by a line portion extending from the first lead junction to the end of the emitter electrode along a straight line from the second lead junction through the first lead junction to the end of the emitter electrode, and the end of the emitter electrode. When the length of the line portion is set to L, the current density in the cross-sectional direction flowing between the connection portion and the first lead junction is set to Is, the specific resistance of the emitter electrode is set to ρ, the number of diodes in series included in the temperature sensing portion is set to N, and the voltage between the connection portion and the first lead junction is set to ΔV, ΔV=Is×ρ×L<0.7×N holds true.

6. The semiconductor device according to claim 4 or 5, wherein, The ΔV is less than 50% of the amplitude of the upper and lower limits of the standard voltage of the temperature sensing unit.

7. The semiconductor device according to claim 4 or 5, wherein, The ΔV is less than 30% of the amplitude of the upper and lower limits of the standard voltage of the temperature sensing unit.

8. The semiconductor device according to claim 4 or 5, wherein, The ΔV is less than 10% of the amplitude of the upper and lower limits of the standard voltage of the temperature sensing unit.

9. The semiconductor device according to claim 4 or 5, wherein, The ΔV is less than 1% of the amplitude of the upper and lower limits of the standard voltage of the temperature sensing unit.

10. The semiconductor device according to any one of claims 1 to 9, wherein, It also includes an electrode pad, which is disposed on the side opposite to the sensing wiring relative to the connection portion and is separate from the emitter electrode.

11. The semiconductor device according to any one of claims 1 to 10, wherein, It also has an insulating film that covers the emitter electrode and the first main surface, and has an opening that exposes the first lead joint.

12. The semiconductor device according to any one of claims 1 to 10, wherein, It also includes an insulating film that exposes the first lead junction and covers at least a portion of the emitter electrode and the first main surface, except for the area between the first lead junction and the end of the semiconductor substrate.

13. The semiconductor device according to any one of claims 1 to 12, wherein, The region in the semiconductor substrate where the first lead junction is located is an invalid region.

14. The semiconductor device according to any one of claims 1 to 13, wherein, It also includes wiring that is connected to the temperature sensing unit and overlaps with at least a portion of the sensing wiring when viewed from above.

15. The semiconductor device according to any one of claims 1 to 14, wherein, The semiconductor substrate has a rectangular shape when viewed from above. The first lead junction is disposed on the long side of the semiconductor substrate.

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