Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. The method comprises the following steps: obtaining a wafer on which a source region, a drain region, a gate and a field oxide layer are formed; forming an etching stop layer covering the source electrode region, the drain electrode region and the grid electrode; forming a silicon oxynitride composite layer on the etching stop layer; from the bottom to the top of the silicon oxynitride composite layer, the ratio of nitrogen to oxygen tends to rise; the silicon oxynitride composite layer is photoetched and etched to form a silicon oxynitride field plate, etching windows are located above the source electrode region and the grid electrode and are far away from the upper portion of the drain electrode region, etching is conducted through an etching agent, and the etching rate of the etching agent is increased along with increase of the ratio of nitrogen to oxygen in silicon oxynitride; the silicon oxynitride field plate has a shape which is gradually raised in a direction from the source region to the drain region. The step / slope field plate can be formed only through one-step photoetching and etching, and the preparation process is simple. And the formed silicon oxynitride field plate has a good RESURF effect, so that the device has excellent breakdown voltage and on-resistance value.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor device, and also to a method for manufacturing a semiconductor device. Background Technology

[0002] Two key evaluation parameters for laterally diffused metal-oxide-semiconductor field-effect transistors (LDMOSFETs) are the device's breakdown voltage and on-resistance. To achieve excellent breakdown voltage and on-resistance values ​​for LDMOSFETs, the current mainstream approach is to add a field plate to the drift region. This field plate, together with the polysilicon plate of the gate, acts as a resurfacing agent, optimizing the surface electric field distribution of the LDMOSFET and preventing premature breakdown due to excessively high local electric fields.

[0003] Theoretical calculations demonstrate that a field plate with a gradient from the drain to the source in the drift region provides optimal surface electric field modulation. However, ramped field plates are difficult to implement in practice, and the angle of the resulting ramped field plate is unstable. Therefore, stepped field plates can be used instead of ramped field plates. Summary of the Invention

[0004] Therefore, it is necessary to provide a method for manufacturing semiconductor devices with stepped or sloping field plates and a simple manufacturing process for such field plates.

[0005] A method for manufacturing a semiconductor device includes: obtaining a wafer having an active region, a drain region, a gate, and a field oxide layer; the field oxide layer being located between the source and drain regions, the gate extending from the edge of the source region toward the drain region and above the field oxide layer; forming an etch stop layer covering the source, drain, and gate regions; forming a silicon oxynitride composite layer on the etch stop layer; the ratio of nitrogen to oxygen in the silicon oxynitride composite layer increasing from bottom to top; photolithographically etching the silicon oxynitride composite layer, the etch stop layer serving as the etch stop layer for the etching, forming a silicon oxynitride field plate, the etching window being located above the source region and the gate and away from the drain region, the etching employing an etchant whose etching rate increases with the increasing ratio of nitrogen to oxygen in the silicon oxynitride, and the silicon oxynitride field plate having a shape that gradually rises in the direction from the source region toward the drain region.

[0006] The aforementioned semiconductor device fabrication method utilizes a silicon oxynitride composite layer with a gradually increasing nitrogen-to-oxygen ratio as a field plate. After the silicon oxynitride composite layer is etched by an etchant whose etching rate increases with the nitrogen-to-oxygen ratio, a gradually rising field plate shape can be formed. This stepped / ramp field plate can be formed in a single photolithography and etching step, simplifying the fabrication process. The resulting silicon oxynitride field plate exhibits excellent resurfacing properties, resulting in devices with superior breakdown voltage and on-resistance values.

[0007] In one embodiment, the silicon oxynitride composite layer comprises multiple stacked silicon oxynitride layers, wherein the ratio of nitrogen to oxygen in each of the silicon oxynitride layers from bottom to top is greater than that in the previous layer; the silicon oxynitride field plate comprises a multi-stage staircase located between the gate and the drain region, wherein the multi-stage staircase is an ascending staircase in the direction from the source region to the drain region.

[0008] In one embodiment, the etchant is phosphoric acid.

[0009] In one embodiment, the silicon oxynitride composite layer is formed by deposition, and the nitrogen to oxygen ratio is adjusted by regulating the flow rate of NH3 during the deposition process.

[0010] In one embodiment, the etching stop layer is made of silicon oxide.

[0011] In one embodiment, the top of the bottommost silicon oxynitride layer in the silicon oxynitride composite layer is higher than the top of the gate.

[0012] In one embodiment, after the step of photolithography and etching the silicon oxynitride composite layer, the method further includes: forming an interlayer dielectric layer covering the gate and the silicon oxynitride field plate; etching the interlayer dielectric layer to form a plurality of contact holes, the contact holes including field plate contact holes located on the silicon oxynitride field plate.

[0013] In one embodiment, the field plate contact hole spans the multilayer silicon oxynitride layer, thereby making the bottom of the field plate contact hole stepped.

[0014] In one embodiment, the thickness of each of the silicon oxynitride layers is 150 Å.

[0015] In one embodiment, the material of each of the silicon oxynitride layers is a high dielectric constant medium with a relative permittivity greater than 20.

[0016] In one embodiment, the semiconductor device is a power device.

[0017] In one embodiment, the semiconductor device is a laterally double-diffused metal-oxide-semiconductor field-effect transistor.

[0018] It is also necessary to provide a semiconductor device.

[0019] A semiconductor device includes: a source region; a drain region; a field oxide layer located between the source region and the drain region; a gate located between the source region and the drain region and extending from the edge of the source region to the field oxide layer; and a silicon oxynitride field plate having an increasing nitrogen-to-oxygen ratio from bottom to top, the silicon oxynitride field plate having a shape that gradually rises in the direction from the source region to the drain region.

[0020] In the aforementioned semiconductor device, the nitrogen-to-oxygen ratio of the silicon oxynitride field plate gradually increases from bottom to top. Therefore, when forming the silicon oxynitride field plate, only an etchant with an etching rate that increases with the nitrogen-to-oxygen ratio is needed. This allows for the formation of the gradually rising field plate shape through a single photolithography and etching step, simplifying the fabrication process. The resulting silicon oxynitride field plate exhibits excellent resurfacing properties, leading to superior breakdown voltage and on-resistance values ​​in the device.

[0021] In one embodiment, the silicon oxynitride field plate includes a multi-stage staircase located between the gate and the drain region. The multi-stage staircase is an ascending staircase in the direction from the source region to the drain region. Each stage of the multi-stage staircase is a silicon oxynitride layer, and the ratio of nitrogen to oxygen in each of these silicon oxynitride layers from bottom to top is greater than that in the previous layer.

[0022] In one embodiment, the semiconductor device is a laterally double-diffused metal-oxide-semiconductor field-effect transistor.

[0023] In one embodiment, the semiconductor device further includes an interlayer dielectric layer covering the silicon oxynitride field plate and the gate, and a contact hole penetrating the interlayer dielectric layer, the contact hole including a field plate contact hole that spans multiple silicon oxynitride layers, such that the bottom of the field plate contact hole is stepped.

[0024] It is also necessary to provide a semiconductor device formed by a method for manufacturing a semiconductor device according to any of the foregoing embodiments. Attached Figure Description

[0025] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0026] Figure 1 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application.

[0027] Figure 2 This is a schematic diagram of the device structure after step S110 is completed in one embodiment of this application.

[0028] Figure 3 This is a schematic diagram of the device structure after step S130 is completed in one embodiment of this application.

[0029] Figure 4 This is a schematic diagram of the device structure after step S140 is completed in one embodiment of this application.

[0030] Figure 5 This is a schematic diagram of the device structure after step S160 is completed in one embodiment of this application.

[0031] Figure 6 This is a schematic diagram of the device structure after step S140 is completed in another embodiment of this application.

[0032] Figure 7 This is a flowchart of a method for manufacturing a semiconductor device according to another embodiment of this application. Detailed Implementation

[0033] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0035] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0036] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0038] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0039] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0040] This application proposes a semiconductor device with a dielectric field plate having a gradually rising shape (e.g., a step or a ramp), which can be fabricated through a relatively simple process. Figure 1 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application, including the following steps:

[0041] S110, to obtain a wafer with an active electrode region, a drain electrode region, a gate electrode, and a field oxide layer formed.

[0042] In one embodiment of this application, a front-end of line (FOEL) chip manufacturing process is first performed to obtain a wafer with structures such as active region 132, drain region 134, gate 136 and field oxide layer 142. Figure 2 This is a schematic diagram of the device structure after step S110 is completed in one embodiment of this application. In this embodiment, the device is an LDMOSFET. (Refer to...) Figure 2 The field oxide layer 142 is located above the region between the source region 132 and the drain region 134. The gate 136 extends from the edge of the source region 132 toward the drain region 134 and extends above the field oxide layer 142. The source region 132 and the drain region 134 have the same conductivity type. (This application) Figures 2 to 6 The device structure shown is symmetrical from left to right, so some structures in these figures are labeled only on one side.

[0043] exist Figure 2In the illustrated embodiment, the wafer further includes a substrate 110, a drift region 120 at least partially located on the substrate 110, a body region 122 located within the drift region 120, and a gate dielectric layer 135 under the gate 136. A source region 132 is located within the body region 122. The drift region 120, source region 132, and drain region 134 have a first conductivity type, and the substrate 110 and body region 122 have a second conductivity type. Figure 2 In the illustrated embodiment, the device is an N-channel LDMOSFET, with N-type as the first conductivity type and P-type as the second conductivity type. In other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type.

[0044] The substrate 110 is a semiconductor substrate, and its material can be undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc., or it can be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. Figure 2 In the embodiment shown, the substrate 110 is made of P-type single-crystal silicon.

[0045] In one embodiment of this application, the gate 136 is made of polysilicon. The polysilicon of the gate 136 can be configured as a stepped polysilicon field plate. The stepped polysilicon field plate can be formed using techniques known in the art, and this application is not limited thereto. In other embodiments, metals, metal nitrides, metal silicides, or similar compounds may also be used as the material of the gate 136.

[0046] In one embodiment of this application, the gate dielectric layer 135 may comprise conventional dielectric materials such as silicon oxides, nitrides, and oxynitrides having a dielectric constant from about 4 to about 20 (measured in vacuum), or the gate dielectric layer 135 may comprise a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).

[0047] S120 forms an etch stop layer covering the source region, drain region, and gate.

[0048] In one embodiment of this application, silicon oxide (e.g., dioxide) is deposited on the front side of the wafer as an etch stop layer 144 for subsequent etching.

[0049] S130, a silicon oxynitride composite layer is formed on the etch stop layer.

[0050] The nitrogen-to-oxygen ratio in the silicon oxynitride composite layer 150 increases from bottom to top. In one embodiment of this application, the silicon oxynitride composite layer 150 comprises multiple stacked silicon oxynitride layers, and the nitrogen-to-oxygen ratio of each layer from bottom to top is greater than that of the previous layer. Figure 3 In the illustrated embodiment, the silicon oxynitride composite layer 150 comprises three silicon oxynitride layers: silicon oxynitride layer 152, silicon oxynitride layer 154, and silicon oxynitride layer 156, wherein the ratio of nitrogen to oxygen is silicon oxynitride layer 156 > silicon oxynitride layer 154 > silicon oxynitride layer 152. For example, the chemical formula of silicon oxynitride layer 152 may be Si. x O1N1, the chemical formula of silicon oxynitride layer 154 is Si x O1N2, the chemical formula of silicon oxynitride layer 156 is Si x O1N3.

[0051] In one embodiment of this application, the silicon oxynitride composite layer 150 is formed by a deposition process. The nitrogen-to-oxygen ratio in the silicon oxynitride layer is adjusted by regulating the flow rate of NH3 during the deposition process; that is, increasing the flow rate of NH3 increases the nitrogen content in the silicon oxynitride layer. Figure 3 In the illustrated embodiment, the NH3 flow rate during the deposition of the silicon oxynitride layer 154 is greater than that during the deposition of the silicon oxynitride layer 152, and the NH3 flow rate during the deposition of the silicon oxynitride layer 156 is greater than that during the deposition of the silicon oxynitride layer 154. In another embodiment of this application, the NH3 flow rate is gradually increased during the deposition of the silicon oxynitride composite layer 150, thereby obtaining a silicon oxynitride composite layer 150 in which the ratio of nitrogen to oxygen gradually increases smoothly from bottom to top.

[0052] S140, photolithography and etching of silicon oxynitride composite layer to form silicon oxynitride field plate.

[0053] Photoresist is coated on the upper surface of the silicon oxynitride composite layer 150, and then exposed using a field plate photomask. After development, the remaining photoresist layer 192 exposes the etching window. See also Figure 4The etching window is located above the source region 132 and the gate region 136, and away from the drain region 134 (i.e., the drain region 134 is covered by the photoresist layer 192). An etchant with an etching rate that increases with the nitrogen-to-oxygen ratio in silicon oxynitride is used to etch the silicon oxynitride composite layer 150, forming a silicon oxynitride field plate 150a. Because the etching rates are inconsistent between the upper and lower parts of the silicon oxynitride composite layer 150, the lateral etching rate is relatively faster at the upper part and slower at the lower part, and etching does not continue downwards after reaching the etch stop layer 144. Therefore, the formed silicon oxynitride field plate 150a has a shape that gradually rises in the direction from the source region 132 to the drain region 134. Figure 4 In the illustrated embodiment, the silicon oxynitride field plate 150a includes a multi-stage staircase located between the gate 136 and the drain region 134, which are ascending staircases in the direction from the source region 132 to the drain region 134.

[0054] In the aforementioned embodiment, "by gradually increasing the NH3 flow rate during the deposition process to obtain a silicon oxynitride composite layer 150 in which the nitrogen-to-oxygen ratio gradually increases smoothly from bottom to top," the silicon oxynitride field plate 150a obtained after step S140 is sloped, see [reference]. Figure 6 .

[0055] The aforementioned semiconductor device manufacturing method utilizes a silicon oxynitride composite layer 150 with a gradually increasing nitrogen-to-oxygen ratio from bottom to top as a field plate. After the silicon oxynitride composite layer 150 is etched by an etchant whose etching rate increases with the nitrogen-to-oxygen ratio, a gradually rising field plate shape can be formed. This stepped / sloping field plate can be formed in a single photolithography and etching step, simplifying the fabrication process and demonstrating strong compatibility with traditional processes. Furthermore, by adjusting the thickness and number of silicon oxynitride layers in the silicon oxynitride composite layer 150, the height and length of each step can be adjusted, ensuring compatibility with devices at different voltage levels. The formed silicon oxynitride field plate 150a exhibits excellent resurfacing properties, further optimizing the electric field in the drift region, thereby resulting in devices with superior breakdown voltage and on-resistance values.

[0056] See Figure 7 In one embodiment of this application, the method further includes the following after step S140:

[0057] S150, forming an interlayer dielectric layer covering the gate and the silicon oxynitride field plate.

[0058] In one embodiment of this application, an interlayer dielectric (ILD) layer 160 is deposited on the front side of the wafer, see [link to relevant documentation]. Figure 5The interlayer dielectric can be a silicon oxide layer, such as a doped or undoped silicon oxide material layer formed using thermal chemical vapor deposition (TCVD) or high-density plasma chemical vapor deposition (HDPCVD) processes. Specifically, it can be undoped silicon glass (USG), phosphosilicate glass (PSG), or borosilicate glass (BPSG). Alternatively, the interlayer dielectric can also be boron-doped or phosphorus-doped spin-on-glass (SOG), phosphorus-doped tetraethoxysilane (PTEOS), or boron-doped tetraethoxysilane (BTEOS), etc.

[0059] In one embodiment of this application, before forming the interlayer dielectric layer 160, a step of forming a metal silicide area block (SAB) layer is included. Metal silicides can be formed on the surfaces of the source region 132, drain region 134, and gate region 136. The presence of metal silicides can reduce contact resistance. Self-aligned metal silicide (salicide) is a relatively simple and convenient contact metallization process. During the fabrication of semiconductor devices, some areas require a salicide process, while others require a non-salicide process. For devices requiring a non-salicide process, the properties of salicide are utilized, and the areas requiring non-salicide are covered with a material that does not react with metal. This material used to cover non-salicide devices is called a self-aligned metal silicide area block (SAB).

[0060] In one embodiment of this application, the metal silicide can be made of CoSi. x NiSi x PtSi x Or a combination of these compounds.

[0061] In one embodiment of this application, the metal silicide barrier layer includes an oxide layer, such as silicon oxide. Further, the metal silicide barrier layer may also be a multilayer structure, for example, including an oxide layer, a nitride layer, and an oxide-oxygen nitride layer stacked sequentially from bottom to top.

[0062] S160, etching the interlayer dielectric layer to form several contact holes.

[0063] See Figure 5 The interlayer dielectric layer 160 is photolithographically etched and etched to form several contact holes, including field plate contact holes 172 on the silicon oxynitride field plate 150a. Each contact hole is filled with a conductive material, such as tungsten. Figure 5In the illustrated embodiment, the field plate contact hole 172 spans multiple layers of silicon oxynitride, with its bottom stopping on each silicon oxynitride layer, thus making the bottom of the field plate contact hole 172 stepped. The contact holes also include source contact holes on the source region 132, drain contact holes on the drain region 134, gate contact holes on the gate 136, etc.

[0064] In one embodiment of this application, the etching in step S140 is performed using a wet etching process with phosphoric acid as the etchant. In other embodiments, the etching in step S140 may also be performed using a dry etching process.

[0065] See Figure 5 In one embodiment of this application, the bottom of the lowest layer (i.e., silicon oxynitride layer 152) of the silicon oxynitride composite layer 150 is not lower than the top of the gate 136.

[0066] In one embodiment of this application, the material of each silicon oxynitride layer in the silicon oxynitride composite layer 150 is a high-k dielectric with a relative permittivity greater than 20, i.e., high-k silicon oxynitride. In one embodiment of this application, the thickness of each silicon oxynitride layer is 150 Å.

[0067] This application provides a semiconductor device with a stepped or ramped field plate, which can be manufactured using the semiconductor device manufacturing method described in any of the foregoing embodiments. The semiconductor device can be a power device, including a source region 132, a drain region 134, a gate 136, a field oxide layer 142, and a silicon oxynitride field plate 150a. The field oxide layer 142 is located between the source region 132 and the drain region 134. The gate 136 is located between the source region 132 and the drain region 134, and extends from the edge of the source region 132 onto the field oxide layer 142. The ratio of nitrogen to oxygen in the silicon oxynitride field plate 150a increases from bottom to top, and the silicon oxynitride field plate 150a has a shape that gradually rises in the direction from the source region 132 to the drain region 134. In one embodiment of this application, the silicon oxynitride field plate 150a is stepped, including multiple steps located between the gate 136 and the drain region 134, these steps being ascending steps in the direction from the source region 132 to the drain region 134. In another embodiment of this application, the silicon oxynitride field plate 150a is ramp-shaped.

[0068] In the aforementioned semiconductor device, the nitrogen-oxygen ratio of the silicon oxynitride field plate 150a gradually increases from bottom to top. Therefore, when forming the silicon oxynitride field plate 150a, only an etchant with an etching rate that increases with the nitrogen-oxygen ratio is needed. This allows for the formation of the gradually rising field plate shape through a single photolithography and etching step, simplifying the fabrication process. The resulting silicon oxynitride field plate 150a exhibits excellent resurfacing properties, thereby giving the device superior breakdown voltage and on-resistance values.

[0069] See Figure 5 In one embodiment of this application, the semiconductor device further includes a substrate 110, a drift region 120 at least partially located on the substrate 110, a body region 122 located in the drift region 120, and a gate dielectric layer 135 under the gate 136. The source region 132 is located in the body region 122. The drift region 120, source region 132, and drain region 134 have a first conductivity type, and the substrate 110 and body region 122 have a second conductivity type. Figure 5 In the illustrated embodiment, the device is an N-channel LDMOSFET, with N-type as the first conductivity type and P-type as the second conductivity type. In other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type.

[0070] The substrate 110 is a semiconductor substrate, and its material can be undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc., or it can be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. Figure 5 In the embodiment shown, the substrate 110 is made of P-type single-crystal silicon.

[0071] In one embodiment of this application, the gate 136 is made of polysilicon. The polysilicon of the gate 136 can be configured as a stepped polysilicon field plate. The stepped polysilicon field plate can be fabricated using techniques known in the art, and this application is not limited thereto. In other embodiments, metals, metal nitrides, metal silicides, or similar compounds can also be used as the material of the gate 136.

[0072] In one embodiment of this application, the gate dielectric layer 135 may comprise conventional dielectric materials such as silicon oxides, nitrides, and oxynitrides having a dielectric constant from about 4 to about 20 (measured in vacuum), or the gate dielectric layer 135 may comprise a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).

[0073] In one embodiment of this application, the material of the silicon oxynitride field plate 150a is a high-k dielectric with a relative permittivity greater than 20.

[0074] exist Figure 5In the illustrated embodiment, the silicon oxynitride field plate 150a comprises three silicon oxynitride layers: silicon oxynitride layer 152, silicon oxynitride layer 154, and silicon oxynitride layer 156, wherein the ratio of nitrogen to oxygen is silicon oxynitride layer 156 > silicon oxynitride layer 154 > silicon oxynitride layer 152. For example, the chemical formula of silicon oxynitride layer 152 is Si. x O1N1, the chemical formula of silicon oxynitride layer 154 is Si x O1N2, the chemical formula of silicon oxynitride layer 156 is Si x O1N3.

[0075] In one embodiment of this application, the semiconductor device further includes an interlayer dielectric layer 160 covering the silicon oxynitride field plate 150a and the gate 136. Contact holes penetrate the interlayer dielectric layer 160 to bring out structures such as the source region 132, drain region 134, and gate 146. The contact holes include field plate contact holes 172, which span multiple silicon oxynitride layers, resulting in a stepped bottom.

[0076] The material of the interlayer dielectric layer 160 can be a silicon oxide layer, such as a doped or undoped silicon oxide material layer formed by thermal chemical vapor deposition (TCVD) or high-density plasma chemical vapor deposition (HDPCVD) processes. Specifically, it can be an undoped silicon glass (USG), phosphosilicate glass (PSG), or borosilicate glass (BPSG). Alternatively, the interlayer dielectric can also be a boron-doped or phosphorus-doped spin-on-glass (SOG), a phosphorus-doped tetraethoxysilane (PTEOS), or a boron-doped tetraethoxysilane (BTEOS), etc.

[0077] In one embodiment of this application, the semiconductor device further includes an etch stop layer 144 covering the drift region 120, the field oxide layer 142, the gate 136, and the gate dielectric layer 135. In one embodiment of this application, the etch stop layer 144 is made of silicon oxide, such as silicon dioxide.

[0078] The semiconductor device manufacturing method of this application is based on the same inventive concept as the semiconductor device. For details not specifically described in the semiconductor device manufacturing method, please refer to the above introduction of the semiconductor device.

[0079] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0080] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0081] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0082] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: Obtain a wafer in which the active electrode region, drain electrode region, gate electrode and field oxide layer are formed; The field oxide layer is located between the source region and the drain region, and the gate extends from the edge of the source region to the drain region and extends above the field oxide layer; An etch stop layer is formed covering the source region, drain region, and gate. A silicon oxynitride composite layer is formed on the etching stop layer; the ratio of nitrogen to oxygen in the silicon oxynitride composite layer increases from bottom to top. The silicon oxynitride composite layer is photolithographically etched and etched, with an etch stop layer serving as the etch stop layer to form a silicon oxynitride field plate. The etch window is located above the source region and above the gate region and away from the drain region. The etching uses an etchant whose etching rate increases with the ratio of nitrogen to oxygen in silicon oxynitride. The silicon oxynitride field plate has a shape that gradually rises in the direction from the source region to the drain region.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The silicon oxynitride composite layer comprises multiple stacked silicon oxynitride layers, wherein the ratio of nitrogen to oxygen in each of these silicon oxynitride layers is greater than that in the previous layer from bottom to top; the silicon oxynitride field plate comprises multiple steps located between the gate and the drain region, wherein the multiple steps are ascending steps in the direction from the source region to the drain region.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that, The etching agent is phosphoric acid.

4. The method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that, The silicon oxynitride composite layer is formed by deposition, and the ratio of nitrogen to oxygen is adjusted by regulating the flow rate of NH3 during the deposition process.

5. The method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that, The etching stop layer is made of silicon oxide.

6. The method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that, The semiconductor device is a laterally double-diffused metal-oxide-semiconductor field-effect transistor.

7. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The top of the bottommost silicon oxynitride layer in the silicon oxynitride composite layer is higher than the top of the gate.

8. The method for manufacturing a semiconductor device according to claim 2, characterized in that, After the step of photolithography and etching the silicon oxynitride composite layer, the method further includes: An interlayer dielectric layer is formed covering the gate and the silicon oxynitride field plate; The interlayer dielectric layer is etched to form a plurality of contact holes, including field plate contact holes located on the silicon oxynitride field plate.

9. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The field plate contact hole spans the multilayer silicon oxynitride layer, thus making the bottom of the field plate contact hole stepped.

10. A semiconductor device, characterized in that, include: Source region; Drain region; A field oxygen layer is located between the source region and the drain region; A gate is located between the source region and the drain region, and extends from the edge of the source region to the field oxide layer; The silicon oxynitride field plate has an increasing ratio of nitrogen to oxygen from bottom to top, and has a shape that gradually rises in the direction from the source region to the drain region.

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