Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and the method comprises the steps: providing a substrate, and forming at least one groove-type gate structure in the substrate; forming an interlayer dielectric layer covering the substrate and the groove type gate structure; forming a patterned photoresist layer with a preset angle on the interlayer dielectric layer, etching the interlayer dielectric layer by taking the photoresist layer as a mask so as to form at least one contact hole and enable the residual interlayer dielectric layer to form a bag-shaped structure above the groove-type gate structure at the same time, the contact hole is of a structure with a wide upper part and a narrow lower part, and the contact hole exposes a part of the surface of the substrate. By etching the interlayer dielectric layer to form the contact hole and enabling the remaining interlayer dielectric layer to form the bag-shaped structure on the groove-type gate structure, the problem that the surface of the interlayer dielectric layer is not flat is eliminated, the technological process is optimized, the technological time is saved, and the technological cost is reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] In integrated circuit manufacturing, power metal-oxide-semiconductor field-effect transistors (MOS) typically use undoped silicon glass (USG) and boro-phospho-silicate glass (BPSG) for their interlayer dielectric layers. Planar device designs have relatively small overall steps, and normal reflow processes can keep the interlayer dielectric layer flat. However, for trench-type MOS devices, due to the presence of trenches, after backfilling and dry etching to the substrate surface, a depression always exists at the top of the trench due to filling issues. This depression in the interlayer dielectric layer also persists. Reflow cannot improve this depression and achieve a flat interlayer dielectric layer. Subsequent via etching results in a basin-shaped interlayer dielectric layer at the top of the trench. This affects subsequent metal layer coverage and makes the interlayer dielectric layer difficult to maintain, impacting trench coverage and the stability of the critical dimension (CD) of the contact holes.

[0003] In related technologies, to eliminate the unevenness of the interlayer dielectric layer caused by trench step differences, chemical mechanical polishing (CMP) is used to planarize the interlayer dielectric layer after deposition. CMP is used to planarize the interlayer dielectric layer above the trench, followed by hole etching and metal filling. After metal filling, CMP is used again to smooth the surface and ensure overall step flatness. While the above technology can achieve planarization, both the interlayer dielectric layer and the metal layer require CMP, which is time-consuming and costly. Summary of the Invention

[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] To address the existing problems, this application provides a method for manufacturing a semiconductor device, comprising: providing a substrate in which at least one trench gate structure is formed; forming an interlayer dielectric layer covering the substrate and the trench gate structure; forming a patterned photoresist layer with a preset angle on the interlayer dielectric layer; etching the interlayer dielectric layer using the photoresist layer as a mask to form at least one contact hole while simultaneously forming a cladding structure of the remaining interlayer dielectric layer above the trench gate structure, wherein the contact hole has a structure that is wider at the top and narrower at the bottom, and the contact hole exposes a portion of the surface of the substrate.

[0006] For example, the step of forming a patterned photoresist layer with a preset angle on the interlayer dielectric layer, and etching the interlayer dielectric layer using the photoresist layer as a mask to form at least one contact hole while simultaneously forming a sac-like structure of the remaining interlayer dielectric layer above the trench gate structure includes: forming a patterned first photoresist layer with a first preset angle on the interlayer dielectric layer; and performing a first etching on the interlayer dielectric layer using the first photoresist layer as a mask to form at least one first contact hole while simultaneously forming a first sac-like structure of the remaining interlayer dielectric layer above the trench gate structure, wherein the first contact hole exposes a portion of the substrate surface, and the first contact hole has an inverted trapezoidal aperture structure, and the first sac-like structure is a triangular sac-like structure.

[0007] For example, the first preset angle is 60 degrees to 85 degrees.

[0008] For example, the etching gas for the first etching includes at least one of the following: carbon tetrafluoride, trifluoromethane, and difluoromethane.

[0009] For example, the step of forming a patterned photoresist layer with a preset angle on the interlayer dielectric layer, and etching the interlayer dielectric layer using the photoresist layer as a mask to form at least one contact hole while simultaneously forming a cladding structure on the remaining interlayer dielectric layer above the trench gate structure includes: forming a patterned first photoresist layer with a first preset angle on the interlayer dielectric layer; performing a first etching on the interlayer dielectric layer using the first photoresist layer as a mask to form at least one first contact hole, wherein the first contact hole exposes a portion of the substrate surface and has an inverted trapezoidal aperture structure; after forming the first contact hole, continuing to reflow the remaining interlayer dielectric layer to form at least one second contact hole while simultaneously forming a second cladding structure on the remaining interlayer dielectric layer after the reflow treatment above the trench gate structure, wherein the second contact hole exposes a portion of the substrate surface and has an arc-shaped aperture structure, and the second cladding structure is an arc-shaped cladding structure.

[0010] For example, the step of forming a patterned photoresist layer with a preset angle on the interlayer dielectric layer, and etching the interlayer dielectric layer using the photoresist layer as a mask to form at least one contact hole while simultaneously forming a cladding structure above the trench gate structure in the remaining interlayer dielectric layer includes: forming a patterned second photoresist layer with a second preset angle on the interlayer dielectric layer; performing a second etching on a portion of the interlayer dielectric layer using the second photoresist layer as a mask to form at least one arc-shaped hole opening in the interlayer dielectric layer; and continuing etching the interlayer dielectric layer below the arc-shaped hole opening. The dielectric layer undergoes a third etching to form a trapezoidal aperture below the arc-shaped aperture opening, the arc-shaped aperture opening communicating with the trapezoidal aperture opening and exposing a portion of the substrate surface; the second photoresist layer is removed, and the remaining interlayer dielectric layer is further etched a fourth time to form at least one third contact hole while simultaneously forming a third sac-like structure above the trench gate structure, wherein the third contact hole exposes a portion of the substrate surface, and the third contact hole has a bowl-shaped aperture structure, and the third sac-like structure is an arc-shaped triangular sac-like structure.

[0011] For example, the second preset angle is 85 degrees to 90 degrees.

[0012] For example, the second etching and the fourth etching are wet etching, wherein hydrofluoric acid is the main etching solution and ammonium fluoride is the buffer.

[0013] For example, after forming at least one contact hole, the method further includes forming a metal layer that covers the package-like structure and fills the contact hole.

[0014] In another aspect, this application provides a semiconductor device manufactured using the method described above.

[0015] The semiconductor device and manufacturing method provided in this application form a photoresist layer with a preset angle on the interlayer dielectric layer, and use the photoresist layer as a mask to etch the interlayer dielectric layer. This forms a contact hole while the remaining interlayer dielectric layer forms a cladding structure on the trench gate structure. This eliminates the problem of uneven surface of the interlayer dielectric layer, ensures the flatness of the overall step after subsequent metal material filling, optimizes the process flow, saves process time, and reduces process cost. Attached Figure Description

[0016] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.

[0017] In the attached image:

[0018] Figure 1 A flowchart illustrating a semiconductor device manufacturing method according to a specific embodiment of this application is shown;

[0019] Figures 2A to 2D A cross-sectional schematic diagram of a semiconductor device manufacturing method according to a specific embodiment of this application is shown, showing the device obtained by sequentially implementing the method.

[0020] Figures 2E to 2F A cross-sectional schematic diagram of a semiconductor device manufacturing method according to another specific embodiment of this application is shown, showing the device obtained by sequentially implementing the manufacturing method.

[0021] Figures 2G to 2K This diagram shows a cross-sectional view of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to another specific embodiment of this application. Detailed Implementation

[0022] The present application will now be described more fully with reference to the accompanying drawings, in which embodiments of the present application are illustrated. However, the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0023] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0024] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0026] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0027] Currently, in related technologies, CMP (Chemical Mechanical Polishing) is used for planarization to eliminate the unevenness of the interlayer dielectric layer caused by trench step differences. First, a trench-type gate structure is formed in the substrate, creating an interlayer dielectric layer covering both the substrate and the trench-type gate structure. Due to the presence of the trenches, a depression exists in the interlayer dielectric layer above the trenches. Second, CMP is used to planarize the interlayer dielectric layer. Finally, via etching is performed, followed by metal filling, and then CMP is used again to planarize the metal layer, ensuring overall step flatness. Although these technologies achieve planarization, both the interlayer dielectric layer and the metal layer require CMP, which is time-consuming and costly.

[0028] Therefore, in view of the aforementioned technical problems, this application proposes a method for manufacturing a semiconductor device, such as... Figure 1 As shown, it mainly includes the following steps:

[0029] Step S101: Provide a substrate in which at least one trench gate structure is formed;

[0030] Step S102: Form an interlayer dielectric layer covering the substrate and the trench gate structure;

[0031] Step S103: A patterned photoresist layer with a preset angle is formed on the interlayer dielectric layer. The interlayer dielectric layer is etched using the photoresist layer as a mask to form at least one contact hole while the remaining interlayer dielectric layer forms a cladding structure above the trench gate structure. The contact hole has a structure that is wider at the top and narrower at the bottom, and the contact hole exposes part of the surface of the substrate.

[0032] The semiconductor device manufacturing method of this application forms a photoresist layer with a preset angle on the interlayer dielectric layer, and uses the photoresist layer as a mask to etch the interlayer dielectric layer to form contact holes while the remaining interlayer dielectric layer forms a cladding structure on the trench gate structure. This eliminates the problem of uneven surface of the interlayer dielectric layer, ensures the flatness of the overall step after subsequent metal material filling, optimizes the process flow, saves process time, and reduces process costs.

[0033] Example 1

[0034] Below, for reference Figure 1 as well as Figures 2A to 2D The method for manufacturing the semiconductor device of this application is described in detail, wherein, Figure 1 A flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of this application is shown. Figures 2A to 2D This illustration shows a cross-sectional schematic diagram of a semiconductor device manufacturing method according to a specific embodiment of the present application, resulting in a device obtained by sequential implementation.

[0035] For example, the method for manufacturing the semiconductor device of this application includes the following steps:

[0036] First, step S101 is performed to provide a substrate in which at least one trench gate structure is formed.

[0037] In one example, such as Figure 2AAs shown, the substrate 201 is made of at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), sapphire, or other III / V compound semiconductors; or silicon on dielectric (SOI), silicon on dielectric (SSOI), silicon germanium on dielectric (S-SiGeOI), silicon germanium on dielectric (SiGeOI), and germanium on dielectric (GeOI); or it may be a double-sided polished wafer (DSP), a ceramic substrate such as alumina, a quartz, or a glass substrate. Although several examples of materials that can form a substrate have been described herein, any material that can serve as a substrate falls within the spirit and scope of this application.

[0038] In one example, such as Figure 2AAs shown, at least one trench gate structure 202 is formed in the substrate 201. Specifically, firstly, a patterned photoresist layer is formed on the surface of the substrate 201, exposing the area corresponding to the trench. The substrate 201 is etched using the photoresist layer as a mask, and then the photoresist layer is removed. Exemplarily, the etching of the substrate 201 can be performed using conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, or plasma etching to form one or more trenches 2021. Alternatively, a hard mask layer can be formed first on the substrate surface, and then the pattern can be transferred onto the hard mask layer using the photoresist layer as a mask. The substrate is then etched using the hard mask layer to form the one or more trenches 2021, and finally the hard mask layer is removed. The above-described trench formation method is common in the art and will not be described or limited in detail here. In short, any method that can form the desired trench in the substrate is within the scope of protection of this application. Next, a gate oxide layer 2022 is formed in the trench 2021. The material of the gate oxide layer 2022 can be silicon oxide or silicon oxynitride, or other suitable materials, such as high-k materials, without specific limitation. Exemplarily, the gate oxide layer 2022 can be formed on the sidewalls and bottom of the trench 2021 using deposition processes such as chemical vapor deposition (CVD), or the gate oxide layer 2022 can be formed by a high-temperature furnace tube thermal oxidation process. Finally, a gate material layer 2023 is formed to fill the trench 2021. The gate material layer 2023 can be polysilicon or doped polysilicon, or other suitable materials, without specific limitation. Specifically, polysilicon can be deposited on the gate material layer 2023 by low-pressure chemical vapor deposition (LPVCD) so that the polysilicon covers the sidewalls and bottom of the gate oxide layer 2022 and fills the trench 2021, thereby forming a trench gate structure 202.

[0039] Next, step S102 is performed to form an interlayer dielectric layer covering the substrate and the trench gate structure.

[0040] In one example, such as Figure 2AAs shown, an interlayer dielectric layer 203 is formed covering the substrate 201 and the trench gate structure 202. The interlayer dielectric layer can be a silicon oxide layer, such as a doped or undoped silicon oxide material layer formed using thermal chemical vapor deposition (TCVD) or high-density plasma chemical vapor deposition (HDPCVD) processes. Specifically, the interlayer dielectric layer 203 may include undoped silicon glass (USG) and borosilicate glass (BPSG) stacked sequentially. For example, the USG can be deposited using, but not limited to, deposition processes such as plasma-enhanced chemical vapor deposition (PECVD) to deposit a certain thickness. Next, the BPSG is deposited using, but not limited to, deposition processes such as atmospheric pressure chemical vapor deposition (APCVD) to deposit a certain thickness, thereby forming the interlayer dielectric layer 203. Depositing USG under BPSG can prevent the diffusion of boron and phosphorus elements precipitated in borosilicate glass into the substrate 201, thereby preventing contamination of the substrate 201. In another embodiment, the interlayer dielectric layer 203 can also be other suitable materials, such as silicon nitride, silicon boron nitride, silicon carbon oxynitride, or silicon oxynitride, etc., without specific limitation.

[0041] Finally, step S103 is performed to form a patterned photoresist layer with a preset angle on the interlayer dielectric layer. The interlayer dielectric layer is etched using the photoresist layer as a mask to form at least one contact hole while the remaining interlayer dielectric layer forms a sac-like structure above the trench gate structure. The contact hole has a structure that is wider at the top and narrower at the bottom, and the contact hole exposes part of the substrate surface.

[0042] In one example, such as Figure 2B and Figure 2CAs shown, a patterned first photoresist layer 2041 with a first preset angle is formed on the interlayer dielectric layer 203. Specifically, during the photolithography process, a photomask is used for exposure and development. The exposure and development process patterns the first photoresist layer 2041, giving it a certain angle (i.e., the first preset angle). The opening in the first photoresist layer 2041 is the location where the first contact hole 2051 will be formed on the interlayer dielectric layer 203. The patterned shape of the first photoresist layer 2041 represents the structural shape of the subsequently formed first contact hole 2051. For example, the angle of the first photoresist layer 2041 can be from 60 degrees to 85 degrees, that is, the angle between the sidewall of the first photoresist layer 2041 and the bottom surface can be from 60 degrees to 85 degrees.

[0043] In one example, such as Figure 2B and Figure 2C As shown, the interlayer dielectric layer 203 is etched using the first photoresist layer 2041 as a mask to form at least one first contact hole 2051. The first contact hole 2051 exposes a portion of the substrate 201 surface and has an inverted trapezoidal opening. Specifically, etching the interlayer dielectric layer 203 may include the following steps: forming the first photoresist layer 2041 in the interlayer dielectric layer 203; etching the interlayer dielectric layer 203 using the first photoresist layer 2041 as a mask; and then removing the first photoresist layer 2041. Specifically, in the first etching step, conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, and plasma etching can be used to etch the first sacrificial layer 204 to form one or more first contact holes 2051. For example, an anisotropic dry etching technique can be used as the first etching, and carbon-fluorine gases such as carbon tetrafluoride (CF4), trifluoromethane (CHF3), and difluoromethane (CH2F2) can be used as the etching gas for the first etching. The interlayer dielectric layer 203 is etched by the etching gas to form one or more first contact holes 2051. Other suitable gases can also be used for gas etching, and there is no specific limitation. The first contact hole 2051 exposes a portion of the surface of the substrate 201, and the cross-sectional width of the first contact hole 2051 decreases linearly from the top surface to the bottom surface. For example, the first contact hole 2051 has an inverted trapezoidal structure.

[0044] In this example, such as Figure 2CAs shown, the remaining interlayer dielectric layer 203 forms a first sac-like structure 2061 above the trench gate structure 202. The first sac-like structure 2061 is a triangular sac-like structure. Specifically, while forming the first contact hole 2051 after the first etching, the remaining interlayer dielectric layer 203 forms the first sac-like structure 2061 on the corresponding trench gate structure 202. The first sac-like structure 2061 corresponds to the trench gate structure 202; that is, a first sac-like structure 2061 is correspondingly disposed above each trench gate structure 202, and the first sac-like structure 2061 is a triangular sac-like structure (i.e., the first sac-like structure 2061 is a triangular structure). The step coverage of the formed triangular sac-like structure ensures a smooth step after subsequent metal material filling, achieving a planarization effect in one step. This reduces process time and cost, and also helps stabilize the contact resistance in the contact hole, reducing the on-resistance.

[0045] In one example, such as Figure 2D As shown, after forming at least one first contact hole 2051, the method further includes: forming a metal layer 207, which covers the first envelope structure 2061 and fills the first contact hole 2051. Exemplarily, the metal layer 207 can be formed using processes such as sputtering, and the metal layer 207 fills the first contact hole 2051. Exemplarily, the material of the metal layer can be a suitable conductive material such as aluminum, tungsten, or copper, without specific limitation. In another example, other suitable deposition processes can also be used to deposit the metal layer 207, such as physical vapor deposition (PVD) processes like vacuum evaporation, without specific limitation.

[0046] Example 2

[0047] The preceding process steps in this embodiment are the same as those in Embodiment 1 above, and will not be described again here. Below, refer to... Figure 2E and Figure 2F The method for fabricating the semiconductor device according to the embodiments of this application is described in detail, wherein, Figure 2E and Figure 2F A schematic cross-sectional view of a semiconductor device obtained by sequentially performing the steps of a method for manufacturing a semiconductor device according to another embodiment of this application is shown.

[0048] This embodiment is based on the above. Figure 2C After the steps shown, as Figure 2EAs shown, after forming the first contact hole 2051, the remaining interlayer dielectric layer 203 is reflowed to form at least one second contact hole 2052. The second contact hole 2052 exposes a portion of the substrate 201 surface and has an arc-shaped opening. Exemplarily, the interlayer dielectric layer 203 may include USG and BPSG stacked sequentially. Because BPSG is doped with boron and phosphorus, it alters the original ordered network structure of silicon dioxide, giving it liquid-like flowability at high temperatures. Therefore, the reflow characteristics of BPSG dielectric are utilized to reflow the remaining interlayer dielectric layer 203. The reflow process conditions are: an inert gas atmosphere, a process temperature of 600 to 1000 degrees Celsius, and a processing time of 2 to 5 minutes. Exemplarily, the inert gas may include gases such as nitrogen, but is not limited to the above example. In another example, the reflow process conditions may also be other suitable conditions, which are not specifically limited. By adjusting the reflow temperature and time under an inert gas atmosphere, BPSG can soften, melt, and flow at a lower temperature. Utilizing the property of liquids to minimize surface tension, it can maximize surface smoothing, thereby forming the second contact hole 2052. The second contact hole 2052 exposes a portion of the substrate 201 surface. The second contact hole 2052 has an arc-shaped opening, arc-shaped sidewalls, and a cross-sectional width that gradually decreases from top to bottom.

[0049] In this example, such as Figure 2E As shown, the remaining interlayer dielectric layer 203 after reflow treatment forms a second cladding structure 2062 above the trench gate structure 202. The second cladding structure 2062 is an arc-shaped cladding structure. Specifically, after forming the first contact hole 2051, while reflowing the remaining interlayer dielectric layer 203 to form the second contact hole 2052, the remaining interlayer dielectric layer 203 after reflow treatment forms a second cladding structure 2062 on the corresponding trench gate structure 202. The second cladding structure 2062 corresponds to the trench gate structure 202, that is, a second cladding structure 2062 is correspondingly disposed above each trench gate structure 202, and the second cladding structure 2062 is an arc-shaped cladding structure (i.e., the second cladding structure 2062 is a semi-circular arc structure). The stepped coverage of the formed arc-shaped structure ensures that the steps are flat after subsequent metal filling, achieving a flattening effect in one step. This process is quick, low-cost, and also helps stabilize the contact resistance in the contact hole, reducing the conduction resistance.

[0050] In one example, such as Figure 2FAs shown, after forming at least one second contact hole 2052, the method further includes: forming a metal layer 207, which covers the second envelope structure 2062 and fills the second contact hole 2052. Exemplarily, the metal layer 207 can be formed using processes such as sputtering, and the metal layer 207 fills the second contact hole 2052. The material of the metal layer can be a suitable conductive material such as aluminum, tungsten, or copper, and is not specifically limited thereto. In another example, other suitable deposition processes can be used to deposit the metal layer 207, such as PVD processes like vacuum evaporation, and is not specifically limited thereto.

[0051] Example 3

[0052] The preceding process steps in this embodiment are the same as those in Embodiment 1 above, and will not be described again here. Below, refer to... Figures 2G to 2K The method for fabricating the semiconductor device according to the embodiments of this application is described in detail, wherein, Figures 2G to 2K This diagram shows a cross-sectional view of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to another specific embodiment of this application.

[0053] In one example, such as Figure 2G As shown, a patterned second photoresist layer 2042 with a second preset angle is formed on the interlayer dielectric layer 203. Specifically, during the photolithography process, a photomask is used for exposure and development. Exposure and development pattern the second photoresist layer 2042, giving it a certain angle (i.e., the second preset angle). The opening in the second photoresist layer 2042 is the location where the third contact hole 2053 will be formed on the interlayer dielectric layer 203. For example, the angle of the second photoresist layer 2042 can be 85 degrees to 90 degrees, that is, the angle between the sidewall and the bottom surface of the second photoresist layer 2042 can be 85 degrees to 90 degrees. For example, as... Figure 2G As shown, the angle of the second photoresist layer 2042 is 90 degrees.

[0054] In one example, such as Figure 2HAs shown, a portion of the interlayer dielectric layer 203 is etched using the second photoresist layer 2042 as a mask to form at least one arc-shaped hole opening 2053a in the interlayer dielectric layer 203. Exemplarily, the second etching is a wet etching process, which may include the following steps: etching a portion of the interlayer dielectric layer 203 using a mixed solution of hydrofluoric acid (HF) and ammonium fluoride (NH4F), wherein hydrofluoric acid is the main etching solution and ammonium fluoride is the buffer; through the second etching (i.e., wet etching), one or more arc-shaped hole openings 2053a are formed in the interlayer dielectric layer 203, and the arc-shaped hole openings 2053a do not expose the surface of the substrate 201. During the wet etching process, a portion of the second photoresist layer 2042 is lost, and the wet etching time depends on the thickness of the interlayer dielectric layer 203.

[0055] In one example, such as Figure 2I As shown, a third etching is performed on the portion of the interlayer dielectric layer 203 below the arc-shaped aperture opening 2053a to form a trapezoidal aperture opening 2053b located below the arc-shaped aperture opening 2053a. The arc-shaped aperture opening 2053a and the trapezoidal aperture opening 2053b are connected and expose a portion of the substrate 201 surface. Specifically, continuing the etching (i.e., the third etching) of the portion of the interlayer dielectric layer 203 below the arc-shaped aperture opening 2053a may include the following steps: forming a patterned photoresist layer in the interlayer dielectric layer 203 below the arc-shaped aperture opening 2053a; etching the interlayer dielectric layer 203 using the patterned photoresist layer as a mask; and then removing the photoresist layer. For example, in the third etching step, conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, and plasma etching can be used to etch the interlayer dielectric layer 203 below the arc-shaped hole opening 2053a to form a trapezoidal hole opening 2053b located below the arc-shaped hole opening 2053a. For example, anisotropic dry etching technology can be used as the third etching, and carbon-fluorine gases such as carbon tetrafluoride (CF4), trifluoromethane (CHF3), and difluoromethane (CH2F2) can be used as the etching gas for the third etching. The interlayer dielectric layer 203 is etched by the etching gas to form the trapezoidal hole opening 2053b. Specifically, other suitable gases can also be used for gas etching, and there is no specific limitation on this. Specifically, the arc-shaped hole opening 2053a is connected to the trapezoidal hole opening 2053b, and the trapezoidal hole opening 2053b exposes part of the surface of the substrate 201. The cross-sectional width of the arc-shaped hole opening 2053a is greater than the cross-sectional width of the trapezoidal hole opening 2053b, and the cross-sectional width of the trapezoidal hole opening 2053b decreases linearly from top to bottom. For example, the trapezoidal hole opening 2053b is an inverted trapezoidal structure.

[0056] In one example, such as Figure 2JAs shown, after removing the second photoresist layer 2042, the remaining interlayer dielectric layer 203 is further etched in a fourth etching process to form at least one third contact hole 2053. The third contact hole 2053 exposes a portion of the substrate 201 surface and has a bowl-shaped opening. Exemplarily, the fourth etching is a wet etching process. Wet etching of the remaining interlayer dielectric layer 203 may include the following steps: etching the remaining interlayer dielectric layer 203 using a mixed solution of hydrofluoric acid (HF) and ammonium fluoride (NH4F), wherein hydrofluoric acid is the main etching solution and ammonium fluoride is the buffer; etching the interlayer dielectric layer 203 through the fourth etching (i.e., wet etching) to form one or more third contact holes 2053, the wet etching time depending on the thickness of the interlayer dielectric layer 203. The third contact hole 2053 exposes part of the surface of the substrate 201. The third contact hole 2053 has a bowl-shaped opening structure, the sidewall of the third contact hole 2053 is arc-shaped, and the cross-sectional width of the third contact hole 2053 gradually decreases from the top to the bottom.

[0057] In one example, such as Figure 2J As shown, the remaining interlayer dielectric layer 203 forms a third cladding structure 2063 above the trench gate structure 7. The third cladding structure 2063 is an arc-shaped triangular cladding structure. Specifically, while forming the third contact hole 2053 after the fourth etching, the remaining interlayer dielectric layer 203 forms the third cladding structure 2063 on the corresponding trench gate structure 202. The third cladding structure 2063 corresponds to the trench gate structure 202, that is, a third cladding structure 2063 is provided above each trench gate structure 202, and the third cladding structure 2063 is an arc-shaped triangular cladding structure (that is, the third cladding structure 2063 has a triangular structure with arc-shaped sidewalls). The step coverage of the formed arc-shaped triangular cladding structure ensures that the step is flat after subsequent metal filling, achieving a planarization effect in one step. This reduces the process time and cost, and also helps stabilize the contact resistance in the contact hole, reducing the on-resistance.

[0058] In one example, such as Figure 2K As shown, after forming at least one third contact hole 2053, the method further includes: forming a metal layer 207, which covers the third envelope structure 2063 and fills the third contact hole 2053. Exemplarily, the metal layer 207 can be formed using processes such as sputtering, and the metal layer 207 fills the third contact hole 2053. The material of the metal layer can be a suitable conductive material such as aluminum, tungsten, or copper, without specific limitation. In another example, the metal layer 207 can also be deposited using other suitable deposition processes, such as PVD processes such as vacuum evaporation, without specific limitation.

[0059] It is worth mentioning that the above steps are only examples, and the order of the steps can be adjusted without conflict.

[0060] Thus, the process steps of the semiconductor device manufacturing method according to the embodiments of this application are completed. It is understood that the semiconductor device manufacturing method of this embodiment includes not only the above steps, but may also include other necessary steps before, during or after the above steps, all of which are included in the scope of the manufacturing method of this embodiment.

[0061] In summary, the semiconductor device manufacturing method of this application forms a photoresist layer with a preset angle in the interlayer dielectric layer, and uses the photoresist layer as a mask to etch the interlayer dielectric layer. This forms contact holes while simultaneously creating a cladding structure of the remaining interlayer dielectric layer on the trench gate structure. This eliminates the problem of uneven surface of the interlayer dielectric layer, ensures the flatness of the overall step after subsequent metal material filling, optimizes the process flow, saves process time, and reduces process costs.

[0062] Example 4

[0063] This application also provides a semiconductor device that can be prepared by the methods described in Embodiments 1, 2 and 3 above.

[0064] Below, refer to Figures 2A to 2K The semiconductor devices in the embodiments of this application are described in detail. It is worth mentioning that, in order to avoid repetition, only a brief description is given for the same components and structures as in the above embodiments. For specific explanations and descriptions, please refer to the descriptions in the above embodiments.

[0065] Specifically, such as 2A to Figure 2K As shown, the semiconductor device of this application includes: a substrate 201, in which at least one trench gate structure 202 is formed; a package-like structure disposed above the trench gate structure 202, with contact holes formed between the package-like structures, wherein the contact holes have a structure that is wider at the top and narrower at the bottom, and the contact holes expose a portion of the surface of the substrate 201; and a metal layer 207 covering the package-like structure and filling the contact holes.

[0066] This concludes the introduction to the structure of the semiconductor device of this application. The complete device may also include other components, which will not be described in detail here.

[0067] The semiconductor device provided in this application forms a photoresist layer with a preset angle in the interlayer dielectric layer, and uses the photoresist layer as a mask to etch the interlayer dielectric layer. This forms a contact hole while simultaneously creating a cladding structure on the trench gate structure with the remaining interlayer dielectric layer. This eliminates the problem of uneven surface of the interlayer dielectric layer, ensures the flatness of the overall step after subsequent metal material filling, optimizes the process flow, saves process time, and reduces process costs.

[0068] Example 5

[0069] This application also provides an electronic device comprising the semiconductor device described in Embodiment 4 or a semiconductor device manufactured by the methods described in Embodiments 1, 2 and 3.

[0070] The electronic device in this embodiment can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD player, DVD player, navigator, digital photo frame, camera, camcorder, voice recorder, MP3 player, MP4 player, PSP, etc., or it can be an intermediate product having the aforementioned semiconductor devices. The electronic device in this application embodiment has better performance because it uses the aforementioned semiconductor devices.

[0071] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will arise in the mind of those skilled in the art, all of which will fall within the spirit and scope of the concept disclosed herein. More specifically, various modifications and changes may be made in terms of the arrangement and / or components of the subject matter within the scope of this disclosure, the drawings, and the appended claims. In addition to modifications and changes in the components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The method includes: A substrate is provided in which at least one trench gate structure is formed; An interlayer dielectric layer is formed covering the substrate and the trench gate structure; A patterned photoresist layer with a preset angle is formed on the interlayer dielectric layer. The interlayer dielectric layer is etched using the photoresist layer as a mask to form at least one contact hole while the remaining interlayer dielectric layer forms a cladding structure above the trench gate structure. The contact hole has a structure that is wider at the top and narrower at the bottom, and the contact hole exposes a portion of the surface of the substrate.

2. The method as described in claim 1, characterized in that, The process involves forming a patterned photoresist layer with a predetermined angle on the interlayer dielectric layer, and etching the interlayer dielectric layer using the photoresist layer as a mask to form at least one contact hole while simultaneously forming a cladding structure of the remaining interlayer dielectric layer above the trench gate structure. This includes: A patterned first photoresist layer with a first preset angle is formed on the interlayer dielectric layer; Using the first photoresist layer as a mask, the interlayer dielectric layer is etched to form at least one first contact hole, while the remaining interlayer dielectric layer forms a first sac-like structure above the trench gate structure. The first contact hole exposes part of the substrate surface and has an inverted trapezoidal opening. The first sac-like structure is a triangular sac-like structure.

3. The method as described in claim 2, characterized in that, The first preset angle is between 60 and 85 degrees.

4. The method as described in claim 2, characterized in that, The etching gas used in the first etching includes at least one of the following: carbon tetrafluoride, trifluoromethane, and difluoromethane.

5. The method as described in claim 1, characterized in that, The process involves forming a patterned photoresist layer with a predetermined angle on the interlayer dielectric layer, and etching the interlayer dielectric layer using the photoresist layer as a mask to form at least one contact hole while simultaneously forming a cladding structure of the remaining interlayer dielectric layer above the trench gate structure. This includes: A patterned first photoresist layer with a first preset angle is formed on the interlayer dielectric layer; The first photoresist layer is used as a mask to perform a first etching on the interlayer dielectric layer to form at least one first contact hole, wherein the first contact hole exposes a portion of the surface of the substrate, and the first contact hole has an inverted trapezoidal hole opening structure; After forming the first contact hole, the remaining interlayer dielectric layer is reflowed to form at least one second contact hole while simultaneously forming a second cladding structure above the trench gate structure. The second contact hole exposes a portion of the substrate surface and has an arc-shaped opening. The second cladding structure is an arc-shaped cladding structure.

6. The method as described in claim 1, characterized in that, The process involves forming a patterned photoresist layer with a predetermined angle on the interlayer dielectric layer, and etching the interlayer dielectric layer using the photoresist layer as a mask to form at least one contact hole while simultaneously forming a cladding structure of the remaining interlayer dielectric layer above the trench gate structure. This includes: A patterned second photoresist layer with a second preset angle is formed on the interlayer dielectric layer; Using the second photoresist layer as a mask, a portion of the interlayer dielectric layer is etched a second time to form at least one arc-shaped hole opening in the interlayer dielectric layer; Continue etching the interlayer dielectric layer below the arc-shaped hole opening to form a trapezoidal hole opening located below the arc-shaped hole opening. The arc-shaped hole opening communicates with the trapezoidal hole opening and exposes a portion of the substrate surface. The second photoresist layer is removed, and the remaining interlayer dielectric layer is etched a fourth time to form at least one third contact hole while forming a third sac-like structure above the trench gate structure. The third contact hole exposes part of the substrate surface and has a bowl-shaped opening. The third sac-like structure is an arc-shaped triangular sac-like structure.

7. The method as described in claim 6, characterized in that, The second preset angle is 85 to 90 degrees.

8. The method as described in claim 6, characterized in that, The second and fourth etching processes are wet etching processes, wherein hydrofluoric acid is the main etching solution and ammonium fluoride is the buffer.

9. The method as described in claim 1, characterized in that, After forming at least one contact hole, the method further includes: forming a metal layer that covers the package-like structure and fills the contact hole.

10. A semiconductor device, characterized in that, The semiconductor device is formed by the manufacturing method of a semiconductor device as described in any one of claims 1 to 9.

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