Groove type VDMOS device and manufacturing method thereof

Abstract

The invention relates to the technical field of VDMOS, and discloses a groove type VDMOS device and a manufacturing method thereof. Comprising the following steps of substrate preparation and initial oxidation, active region and groove pattern definition, double-step groove etching and forming, gate medium and polysilicon gate integration, self-alignment body region and source region construction, interlayer medium deposition and contact hole etching, front face metallization and alloy annealing, wafer thinning and back face injection and metallization. According to the scheme, electric field distribution is optimized through a double-step groove, gate oxide reliability is improved, a deep P + body contact wall is integrated on a cellular boundary in a self-alignment mode, latch inhibition capacity is enhanced, a source region adopts self-alignment N + injection defined by a side wall, the source region and the P + wall form a controlled coplanar structure, source and body common contact is achieved, PN junction integrity is kept, extra photoetching is not needed in the process, and the cost is reduced. And a standard platform is compatible, and good balance is achieved among conduction performance, switching characteristics and manufacturing efficiency.

Description

Technical Field

[0001] This invention relates to the field of VDMOS technology, and in particular to a trench-type VDMOS device and its manufacturing method. Background Technology

[0002] Vertical double-diffused metal-oxide-semiconductor field-effect transistors (VDMOS) are core switching elements in modern power electronic systems. Based on structural differences, VDMOS is mainly divided into planar, trench, and superjunction types. Among them, trench VDMOS eliminates the limitation of the JFET effect region in the traditional planar structure by embedding the gate inside the silicon wafer, thereby achieving lower on-resistance and higher cell integration density, making it widely used in power management, motor drive, automotive electronics and other fields.

[0003] In the field of medium-voltage 60–150 V power devices, trench VDMOS is widely used in key scenarios such as server power supplies, new energy vehicle OBC / DC-DC converters, and industrial motor drives due to its advantages of low on-resistance and high cell density. However, existing manufacturing processes have long faced a fundamental challenge: to reduce on-resistance (RDS(on)), deeper and denser trench designs are required. However, such optimizations often exacerbate the concentration of internal electric fields in the device under high-voltage off-state, leading to a significant decrease in the reliability of the gate dielectric layer. Especially under severe stresses such as non-clamped inductive switches or high-temperature and high-humidity bias, early failure is likely to occur. On the other hand, if a conservative design is adopted to improve reliability, the on-performance is sacrificed, and the requirement for low loss cannot be met. Therefore, how to achieve low RDS(on) and high reliability simultaneously without significantly increasing process complexity has become the current problem for the upgrading of medium-voltage trench VDMOS technology. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies by proposing a trench-type VDMOS device and its manufacturing method.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A trench-type VDMOS device and its manufacturing method include the following steps: S1, substrate preparation and initial oxidation: providing an N-type substrate including an N-type epitaxial layer as the basic structure of the device, and forming an initial protective oxide layer; S2, active region and trench pattern definition: defining the active region window and trench pattern sequentially through photolithography and etching to provide an alignment reference for subsequent processes; S3, double-step trench etching and forming: forming a double-step trench structure with electric field modulation capability to actively control the internal electric field distribution in the device's off state; S4, gate dielectric and polysilicon gate integration: growing a gate oxide layer on the inner wall of the trench formed in step S3, depositing polysilicon inside the trench and on the wafer surface, and forming an independent trench gate through patterned etching; S5, self-aligned body region and source region construction: using the polysilicon gate as a mask, performing high-energy deep P-type etching sequentially. + Injection, P-body injection and co-annealing, then self-aligned N defined via sidewalls + Source region; S6, Interlayer dielectric deposition and contact hole etching: After depositing the interlayer dielectric and reflowing for planarization, the contact holes are etched by photolithography to prepare for the common metal contact; S7, Front metallization and alloy annealing: The alloy is sputtered and patterned, and then annealed to form a low-resistance ohmic contact source and gate interconnect structure; S8, Wafer thinning, backside implantation and metallization: The wafer is thinned, the backside is N-type heavily doped and activated by laser annealing to construct the drain ohmic contact.

[0007] As a preferred technical solution of the present invention, the double-step trench etching and shaping in step S3 includes the following steps: First trench etching: etching is performed based on the hard mask trench pattern formed in step S2 to form a rectangular initial trench; Thin layer oxidation: the wafer is transferred to a high-temperature oxidation furnace, and a uniformly thick sacrificial oxide layer is grown in a dry oxygen atmosphere; Isotropic wet etching: the wafer is immersed in a diluted hydrofluoric acid solution to remove the sacrificial oxide layer, while reducing the width of the central region at the bottom of the trench; Second trench etching: etching is performed again on the basis of the reduced width of the central region at the bottom of the trench, until the total depth of the trench is etched to the final target value. At this time, the overall structure of the trench presents a double-step shape that is wider at the top and narrower at the bottom.

[0008] As a preferred technical solution of the present invention, in the step S3 double-step trench etching and forming: the trench opening width of the first trench etching is 0.6~0.9μm; the trench opening width of the second trench etching is approximately the trench opening width of the first trench etching minus the thickness of the sacrificial oxide layer on both sides.

[0009] As a preferred technical solution of the present invention, in step S3, double-step trench etching and forming, the etching depth of the overall trench structure is 2.5~3.5μm.

[0010] As a preferred embodiment of the present invention, in the integration of the gate dielectric and the polysilicon gate in step S4, when the gate oxide layer is formed on the inner wall of the double-step trench formed in step S3, a three-stage cyclic oxidation process of dry-wet-dry is adopted, including the following steps: First dry oxygen stage: oxidation at 950°C in a high-purity O2 atmosphere for 10-15 minutes; wet oxygen stage: heating to 1000°C, switching to high-purity water vapor, and oxidation for 20-40 minutes; Second dry oxygen stage: switching back to the O2 atmosphere and oxidizing at 950°C for 10-15 minutes.

[0011] As a preferred technical solution of the present invention, in step S4, the gate dielectric and polysilicon gate integration is performed by LPCVD process for polysilicon deposition, and the deposition thickness on the wafer surface is 300~500 nm.

[0012] As a preferred embodiment of the present invention, step S5, self-aligned body region and source region construction, includes: deep P + P-body implantation: Using the patterned polysilicon gate strip from step S4 as a self-aligned masking layer, the wafer is placed in a high-energy ion implanter, with boron ions selected as the dopant source; P-body implantation and co-annealing: Conventional low-energy boron ion implantation is performed using an ion implanter to form a P-body, followed by furnace tube annealing at 1050~1100℃ in an N2 atmosphere for 30~60 minutes; Sidewall dielectric layer formation: Insulating dielectric sidewalls are constructed on the sidewalls of the polysilicon gate to provide lateral masking for subsequent self-aligned source region implantation; Self-aligned N + Source implantation: Under the action of the implantation window formed by two adjacent sidewalls, the heavily doped source region of the device is implanted.

[0013] As a preferred embodiment of the present invention, in step S6, interlayer dielectric deposition and contact hole etching, borosilicate glass is used as the interlayer dielectric material, and the deposition thickness is 800~1200 nm.

[0014] As a preferred embodiment of the present invention, in the S7 front-side metallization and alloy annealing process, after wafer thinning and back-side implantation are completed, laser annealing is performed immediately, with a wavelength of 308 nm and an energy density of 0.8~1.2 J / cm². 2 The pulse width is 20~30 ms.

[0015] And a trench-type VDMOS device, which is obtained by the manufacturing method described above.

[0016] The present invention has the following beneficial effects:

[0017] The trench-type VDMOS device and its fabrication method proposed in this solution achieve synergistic optimization in device structure and process integration: by constructing a double-stepped trench that is wider at the top and narrower at the bottom, the electric field distribution in the depletion region under off-state is controlled, and the peak electric field is transferred from the bottom corner of the trench to the shoulder of the step, which helps to improve the long-term reliability of the gate oxide dielectric; deep P + The body contact walls are self-aligned at the cell boundaries, providing a low-impedance hole discharge path for the P-body region and enhancing the latch-up suppression capability of the device under avalanche or inductive switching transients. The source region employs a self-aligned N-type design defined by the sidewalls. + The implantation process enables N to be implanted without adding an additional photolithography layer. + The source region is located at the cell center, with deep P regions preserved on both sides. + In the wall surface area, the two form a controlled coplanar layout on the silicon surface, which not only ensures the electrical connection of the source and body sharing the same contact, but also maintains the integrity of the PN junction. The overall process flow is compatible with standard power device platforms, taking into account conduction performance, switching characteristics and manufacturing efficiency. Attached Figure Description

[0018] Figure 1 This is a flowchart of a trench-type VDMOS device manufacturing method proposed in this invention;

[0019] Figure 2 This is a structural diagram of the trench-type VDMOS device proposed in this invention after step 4;

[0020] Figure 3 This is a structural diagram of the trench-type VDMOS device proposed in this invention after step 7;

[0021] Figure 4 This is a structural diagram of the trench-type VDMOS device proposed in this invention after step 8;

[0022] Figure 5 This is a structural diagram of the trench-type VDMOS device proposed in this invention after step 9;

[0023] Figure 6 This is a structural diagram of the trench-type VDMOS device proposed in this invention after step 10.

[0024] Figure 7 This is a structural diagram of the trench-type VDMOS device proposed in this invention after step 11;

[0025] Figure 8 This is a structural diagram of the trench-type VDMOS device proposed in this invention after interlayer dielectric deposition in step 12;

[0026] Figure 9This is a structural diagram of the trench-type VDMOS device proposed in this invention after contact hole etching in step 12;

[0027] Figure 10 This is a structural diagram of the trench-type VDMOS device proposed in this invention after step 15.

[0028] In the figure: 1. N-type substrate; 11. Drain contact region; 2. N-type epitaxial layer; 21. Trench 1; 22. Trench 2; 23. Deep P + 24. Contact wall; 25. Body region; 26. Source region; 3. Gate oxide layer; 4. Polysilicon; 5. Sidewall dielectric layer; 6. Interlayer dielectric layer; 61. Contact hole; 7. Upper metal layer; 8. Lower metal layer. Detailed Implementation

[0029] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0030] Reference Figure 1 The present invention provides a method for manufacturing a trench-type VDMOS device, comprising the following steps:

[0031] Step 1, Substrate Preparation and Initial Oxidation: Provides the basic structure for the device and forms the initial protective or buffer oxide layer. Please refer to the appendix for details. Figure 2 The basic structure is an N-type substrate 1 with an N-type epitaxial layer 2. It should also be noted that only one cell structure is shown in the figure. This protective or buffer oxide layer is used to buffer the stress generated by subsequent silicon nitride deposition, as a masking layer for subsequent etching or implantation, and at the same time to prevent defects from forming on the silicon surface at high temperature.

[0032] More specifically, N-type epitaxial wafers (N-epi) with a resistivity of 3-8 Ω·cm and a thickness of 8–15 μm are selected. N-epi with these parameters are suitable for medium-voltage devices (60V~150V). They are grown on low-resistivity N-type silicon substrates. After standard RCA cleaning, an initial oxide layer of 50~100 nm thickness is grown in a dry oxygen or humid oxygen environment at 950~1050℃ using a vertical or horizontal diffusion furnace such as the TELCleanTrack series.

[0033] Step 2, Active Area Photolithography and Etching: Define the active area of ​​the device. By patterning and etching windows on the initial oxide layer, the underlying N-type epitaxial silicon surface is exposed, providing a precise positioning reference for subsequent key processes such as P-body implantation and trench etching. Simultaneously, the unetched oxide layer area will serve as a field region, achieving electrical isolation between adjacent devices. Specifically:

[0034] First, g / i-line positive photoresist with a thickness of 1~1.5μm is coated on the initial oxide layer formed in step 1. After pre-baking, exposure and development are performed using a NIKONi12 stepper lithography machine to form the active region window pattern.

[0035] Subsequently, using photoresist as a mask, dry etching equipment such as LamResearch2300 was used, and a mixture of CF4 and O2 gas (typical flow ratio 30 / 10 sccm) was introduced to perform anisotropic etching at a chamber pressure of 80 mTorr and a WICP power of 400 WICP.

[0036] After etching, the silicon surface is successively aerated by O2 plasma and wet-processed with hot sulfuric acid and hydrogen peroxide. Then, it is cleaned by SC-1 in standard RCA and treated with diluted HF (DHF) to remove particles, organic residues and natural oxide layer. Finally, it is rinsed and dried with high-purity deionized water to obtain a clean silicon surface, laying the foundation for subsequent processes.

[0037] Step 3, Trench Lithography: Define the precise location and cell layout of the trench gate. First, deposit a 200nm thick Si3N4 hard mask and a 300nm thick TEOS oxide layer on the silicon wafer surface as an etch-resistant barrier layer. Then, apply i-line photoresist and expose and develop it using a NIKONi12 lithography machine to form a periodically arranged trench pattern. The key dimensions are set according to the target cell spacing, with typical values ​​of 0.8~1.2μm.

[0038] Step 4, Double-step trench etching and shaping: Forming a double-step trench structure with electric field modulation capability. Please refer to... Figure 2 The double-step trench structure consists of trench 1 (21) and trench 2 (22), which actively regulates the internal electric field distribution in the device's off-state state, alleviating the electric field concentration problem at the bottom corner (TBC) of the trench, thereby improving gate oxide reliability. Simultaneously, it creates structural conditions for reducing on-resistance, specifically including:

[0039] First trench etching: Based on the hard mask pattern formed in step 3, a Plasmatherm 790 or LamResearch Kiyo series ICP etching equipment is used to perform high aspect ratio silicon etching under low temperature conditions of -40℃ to -20℃. A mixed gas of SF6, C4F8, and O2 (flow ratio: SF6: 80 sccm, C4F8: 20 sccm, O2: 5 sccm) is introduced. The target etching depth H = H1 + H2 = 2.5~3.5 μm, the first trench etching depth H1 = 0.8~1.2 μm, and H2 is the second trench etching depth. A rectangular initial trench with a sidewall verticality better than 88°, namely trench 21, is formed. The opening width of trench 21 is denoted as W1, and the range of W1 is 0.6~0.9 μm.

[0040] Thin-layer oxidation: The wafer is transferred to a high-temperature oxidation furnace, where a uniform sacrificial oxide layer is grown in a dry oxygen atmosphere at 850~950℃. The thickness is controlled at 30~60nm. Due to the isotropic nature of the oxidation process, the oxide layer grows simultaneously on the sidewalls and bottom of the trench, resulting in a slight reduction in the effective width and depth of the trench.

[0041] Isotropic wet etching (DHF): The wafer is immersed in a diluted hydrofluoric acid solution, HF:H2O=1:(50~100), and processed at room temperature for 30~90 seconds. This step uniformly removes the oxide layer, and due to the slight isotropic etching effect of HF on silicon, an additional lateral etching distance approximately equal to the oxide layer thickness is made in the central region at the bottom of the original trench, causing the width of the central region at the bottom of the trench to shrink from W1 to W2, where W2≈W1-2×oxide layer thickness. For example, if W1=0.6μm and the oxide layer thickness is 50nm, then W2≈0.5μm. At this time, the cross-section of the trench forms an inward-shrinking "step" feature at the bottom.

[0042] Second trench etching: ICP etching is used again to etch the total depth of the trench to the final target value H, resulting in trench 22. At this time, the overall structure of the trench presents a double-step shape that is wider at the top and narrower at the bottom.

[0043] When the device is turned off and withstands a high drain-source voltage (VDS), N - The depletion region between the epitaxial layer and the P-body extends from bottom to top. When the depletion front reaches the step shoulder at the junction of W1 and W2, this location becomes the region with the largest potential gradient due to the geometric change. A large number of electric field lines converge and terminate here, making it a new controllable electric field peak point. The actual trench bottom, i.e. the width W2 region, located further below, is "shielded" by the depletion region above, and the electric field strength it bears is significantly reduced. This mechanism effectively avoids premature breakdown of the gate oxide at TBC, and the gate oxide TDDB lifetime can be greatly improved. At the same time, it allows for the design of deeper trenches, further reducing the on-resistance RDS(on), and improving the reliability and operating performance of the device.

[0044] Step 5, Gate oxide growth: A gate oxide layer 3 with uniform thickness, low interface state density and high breakdown field strength is formed on the inner wall of the double-step trench formed in step 4. It serves as the insulating medium and electric field control core of the MOS structure. Specifically, the wafer after trench formation is thoroughly cleaned: SC-1 solution is used to remove particles and organic residues in sequence, and then diluted HF is used to remove the natural oxide layer to ensure that the oxide interface is free of contamination.

[0045] After thorough cleaning, the wafer is placed in a high-precision vertical oxidation furnace equipped with an in-situ high-purity steam generator, such as the TELAW-8200 or Kokusai DG series, to perform a three-stage dry-wet-dry cyclic oxidation process to grow a 30-60 nm thick gate oxide layer. The wet oxidation step is used to accelerate growth, while the preceding and following dry oxidation steps are used to improve interface quality. Specifically, these steps include:

[0046] The first dry oxygen stage: Oxidize for 10-15 minutes at 950℃ in a high-purity O2 atmosphere (flow rate of 3-5 slm) to grow an initial thin oxide layer of about 5-10 nm. The main function of this stage is to form a high-quality Si-SiO2 interface, effectively passivate the dangling bonds on the silicon surface, and significantly reduce the interface state density.

[0047] Humidification stage: The temperature is raised to 1000℃ and switched to high-purity water vapor. The water vapor is generated by the on-site cracking of H2 and O2 by the ISG system to avoid metal contamination. The oxidation continues for 20 to 40 minutes. The diffusion rate of water molecules is much higher than that of oxygen, which can greatly accelerate the oxidation process and efficiently build the thickness of the main oxide layer. At this time, the target total thickness is 20 to 45 nm.

[0048] The second dry oxygen stage: switch back to the O2 atmosphere and oxidize at 950°C for 10-15 minutes. This step densifies the surface of the wet oxygen layer, reduces the content of OH⁻ groups, improves the overall uniformity and dielectric strength of the oxide layer, and further optimizes the interface characteristics.

[0049] Through the above process, a gate oxide layer with a total thickness of 30~60 nm is finally formed on the sidewall and bottom of the trench. The synergy of the dry-wet-dry process can ensure the growth efficiency and interface quality of the oxide layer, effectively cover the geometrically complex W1 and W2 transition regions in the double-step trench, and avoid oxidation weak points caused by stress concentration at the step.

[0050] Step 6: Polycrystalline Silicon Gate Deposition and Doping: Fill the trenches and uniformly deposit and dope a layer of conductive polycrystalline silicon 4 on the entire wafer surface to serve as the gate material for the device and form a conductive gate. First, the cleaned wafer is placed into a low-pressure chemical vapor deposition (LPCVD) furnace tube system. Deposition is carried out at a temperature window of 580~620℃, using high-purity silane with a flow rate of 100~200 sccm as the source gas, and at a reaction chamber pressure of 0.2~0.4 Torr. It should be noted that this temperature range ensures that the deposited silicon film is amorphous, guaranteeing that it covers the complex three-dimensional morphology of the double-step trench. In subsequent high-temperature processes where the temperature exceeds 650℃, the amorphous silicon will naturally recrystallize into polycrystalline silicon. That is, the material used in this step is amorphous silicon, and the final device is polycrystalline silicon. This step is directly named polycrystalline silicon according to the final function and morphology of the material in the device.

[0051] It is worth noting that since the bottom width W2 of the trench is smaller than the upper width W1, higher requirements are placed on the conformal deposition of polysilicon. The LPCVD process can ensure its step coverage capability, which can ensure that a continuous and dense polysilicon film is formed even in the W2 region, avoiding gate open circuit or local electric field distortion caused by film breakage or voids, thereby ensuring device reliability and parameter consistency.

[0052] The deposition thickness is controlled at 300~500nm: if it is too thin, it may cause "bridging" at the top of the trench or excessive resistance; if it is too thick, it is easy to generate residue or increase stress during etching. For trenches with a depth of about 3μm and an opening width of 0.6~0.9μm, 400nm is preferred.

[0053] After deposition, N-type heavy doping is performed immediately to reduce the sheet resistance of the polysilicon gate and improve the gate charge and discharge speed, so that the sheet resistance of the polysilicon gate is lower than 20Ω / sq. This low resistance characteristic can significantly reduce the gate RC delay and improve the device switching speed, especially in high-frequency applications such as server VRM and fast charging.

[0054] The doping methods include:

[0055] In-situ POCl3 doping: In the same LPCVD chamber, phosphorus oxychloride (POCl3) gas is introduced at the end of silicon deposition at a partial pressure of about 0.1~0.3 Torr, and co-deposition doping is carried out at 600℃. This method has high process integration and good doping uniformity, and is suitable for mass production.

[0056] Ion implantation doping: After depositing undoped polysilicon, arsenic or phosphorus ions are implanted using an ion implanter to form N₂. + Polycrystalline silicon gate, implantation energy of 80 keV, dose of 5 × 10⁻⁶ 15 cm -2 This method allows for more precise and controllable doping concentration, but requires additional photolithography masking, typically using photoresist to cover the field area.

[0057] Step 7, Polysilicon Gate Lithography and Etching: Used to etch the entire N-facet deposited in Step 6. + Polysilicon is patterned in four layers to form independent trench gate structures, see attached diagram. Figure 3 First, the gate strip pattern is defined using i-line photolithography. Then, anisotropic etching of the polysilicon is performed using a plasma dry etching process with a mixed gas of HBr, Cl2, and O2, precisely terminating at the gate oxide layer surface to ensure that the 30-60nm thick gate dielectric underneath is not damaged. After etching, residual polymer and particles are removed by plasma resist removal and standard wet cleaning to obtain a clean gate structure.

[0058] Step 8, Deep P + Injection into the body contact wall: Please refer to the following for details. Figure 4Through a single high-energy ion implantation, a deep P-epi line is constructed in the boundary region of each cell, extending vertically from the silicon surface into the interior of the N-epi. + Contact wall 23, serving as a low-resistance potential clamping path in the P-body region, suppresses the conduction of parasitic bipolar transistors, thereby improving the device's latch-up immunity and avalanche energy tolerance. Specifically:

[0059] Using the patterned polysilicon gate strips from step 7 as a self-aligned masking layer, the wafer is placed in a high-energy ion implanter. Boron ions are selected as the dopant source, with an implantation energy of 180~250 keV and a dose of 2×10⁻⁶. 14 ~5×10 14 cm -2 This high-energy condition ensures that boron atoms penetrate the subsequently formed P-body region and form P-body regions with a depth of 2.0~2.5 μm in the N-type epitaxial layer 2. + Type-3 doped regions; because implantation occurs within the exposed silicon windows on both sides of the polysilicon gate and is periodically arranged along the cell array, the resulting P-type doped regions... + The region, in its three-dimensional structure, presents itself as a continuous "wall-like" structure surrounding each cell, i.e., deep P. + Body contact wall 23.

[0060] The core principle of this fabrication method lies in latch-up suppression: when the device is turned off due to avalanche or inductive load shutdown, holes accumulate in the P-body region due to the generation of electron-hole pairs. If there is no effective discharge path, the P-body potential rises, which may trigger latch-up by N... + Source, P-body, N-epi, N + The parasitic NPN transistor formed by the substrate conducts, leading to thermal runaway and device failure. In contrast, the deep P-type transistor in this solution... + Contact wall 23, with its high doping level and sufficient depth, provides an ultra-low resistance channel directly to the source metal, allowing holes to be rapidly extracted. The P-body potential is firmly clamped at the source potential, preventing the parasitic BJT base from reaching the 0.7V turn-on voltage, thus eliminating latch-up from a physical mechanism.

[0061] In addition, the structure also has:

[0062] Supports cell miniaturization: Traditional volume contacts require an independent layout area, which limits cell miniaturization; however, this solution integrates volume contacts into the cell boundary, eliminating the need for additional contact holes, allowing cell spacing to be safely reduced to below 1.0μm.

[0063] Optimize source region layout: Deep P + Contact wall 23 is located at the edge of the cell, and the middle region is completely left to N. + The source region, by maximizing the source contact area, helps to reduce the total source resistance (RS).

[0064] Step 9: P-body injection and co-annealing: Please refer to the appendix. Figure 5 This forms the MOS channel region and simultaneously activates the deep P injected in step 8. + Impurities are eliminated, and integrated heat treatment of the bulk structure is achieved. Conventional B2O2 processing is performed using an ion implanter. + Injection to form P-type body region 24, wherein the injection energy is 60~80 keV and the dose is 1×10 14 ~5×10 14 cm -2 ;

[0065] Furnace tube annealing is performed at 1050~1100℃ in an N2 atmosphere for 30~60 minutes.

[0066] This annealing process can activate impurities, making the bulk region 24 and deep P... + Boron atoms in contact wall 23 enter substitutional sites, forming electrically active doping; simultaneously, they advance the junction depth, causing the bulk region 24 to diffuse downwards, making its bottom connect with the deep P-type region. + The contact wall 23 achieves good overlap in the vertical direction, ensuring that the entire volume region 24 can pass through the deep P. + Contact wall 23 is effectively grounded, thereby maximizing the latch-up suppression effect.

[0067] Step 10, Formation of the sidewall medium layer: Please refer to the appendix. Figure 6 An insulating sidewall dielectric layer 5 is constructed on the sidewalls of the polysilicon gate to provide precise lateral masking for subsequent self-aligned source region implantation. Specifically, a silicon dioxide thin film with a thickness of 80-120 nm is first uniformly deposited on the wafer surface using plasma-enhanced chemical vapor deposition (PECVD). Subsequently, an anisotropic etching process is performed using a dry etching machine without photoresist masking. By adjusting the ratio of etching gases such as CF4 and CHF3 and the bias power, only the silicon dioxide structure closely attached to both sides of the polysilicon gate is selectively retained, while the remaining areas, including the horizontal surface, are completely removed, thereby forming a sidewall dielectric layer 5 with a clear outline and controllable thickness.

[0068] The position of this sidewall is determined by the polysilicon gate self-alignment, and its outer edge will directly define the subsequent N. + In this design, the thickness of the sidewall dielectric layer 5 at the injection boundary of the source region is controlled at approximately 100 nm. This effectively isolates the source region from the channel, preventing short-channel effects, while also avoiding excessive encroachment on the source region contact area, thus providing process assurance for achieving low source resistance and high cell density.

[0069] Step 11: Self-alignment N + Source implantation: forms the heavily doped source region of the device, and merges with the deep P-type region. +Contact wall 23 achieves a controlled lateral isolation layout on the silicon surface, ensuring reliable electrical connection between the source and body regions without adding additional photolithography steps, eliminating the risk of short circuits, and maximizing the effective contact area of ​​the source metal. For details, please refer to the appendix. Figure 7 High-dose N-type ion implantation is performed by directly using the sidewall dielectric layer 5 formed in step 10 and the polycrystalline silicon 4 as a masking structure.

[0070] Injection using As + or P + The injected energy is 40~60keV, and the dose is 5×10⁻⁶. 15 ~1×10 16 cm -2 This energy window ensures that impurities only penetrate the shallow layer of the silicon surface, with a junction depth of approximately 0.2–0.3 μm, forming low-resistivity N₂. + Source region 25, without interfering with the underlying P-type body region 24 or deep P. + The deep doping distribution of contact wall 23, due to the sidewalls covering both sides of the polysilicon gate, restricts the actual exposed silicon implantation window to the central region between the two sidewalls, which is located precisely in the deep P-layer region. + Within the transverse region occupied by contact wall 23, i.e., N + Injection is in deep P + The process takes place in the central sub-region at the top of contact wall 23, where high-concentration N-type impurities completely compensate for and reverse the original P-type impurities. + Doping makes this local surface layer composed of P + Transform into N + ; and deep P + The areas on both sides of the top of contact wall 23 that are not covered by injection, i.e., the parts blocked by the side walls, remain P. + type;

[0071] This step utilizes the existing gate structure as a mask to automatically define the location of the source region 25, eliminating photolithography alignment errors and ensuring that the source region 25 is highly consistent with the channel boundary position. This improves the uniformity of device parameters, including the uniformity of the device threshold voltage (Vth) and on-resistance (RDS(on)). In subsequent processes, the source metal will simultaneously cover the N... + Source region 25 and the deep P on both sides + Contact wall 23, both are forced to be connected to the same electrode, i.e., the source, which is usually grounded, due to N + With P + At the same potential, the PN junctions are in a zero-biased or slightly reverse-biased state, with no forward conduction current, thus not constituting an electrical short circuit. Furthermore, the entire central region of the cell is completely released for source metal contact, significantly increasing the effective contact area, reducing source series resistance, and consequently reducing conduction losses. Moreover, the controlled N... + With P +The layout significantly reduces off-state leakage current, improves avalanche breakdown stability, and enhances latch-up resistance.

[0072] Step 12: Interlayer dielectric deposition and contact hole etching: An insulating interlayer dielectric layer 6 is formed on the device surface after source region 25 and body region 24 implantation. Contact holes 61 are formed on the interlayer dielectric layer 6 to achieve electrical connection between the source and body regions to the metal layer. Please refer to the appendix. Figure 8 and attached Figure 9 Specifically, borosilicate glass (BPSG) is first used as the interlayer dielectric material, and a BPSG film with a thickness of 800~1200nm is deposited on the wafer surface through atmospheric pressure chemical vapor deposition (APCVD) or plasma enhanced chemical vapor deposition (PECVD) processes; then, reflow annealing is performed at 850~900℃ to planarize the BPSG surface and improve the performance of subsequent photolithography and metal coverage.

[0073] Subsequently, the contact window pattern between the source and bulk regions was defined using photolithography, and anisotropic etching was performed using a dry etching apparatus with fluorine-based gas to penetrate the BPSG dielectric layer, exposing the underlying N-type dielectric. + Source region 25 and deep P + Contact wall area 23.

[0074] Step 13, Front-side metallization: Through metal deposition and patterning, ohmic contacts and interconnect structures for the source and gate are formed on the front side of the wafer, resulting in the upper metal layer 7, as shown below. Figure 10 As shown.

[0075] First, a physical vapor deposition process is used to sputter a layer of aluminum-silicon-copper alloy with a thickness of 3~5μm, wherein Si: 1.0wt%, Cu: 0.5wt%, and the balance is Al. This alloy has good conductivity, anti-electromigration ability, and contact characteristics with silicon. Then, the metal pattern is defined by photolithography, and excess metal is removed by dry etching or wet etching using chlorine-based plasma, retaining the source pads, gate leads, and internal interconnects.

[0076] After etching, the alloy is annealed at 400-450°C for about 30 minutes in a nitrogen-hydrogen mixed atmosphere (N2: 95%, H2: 5%) to promote the bonding between the aluminum and the nitrogen atoms below. + Source area, deep P + A low-resistance, stable ohmic contact is formed between the contact wall 23 and the polysilicon gate, which at the same time relieves the stress at the metal-dielectric interface and improves long-term reliability.

[0077] Step 14: Wafer Thinning and Backside Implantation: To prepare for forming low-resistivity backside source and drain contacts, the wafer with completed frontside processing is mechanically ground and chemically mechanically polished from the backside to reduce its total thickness to a target value suitable for medium-voltage power device applications. Specifically, the wafer thickness is first reduced to approximately 150-200 μm through rough grinding on the backside, followed by fine grinding and CMP treatment, ultimately controlling the total wafer thickness within the range of 100-150 μm.

[0078] After thinning, immediately perform back-side N-type laser treatment. + Heavy doping implantation yields drain contact region 11, using phosphorus or arsenic ions at a dose of 5 × 10⁻⁶. 15 ~1×10 16 cm -2 The energy is 60~100keV.

[0079] Step 15, Laser Annealing and Backside Metallization: High-dose impurities are injected into the backside using an ultra-low thermal budget method to form high-performance ohmic contacts. This achieves extremely low backside contact resistance and excellent high-temperature reliability without damaging the precision structure on the front side. Specifically, this includes:

[0080] Laser annealing: Immediately after wafer thinning and backside implantation in step 14, laser annealing is performed using an XeCl excimer laser annealing system with a wavelength of 308 nm and an energy density controlled between 0.8 and 1.2 J / cm². 2 With a pulse width of 20~30ms, the back side of the wafer is irradiated by high-speed scanning. Under these conditions, the laser energy is efficiently absorbed by the silicon surface, causing the injected area to melt instantly and recrystallize rapidly, achieving an ultra-high activation rate of electroactive impurities. Furthermore, due to the extremely short laser action time, the heat does not have time to be conducted into the wafer, thus avoiding thermal disturbance to the gate oxide, polysilicon gate, sidewall dielectric, and front Al-Si-Cu metal layer, ensuring that the integrity of all the precision structures in the early stage is not affected.

[0081] Backside metallization: After laser annealing, backside metal stacking is performed in a clean environment to obtain the lower metal layer 8. Specifically, the following thin films are sequentially sputtered using physical vapor deposition:

[0082] Titanium (Ti): 20~50nm, used as a silicide forming layer and adhesion layer;

[0083] Titanium nitride (TiN): 30~50nm, used as a diffusion barrier layer;

[0084] Nickel-vanadium alloy (NiV, containing approximately 5–10% V): 100~200 nm, used to form stable, low-resistivity silicide phases;

[0085] Silver (Ag): 1~2μm, used as the main conductive layer, with excellent conductivity and solderability;

[0086] Subsequently, rapid thermal annealing is carried out in a nitrogen atmosphere at 350~400℃ for 10~20 minutes to promote the reaction of Ti, NiV and silicon to generate low-resistivity silicides such as TiSi2 and NiSi, ultimately forming a high-quality ohmic contact Q. Compared with traditional aluminum backing, the NiV and Ag system has better high-temperature stability and anti-electromigration ability.

[0087] Step 16, Packaging: After completing the above steps, the wafer enters the standard packaging process, which includes dicing, mounting, bonding, molding, electroplating, and testing.

[0088] Based on the above manufacturing method, the present invention also provides a trench-type VDMOS device, which is fabricated using the above manufacturing method. The trench-type VDMOS effectively alleviates the electric field concentration at the bottom of the gate through a double-step trench structure, improving gate oxide reliability and deep P-type VDMOS. + Contact wall 23 provides a low-resistance hole discharge path, enhances latch-up and avalanche resistance, and its fully self-aligned process eliminates the need for additional photolithography, balancing high performance, high reliability, and mass production cost, making it suitable for medium-voltage, high-frequency applications.

[0089] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A method for manufacturing a trench-type VDMOS device, characterized in that, Includes the following steps: S1. Substrate preparation and initial oxidation: Provide an N-type substrate including an N-type epitaxial layer as the basic structure of the device, and form an initial protective oxide layer; S2. Definition of active area and trench pattern: The active area window and trench pattern are defined sequentially by photolithography and etching to provide an alignment reference for subsequent processes; S3. Double-step trench etching and forming: Forming a double-step trench structure with electric field modulation capability to actively regulate the internal electric field distribution of the device in the off state; S4. Integration of gate dielectric and polysilicon gate: A gate oxide layer is grown on the inner wall of the trench formed in step S3, and polysilicon is deposited inside the trench and on the wafer surface. Independent trench gates are formed by patterning etching. S5. Construction of self-aligned body and source regions: Using a polysilicon gate as a mask, high-energy deep P-type resonant phases are sequentially constructed. + Injection, P-body injection and co-annealing, then self-aligned N defined via sidewalls + Source region; S6. Interlayer dielectric deposition and contact hole etching: After depositing the interlayer dielectric and reflowing for planarization, the contact holes are etched by photolithography to prepare for shared metal contacts. S7. Front-side metallization and alloy annealing: Sputter alloy and pattern it, then anneal it to form a source and gate interconnect structure with low resistance ohmic contact. S8. Wafer thinning, backside implantation and metallization: The wafer is thinned, the backside is N-type heavily doped and activated by laser annealing to build a drain ohmic contact.

2. The method for manufacturing a trench-type VDMOS device according to claim 1, characterized in that, Step S3, double-step trench etching and shaping, includes the following steps: First trench etching: Etching is performed based on the hard mask trench pattern formed in step S2 to form a rectangular initial trench; Thin-layer oxidation: The wafer is transferred to a high-temperature oxidation furnace, where a uniformly thick sacrificial oxide layer is grown in a dry oxygen atmosphere; Isotropic wet etching: The wafer is immersed in a diluted hydrofluoric acid solution to remove the sacrificial oxide layer, while reducing the width of the central region at the bottom of the trench; Second trench etching: The width of the central area at the bottom of the trench is reduced, and etching is performed again until the total depth of the trench is etched to the final target value. At this time, the overall structure of the trench presents a double-step shape that is wider at the top and narrower at the bottom.

3. The method for manufacturing a trench-type VDMOS device according to claim 2, characterized in that, In step S3, double-step trench etching and shaping: The opening width of the trench in the first trench etching is 0.6~0.9μm; The opening width of the second trench etching is approximately the opening width of the first trench etching minus the thickness of the sacrificial oxide layer on both sides.

4. The method for manufacturing a trench-type VDMOS device according to claim 3, characterized in that, In step S3, double-step trench etching and shaping: The overall etching depth of the trench structure is 2.5~3.5μm.

5. The method for manufacturing a trench-type VDMOS device according to claim 4, characterized in that, In step S4, when integrating the gate dielectric with the polysilicon gate, a three-stage cyclic oxidation process (dry-wet-dry) is used to form the gate oxide layer on the inner wall of the double-step trench formed in step S3, including the following steps: First dry oxygen stage: Oxidation at 950℃ in a high-purity O2 atmosphere for 10-15 minutes; Humidification stage: Heat to 1000℃, switch to high-purity water vapor, and oxidize for 20~40 minutes; Second dry oxygen stage: Switch back to O2 atmosphere and oxidize at 950℃ for 10~15 minutes.

6. The method for manufacturing a trench-type VDMOS device according to claim 5, characterized in that, In step S4, the gate dielectric and polysilicon gate integration is performed using LPCVD process, with a deposition thickness of 300~500 nm on the wafer surface.

7. The method for manufacturing a trench-type VDMOS device according to claim 6, characterized in that, The step S5, self-aligned body region and source region construction, includes: Deep P + Bulk contact wall implantation: Using the polysilicon gate strip patterned in step S4 as a self-aligned masking layer, the wafer is placed in a high-energy ion implanter, and boron ions are selected as the doping source. P-body implantation and co-annealing: P-body was formed by conventional low-energy boron ion implantation using an ion implanter, followed by furnace tube annealing at 1050~1100℃ in an N2 atmosphere for 30~60 min. Sidewall dielectric layer formation: Insulating dielectric sidewalls are constructed on the sidewalls of the polysilicon gate to provide lateral masking for subsequent self-aligned source region implantation; Self-aligned N + Source implantation: Under the action of the implantation window formed by two adjacent sidewalls, the heavily doped source region of the device is implanted.

8. The method for manufacturing a trench-type VDMOS device according to claim 1, characterized in that, In step S6, interlayer dielectric deposition and contact hole etching, borosilicate glass is used as the interlayer dielectric material, and the deposition thickness is 800~1200 nm.

9. The method for manufacturing a trench-type VDMOS device according to claim 1, characterized in that, In the S7 front-side metallization and alloy annealing process, laser annealing is performed immediately after wafer thinning and back-side implantation are completed, with a wavelength of 308 nm and an energy density of 0.8~1.2 J / cm². 2 The pulse width is 20~30 ms.

10. A trench-type VDMOS device, characterized in that, The trench-type VDMOS device is manufactured using the method for manufacturing trench-type VDMOS devices according to any one of claims 1-9.

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