Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a semiconductor device manufacturing method. The semiconductor device includes: a substrate having a first surface and a second surface facing the first surface; a first nitride semiconductor layer having a third surface in contact with the second surface and a fourth surface facing the third surface, the fourth surface having a recess formed therein; and a second nitride semiconductor layer provided in the recess, in which an opening is formed in the substrate and the first nitride semiconductor layer, the opening penetrating through the substrate and the first nitride semiconductor layer and reaching the second nitride semiconductor layer, and the second nitride semiconductor layer has a bottom surface, the semiconductor device includes a first metal layer that covers the first surface and an inner wall surface of the opening and is in contact with the second nitride semiconductor layer at the bottom surface, and the second nitride semiconductor layer contains impurity atoms at a concentration of 1.0 * 1018 cm-3 or more.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device. Background Technology

[0002] A semiconductor device is known as follows: a metal layer is formed on a semiconductor layer containing a high concentration of charge carriers as an ohmic contact layer with the semiconductor layer as an etch stopper, a through-hole is formed in the semiconductor layer that reaches the etch stopper, and an electrode that contacts the etch stopper is formed in the through-hole.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2011-077434

[0006] Patent Document 2: Japanese Patent Application Publication No. 2020-017647

[0007] Patent Document 3: Japanese Patent Application Publication No. 2024-092747

[0008] In conventional semiconductor devices, the contact resistance between the electrode and the semiconductor layer can sometimes increase, resulting in a lower yield. Summary of the Invention

[0009] The purpose of this disclosure is to provide a semiconductor device and a method for manufacturing a semiconductor device that can improve yield.

[0010] The semiconductor device disclosed herein includes: a substrate having a first surface and a second surface opposite to the first surface; a first nitride semiconductor layer having a third surface contacting the second surface and a fourth surface opposite to the third surface, wherein a recess is formed on the fourth surface; and a second nitride semiconductor layer disposed in the recess, wherein an opening is formed in the substrate and the first nitride semiconductor layer, wherein the opening penetrates the substrate and the first nitride semiconductor layer and reaches the second nitride semiconductor layer, the opening having a bottom surface in the second nitride semiconductor layer, the semiconductor device having a first metal layer, wherein the first metal layer covers the inner wall surface of the first surface and the opening, and contacts the second nitride semiconductor layer on the bottom surface, the second nitride semiconductor layer having an opening at a depth greater than or equal to 1.0 × 10⁻⁶. 18 cm -3 The concentration contains impurity atoms.

[0011] Invention Effects

[0012] According to this disclosure, the yield rate can be improved. Attached Figure Description

[0013] Figure 1 This is a diagram showing the layout of the gate electrode and drain wiring in the semiconductor device of the first embodiment.

[0014] Figure 2 This is a cross-sectional view showing the semiconductor device according to the first embodiment.

[0015] Figure 3 This is a diagram showing the band structure of the semiconductor layer (regenerated layer).

[0016] Figure 4 This is a cross-sectional view (one of the first examples) showing a method for manufacturing a semiconductor device according to the first embodiment.

[0017] Figure 5 This is a cross-sectional view (second example) showing a first example of a method for manufacturing a semiconductor device according to the first embodiment.

[0018] Figure 6 This is a cross-sectional view (third example) showing a first example of a method for manufacturing a semiconductor device according to the first embodiment.

[0019] Figure 7 This is a cross-sectional view (fourth example) showing a first example of a method for manufacturing a semiconductor device according to the first embodiment.

[0020] Figure 8 This is a cross-sectional view (fifth) showing a first example of a method for manufacturing a semiconductor device according to the first embodiment.

[0021] Figure 9 This is a cross-sectional view (sixth) showing a first example of a method for manufacturing a semiconductor device according to the first embodiment.

[0022] Figure 10 This is a cross-sectional view (seventh example) showing a first example of a method for manufacturing a semiconductor device according to the first embodiment.

[0023] Figure 11 This is a cross-sectional view (eighth example) showing a first example of a method for manufacturing a semiconductor device according to the first embodiment.

[0024] Figure 12 This is a cross-sectional view (nine) showing a first example of a method for manufacturing a semiconductor device according to the first embodiment.

[0025] Figure 13 This is a cross-sectional view (tenth) showing a first example of a method for manufacturing a semiconductor device according to the first embodiment.

[0026] Figure 14 This is a cross-sectional view (one of two) showing a second example of a method for manufacturing a semiconductor device according to the first embodiment.

[0027] Figure 15 This is a cross-sectional view (second example) illustrating a method for manufacturing a semiconductor device according to the first embodiment.

[0028] Figure 16 This is a cross-sectional view of a semiconductor device for reference.

[0029] Figure 17 This is a cross-sectional view (one of the examples) showing a method for manufacturing a semiconductor device according to a reference example.

[0030] Figure 18 This is a cross-sectional view (second example) showing a method for manufacturing a semiconductor device according to a reference example.

[0031] Figure 19 This is a cross-sectional view (third one) showing a method for manufacturing a semiconductor device according to a reference example.

[0032] Figure 20 This is a cross-sectional view (fourth) illustrating a method for manufacturing a semiconductor device according to a reference example.

[0033] Figure 21 This is a cross-sectional view (fifth) showing a method for manufacturing a semiconductor device according to a reference example.

[0034] Figure 22 This is a cross-sectional view (sixth) illustrating a method for manufacturing a semiconductor device according to a reference example.

[0035] Figure 23 This is a cross-sectional view (seventh) illustrating a method for manufacturing a semiconductor device according to a reference example.

[0036] Figure 24 This is a diagram showing the layout of the gate electrode, source wiring, and drain wiring in the semiconductor device of the second embodiment.

[0037] Figure 25 This is a cross-sectional view showing the semiconductor device according to the second embodiment.

[0038] Explanation of reference numerals in the attached figures:

[0039] 11: Substrate; 11A: First surface; 11B: Second surface; 12: Semiconductor layer; 12C: Third surface; 12D: Fourth surface; 13D, 13S: Recess; 15: Gate common connection; 21D, 21S: Semiconductor layer; 22: Gate electrode; 26: Conductor band; 27: Valence band; 30D: Drain electrode; 30S: Source electrode; 30X: Gap; 31D, 31S: Ni layer; 32D, 32S: Au layer; 50, 61D, 61G, 61S, 62D, 62S, 81: Opening; 50X: Through hole; 51: Back electrode; 52D: Drain wiring; 52S: Source wiring; 55: Drain pad; 61, 62, 63: Insulating film; 71: Bottom surface; 72: Inner wall surface; 89: Crystal defect; 100, 100X, 200: Semiconductor device. Detailed Implementation

[0040] [Description of embodiments of this disclosure]

[0041] First, the implementation plan disclosed herein will be listed for explanation.

[0042] [1] A semiconductor device according to one aspect of this disclosure includes: a substrate having a first surface and a second surface opposite to the first surface; a first nitride semiconductor layer having a third surface in contact with the second surface and a fourth surface opposite to the third surface, wherein a recess is formed on the fourth surface; and a second nitride semiconductor layer disposed in the recess, wherein an opening is formed in the substrate and the first nitride semiconductor layer, wherein the opening extends through the substrate and the first nitride semiconductor layer to the second nitride semiconductor layer, the opening having a bottom surface in the second nitride semiconductor layer, the semiconductor device having a first metal layer, wherein the first metal layer covers the inner wall surface of the first surface and the opening, and contacts the second nitride semiconductor layer on the bottom surface, the second nitride semiconductor layer having an opening at a depth greater than or equal to 1.0 × 10⁻⁶. 18 cm -3 The concentration contains impurity atoms.

[0043] A second nitride semiconductor layer is formed in a recess on the fourth side of the first nitride semiconductor layer, the second nitride semiconductor layer having a density greater than or equal to 1.0 × 10⁻⁶. 18 cm -3 The concentration contains impurity atoms. Furthermore, the first metal layer contacts the second nitride semiconductor layer at the bottom surface of the opening, forming an ohmic contact. Therefore, the resistance between the first nitride semiconductor layer and the first metal layer is low. Consequently, compared to cases where other metal layers exist in the current path between the first metal layer and the first nitride semiconductor layer, the resistance between the first metal layer and the first nitride semiconductor layer is more stable, improving yield.

[0044] [2] In [1], the thickness of the second nitride semiconductor layer may also be greater than or equal to 20 nm and less than or equal to 1000 nm. A thickness of 20 nm or more allows for easier stopping of etching the first and second nitride semiconductor layers before the opening penetrates the second nitride semiconductor layer during the formation of the opening. A thickness of 1000 nm or less allows for a shorter timeframe for forming the recess and the second nitride semiconductor layer.

[0045] [3] In [1] or [2], the second nitride semiconductor layer may also be a gallium nitride layer. In this case, it is easy to obtain a low resistance in the second nitride semiconductor layer.

[0046] [4] In any of [1] to [3], the Fermi level in the second nitride semiconductor layer may be higher than the energy at the lower end of the conduction band. In this case, an ohmic contact is easily obtained between the second nitride semiconductor layer and the first metal layer.

[0047] [5] In any of [1] to [4], the carrier density in the second nitride semiconductor layer may also be higher than the carrier density in the first nitride semiconductor layer. In this case, it is easier to reduce the resistance of the second nitride semiconductor layer.

[0048] [6] In any of [1] to [5], the semiconductor device may also have: a second metal layer disposed on the second nitride semiconductor layer, the second nitride semiconductor layer being located between the first metal layer and the second metal layer. In this case, the second metal layer can be used to perform characteristic checks.

[0049] [7] Another aspect of the present disclosure discloses a method for manufacturing a semiconductor device comprising the following steps: forming a first nitride semiconductor layer on a substrate, wherein the substrate has a first surface and a second surface opposite to the first surface, the first nitride semiconductor layer has a third surface in contact with the second surface and a fourth surface opposite to the third surface; forming a recess on the fourth surface; forming a second nitride semiconductor layer in the recess; forming an opening on the substrate and the first nitride semiconductor layer, wherein the opening penetrates the substrate and the first nitride semiconductor layer and reaches the second nitride semiconductor layer, the opening having a bottom surface on the second nitride semiconductor layer; and forming a first metal layer, wherein the first metal layer covers the inner wall surface of the first surface and the opening, and contacts the second nitride semiconductor layer on the bottom surface, the second nitride semiconductor layer having an opening at a depth greater than or equal to 1.0 × 10⁻⁶. 18 cm -3The concentration contains impurity atoms.

[0050] A recess is formed on the fourth surface of the first nitride semiconductor layer, and a second nitride semiconductor layer is formed in the recess. The second nitride semiconductor layer has a density greater than or equal to 1.0 × 10⁻⁶. 18 cm -3 The concentration contains impurity atoms. Furthermore, the first metal layer contacts the second nitride semiconductor layer at the bottom surface of the opening, forming an ohmic contact. Therefore, the resistance between the first nitride semiconductor layer and the first metal layer is low. Consequently, compared to cases where other metal layers exist in the current path between the first metal layer and the first nitride semiconductor layer, the resistance between the first metal layer and the first nitride semiconductor layer is more stable, improving yield.

[0051] [Details of the embodiments of this disclosure]

[0052] The embodiments of this disclosure will now be described in detail, but this disclosure is not limited thereto. It should be noted that in this specification and accompanying drawings, constituent elements having substantially the same functional configuration are labeled with the same reference numerals, thus sometimes omitting repeated descriptions. Furthermore, in the following description, an XYZ orthogonal coordinate system is used, but this coordinate system is determined for illustrative purposes and is not intended to limit the orientation of the semiconductor device. Additionally, when viewed from any point, the +Z side is sometimes referred to as above, upper, or upper, and the -Z side is sometimes referred to as below, lower, or lower.

[0053] (First Implementation)

[0054] The first embodiment will be described. The first embodiment relates to a semiconductor device including a GaN-based high electron mobility transistor (HEMT).

[0055] [Structure of a semiconductor device]

[0056] The structure of the semiconductor device according to the first embodiment will be described. Figure 1 This is a diagram showing the layout of the gate electrode and drain wiring in the semiconductor device of the first embodiment. Figure 2 This is a cross-sectional view showing the semiconductor device according to the first embodiment. Figure 2 Equivalent to along Figure 1 A sectional view along line II-II in the diagram.

[0057] like Figure 1 and Figure 2As shown, the semiconductor device 100 of the first embodiment includes a substrate 11, a semiconductor layer 12, a semiconductor layer 21S, a semiconductor layer 21D, a gate electrode 22, a drain electrode 30D, a drain wiring 52D, and a back electrode 51.

[0058] The substrate 11 is, for example, a silicon carbide (SiC) substrate. The substrate 11 has a first surface 11A and a second surface 11B opposite to the first surface 11A. The second surface 11B is located above the first surface 11A (on the +Z side).

[0059] A semiconductor layer 12 is disposed on the substrate 11. The semiconductor layer 12 has a third surface 12C in contact with the second surface 11B and a fourth surface 12D opposite to the third surface 12C. The fourth surface 12D is located above the third surface 12C (on the +Z side). The semiconductor layer 12 is, for example, a gallium (Ga) nitride semiconductor layer. The nitride semiconductor layer constitutes part of a high electron mobility transistor, such as an electron transit layer (channel layer) and an electron supply layer (blocking layer), and contains a two-dimensional electron gas (2DEG). The semiconductor layer 12 is an example of a first nitride semiconductor layer.

[0060] Multiple recesses 13S and multiple recesses 13D are formed on the fourth surface 12D. The recesses 13S and 13D extend parallel to the Y-axis and are alternately arranged along the X-axis. For example, the recesses 13S and 13D reach the electron transit layer (channel layer). Alternatively, the bottom surfaces of the recesses 13S and 13D may be located in the electron transit layer.

[0061] Semiconductor device 100 includes an insulating film 61. The insulating film 61 covers the fourth surface 12D of semiconductor layer 12. For example, the insulating film 61 is a silicon nitride (SiN) film or other nitride film. A plurality of openings 61S, a plurality of openings 61D, and a plurality of openings 61G are formed on the insulating film 61. The openings 61S, 61D, and 61G extend parallel to the Y-axis. The openings 61S are connected to the recesses 13S, and the openings 61D are connected to the recesses 13D. The openings 61G are located between adjacent openings 61S and 61D along the X-axis.

[0062] Semiconductor layer 21S is disposed in recess 13S, and semiconductor layer 21D is disposed in recess 13D. Alternatively, a portion of semiconductor layer 21S may be located inside opening 61S, and a portion of semiconductor layer 21D may be located inside opening 61D. For example, semiconductor layers 21S and 21D are n-type gallium nitride (GaN) layers. Semiconductor layers 21S and 21D are regrown layers. The carrier density in semiconductor layers 21S and 21D is higher than the carrier density in semiconductor layer 12. Semiconductor layers 21S and 21D have a carrier density greater than or equal to 1.0 × 10⁻⁶.18 cm -3 The concentration contains n-type impurity atoms. Semiconductor layers 21S and 21D are, for example, degenerate semiconductor layers. The n-type impurity is, for example, silicon (Si) or germanium (Ge). Semiconductor layer 21S is an example of a second nitride semiconductor layer.

[0063] The gate electrode 22 extends parallel to the Y-axis. The gate electrode 22 covers the opening 61G of the insulating film 61, and through the opening 61G, it makes a Schottky contact with the semiconductor layer 12. The gate electrode 22, for example, has nickel (Ni) and gold (Au) layers sequentially stacked upwards. Figure 1 As shown, multiple gate electrodes 22 are connected to the gate common connection portion 15.

[0064] The drain electrode 30D extends parallel to the Y-axis. When viewed from above, the drain electrode 30D has a Ni layer 31D and an Au layer 32D inside the opening 61D. The Ni layer 31D is disposed above the semiconductor layer 21D, and the Au layer 32D is disposed above the Ni layer 31D. The Ni layer 31D is in direct contact with the semiconductor layer 21D.

[0065] Semiconductor device 100 has an insulating film 62. The insulating film 62 covers the drain electrode 30D, the gate electrode 22, the insulating film 61, the semiconductor layer 21S, and the semiconductor layer 21D. For example, the insulating film 62 is a nitride film such as a SiN film. A plurality of openings 62D are formed in the insulating film 62. The openings 62D extend parallel to the Y-axis. The openings 62D reach the drain electrode 30D.

[0066] Drain wiring 52D is located above drain electrode 30D. Drain wiring 52D is disposed on insulating film 62. Drain wiring 52D contacts drain electrode 30D through opening 62D. Drain wiring 52D, for example, has a seed layer and a plating layer above the seed layer. For example, the seed layer includes a titanium (Ti) layer, and the plating layer includes a gold (Au) layer. Figure 1 As shown, it is also possible that multiple drain wirings 52D are connected to the drain pad 55.

[0067] Semiconductor device 100 has an insulating film 63. The insulating film 63 covers the drain wiring 52D and the insulating film 62. For example, the insulating film 63 is a nitride film such as a SiN film.

[0068] Although not shown in the figure, an opening leading to the gate common connection portion 15 is formed on the insulating film 62, and a gate pad that contacts the gate common connection portion 15 through this opening is formed on the insulating film 62. In addition, openings leading to the gate pad and openings leading to the drain pad 55 are formed on the insulating film 63.

[0069] An opening 50 penetrating through the substrate 11 and the semiconductor layer 12 is formed in the substrate 11 and the semiconductor layer 12. The opening 50 reaches the semiconductor layer 21S. The opening 50 has a bottom surface 71 and an inner wall surface 72. The inner wall surface 72 is connected to the lower surface (first surface 11A) of the substrate 11, and the bottom surface 71 is connected to the inner wall surface 72. The bottom surface 71 is located in the semiconductor layer 21S. The opening 50 may also penetrate into the semiconductor layer 21S. At least one opening 50 is formed for each of the semiconductor layers 21S. Alternatively, a plurality of openings 50 may be formed for each of the semiconductor layers 21S.

[0070] A back electrode 51 is formed on the lower surface of the semiconductor layer 21S, the inner wall surface 72 of the opening 50, and the lower surface (first surface 11A) of the substrate 11. The back electrode 51 covers the first surface 11A and the inner wall surface 72 and contacts the semiconductor layer 21S at the bottom surface 71. The back electrode 51 has, for example, a seed layer and a plating layer. For example, the seed layer includes a titanium (Ti) layer, a nickel (Ni) layer, a nickel-chromium (NiCr) alloy layer, or a tantalum (Ta) layer, and the plating layer includes a gold (Au) layer. The back electrode 51 is an example of a first metal layer.

[0071] In the semiconductor device 100, the semiconductor layer 21S is formed in the recess 13S of the semiconductor layer 12, and the semiconductor layer 21S contains impurity atoms at a concentration of 1.0×10 18 cm -3 or more. In such a semiconductor layer 21S, the distance between impurity atoms is short, and as Figure 3 shown, a combined energy band (Japanese: 結束バンド) in which impurity energy levels (E D ) interact with each other is formed, and this combined energy band is related to the conduction band 26. At this time, the Fermi level (E F ) exists in the conduction band, that is, the Fermi level (E F ) is higher than the energy (E C ) at the lower end of the conduction band. Therefore, the semiconductor layer 21S exhibits characteristics similar to those of a metal. That is, the semiconductor layer 21S functions as a degenerate semiconductor layer. Therefore, an ohmic contact is obtained between the semiconductor layer 21S and the back electrode 51. Figure 3 is a diagram showing the energy band structure of the semiconductor layer 21S. Figure 3 In , E V represents the energy at the upper end of the valence band 27.

[0072] [First Example of Manufacturing Method of Semiconductor Device]

[0073] Next, a first example of the manufacturing method of the semiconductor device 100 of the first embodiment will be described. Figures 4 to 13 is a cross-sectional view showing a first example of the manufacturing method of the semiconductor device 100 of the first embodiment.

[0074] In the first case, such as Figure 4 As shown, a semiconductor layer 12 is formed on a substrate 11, for example, by metal-organic chemical vapor deposition (MOCVD). The substrate 11 has a first surface 11A and a second surface 11B opposite to the first surface 11A. The semiconductor layer 12 has a third surface 12C in contact with the second surface 11B and a fourth surface 12D opposite to the third surface 12C. Next, an insulating film 61 is formed on the semiconductor layer 12. The insulating film 61 can be formed, for example, by plasma CVD (chemical vapor deposition). The insulating film 61 covers the fourth surface 12D of the semiconductor layer 12.

[0075] Next, as Figure 5 As shown, openings 61S and 61D are formed on the insulating film 61, and recesses 13S and 13D are formed on the semiconductor layer 12. In the formation of openings 61S and 61D, reactive ion etching (RIE) is performed on the insulating film 61, using a resist pattern as a mask. During the RIE of the insulating film 61, a reactive gas containing fluorine (F) is used, for example. In the formation of recesses 13S and 13D, RIE is performed on the semiconductor layer 12, using the resist pattern used for the formation of openings 61S and 61D as a mask. During the RIE of the semiconductor layer 12, a reactive gas containing chlorine (Cl) is used, for example.

[0076] Next, as Figure 6 As shown, a semiconductor layer 21S is formed in the recess 13S, and a semiconductor layer 21D is formed in the recess 13D. In the formation of semiconductor layers 21S and 21D, crystal growth of the semiconductor layers is performed, for example, using MOCVD, molecular beam epitaxy (MBE), or sputtering with a growth mask, followed by removal of the growth mask. Semiconductor layers 21S and 21D are so-called regrown layers.

[0077] Next, as Figure 7 As shown, a drain electrode 30D is formed on the semiconductor layer 21D. In the formation of the drain electrode 30D, a Ni layer and an Au layer are grown using a vapor deposition method employing a growth mask, after which the growth mask is removed. That is, the drain electrode 30D can be formed, for example, by vapor deposition and stripping.

[0078] Next, as Figure 8As shown, an opening 61G is formed on the insulating film 61. In the formation of the opening 61G, for example, a re-etching process (RIE) using a resist pattern as a mask is performed. In the etching of the insulating film 61, for example, a reactive gas containing F is used. Next, a gate electrode 22 is formed on the insulating film 61. In the formation of the gate electrode 22, a Ni layer and an Au layer are grown using a vapor deposition method employing a growth mask, after which the growth mask is removed. That is, the gate electrode 22 can be formed, for example, by vapor deposition and stripping. The gate electrode 22 makes a Schottky contact with the semiconductor layer 12 through the opening 61G.

[0079] Next, as Figure 9 As shown, an insulating film 62 is formed on the drain electrode 30D, the gate electrode 22, the insulating film 61, the semiconductor layer 21S, and the semiconductor layer 21D. The insulating film 62 can be formed, for example, by plasma CVD. The insulating film 62 covers the drain electrode 30D, the gate electrode 22, the insulating film 61, the semiconductor layer 21S, and the semiconductor layer 21D.

[0080] Next, as Figure 10 As shown, an opening 62D is formed on the insulating film 62. In forming the opening 62D, for example, a resist patterning (RIE) is performed on the insulating film 62, using the resist pattern as a mask. During the RIE of the insulating film 62, for example, a reactive gas containing F is used. Next, a drain wiring 52D, which contacts the drain electrode 30D through the opening 62D, is formed on the insulating film 62.

[0081] Next, as Figure 11 As shown, an insulating film 63 is formed on the insulating film 62. The insulating film 63 can be formed, for example, by plasma CVD. The insulating film 63 covers the drain wiring 52D and the insulating film 62.

[0082] Next, as Figure 12 As shown, an opening 81 is formed through the substrate 11. The opening 81 is formed to reach the semiconductor layer 12. The lower surface of the semiconductor layer 12 is exposed from the opening 81. In forming the opening 81, for example, a re-etching process (RIE) of the substrate 11 is performed. A reactive gas containing F is used, for example, in the RIE of the substrate 11. During the RIE of the substrate 11 used to form the opening 81, a mask is formed on the first surface 11A, and the mask is removed after etching of the substrate 11.

[0083] Next, as Figure 13As shown, re-extraction (RIE) of semiconductor layers 12 and 21S is performed through opening 81, forming an opening 50 that penetrates both substrate 11 and semiconductor layer 12. Opening 50 includes opening 81. Opening 50 is formed to reach semiconductor layer 21S. Opening 50 has a bottom surface 71 and an inner wall surface 72. The inner wall surface 72 is connected to the lower surface (first surface 11A) of substrate 11, and the bottom surface 71 is connected to the inner wall surface 72. The bottom surface 71 is located in semiconductor layer 21S. Opening 50 can also enter semiconductor layer 21S. During RIE of semiconductor layers 12 and 21S, a reactive gas containing Cl is used, for example. RIE of semiconductor layers 12 and 21S is stopped, for example, based on time control, before opening 50 penetrates semiconductor layer 21S. Cleaning is performed within opening 50 after its formation.

[0084] Next, the back electrode 51 is formed (refer to...) Figure 2 The back electrode 51 covers the first surface 11A and the inner wall surface 72, and is in contact with the semiconductor layer 21S on the bottom surface 71. In the formation of the back electrode 51, a seed layer is formed, for example, by sputtering, and then a plating layer is formed on the seed layer.

[0085] In this way, the semiconductor device 100 of the first embodiment can be manufactured.

[0086] [A Second Example of a Semiconductor Device Manufacturing Method]

[0087] Next, a second example of the manufacturing method of the semiconductor device 100 of the first embodiment will be described. Figures 14 to 15 This is a cross-sectional view showing a second example of a method for manufacturing the semiconductor device 100 according to the first embodiment.

[0088] In the second example, the process up to the formation of semiconductor layer 21S and semiconductor layer 21D is performed in the same manner as in the first example (see reference). Figures 4 to 6 Next, as Figure 14 As shown, an opening 61G is formed in the insulating film 61.

[0089] Next, as Figure 15 As shown, a drain electrode 30D is formed on the semiconductor layer 21D, and a gate electrode 22 is formed on the insulating film 61. In the formation of the drain electrode 30D and the gate electrode 22, a Ni layer and an Au layer are grown using a vapor deposition method employing a growth mask, after which the growth mask is removed. The drain electrode 30D and the gate electrode 22 can be formed simultaneously.

[0090] Then, the post-formation processing of insulating film 62 is carried out according to the same process as in the first example (see [reference]). Figures 9 to 13 and Figure 2 ).

[0091] In this way, the semiconductor device 100 of the first embodiment can be manufactured.

[0092] In the first embodiment, in either the first or second example, the mask for the RIE of the substrate 11 may be removed after the opening 50 is formed. Alternatively, the RIE of the substrate 11 and the RIE of the semiconductor layer 12 may be performed continuously using a reactive gas containing F, thereby forming the opening 50, and then the mask may be removed.

[0093] In the semiconductor device 100, the back electrode 51 contacts the semiconductor layer 21S at the bottom surface 71 of the opening 50, forming an ohmic contact with the semiconductor layer 21S. Therefore, the resistance between the semiconductor layer 12 containing 2DEG and the back electrode 51 is low. While crystal defects may sometimes exist in the semiconductor layer 21S, the increase in resistance between the back electrode 51 and the semiconductor layer 21S caused by these defects is negligible. Therefore, according to the semiconductor device 100, the resistance between the back electrode 51 and the semiconductor layer 12 is well-stable, improving yield.

[0094] Here, the resistance between the back electrode 51 and the semiconductor layer 12 will be further explained in comparison with the reference example. Figure 16 This is a cross-sectional view of a semiconductor device for reference. Figures 17 to 23 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device as an example.

[0095] like Figure 16 As shown, the semiconductor device 100X of the reference example has a source electrode 30S and a source wiring 52S. When viewed from above, the source electrode 30S has a Ni layer 31S and an Au layer 32S inside the opening 61S. The Ni layer 31S is disposed above the semiconductor layer 21S, and the Au layer 32S is disposed above the Ni layer 31S. The Ni layer 31S is in direct contact with the semiconductor layer 21S. An insulating film 62 covers the source electrode 30S, and a plurality of openings 62S are formed on the insulating film 62. The openings 62S reach the source electrode 30S.

[0096] The source wiring 52S is located above the source electrode 30S. The source wiring 52S is disposed on the insulating film 62. The source wiring 52S contacts the source electrode 30S through the opening 62S. The insulating film 63 covers the source wiring 52S.

[0097] Alternatively, a through-hole 50X can be formed in the substrate 11, semiconductor layer 12, and semiconductor layer 21S to penetrate the substrate 11, semiconductor layer 12, and semiconductor layer 21S instead of the opening 50. The through-hole 50X reaches the source electrode 30S. A back electrode 51 is formed on the lower surface of the source electrode 30S, the inner wall surface of the through-hole 50X, and the lower surface (first surface 11A) of the substrate 11. The back electrode 51 contacts the source electrode 30S and covers the first surface 11A and the inner wall surface of the through-hole 50X. The back electrode 51 is electrically connected to the source electrode 30S, and the source electrode 30S is in ohmic contact with the semiconductor layer 21S.

[0098] The other components of semiconductor device 100X are the same as those of semiconductor device 100.

[0099] In the manufacturing method of semiconductor device 100X, the process up to the formation of semiconductor layer 21S and semiconductor layer 21D is performed according to the same procedure as in the first example (see reference). Figures 4 to 6 Next, as Figure 17 As shown, the source electrode 30S is formed simultaneously with the formation of the drain electrode 30D.

[0100] Next, as Figure 18 As shown, the process from the formation of the opening 61G to the formation of the insulating film 62 is carried out in the same manner as in the first example.

[0101] Next, as Figure 19 As shown, opening 62D is formed at the same time as opening 62S, and source wiring 52S is formed at the same time as drain wiring 52D.

[0102] Next, as Figure 20 As shown, the process from the formation of the insulating film 63 to the formation of the opening 81 is carried out in the same manner as in the first example.

[0103] Next, as Figure 21 As shown, re-etching (RIE) of semiconductor layers 12 and 21S is performed through opening 81, forming a through-hole 50X that penetrates the substrate 11, semiconductor layers 12, and semiconductor layers 21S. During the formation of the through-hole 50X, the source electrode 30S is used as an etching stop layer, and the through-hole 50X is formed to reach the source electrode 30S. The through-hole 50X can also penetrate the source electrode 30S. During the RIE of semiconductor layers 12 and 21S, a reactive gas containing Cl is used, for example. After the formation of the through-hole 50X, cleaning is performed inside the through-hole 50X.

[0104] Next, the back electrode 51 is formed (refer to...) Figure 16 In this way, the semiconductor device 100X of the reference example can be manufactured.

[0105] In semiconductor device 100X, through-hole 50X reaches source electrode 30S, and source electrode 30S is in ohmic contact with semiconductor layer 21S. However, as Figure 22 As shown, when crystal defects 89 are present in semiconductor layers 12 and 21S, during the removal of the mask used for the RIE of substrate 11, the material used for mask removal reaches the source electrode 30S through the crystal defects 89, sometimes resulting in a partial defect in the source electrode 30S. During cleaning after the formation of the through-hole 50X, sometimes a portion of the source electrode 30S is also damaged. Therefore, as... Figure 23 As shown, even after the back electrode 51 is formed, a gap 30X may still exist between the source electrode 30S and the semiconductor layer 21S. When the gap 30X exists, the contact resistance between the source electrode 30S and the semiconductor layer 21S increases, and the yield decreases. On the other hand, in the semiconductor device 100, the back electrode 51 contacts the semiconductor layer 21S at the bottom surface 71 of the opening 50, and the back electrode 51 and the semiconductor layer 21S are in ohmic contact. Therefore, even if crystal defects 89 exist, the increase in contact resistance as in the reference example will not occur, and the yield can be improved.

[0106] It should be noted that while the back electrode 51 can contact the semiconductor layer 21S on the inner wall surface of the through-hole 50X in the semiconductor device 100X, the contact area is extremely small. Furthermore, etching residue generated during the etching of the semiconductor layer 12 and the semiconductor layer 21S may be present on the inner wall surface of the through-hole 50X. Therefore, even if the back electrode 51 contacts the semiconductor layer 21S on the inner wall surface of the through-hole 50X, this contact is unlikely to contribute to a reduction in contact resistance. Similarly, in the semiconductor device 100, even if the back electrode 51 contacts the semiconductor layer 21S on the inner wall surface 72 of the opening 50, this contact is unlikely to contribute to a reduction in contact resistance. However, in the semiconductor device 100, the back electrode 51 contacts the semiconductor layer 21S on the bottom surface 71 of the opening 50, thus reducing the contact resistance.

[0107] The thickness of semiconductor layer 21S can be, for example, greater than or equal to 20 nm and less than or equal to 1000 nm, or greater than or equal to 150 nm and less than or equal to 400 nm. If the thickness of semiconductor layer 21S is greater than or equal to 20 nm, it is easier to stop the RIE of semiconductor layer 12 and semiconductor layer 21S before the opening 50 penetrates semiconductor layer 21S. If the thickness of semiconductor layer 21S is greater than or equal to 150 nm, it is easier to stop the RIE of semiconductor layer 12 and semiconductor layer 21S before the opening 50 penetrates semiconductor layer 21S. If the thickness of semiconductor layer 21S is less than or equal to 1000 nm, it is easier to shorten the time spent on forming recess 13S and semiconductor layer 21S. If the thickness of semiconductor layer 21S is less than or equal to 400 nm, it is easier to shorten the time spent on forming recess 13S and semiconductor layer 21S. The thickness of the semiconductor layer 21S can be determined using a transmission electron microscope (TEM) or a scanning electron microscope (SEM).

[0108] Semiconductor layer 21S is a GaN layer, which makes it easy to obtain low resistance in semiconductor layer 21S.

[0109] The carrier density in semiconductor layers 21S and 21D is higher than that in semiconductor layer 12, thereby making it easier to reduce the resistance of the semiconductor device 100. Specifically, it is easier to reduce the resistance between the back electrode 51 and the drain wiring 52D.

[0110] Semiconductor layer 21S can be at a density greater than or equal to 1.0 × 10⁻⁶. 19 cm -3 The concentration containing n-type impurity atoms can also be greater than or equal to 1.0 × 10⁻⁶. 20 cm -3 The concentration of n-type impurity atoms in semiconductor layer 21S is higher, making it easier to achieve an ohmic contact between semiconductor layer 21S and back electrode 51. Similarly, semiconductor layer 21D can have a concentration greater than or equal to 1.0 × 10⁻⁶. 19 cm -3 The concentration containing n-type impurity atoms can also be greater than or equal to 1.0 × 10⁻⁶. 20 cm -3 The concentration of n-type impurity atoms is higher in semiconductor layer 21D, making it easier to achieve an ohmic contact between semiconductor layer 21D and drain electrode 30D. The concentration of impurity atoms can be determined by secondary ion mass spectrometry (SIMS).

[0111] (Second Implementation)

[0112] The second embodiment will be described. The second embodiment differs from the first embodiment mainly in that it has a source electrode and source wiring.

[0113] [Structure of a semiconductor device]

[0114] The structure of the semiconductor device according to the second embodiment will be described. Figure 24 This is a diagram showing the layout of the gate electrode, source wiring, and drain wiring in the semiconductor device of the second embodiment. Figure 25 This is a cross-sectional view showing the semiconductor device according to the second embodiment. Figure 25 Equivalent to along Figure 24 A cross-sectional view of the XXV-XXV line.

[0115] like Figure 24 and Figure 25 As shown, the semiconductor device 200 of the second embodiment, in addition to having the configuration of the semiconductor device 100, also includes a source electrode 30S and a source wiring 52S. Multiple source wirings 52S can also be interconnected. The configuration of the source electrode 30S, the insulating film 62, and the source wirings 52S is the same as that of the semiconductor device 100X in the reference example. The source electrode 30S is an example of a second metal layer.

[0116] The other components of semiconductor device 200 are the same as those of semiconductor device 100.

[0117] [Semiconductor Device Manufacturing Method]

[0118] In manufacturing the semiconductor device 200 of the second embodiment, the source electrode 30S and source wiring 52S are formed according to the same process as in the reference example. Furthermore, the opening 81 and opening 50 are formed according to the same process as in the first embodiment. In this way, the semiconductor device 200 of the second embodiment can be manufactured.

[0119] The yield can be improved in the same way as in the first embodiment through the second embodiment. Sometimes, as in the reference example, defects may occur in the source electrode 30S, but the defects in the source electrode 30S will not affect the contact resistance. This is because the back electrode 51 is in contact with the semiconductor layer 21S at the bottom surface 71 of the opening 50, and the back electrode 51 is in ohmic contact with the semiconductor layer 21S.

[0120] Furthermore, in the semiconductor device 200 of the second embodiment, source wiring 52S can be used to perform characteristic checks. For example, characteristic checks can be performed before the formation of the back electrode 51.

[0121] The embodiments have been described in detail above, but this disclosure is not limited to specific embodiments, and various modifications and alterations can be made within the scope of the claims.

Claims

1. A semiconductor device comprising: A substrate having a first surface and a second surface opposite to the first surface; A first nitride semiconductor layer has a third surface in contact with the second surface and a fourth surface opposite to the third surface, wherein a recess is formed on the fourth surface; and A second nitride semiconductor layer is disposed in the recess. An opening is formed in the substrate and the first nitride semiconductor layer, wherein, The opening penetrates the substrate and the first nitride semiconductor layer, reaching the second nitride semiconductor layer, and the opening has a bottom surface in the second nitride semiconductor layer. The semiconductor device has a first metal layer, wherein the first metal layer covers the first surface and the inner wall surface of the opening, and contacts the second nitride semiconductor layer on the bottom surface. The second nitride semiconductor layer has a density greater than or equal to 1.0 × 10⁻⁶. 18 cm -3 The concentration contains impurity atoms.

2. The semiconductor device according to claim 1, wherein, The thickness of the second nitride semiconductor layer is greater than or equal to 20 nm and less than or equal to 1000 nm.

3. The semiconductor device according to claim 1 or 2, wherein, The second nitride semiconductor layer is a gallium nitride layer.

4. The semiconductor device according to claim 1 or 2, wherein, In the second nitride semiconductor layer, the Fermi level has a higher energy than the lower end of the conduction band.

5. The semiconductor device according to claim 1 or 2, wherein, The carrier density in the second nitride semiconductor layer is higher than that in the first nitride semiconductor layer.

6. The semiconductor device according to claim 1 or 2, comprising: A second metal layer is disposed on top of the second nitride semiconductor layer. The second nitride semiconductor layer is located between the first metal layer and the second metal layer.

7. A method for manufacturing a semiconductor device, comprising the following steps: A first nitride semiconductor layer is formed on the substrate, wherein... The substrate has a first surface and a second surface opposite to the first surface, and the first nitride semiconductor layer has a third surface in contact with the second surface and a fourth surface opposite to the third surface; A recess is formed on the fourth surface; A second nitride semiconductor layer is formed in the recess; An opening is formed in the substrate and the first nitride semiconductor layer, wherein the opening penetrates the substrate and the first nitride semiconductor layer to reach the second nitride semiconductor layer, and the opening has a bottom surface in the second nitride semiconductor layer; and A first metal layer is formed, wherein the first metal layer covers the first surface and the inner wall surface of the opening, and contacts the second nitride semiconductor layer on the bottom surface. The second nitride semiconductor layer has a density greater than or equal to 1.0 × 10⁻⁶. 18 cm -3 The concentration contains impurity atoms.

8. A semiconductor device comprising: A substrate having a first surface and a second surface opposite to the first surface; A first nitride semiconductor layer has a third surface in contact with the second surface and a fourth surface opposite to the third surface, wherein a recess is formed on the fourth surface; and A second nitride semiconductor layer is disposed in the recess. Through-holes are formed in the substrate and the first nitride semiconductor layer, wherein, The through-hole penetrates the substrate and the first nitride semiconductor layer, reaching the second nitride semiconductor layer. The through-hole has a bottom surface in the second nitride semiconductor layer. The semiconductor device has a first metal layer, wherein the first metal layer covers the first surface and the inner wall surface of the through hole, and contacts the second nitride semiconductor layer on the bottom surface. The second nitride semiconductor layer has a density greater than or equal to 1.0 × 10⁻⁶. 18 cm -3 The concentration contains impurity atoms.

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