Semiconductor device with embedded epitaxial layer and manufacturing method thereof
By setting a first spacing and adjusting the doping concentration in the embedded epitaxial layer, the problem of increased leakage current in the embedded SiGe epitaxial PMOS transistor was solved, resulting in reduced leakage current and improved performance, while avoiding the negative impact of slowing down the speed.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-30
- Publication Date
- 2026-03-13
AI Technical Summary
In the existing technology, as the process node shrinks, PMOS transistors with embedded SiGe epitaxial layers are prone to increased leakage current in large-size devices, which affects product performance and yield. Furthermore, slowing down the device speed to meet leakage current requirements will lead to performance degradation.
By filling the source-drain trench with an embedded epitaxial layer, setting the first spacing to be less than or equal to the inversion layer thickness, setting the top surface of the main layer to be higher than the top surface of the trench, and adjusting the width and doping concentration of the source-drain formation region, the diffusion of impurities into the channel region is reduced, thereby reducing the leakage path.
It effectively reduces leakage current, improves device performance, ensures that leakage current of different contact widths meets requirements and does not increase with the increase of contact width, and avoids performance degradation caused by slowing down the speed.
Smart Images
Figure CN121665615A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor device having an embedded epitaxial layer, and more particularly to a method for manufacturing a semiconductor device having an embedded epitaxial layer. Background Technology
[0002] Existing ultra-low leakage (ULL) products typically employ embedded epitaxial layers; for example, PMOS transistors in ULL products often use embedded SiGe epitaxial layers. ULL products have high requirements for device leakage current. With the advancement of process technology nodes, smaller process nodes often exhibit an upward curve in the leakage current curve of ULL products, which follows the contact width (thru-W) of the active region between the gate structures. This upward trend leads to more severe leakage current in larger semiconductor devices, impacting product performance and yield. The active region between the gate structures forms the source-drain region.
[0003] like Figure 1 The diagram shown is a schematic of an existing PMOS transistor with an embedded SiGE epitaxial layer; existing PMOS transistors with embedded SiGE epitaxial layers include: Multiple gate structures 102 are formed on the top surface of a semiconductor substrate, such as a silicon substrate 101. Each gate structure 102 includes a gate dielectric layer and a gate conductive material layer stacked sequentially.
[0004] A top cover layer 103 is also included on top of the gate structure 102, and a sidewall 104 is formed on the side of the gate structure 102.
[0005] An embedded SiGe epitaxial layer is formed in the source / drain trench 105.
[0006] The source-drain trench 105 is typically defined by self-alignment of the sidewalls 104 on the sides of adjacent gate structures 102, and is obtained by dry etching followed by a wet etching process with different etching rates for each crystal orientation. Figure 1 The Σ shape shown in the image.
[0007] Embedded SiGE epitaxial layers include: The embedded epitaxial layer includes a buffer layer 106, a main body layer 107, and a cap layer 108.
[0008] The buffer layer 106 includes a first buffer layer 1061 and a second buffer layer 1062 stacked sequentially.
[0009] The first buffer layer 1061 is an undoped structure.
[0010] The second buffer layer 1062 is p-type doped. Both the main layer 107 and the capping layer 108 are heavily p-type doped, and the p-type doping concentration of the capping layer 108 is greater than that of the main layer 107. The p-type doping concentration of the second buffer layer 1062 is less than that of the main layer 107.
[0011] The heavily P-type doped impurities in the source and drain regions of each semiconductor device are respectively composed of heavily P-type doped impurities in the embedded epitaxial layers on both sides of the corresponding gate structure 102. The heavily P-type doped impurities in the source and drain regions of each semiconductor device are mainly composed of P-type doped impurities in the capping layer 108.
[0012] like Figure 2 The figure shows a test curve of the leakage current of an existing PMOS transistor with an embedded SiGE epitaxial layer as a function of contact width; curve 201 is... Figure 1 The figure shows a test curve of leakage current versus contact width for an existing semiconductor device with an embedded epitaxial layer. Figure 2 In the figure, the width of the horizontal axis is the contact width, i.e., thru-W, and the vertical axis is the leakage current, i.e., IOFF.
[0013] It can be seen that as thru-W increases, IOFF also increases. Therefore, following the trend of increasing thru-W, IOFF will inevitably have the defect of leakage current exceeding the required range in large-size devices.
[0014] A common approach is to slow down the device speed to meet customer leakage current requirements, but excessively slow device speeds can also lead to low yield in the final test (FT). Figure 2 In the diagram, curve 202 is obtained by testing the device speed by slowing it down by 9%, based on curve 201. Slowing the device speed by 9% can be achieved by reducing RVP from 0% to -9%. Curve 202 shows an overall reduction in leakage current compared to curve 201, but the upward slope remains the same. Therefore, finding a solution to the increased leakage current caused by increased Thru W without slowing down the device speed is of paramount importance. Summary of the Invention
[0015] The technical problem to be solved by this invention is to provide a semiconductor device with an embedded epitaxial layer that can reduce leakage current while simultaneously improving device performance or without degrading it. It can prevent the defect that leakage current is also high when the contact width is large, and reduce leakage current to meet requirements for various contact widths without increasing with increasing contact width. To this end, this invention also provides a method for manufacturing a semiconductor device with an embedded epitaxial layer.
[0016] To solve the above-mentioned technical problems, the present invention provides a semiconductor device with an embedded epitaxial layer in which multiple semiconductor devices are simultaneously integrated on the same semiconductor substrate.
[0017] Each of the semiconductor devices includes a gate structure formed on the top surface of a semiconductor substrate.
[0018] A channel region doped with a second conductivity type is formed at the bottom of the gate structure, and an inversion layer is formed on the surface of the channel region when the semiconductor device is turned on.
[0019] The region between each of the gate structures is a source / drain formation region, and the width of the source / drain formation region is the contact width.
[0020] Each of the source / drain formation regions includes a source / drain trench, each side of the source / drain trench has a tip, and there is a first gap between the plane where the tip is located and the top surface of the source / drain trench.
[0021] An embedded epitaxial layer is filled in the source-drain trench.
[0022] The embedded epitaxial layer includes a buffer layer, a main layer, and a cap layer.
[0023] The buffer layer includes an undoped structure, and both the main layer and the capping layer are heavily doped with a first conductivity type, with the doping concentration of the first conductivity type in the capping layer being greater than that in the main layer.
[0024] The first conductivity type heavily doped impurities in the source and drain regions of each semiconductor device are respectively composed of the first conductivity type heavily doped impurities in the embedded epitaxial layers on both sides of the corresponding gate structure.
[0025] The first spacing between the tips in each of the source / drain formation regions is less than or equal to the thickness of the inversion layer, and the lowest position of the top surface of the main layer in each of the source / drain formation regions is higher than the top surface of the source / drain trench.
[0026] A further improvement is that the width of the source / drain trench gradually increases from top to bottom between the top surface of the source / drain trench and the plane where the tip is located; and the width of the source / drain trench gradually decreases from top to bottom between the bottom surface of the source / drain trench and the plane where the tip is located.
[0027] The side surface of the main body layer is perpendicular to the top surface of the source / drain trench.
[0028] At the top surface position of each of the source / drain trenches, there is a second spacing greater than 0 nm between the side of the source / drain trench and the side of the main body layer, and in the source / drain trench, the undoped structure of the buffer layer completely encloses the main body layer.
[0029] A further improvement is that the buffer layer comprises a first buffer layer and a second buffer layer stacked sequentially.
[0030] The first buffer layer is formed on the inner surface of the source-drain trench.
[0031] The second buffer layer is formed on the top surface of the first buffer layer.
[0032] The first buffer layer is an undoped structure.
[0033] The second buffer layer is doped with a first conductivity type, and the doping concentration of the first conductivity type of the second buffer layer is less than the doping concentration of the first conductivity type of the host layer.
[0034] A further improvement is that the semiconductor device is a PMOS transistor, with the first conductivity type being P-type and the second conductivity type being N-type.
[0035] A further improvement is that the first buffer layer is a SiGe layer, the second buffer layer is a SiGe layer, the main body layer is a SiGe layer, and the capping layer is a Si layer.
[0036] The Ge content of the second buffer layer is greater than that of the first buffer layer, and the Ge content of the main body layer is greater than that of the second buffer layer.
[0037] A further improvement is that each of the gate structures includes a gate dielectric layer and a gate conductive material layer stacked sequentially, and a sidewall is also formed on the side of the gate structure.
[0038] The top opening of each of the source and drain trenches is defined by the side alignment of the sidewalls of the gate structure on both sides; Each of the aforementioned source and drain trenches has a ∑ shape.
[0039] A further improvement is that the contact width can take multiple values; the doping concentration of the first conductivity type of the source and drain regions of each semiconductor device is the same, and the doping concentration of the first conductivity type of the source and drain regions of each semiconductor device ensures that the leakage current of the semiconductor device with the largest contact width is reduced to below the required value.
[0040] A further improvement is that the thickness of the inversion layer is less than 10 nm.
[0041] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing a semiconductor device with an embedded epitaxial layer, comprising the following steps: Step 1: Provide a semiconductor substrate and form a gate structure on the top surface of the semiconductor substrate in the gate forming region of each semiconductor device.
[0042] A channel region doped with a second conductivity type is formed at the bottom of the gate structure, and an inversion layer is formed on the surface of the channel region when the semiconductor device is turned on.
[0043] The region between each of the gate structures is a source / drain formation region, and the width of the source / drain formation region is the contact width.
[0044] Step 2: Form source / drain trenches in each of the source / drain formation areas and adjust the size of the first spacing.
[0045] Each side of the source / drain trench has a pointed tip, and the first spacing is the distance between the plane where the pointed tip is located and the top surface of the source / drain trench; the first spacing of the pointed tips in each source / drain forming region is less than or equal to the thickness of the inversion layer.
[0046] Step 3: Fill the source-drain trench with an embedded epitaxial layer.
[0047] The embedded epitaxial layer includes a buffer layer, a host layer, and a capping layer; the buffer layer includes an undoped structure, the host layer and the capping layer are both heavily doped with a first conductivity type, and the doping concentration of the first conductivity type of the capping layer is greater than the doping concentration of the first conductivity type of the host layer.
[0048] The first spacing also ensures that the lowest position of the top surface of the main layer in each of the source / drain formation regions is higher than the top surface of the source / drain trench.
[0049] The first conductivity type heavily doped impurities in the source and drain regions of each semiconductor device are respectively composed of the first conductivity type heavily doped impurities in the embedded epitaxial layers on both sides of the corresponding gate structure.
[0050] A further improvement is that the width of the source / drain trench gradually increases from top to bottom between the top surface of the source / drain trench and the plane where the tip is located; and the width of the source / drain trench gradually decreases from top to bottom between the bottom surface of the source / drain trench and the plane where the tip is located.
[0051] The side surface of the main body layer is perpendicular to the top surface of the source / drain trench.
[0052] At the top surface position of each of the source / drain trenches, there is a second spacing greater than 0 nm between the side of the source / drain trench and the side of the main body layer, and in the source / drain trench, the undoped structure of the buffer layer completely encloses the main body layer.
[0053] A further improvement is that the buffer layer comprises a first buffer layer and a second buffer layer stacked sequentially.
[0054] The first buffer layer is formed on the inner surface of the source-drain trench.
[0055] The second buffer layer is formed on the top surface of the first buffer layer.
[0056] The first buffer layer is an undoped structure.
[0057] The second buffer layer is doped with a first conductivity type, and the doping concentration of the first conductivity type of the second buffer layer is less than the doping concentration of the first conductivity type of the host layer.
[0058] A further improvement is that the semiconductor device is a PMOS transistor, with the first conductivity type being P-type and the second conductivity type being N-type.
[0059] A further improvement is that the first buffer layer is a SiGe layer, the second buffer layer is a SiGe layer, the main body layer is a SiGe layer, and the capping layer is a Si layer.
[0060] The Ge content of the second buffer layer is greater than that of the first buffer layer, and the Ge content of the main body layer is greater than that of the second buffer layer.
[0061] A further improvement is that each of the gate structures includes a gate dielectric layer and a gate conductive material layer stacked sequentially, and a sidewall is also formed on the side of the gate structure.
[0062] The top opening of each of the source and drain trenches is defined by the side alignment of the sidewalls of the gate structures on both sides.
[0063] Each of the aforementioned source and drain trenches has a ∑ shape.
[0064] A further improvement is that the thickness of the inversion layer is less than 10 nm.
[0065] A further improvement is that, in step two, the leakage current of the corresponding semiconductor device is reduced by narrowing the first spacing, while the channel conductivity of the semiconductor device is improved at the same time.
[0066] A further improvement is that the contact width can take multiple values; in step three, the doping concentration of the first conductivity type of the source and drain regions of each semiconductor device is the same, and the leakage current of each semiconductor device is reduced by reducing the doping concentration of the first conductivity type of the source and drain regions of each semiconductor device. The doping concentration of the first conductivity type of the source and drain regions of each semiconductor device ensures that the leakage current of the semiconductor device with the largest contact width is reduced to below the required value.
[0067] This invention sets the size of the first distance between the plane at the tip of the source / drain trench in the source / drain formation region and the top surface of the source / drain trench. The first distance is set to be less than or equal to the thickness of the inversion layer and ensures that the lowest position of the top surface of the main layer in each source / drain formation region is higher than the top surface of the source / drain trench, wherein: The first spacing is less than or equal to the thickness of the inversion layer, which can increase the stress effect of the embedded epitaxial layer on the inversion layer in the channel region, thereby increasing the carrier mobility of the inversion layer and improving the device performance such as channel conduction capability.
[0068] Since reducing the first spacing raises the top surface of the main layer, the setting of the first spacing ensures that the lowest position of the top surface of the main layer in each source / drain formation region is higher than the top surface of the source / drain trench. This also increases the spacing between the capping layer with higher doping concentration and the channel region, reducing the diffusion of first conductivity type impurities into the channel region. Therefore, it can reduce the leakage path caused by the diffusion of first conductivity type impurities into the channel region. Thus, the present invention can also reduce the leakage current of the device by reducing the first spacing.
[0069] Based on adjusting the first spacing, this invention can further reduce the doping concentration of the first conductivity type in the source and drain regions. This further reduces the amount of first conductivity type impurities diffusing into the channel region, thereby further reducing the leakage path and thus further reducing the leakage current of the device. By setting the doping concentration of the first conductivity type in the source and drain regions of the semiconductor device to ensure that the leakage current of the semiconductor device with the largest contact width is reduced to below the required value, the defect of large leakage current when the contact width is too large can be prevented. The leakage current of various contact widths is reduced to meet the requirements and does not increase with the increase of contact width, thereby making the leakage current of semiconductor devices with various contact widths small and consistent. Attached Figure Description
[0070] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is a schematic diagram of an existing PMOS transistor with an embedded SiGE epitaxial layer; Figure 2This is a test graph showing the leakage current of an existing PMOS transistor with an embedded SiGE epitaxial layer as a function of contact width. Figure 3 This is a schematic diagram of the structure of a semiconductor device with an embedded epitaxial layer according to an embodiment of the present invention; Figure 4 This is a test graph showing the change in leakage current of a semiconductor device with an embedded epitaxial layer as a function of contact width, according to an embodiment of the present invention. Detailed Implementation
[0071] The technical solutions of the embodiments of the present invention are derived from an in-depth analysis of the causes of technical problems in existing technical solutions. Before describing the technical solutions of the embodiments of the present invention in detail, the applicant will... Figure 1 The reason why the leakage current of the existing PMOS transistor with embedded SiGE epitaxial layer increases with Thru-W is explained as follows: Depend on Figure 1 As shown, the source / drain trench 105 has a tip, and there is a spacing SMD between the plane at the tip and the top surface of the source / drain trench 105. If the top opening of the source / drain trench 105 is increased, the spacing SMD will increase under the same etching process conditions.
[0072] At the same time, as Thru-W increases, the top surface of the filled main body layer 107 decreases. Figure 1 In this context, RH represents the thickness of the main layer 107 located above the top surface of the source / drain trench 105. That is, RH decreases as Thru-W increases. Furthermore, the top surface of the main layer 107 is typically not flat. While the RH in the middle region remains positive, the RH in the edge region of the source / drain trench 105 may be 0 or negative. In other words, the top surface of the main layer 107 may be flush with or below the top surface of the source / drain trench 105. In this case, the capping layer 108 is closer to the channel region, and heavily doped boron impurities in the capping layer 108 easily diffuse into the channel region, as indicated by the arrow corresponding to label 109. Moreover, the amount of boron impurities diffusing into the channel region increases with Thru-W. Since the channel region is N-type doped, the diffusion of p-type boron impurities into the channel region creates a leakage path, which increases the leakage current.
[0073] in addition, Figure 1In the diagram, the first buffer layer 1061 and the second buffer layer 1062 are separated by a dashed line. It can be seen that as Thru-W increases, the first buffer layer 1061 cannot completely cover the sides of the source-drain trench 105, especially the top corner area of the source-drain trench 105. The main body layer 107 or the cap layer 108 is prone to contact with the sides of the top corner of the source-drain trench 105, which will further increase the diffusion of B impurities, thereby further increasing the leakage current.
[0074] like Figure 3 The diagram shown is a schematic diagram of the structure of a semiconductor device with an embedded epitaxial layer according to an embodiment of the present invention. In the semiconductor device with an embedded epitaxial layer according to an embodiment of the present invention, multiple semiconductor devices are simultaneously integrated on the same semiconductor substrate 301.
[0075] Each of the semiconductor devices includes a gate structure 302 formed on the top surface of the semiconductor substrate 301. Figure 3 The image shows three gate structures 302, each corresponding to a semiconductor device.
[0076] In this embodiment of the invention, each gate structure 302 includes a gate dielectric layer (not shown) and a gate conductive material layer (not shown) stacked sequentially. A sidewall 303 is also formed on the side of the gate structure 302.
[0077] A channel region doped with a second conductivity type is formed at the bottom of the gate structure 302. In some embodiments, the semiconductor substrate has a second conductivity type doping, and the channel region is directly formed by the semiconductor substrate at the bottom of the gate structure 302. Figure 3 The channel region shown is directly formed by the semiconductor substrate at the bottom of the gate structure 302. In other embodiments, a second conductivity type doped region may be formed in the surface region of the semiconductor substrate 301, and the channel region may be formed by the second conductivity type doped region at the bottom of the gate structure 302.
[0078] When the semiconductor device is turned on, an inversion layer 304 is formed on the surface of the channel region. Since the channel region is doped with the second conductivity type, the conductivity type of the carriers in the inversion layer 304 is opposite to the doping type of the channel region. Therefore, the carriers in the inversion layer 304 are carriers of the first conductivity type.
[0079] In some embodiments, the thickness of the inversion layer 304 is less than 10 nm.
[0080] The region between each of the gate structures 302 is a source / drain formation region, and the width of the source / drain formation region is the contact width Thru-W, which can take multiple values. Figure 3 Only one source / drain formation region is shown, therefore only one contact width Thru-W is shown. In reality, multiple semiconductor devices are integrated on the semiconductor substrate 301, and the contact width Thru-W of each semiconductor device is set according to the actual situation. Therefore, the contact width Thru-W can have multiple values, and the contact width Thru-W corresponding to each value will include multiple semiconductor devices. Figure 3 In this context, the contact width Thru-W is the distance between two adjacent sidewalls 303. A lightly doped drain region (LDD) is typically formed at the bottom of each sidewall 303.
[0081] Each of the source / drain formation regions includes a source / drain trench 305, each side of the source / drain trench 305 having a tip, and a first gap SMD between the plane where the tip is located and the top surface of the source / drain trench 305. Figure 3 In the diagram, the dashed line CC represents the plane where the tip is located, and the dashed line DD represents the top surface of the source / drain trench 305.
[0082] In this embodiment of the invention, the top opening of each source-drain trench 305 is defined by the side alignment of the sidewalls 303 of the gate structure 302 on both sides.
[0083] An embedded epitaxial layer is filled in the source-drain trench 305.
[0084] The embedded epitaxial layer includes a buffer layer 306, a main body layer 307, and a cap layer 308.
[0085] The buffer layer 306 includes an undoped structure, and both the main layer 307 and the capping layer 308 are heavily doped with a first conductivity type, and the doping concentration of the first conductivity type of the capping layer 308 is greater than the doping concentration of the first conductivity type of the main layer 307.
[0086] In this embodiment of the invention, the buffer layer 306 includes a first buffer layer 3061 and a second buffer layer 3062 stacked sequentially.
[0087] The first buffer layer 3061 is formed on the inner surface of the source-drain trench 305.
[0088] The second buffer layer 3062 is formed on the top surface of the first buffer layer 3061.
[0089] The first buffer layer 3061 is an undoped structure.
[0090] The second buffer layer 3062 is doped with a first conductivity type, and the doping concentration of the first conductivity type of the second buffer layer 3062 is less than the doping concentration of the first conductivity type of the main body layer 307.
[0091] The heavily doped impurities of the first conductivity type in the source and drain regions of each semiconductor device are respectively composed of heavily doped impurities of the first conductivity type in the embedded epitaxial layers on both sides of the corresponding gate structure 302. The heavily doped impurities of the first conductivity type in the source and drain regions of each semiconductor device are mainly composed of doped impurities of the first conductivity type in the capping layer 308.
[0092] The first pitch SMD of the tips in each of the source / drain formation regions is less than or equal to the thickness of the inversion layer 304, and the lowest position of the top surface of the main body layer 307 in each of the source / drain formation regions is higher than the top surface of the source / drain trench 305. Figure 3 The diagram shows that the top surface of the main body layer 307 is a flat surface. However, in reality, the top surface of the main body layer 307 has a certain degree of undulation. The position of the top surface of the main body layer 307 is higher closer to the middle region of the source-drain trench 305, and lower closer to the edge region of the source-drain trench 305.
[0093] In this embodiment of the invention, the width of the source / drain trench 305 gradually increases from top to bottom between the top surface of the source / drain trench 305 and the plane where the tip is located; and the width of the source / drain trench 305 gradually decreases from top to bottom between the bottom surface of the source / drain trench 305 and the plane where the tip is located.
[0094] In some preferred embodiments, each of the source / drain trenches 305 has a ∑ shape.
[0095] The side surface of the main body layer 307 is perpendicular to the top surface of the source / drain trench 305.
[0096] At the top surface of each of the source / drain trenches 305, there is a second spacing greater than 0 nm between the side surface of the source / drain trench 305 and the side surface of the main body layer 307. Within the source / drain trench 305, the undoped structure of the buffer layer 306 completely encloses the main body layer 307. For example... Figure 3 As shown, on the plane corresponding to the dashed line BB, the undoped structure of the buffer layer 306, namely the first buffer layer 3061, has a lateral width, thus completely enclosing the main body layer 307. This prevents impurities of the first conductivity type in the main body layer 307 and the capping layer 308 from diffusing from the apex of the source / drain trench 305 into the channel region, thereby reducing leakage paths and thus reducing leakage.
[0097] In this embodiment of the invention, the semiconductor device is a PMOS transistor, with a first conductivity type of P-type and a second conductivity type of N-type. In other embodiments, the semiconductor device can also be an NMOS transistor, with a first conductivity type of N-type and a second conductivity type of P-type. The following explanation uses a PMOS transistor as an example: The first buffer layer 3061 is a SiGe layer, the second buffer layer 3062 is a SiGe layer, the main body layer 307 is a SiGe layer, and the cap layer 308 is a Si layer.
[0098] The Ge content of the second buffer layer 3062 is greater than that of the first buffer layer 3061, and the Ge content of the main body layer 307 is greater than that of the second buffer layer 3062.
[0099] In some embodiments, the first buffer layer 3061 is a SiGe layer with a Ge content of 25% and is undoped; the second buffer layer 3062 is a SiGe layer with a Ge content of 25% to 30%, and the p-type dopant is typically boron with a boron concentration of 5E19cm⁻¹. -3 The main body layer 307 is a SiGe layer with a Ge content of 30%–40% and a B concentration of 3E20cm⁻¹. -3 The capping layer 308 has a Ge content of 0 and a B concentration greater than 1E21cm. -3 .
[0100] In this embodiment of the invention, the doping concentration of the first conductivity type of the source and drain regions of each semiconductor device is the same, and the doping concentration of the first conductivity type of the source and drain regions of each semiconductor device is guaranteed to reduce the leakage current of the semiconductor device with the largest contact width Thru-W to below the required value.
[0101] In this embodiment of the invention, the size of the first spacing SMD between the plane at the tip of the source / drain trench 305 in the source / drain formation region and the top surface of the source / drain trench 305 is set. The first spacing SMD is set to be less than or equal to the thickness of the inversion layer 304 and to ensure that the lowest position of the top surface of the main layer 307 in each source / drain formation region is higher than the top surface of the source / drain trench 305, wherein: The first spacing SMD is less than or equal to the thickness of the inversion layer 304, which can increase the stress effect of the embedded epitaxial layer on the inversion layer 304 in the channel region, thereby increasing the carrier mobility of the inversion layer 304 and improving the device performance such as channel conduction capability.
[0102] Since reducing the first spacing SMD raises the top surface of the main layer 307, the setting of the first spacing SMD ensures that the lowest position of the top surface of the main layer 307 in each source / drain formation region is higher than the top surface of the source / drain trench 305. This also increases the spacing between the capping layer 308 with higher doping concentration and the channel region, reducing the diffusion of first conductivity type impurities into the channel region. Therefore, it can reduce the leakage path caused by the diffusion of first conductivity type impurities into the channel region. Thus, the embodiment of the present invention can reduce the leakage current of the device by reducing the first spacing SMD.
[0103] In addition to adjusting the first spacing SMD, this invention can further reduce the doping concentration of the first conductivity type in the source and drain regions. This further reduces the amount of first conductivity type impurities diffusing into the channel region, thereby further reducing the leakage path and thus further reducing the leakage current of the device. By setting the doping concentration of the first conductivity type in the source and drain regions of the semiconductor device to ensure that the leakage current of the semiconductor device with the largest contact width Thru-W is reduced to below the required value, the defect that the leakage current is also large when the contact width Thru-W is too large can be prevented. The leakage current of various contact widths Thru-W is reduced to meet the requirements and does not increase with the increase of the contact width Thru-W. This makes the leakage current of semiconductor devices with various contact widths Thru-W small and consistent.
[0104] The method for manufacturing a semiconductor device with an embedded epitaxial layer according to embodiments of the present invention includes the following steps: Step 1: Provide a semiconductor substrate 301, and form a gate structure 302 on the top surface of the semiconductor substrate 301 in the gate forming region of each semiconductor device.
[0105] A channel region doped with a second conductivity type is formed at the bottom of the gate structure 302. When the semiconductor device is turned on, an inversion layer 304 is formed on the surface of the channel region.
[0106] In the method of this embodiment, each gate structure 302 includes a gate dielectric layer (not shown) and a gate conductive material layer (not shown) stacked sequentially. A sidewall 303 is also formed on the side of the gate structure 302.
[0107] In some embodiments, the semiconductor substrate is doped with a second conductivity type, and the channel region is directly formed by the semiconductor substrate at the bottom of the gate structure 302. Figure 3 The channel region shown is directly formed by the semiconductor substrate at the bottom of the gate structure 302. In other embodiments, a second conductivity type doped region may be formed in the surface region of the semiconductor substrate 301, and the channel region may be formed by the second conductivity type doped region at the bottom of the gate structure 302.
[0108] Since the channel region is doped with the second conductivity type, the conductivity type of the carriers in the inversion layer 304 is opposite to that of the channel region. Therefore, the carriers in the inversion layer 304 are carriers of the first conductivity type. Taking a PMOS transistor as an example, the first conductivity type is P-type, the second conductivity type is N-type, and the carriers in the inversion layer 304 are holes.
[0109] In some embodiments, the thickness of the inversion layer 304 is less than 10 nm.
[0110] The region between each of the gate structures 302 is a source / drain formation region, and the width of the source / drain formation region is the contact width Thru-W; the contact width Thru-W can take multiple values.
[0111] Step 2: Form source / drain trenches 305 in each of the source / drain formation regions and adjust the size of the first spacing SMD.
[0112] Each side of the source / drain trench 305 has a tip, and the first spacing SMD is the distance between the plane where the tip is located and the top surface of the source / drain trench 305; the first spacing SMD of the tip in each source / drain forming region is less than or equal to the thickness of the inversion layer 304.
[0113] In the method of this embodiment of the invention, the width of the source / drain trench 305 gradually increases from top to bottom between the top surface of the source / drain trench 305 and the plane where the tip is located; the width of the source / drain trench 305 gradually decreases from top to bottom between the bottom surface of the source / drain trench 305 and the plane where the tip is located.
[0114] In some preferred embodiments, each of the source / drain trenches 305 has a ∑ shape.
[0115] Typically, the source / drain trench 305 is achieved through two etching processes. The first etching is a dry etching process, which is anisotropic, and the trenches formed by the etching process have vertical sides. The second etching process is a wet etching process. Taking the semiconductor substrate 301 as a silicon substrate as an example, the wet etching solution can be tetramethylammonium hydroxide (TMAH). This results in different etching rates for different crystal orientations, causing the trenches to expand and become the source / drain trench 305 with a Σ shape.
[0116] In the method of this embodiment, the top opening of each source / drain trench 305 is defined by the side alignment of the sidewalls 303 of the gate structure 302 on both sides. That is, the width of the top opening of the source / drain trench 305 is determined by the contact width Thru-W. Since the source / drain trenches 305 are formed using the same etching process, different widths of the top openings of the source / drain trenches 305 result in different etching loads, ultimately leading to different etching depths. Generally, under the same etching conditions, the larger the width of the top opening of the source / drain trench 305, the deeper the source / drain trench 305.
[0117] Step 3: Fill the source-drain trench 305 with an embedded epitaxial layer.
[0118] The embedded epitaxial layer includes a buffer layer 306, a main layer 307, and a capping layer 308; the buffer layer 306 includes an undoped structure, the main layer 307 and the capping layer 308 are both heavily doped with a first conductivity type, and the doping concentration of the first conductivity type of the capping layer 308 is greater than the doping concentration of the first conductivity type of the main layer 307.
[0119] In the method of this embodiment of the invention, the buffer layer 306 includes a first buffer layer 3061 and a second buffer layer 3062 stacked sequentially.
[0120] The first buffer layer 3061 is formed on the inner surface of the source-drain trench 305.
[0121] The second buffer layer 3062 is formed on the top surface of the first buffer layer 3061.
[0122] The first buffer layer 3061 is an undoped structure.
[0123] The second buffer layer 3062 is doped with a first conductivity type, and the doping concentration of the first conductivity type of the second buffer layer 3062 is less than the doping concentration of the first conductivity type of the main body layer 307.
[0124] The heavily doped impurities of the first conductivity type in the source and drain regions of each semiconductor device are respectively composed of heavily doped impurities of the first conductivity type in the embedded epitaxial layers on both sides of the corresponding gate structure 302. The heavily doped impurities of the first conductivity type in the source and drain regions of each semiconductor device are mainly composed of doped impurities of the first conductivity type in the capping layer 308.
[0125] The first spacing SMD also ensures that the lowest position of the top surface of the main layer 307 in each of the source / drain formation regions is higher than the top surface of the source / drain trench 305. This prevents the capping layer 308 with the highest doping concentration from approaching the channel region, thereby preventing the diffusion of the first conductivity type impurities generated on the right side of the capping layer 308 into the channel region, thus reducing the leakage path generated on the right side.
[0126] The first conductivity type heavily doped impurities in the source and drain regions of each semiconductor device are respectively composed of the first conductivity type heavily doped impurities in the embedded epitaxial layers on both sides of the corresponding gate structure 302.
[0127] The side surface of the main body layer 307 is perpendicular to the top surface of the source / drain trench 305.
[0128] In the source / drain formation region corresponding to at least the largest contact width Thru-W, at the top surface position of the source / drain trench 305, there is a second spacing greater than 0 nm between the side surface of the source / drain trench 305 and the side surface of the main body layer 307. In the source / drain trench 305, the undoped structure of the buffer layer 306 completely encloses the main body layer 307. The structure in which the undoped structure of the buffer layer 306 completely encloses the main body layer 307 further prevents the diffusion of second conductivity type dopants from the main body layer 307 and the capping layer 308 into the channel region.
[0129] In the method of this embodiment of the invention, the buffer layer 306 includes a first buffer layer 3061 and a second buffer layer 3062 stacked sequentially.
[0130] The first buffer layer 3061 is formed on the inner surface of the source-drain trench 305.
[0131] The second buffer layer 3062 is formed on the top surface of the first buffer layer 3061.
[0132] The first buffer layer 3061 is an undoped structure.
[0133] The second buffer layer 3062 is doped with a first conductivity type, and the doping concentration of the first conductivity type of the second buffer layer 3062 is less than the doping concentration of the first conductivity type of the main body layer 307.
[0134] In the method of this embodiment, the semiconductor device is a PMOS transistor, with a first conductivity type of P-type and a second conductivity type of N-type. In other embodiments, the semiconductor device can also be an NMOS transistor, with a first conductivity type of N-type and a second conductivity type of P-type. The following explanation uses a PMOS transistor as an example only: The first buffer layer 3061 is a SiGe layer, the second buffer layer 3062 is a SiGe layer, the main body layer 307 is a SiGe layer, and the cap layer 308 is a Si layer.
[0135] The Ge content of the second buffer layer 3062 is greater than that of the first buffer layer 3061, and the Ge content of the main body layer 307 is greater than that of the second buffer layer 3062.
[0136] In the method of this embodiment of the invention, in step two, the leakage current of the corresponding semiconductor device is reduced by decreasing the first spacing SMD, while the channel conductivity of the semiconductor device is simultaneously improved. That is, when the leakage current of the semiconductor device is large, the first spacing SMD can be further reduced. Reducing the first spacing SMD not only reduces the leakage current, but also further improves the device performance. This is mainly achieved by reducing the stress in the channel region and thereby increasing the mobility of channel carriers.
[0137] In step three, the doping concentration of the first conductivity type in the source and drain regions of each semiconductor device is the same. By reducing the doping concentration of the first conductivity type in the source and drain regions of each semiconductor device, the leakage current of each semiconductor device is reduced. The doping concentration of the first conductivity type in the source and drain regions of each semiconductor device ensures that the leakage current of the semiconductor device with the largest contact width Thru-W is reduced to below the required value. In the method of this embodiment, the opening width of the source-drain trench 305 is defined by the contact width Thru-W. Since the source-drain trenches 305 of various widths are formed using the same etching process, the source-drain trench 305 with the largest opening will have the deepest etching depth. The corresponding spacing between the capping layer 308 and the channel region is the smallest, and it is also the easiest for the first conductivity type impurities to diffuse into the channel region. Therefore, by reducing the doping concentration of the source and drain regions of the semiconductor devices, the leakage current of the semiconductor device corresponding to the source-drain trench 305 with the largest opening meets the requirements, and the leakage current of the semiconductor devices corresponding to the source-drain trenches 305 with smaller openings also meets the requirements.
[0138] Therefore, in the method of the present invention, the leakage current of the device can be reduced and the performance of the device can be guaranteed by reducing the first spacing SMD and reducing the doping concentration of the source and drain regions of each semiconductor device. Finally, it can be achieved that the leakage current of the semiconductor devices corresponding to various contact widths Thru-W meets the requirements and the leakage current does not increase with the increase of the contact width Thru-W.
[0139] like Figure 4 The figure shown is a test graph of the leakage current of a semiconductor device with an embedded epitaxial layer as a function of contact width according to an embodiment of the present invention. Figure 4 middle: Curve 201 and Figure 2 The curves in the figure are the same as those in curve 201, which are test curves of leakage current versus contact width for existing semiconductor devices with embedded epitaxial layers. Curve 202 and Figure 2 The curve 202 is the same as the curve 201. It is obtained by testing when the device speed is slowed down by 9%. Slowing down the device speed by 9% can be achieved by reducing RVP from 0% to -9%. The leakage current is reduced in the whole by curve 201, but the upward slope is the same.
[0140] Curve 203 is a test curve of leakage current versus contact width obtained by reducing the doping concentration of the first conductivity type in the source and drain regions, such as the B concentration corresponding to a PMOS transistor, based on the existing semiconductor device with embedded epitaxial layer corresponding to curve 201. It can be seen that although the leakage current does not change with the contact width, the leakage current is still relatively high and cannot be further reduced. If the B concentration is further reduced, it will inevitably affect the performance of the device, such as increasing the resistance of the source and drain regions and decreasing the conduction current of the device.
[0141] Curve 204 corresponds to Figure 4 Curve 204 is a test curve showing the leakage current of a semiconductor device with an embedded epitaxial layer as a function of contact width, obtained by further reducing the first spacing SMD of the existing semiconductor device with an embedded epitaxial layer, as shown in Curve 203. It can be seen that reducing the first spacing SMD can further reduce the leakage current, and Curve 204 will shift further downward based on Curve 203. It can be seen from Curve 204 that the leakage current of semiconductor devices with various contact widths meets the requirements and does not cause an upward tilt.
[0142] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.
Claims
1. A semiconductor device having an embedded epitaxial layer, characterized in that: Multiple semiconductor devices are integrated on the same semiconductor substrate; Each of the semiconductor devices includes a gate structure formed on the top surface of a semiconductor substrate; A channel region doped with a second conductivity type is formed at the bottom of the gate structure, and an inversion layer is formed on the surface of the channel region when the semiconductor device is turned on. The region between each of the gate structures is a source / drain formation region, and the width of the source / drain formation region is the contact width; Each of the source / drain formation regions includes a source / drain trench, each side of the source / drain trench has a tip, and there is a first gap between the plane where the tip is located and the top surface of the source / drain trench; An embedded epitaxial layer is filled in the source-drain trench; The embedded epitaxial layer includes a buffer layer, a main body layer, and a capping layer; The buffer layer includes an undoped structure, and both the main layer and the capping layer are heavily doped with a first conductivity type, with the doping concentration of the first conductivity type of the capping layer being greater than the doping concentration of the first conductivity type of the main layer. The first conductivity type of heavily doped impurities in the source and drain regions of each semiconductor device are respectively composed of the first conductivity type of heavily doped impurities in the embedded epitaxial layers on both sides of the corresponding gate structure; The first spacing between the tips in each of the source / drain formation regions is less than or equal to the thickness of the inversion layer, and the lowest position of the top surface of the main layer in each of the source / drain formation regions is higher than the top surface of the source / drain trench.
2. The semiconductor device with an embedded epitaxial layer as described in claim 1, characterized in that: Between the top surface of the source / drain trench and the plane where the tip is located, the width of the source / drain trench gradually increases from top to bottom; between the bottom surface of the source / drain trench and the plane where the tip is located, the width of the source / drain trench gradually decreases from top to bottom. The side surface of the main body layer is perpendicular to the top surface of the source / drain trench; At the top surface position of each of the source / drain trenches, there is a second spacing greater than 0 nm between the side of the source / drain trench and the side of the main body layer, and in the source / drain trench, the undoped structure of the buffer layer completely encloses the main body layer.
3. The semiconductor device with an embedded epitaxial layer as described in claim 2, characterized in that: The buffer layer includes a first buffer layer and a second buffer layer stacked sequentially. The first buffer layer is formed on the inner surface of the source-drain trench; The second buffer layer is formed on the top surface of the first buffer layer; The first buffer layer is a non-doped structure; The second buffer layer is doped with a first conductivity type, and the doping concentration of the first conductivity type of the second buffer layer is less than the doping concentration of the first conductivity type of the host layer.
4. The semiconductor device with an embedded epitaxial layer as described in claim 3, characterized in that: The semiconductor device is a PMOS transistor, with the first conductivity type being P-type and the second conductivity type being N-type.
5. The semiconductor device with an embedded epitaxial layer as described in claim 4, characterized in that: The first buffer layer is a SiGe layer, the second buffer layer is a SiGe layer, the main body layer is a SiGe layer, and the capping layer is a Si layer; The Ge content of the second buffer layer is greater than that of the first buffer layer, and the Ge content of the main body layer is greater than that of the second buffer layer.
6. The semiconductor device with an embedded epitaxial layer as described in claim 4, characterized in that: Each of the gate structures includes a gate dielectric layer and a gate conductive material layer stacked sequentially, and a sidewall is also formed on the side of the gate structure; The top opening of each of the source and drain trenches is defined by the side alignment of the sidewalls of the gate structure on both sides; Each of the aforementioned source / drain trenches has a ∑ shape.
7. The semiconductor device with an embedded epitaxial layer as described in claim 4, characterized in that: The contact width can take multiple values; the doping concentration of the first conductivity type of the source and drain regions of each semiconductor device is the same, and the doping concentration of the first conductivity type of the source and drain regions of each semiconductor device is guaranteed to reduce the leakage current of the semiconductor device with the largest contact width to below the required value.
8. The semiconductor device with an embedded epitaxial layer as described in claim 1, characterized in that: The thickness of the inversion layer is less than 10 nm.
9. A method for manufacturing a semiconductor device having an embedded epitaxial layer, characterized in that, Includes the following steps: Step 1: Provide a semiconductor substrate and form a gate structure on the top surface of the semiconductor substrate in the gate forming region of each semiconductor device; A channel region doped with a second conductivity type is formed at the bottom of the gate structure, and an inversion layer is formed on the surface of the channel region when the semiconductor device is turned on. The region between each of the gate structures is a source / drain formation region, and the width of the source / drain formation region is the contact width; Step 2: Form source / drain trenches in each of the source / drain formation regions and adjust the size of the first spacing; Each side of the source / drain trench has a pointed tip, and the first spacing is the distance between the plane where the pointed tip is located and the top surface of the source / drain trench; the first spacing of the pointed tips in each source / drain formation region is less than or equal to the thickness of the inversion layer; Step 3: Fill the source / drain trenches with an embedded epitaxial layer; The embedded epitaxial layer includes a buffer layer, a host layer, and a capping layer; the buffer layer includes an undoped structure, and both the host layer and the capping layer are heavily doped with a first conductivity type, with the doping concentration of the first conductivity type of the capping layer being greater than the doping concentration of the first conductivity type of the host layer; The first spacing also ensures that the lowest position of the top surface of the main layer in each of the source / drain formation regions is higher than the top surface of the source / drain trench; The first conductivity type heavily doped impurities in the source and drain regions of each semiconductor device are respectively composed of the first conductivity type heavily doped impurities in the embedded epitaxial layers on both sides of the corresponding gate structure.
10. The method for manufacturing a semiconductor device having an embedded epitaxial layer as described in claim 9, characterized in that: Between the top surface of the source / drain trench and the plane where the tip is located, the width of the source / drain trench gradually increases from top to bottom; between the bottom surface of the source / drain trench and the plane where the tip is located, the width of the source / drain trench gradually decreases from top to bottom. The side surface of the main body layer is perpendicular to the top surface of the source / drain trench; At the top surface position of each of the source / drain trenches, there is a second spacing greater than 0 nm between the side of the source / drain trench and the side of the main body layer, and in the source / drain trench, the undoped structure of the buffer layer completely encloses the main body layer.
11. The method for manufacturing a semiconductor device having an embedded epitaxial layer as described in claim 10, characterized in that: The buffer layer includes a first buffer layer and a second buffer layer stacked sequentially. The first buffer layer is formed on the inner surface of the source-drain trench; The second buffer layer is formed on the top surface of the first buffer layer; The first buffer layer is a non-doped structure; The second buffer layer is doped with a first conductivity type, and the doping concentration of the first conductivity type of the second buffer layer is less than the doping concentration of the first conductivity type of the host layer.
12. The method for manufacturing a semiconductor device with an embedded epitaxial layer as described in claim 11, characterized in that: The semiconductor device is a PMOS transistor, with the first conductivity type being P-type and the second conductivity type being N-type.
13. The method for manufacturing a semiconductor device having an embedded epitaxial layer as described in claim 12, characterized in that: The first buffer layer is a SiGe layer, the second buffer layer is a SiGe layer, the main body layer is a SiGe layer, and the capping layer is a Si layer; The Ge content of the second buffer layer is greater than that of the first buffer layer, and the Ge content of the main body layer is greater than that of the second buffer layer.
14. The method for manufacturing a semiconductor device having an embedded epitaxial layer as described in claim 12, characterized in that: Each of the gate structures includes a gate dielectric layer and a gate conductive material layer stacked sequentially, and a sidewall is also formed on the side of the gate structure; The top opening of each of the source and drain trenches is defined by the side alignment of the sidewalls of the gate structure on both sides; Each of the aforementioned source / drain trenches has a ∑ shape.
15. The method for manufacturing a semiconductor device having an embedded epitaxial layer as described in claim 9, characterized in that: The thickness of the inversion layer is less than 10 nm.
16. The method for manufacturing a semiconductor device having an embedded epitaxial layer as described in claim 12, characterized in that: In step two, the leakage current of the corresponding semiconductor device is reduced by narrowing the first spacing, while the channel conductivity of the semiconductor device is improved at the same time.
17. The method for manufacturing a semiconductor device having an embedded epitaxial layer as described in claim 16, characterized in that: The contact width can take multiple values; in step three, the doping concentration of the first conductivity type of the source and drain regions of each semiconductor device is the same. By reducing the doping concentration of the first conductivity type of the source and drain regions of each semiconductor device, the leakage current of each semiconductor device is reduced. The doping concentration of the first conductivity type of the source and drain regions of each semiconductor device ensures that the leakage current of the semiconductor device with the largest contact width is reduced to below the required value.