Semiconductor device and method of manufacturing the same

Abstract

According to one embodiment, a semiconductor device includes: a first electrode; the semiconductor part is arranged on the first electrode and is provided with a groove extending along a first direction; the semiconductor portion includes a first semiconductor layer of a first conductivity type connected to the first electrode, a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and a third semiconductor layer of the first conductivity type provided on the second semiconductor layer. And a gate electrode disposed in the trench so as to face the second semiconductor layer and the third semiconductor layer in a second direction orthogonal to the first direction, and having an opposing surface formed so as to be separated from the third semiconductor layer upward at a position facing the third semiconductor layer.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2024-157600 (filed on September 11, 2024). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention generally relate to semiconductor devices and methods of manufacturing the same. Background Technology

[0004] Technologies related to trench-structured MOS (metal-oxide-semiconductor) have been developed. Summary of the Invention

[0005] According to one embodiment, a semiconductor device includes: a first electrode; a semiconductor portion disposed on the first electrode and having a trench extending along a first direction, the semiconductor portion having: a first semiconductor layer of a first conductivity type connected to the first electrode, a second semiconductor layer of a second conductivity type disposed on the first semiconductor layer, and a third semiconductor layer of the first conductivity type disposed on the second semiconductor layer; a gate electrode disposed in the trench in a second direction orthogonal to the first direction, such that it is opposite to the second semiconductor layer and the third semiconductor layer, and having a facing surface formed at the position opposite to the third semiconductor layer such that it moves away from the third semiconductor layer as it faces upward; a first insulating portion continuously disposed on the semiconductor portion and in the trench; a second insulating portion disposed on the gate electrode and having a different material than the first insulating portion; and a second electrode disposed on the semiconductor portion and connected to the second semiconductor layer and the third semiconductor layer.

[0006] According to another embodiment, a method for manufacturing a semiconductor device includes: a step of forming a silicon nitride film on a structure, the structure including: a semiconductor portion having a trench extending along a first direction and containing silicon; a gate electrode disposed within the trench and containing silicon; and an insulating portion disposed between the semiconductor portion and the gate electrode, having a recess formed on the gate electrode; a step of forming a silicon oxide film on the silicon nitride film; a step of removing the silicon oxide film in a region other than the area directly above the recess by performing a planarization process; a step of etching the silicon nitride film using the silicon oxide film on the recess as a mask; and a step of oxidizing the gate electrode.

[0007] According to this embodiment, a trench structure semiconductor device and a method thereof can be provided that can reduce Qg (total gate charge) without increasing Ron (also known as drain-source resistance / on-resistance). Attached Figure Description

[0008] Figure 1 This is a top view of the semiconductor device according to the embodiment.

[0009] Figure 2 This is a cross-sectional view at height L1 of region D1.

[0010] Figure 3 This is a cross-sectional view at height L2 of region D1.

[0011] Figure 4 This is a cross-sectional view at height L3 of region D1.

[0012] Figure 5 yes Figures 2-4 The VV line section view in the diagram.

[0013] Figure 6 This is a magnified view of region D4.

[0014] Figure 7 yes Figures 2-4 Sectional view along line VII-VII.

[0015] Figure 8 yes Figures 2-4 Sectional view along line VIII-VIII.

[0016] Figure 9 It is a schematic 3D representation of region D2.

[0017] Figure 10 It is a three-dimensional diagram schematically representing a portion of the structure of region D3.

[0018] Figure 11 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0019] Figure 12 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0020] Figure 13 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0021] Figure 14 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0022] Figure 15 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0023] Figure 16 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0024] Figure 17 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0025] Figure 18 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0026] Figure 19 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0027] Figure 20 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0028] Figure 21 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment. Detailed Implementation

[0029] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. These embodiments do not limit the scope of the invention. The drawings are schematic or conceptual, and the proportions of the parts may not be identical to those in reality. In the specification and drawings, elements identical to those previously described in the accompanying drawings are labeled with the same reference numerals, and detailed descriptions are omitted where appropriate.

[0030] In the description of the implementation method, an XYZ orthogonal coordinate system is used. The direction from the drain electrode 41 toward the source electrode 42 is defined as the Z direction. The two directions perpendicular to and orthogonal to the Z direction are defined as the X direction and the Y direction.

[0031] Furthermore, terms used in this specification that define shape, geometry, and their degree, such as "parallel" and "identical," are not strictly defined and are interpreted to include the range of degrees to which the same function can be expected.

[0032] In the following explanation, n + n - and p + The terms "p" and "n" indicate the relative levels of impurity concentration in each conductivity type. Specifically, a term marked with "+" indicates a relatively higher impurity concentration compared to a term without either "+" or "-", while a term marked with "-" indicates a relatively lower impurity concentration compared to a term without either. When each region contains both p-type and n-type impurities, these terms represent the relative levels of actual impurity concentration after mutual compensation. Regarding the embodiments described below, each embodiment can also be implemented by reversing the p-type and n-type characteristics of each semiconductor region.

[0033] (1. Structure of semiconductor device 100)

[0034] Reference Figures 1-10 The semiconductor device 100 of this embodiment will be described.

[0035] Figure 1 This is a top view of the semiconductor device according to the embodiment.

[0036] Figure 2 This is a cross-sectional view at height L1 of region D1.

[0037] Figure 3 This is a cross-sectional view at height L2 of region D1.

[0038] Figure 4 This is a cross-sectional view at height L3 of region D1.

[0039] Figure 5 yes Figures 2-4 The VV line section view in the diagram.

[0040] Figure 6 This is a magnified view of region D4.

[0041] Figure 7 yes Figures 2-4 Sectional view along line VII-VII.

[0042] Figure 8 yes Figures 2-4 Sectional view along line VIII-VIII.

[0043] Figure 9 It is a schematic 3D representation of region D2.

[0044] Figure 10 It is a three-dimensional diagram schematically representing a portion of the structure of region D3.

[0045] Semiconductor device 100 is, for example, a power MOSFET. Figure 1 As shown, a source electrode 42 serving as a second electrode, a gate pad 61, and a gate wiring 62 are disposed on the upper surface of the semiconductor device 100. Furthermore, a drain electrode 41 serving as a first electrode is disposed throughout the lower surface of the semiconductor device 100.

[0046] The source electrode 42 is configured as a rectangle having a long side in the first direction (Y direction in the figure, hereinafter referred to as the Y direction) when viewed from above. As an example, three source electrodes 42 are disposed on the upper surface of the semiconductor device 100, but this is not a limitation. As an example, the gate pad 61 is rectangular when viewed from above, located at one end of a second direction orthogonal to the first direction (X direction in the figure, hereinafter referred to as the X direction) and at one end of the Y direction. The gate wiring 62 is configured to extend from the gate pad 61 along the X direction, and further, to extend along the Y direction adjacent to the source electrode 42. Furthermore, the location of the gate pad 61 is not limited to this example.

[0047] like Figures 2-4 As shown, in the semiconductor device 100, there are provided a cell section (a region having a structure represented by a VV cross section), a gate finger section (a region having a structure represented by a VII-VII cross section), and a source finger section (a region having a structure represented by a VIII-VIII cross section).

[0048] like Figure 5 As shown, the unit section includes a semiconductor section 10, a drain electrode 41 serving as a first electrode, and a source electrode 42.

[0049] The semiconductor section 10, for example, includes silicon and is disposed between the drain electrode 41 and the source electrode 42. The semiconductor section 10 includes a first semiconductor layer 10a of a first conductivity type, a second semiconductor layer 10b of a second conductivity type, a third semiconductor layer 10c of a first conductivity type, and a fourth semiconductor layer 10d of a second conductivity type. Hereinafter, as an example, the first conductivity type will be described as n-type and the second conductivity type as p-type, but it is not limited to this.

[0050] The first semiconductor layer 10a, for example, includes n disposed on the upper surface of the drain electrode 41. + Type drift layer, and configured in n + n on the upper surface of the drift layer - Type-shifting layer. The first semiconductor layer 10a extends between the drain electrode 41 and the source electrode 42.

[0051] The second semiconductor layer 10b is, for example, a p-type substrate layer. The second semiconductor layer 10b is disposed on the first semiconductor layer 10a.

[0052] The third semiconductor layer 10c is, for example, n. + A third semiconductor layer 10c is partially disposed on the second semiconductor layer 10b. The third semiconductor layer 10c is electrically connected to the source electrode 42.

[0053] The fourth semiconductor layer 10d is, for example, p. +Type contact layer. The fourth semiconductor layer 10d is partially disposed on the second semiconductor layer 10b. The fourth semiconductor layer 10d contains a second conductivity type impurity with a higher concentration than the second semiconductor layer 10b. The source electrode 42 is electrically connected to the second semiconductor layer 10b, the third semiconductor layer 10c and the fourth semiconductor layer 10d via the source contact 51.

[0054] A plurality of trenches TR extending along the X direction are formed in the semiconductor section 10. As an example, the trenches TR are formed into elongated grooves with curved bottoms, but this is not limited to this example. A field plate electrode 11, a gate electrode 12, and a first insulating portion 30 are disposed within the trenches TR.

[0055] The field plate electrode 11 is provided such that it extends along the X direction at the lower part of the trench TR in the cell section. Specifically, the field plate electrode 11 is arranged opposite to the first semiconductor layer 10a. The field plate electrode 11 is a conductor and, as described later, is electrically connected to the source electrode 42 via the field plate contact portion 57 in the source finger portion. The shape of the field plate electrode 11 in the ZX plane can also be, for example, a semi-elongated cylinder that is elongated vertically and curved along the cross section of the trench TR, but it is not limited to this example.

[0056] The gate electrode 12 is provided such that it extends along the X direction above the trench TR in the cell portion. As an example, the gate electrode 12 may also be polysilicon mixed with impurities. Specifically, the gate electrode 12 is arranged opposite to the second semiconductor layer 10b and the third semiconductor layer 10c. At the position opposite to the third semiconductor layer 10c, the gate electrode 12 has opposing surfaces 13 at both ends along the Y direction, formed such that they move away from the third semiconductor layer 10c as they move upwards. The shape in the ZX plane below the opposing surface 13 of the gate electrode 12 may be rectangular, but is not limited to this example. Details of the opposing surface 13 will be described later.

[0057] The first insulating portion 30 comprises silicon oxide (SiO2) and is continuously disposed within the trench TR and on the semiconductor portion 10. Specifically, the first insulating portion 30 includes a field plate insulating portion 30a, an interlayer portion 30b, a gate insulating portion 30c, and an upper layer portion 30d.

[0058] To insulate the field plate electrode 11 from the first semiconductor layer 10a, a field plate insulating portion 30a is disposed around the side and below the field plate electrode 11. To insulate the gate electrode 12 from the field plate electrode 11, an interlayer portion 30b is disposed in a layered manner between the gate electrode 12 and the field plate electrode 11.

[0059] The gate insulating portion 30c is disposed around the side of the gate electrode 12 to insulate the gate electrode 12 from the second semiconductor layer 10b and the third semiconductor layer 10c. In order to insulate the third semiconductor layer 10c from the gate electrode 12, the upper layer portion 30d is disposed layered on the third semiconductor layer 10c.

[0060] A second insulating portion 31, made of a different material than the first insulating portion 30, is disposed above the gate electrode 12. For example, the second insulating portion 31 comprises silicon nitride (SiN), insulating the gate electrode 12 from the source electrode 42. For instance, the length (width) of the second insulating portion 31 in the Y direction is shorter than the length of the gate electrode 12 in the Y direction. A portion of the second insulating portion 31 is parallel to a portion of the third semiconductor layer 10c in the Y direction. The distance in the Y direction between the second insulating portion 31 and the third semiconductor layer 10c is longer than the distance in the Y direction between the opposing surface 13 and the third semiconductor layer 10c.

[0061] like Figure 6 As shown, the opposing surface 13 is formed at both ends along the Y direction, opposite to the third semiconductor layer 10c, in a manner that it moves away from the third semiconductor layer 10c as it faces upwards. The distance in the Y direction between the gate electrode 12 and the third semiconductor layer 10c is longer than the distance in the Y direction between the gate electrode 12 and the second semiconductor layer 10b. As an example, the opposing surface 13 could be... Figure 6 The curved surface shown can also be a plane, as another example. The length (height H1) of the opposing surface 13 in the Z direction is less than the height H2 of the third semiconductor layer 10c in the Z direction. The height H1 of the opposing surface 13 in the Z direction is preferably about H1 / H2 = 1 / 2 relative to the height H2 of the third semiconductor layer 10c. In addition, the width W3 of the opposing surface 13 in the Y direction is preferably about W3 / W4 = 1 / 3 relative to the distance W4 between the second semiconductor layer 10b and the gate electrode.

[0062] like Figure 7 As shown, a drain electrode 41, a semiconductor section 10, and a gate wiring 62 are disposed in the gate finger section.

[0063] The semiconductor portion 10 of the gate finger includes a first semiconductor layer 10a of a first conductivity type and a second semiconductor layer 10b of a second conductivity type. A pair of gate trenches TG extending along the Y direction are formed in the semiconductor portion 10 of the gate finger. As an example, the gate trenches TG are formed into elongated grooves with curved bottoms, but this is not a limitation. A field plate electrode 11, a gate electrode 12, and a gate contact portion 55 are disposed within the gate trenches TG.

[0064] The gate contact 55 is conductive, electrically connecting the gate wiring 62 to the first connection portion 12a of the gate electrode 12. Thus, current flows from the gate wiring 62 through the first connection portion 12a to the gate electrode 12. Furthermore, as an example, Figure 7 The cross-sectional area (area in the XZ plane) S1 of the gate electrode 12 in the gate finger portion shown can also be smaller than Figure 5 The cross-sectional area (area in the YZ plane) of the gate electrode 12 in the unit shown is S2. A first insulating portion 30 is disposed around the field plate electrode 11 and the gate electrode 12.

[0065] like Figure 8 As shown, a drain electrode 41, a semiconductor section 10, and a source electrode 42 are disposed in the source finger section.

[0066] The semiconductor portion 10 of the source finger includes a first semiconductor layer 10a of a first conductivity type and a second semiconductor layer 10b of a second conductivity type. A pair of source trenches TS extending along the Y direction are formed in the semiconductor portion 10 of the source finger. As an example, the source trenches TS are formed into elongated grooves with curved bottoms, but this is not a limitation. Field plate electrodes 11 and field plate contacts 57 are disposed within the source trenches TS.

[0067] The field plate contact 57 is conductive, electrically connecting the source electrode 42 to the second connection portion 11a of the field plate electrode 11. Thus, current flows from the source electrode 42 to the field plate electrode 11. Furthermore, the field plate electrode 11 in the source finger portion is a semi-cylindrical shape that is elongated vertically and curved along the cross-section of the source trench TS, positioned from a position opposite to the first semiconductor layer 10a to a position opposite to the second semiconductor layer 10b. A first insulating portion 30 is disposed around the field plate electrode 11.

[0068] like Figure 9 as well as Figure 10 As shown, the field electrode 11 is disposed in the source finger portion at a position opposite to the first semiconductor layer 10a and to the second semiconductor layer 10b within the source trench TS. In the cell portion and the gate finger portion, it is disposed at a position opposite to the first semiconductor layer 10a within the trench TR or the gate trench TG. The gate electrode 12 is not disposed in the source finger portion. In the cell portion and the gate finger portion, the gate electrode 12 is disposed at a position opposite to the second semiconductor layer 10b and the third semiconductor layer 10c within the trench TR or the gate trench TG.

[0069] (2. Method for manufacturing semiconductor device 100)

[0070] The following is for reference Figures 11-21 The manufacturing method of the semiconductor device 100 according to the embodiment will be described. Furthermore, in Figures 11-21In the diagram, (a) represents the cell portion, (b) represents the gate finger portion, and (c) represents the source finger portion. Furthermore, in the following description, the trench TR in the cell portion, the gate trench TG in the gate finger portion, and the source trench TS in the source finger portion are collectively referred to as trenches.

[0071] First, such as Figure 11 As shown in (a) to (c), a structure Y is prepared using a known method. This structure Y has trenches, includes a semiconductor portion 10 containing silicon of a first conductivity type, a field electrode 11 and a gate electrode 12 disposed within the trenches, and a first insulating portion 30 disposed between the semiconductor portion 10 and the gate electrode 12. A recess C is formed on the gate electrode 12. Then, a silicon nitride film 71 is formed on the structure Y using, for example, a CVD (Chemical Vapor Deposition) method. Consequently, a recess C1 reflecting the recess C is formed on the upper surface of the silicon nitride film 71.

[0072] Next, as Figure 12 As shown in (a) to (c), a silicon oxide film 72 is formed on a silicon nitride film 71 by CVD. As a result, a recess C2 reflecting the recess C1 is formed on the upper surface of the silicon oxide film 72.

[0073] Next, as Figure 13 As shown in (a) to (c), for example, by performing a planarization process based on CMP (Chemical Mechanical Polishing), the silicon oxide film 72 is removed in the region other than the area directly above the recess C. Thus, the silicon oxide film 72 remains only in the region directly above the recess C.

[0074] Next, as Figure 14 As shown in (a) to (c), the silicon oxide film 72 above the recess C is used as a mask material to etch the silicon nitride film 71. The etching can be anisotropic etching such as RIE (Reactive Ion Etching). As a result, the silicon nitride film 71 remains only in the region directly above the recess C, excluding the peripheral area. After the etching process of the silicon nitride film 71, the length of the silicon oxide film 72 in the Y direction is longer than the length of the silicon nitride film 71 in the Y direction.

[0075] Next, as Figure 15As shown in (a) to (c), the silicon oxide film 72 formed on the silicon nitride film 71 is retracted by etching. Here, the etching can be isotropic etching such as wet etching. As a result, the length of the trenches in the width direction of the silicon oxide film 72 formed on the silicon nitride film 71 is shorter than the length of the silicon nitride film 71 in the width direction. Furthermore, in the cell portion and the gate finger portion, the peripheral portion of the upper surface of the gate electrode 12 is exposed. After the etching process of the silicon oxide film 72, the length of the silicon oxide film 72 in the Y direction is shorter than the length of the silicon nitride film 71 in the Y direction. Additionally, the length of the silicon oxide film 72 in the Z direction is shorter than the length of the silicon nitride film 71 in the Z direction.

[0076] Next, as Figure 16 As shown in (a) to (c), the gate electrode 12 is subjected to an oxidation treatment. As a result, the exposed portions of the gate electrode 12 in the cell portion and the gate finger portion are oxidized and become part of the first insulating portion 30. Consequently, at the ends of the gate electrode 12 in the cell portion and the gate finger portion, opposing surfaces 13 are formed with a shape that moves away from the semiconductor portion 10 as it faces upwards. After the oxidation treatment, the length in the Y direction of the upper portion of the gate electrode 12 is shorter than the length in the Y direction of the lower portion of the gate electrode 12.

[0077] Next, as Figure 17 As shown in (a) to (c), impurities are implanted into the upper portion of the semiconductor portion 10 in the cell portion, gate finger portion, and source finger portion to form a second semiconductor layer 10b of the second conductivity type. Furthermore, impurities are implanted into the upper portion of the second semiconductor layer 10b in the cell portion to form a third semiconductor layer 10c of the first conductivity type. Thus, in the cell portion, the portion oxidized in the gate electrode 12, i.e., the opposing surface 13, faces the third semiconductor layer 10c of the first conductivity type.

[0078] Next, as Figure 18 As shown in (a) to (c), a silicon oxide film 73 is formed, for example, by CVD, on the third semiconductor layer 10c of the cell portion and on the second semiconductor layer 10b of the gate finger portion and the source finger portion.

[0079] Next, as Figure 19 As shown in (a) to (c), by performing a CMP-based planarization process, the silicon oxide film 73 is removed, exposing the upper surface of the silicon nitride film 71 located above the field electrode 11 or the gate electrode 12.

[0080] Next, as Figure 20As shown in (a) to (c), a resist pattern 74 with first openings P1 formed between multiple trenches TR is formed on the silicon oxide film 73. In the gate finger portion, the gate electrode 12 has a first connection portion 12a that connects to the gate wiring 62 provided on the upper surface of the semiconductor device 100, and the resist pattern 74 is formed without covering the first connection portion 12a. In addition, in the source finger portion, the field plate electrode 11 has a second connection portion 11a that connects to the source electrode 42 provided on the upper surface of the semiconductor device 100, and the resist pattern 74 is formed without covering the second connection portion 11a.

[0081] Then, using the resist pattern 74 as a mask, the silicon nitride film 71 is subjected to RIE (Resist-Enhanced Electrode) treatment. As a result, the silicon nitride film 71 disposed on the first connection portion 12a is removed, forming a second opening P2 for disposing of the gate contact 55. Additionally, the silicon nitride film 71 disposed on the second connection portion 11a is removed, forming a third opening P3.

[0082] Next, as Figure 21 As shown in (a) to (c), the silicon oxide film 73 is subjected to RIE using the resist pattern 74 as a mask. This forms a fourth opening P4 in the unit section for arranging the source contact 51. Furthermore, in the source finger section, the silicon oxide film 73 disposed on the second connecting portion 11a is removed, forming a fifth opening P5 for arranging the field plate contact 57.

[0083] Then, a source contact 51 is disposed in the fourth opening P4 in the unit section. Furthermore, a drain electrode 41 serving as a first electrode is disposed on the lower surface of the semiconductor section 10, and a source electrode 42 serving as a second electrode is disposed on the upper surface of the semiconductor section 10. Thus, a semiconductor device 100 is manufactured.

[0084] (3. Summary)

[0085] As described above, the semiconductor device 100 of this embodiment includes: a drain electrode 41 serving as a first electrode; a semiconductor portion 10 disposed on the drain electrode 41, comprising: a first semiconductor layer 10a of a first conductivity type connected to the drain electrode 41, a second semiconductor layer 10b of a second conductivity type disposed on the first semiconductor layer, and a third semiconductor layer 10 of a first conductivity type disposed on the second semiconductor layer, the semiconductor portion 10 having a trench extending along a Y direction, which is a first direction, and comprising silicon; and a gate electrode disposed within the trench along a second direction orthogonal to the Y direction, namely the X direction, and perpendicular to the second half-wavelength direction. The conductor layer 10b and the third semiconductor layer 10c are arranged opposite each other. At the positions opposite to the third semiconductor layer 10c, there are opposing surfaces 13 formed at both ends along the X direction, which move away from the third semiconductor layer 10c as they face upwards. A first insulating portion 30 is disposed above the semiconductor portion 10 and in the trench TR, and includes silicon oxide. A second insulating portion 31 is disposed above the gate electrode 12 and includes silicon nitride, which is made of a different material than the first insulating portion 30. A source electrode 42, which serves as the second electrode, is disposed above the semiconductor portion 10 and is connected to the second semiconductor layer 10b and the third semiconductor layer 10c.

[0086] By employing this structure, the height H1 of the third semiconductor layer 10c of the first conductivity type facing the gate electrode 12 can be ensured, and the distance in the Y direction between the third semiconductor layer 10c and the gate electrode 12 can be isolated. Therefore, the dominant force of the gate electrode 12 relative to the second semiconductor layer 10b can be ensured, and the parasitic capacitance between the third semiconductor layer 10c and the gate electrode 12 can be reduced. As a result, Qg can be reduced, and the rise of Ron can be suppressed.

[0087] Furthermore, the manufacturing method of the semiconductor device 100 includes: a step of forming a silicon nitride film 71 on a structure Y, the structure Y including: a semiconductor portion 10 having a trench TR extending along the Y direction and containing silicon; a gate electrode 12 disposed in the trench TR and containing silicon; and a first insulating portion 30 disposed between the semiconductor portion 10 and the gate electrode 12, with a recess C formed on the gate electrode 12; a step of forming a silicon oxide film 72 on the silicon nitride film 71; and a step of performing a planarization process to form a silicon oxide film 72 in the region directly above the recess C. The process includes: removing the silicon oxide film 72 in the area outside the recess; etching the silicon nitride film 71 using the silicon oxide film 72 on the recessed portion C as a mask; etching the silicon oxide film 72; oxidizing the gate electrode 12; implanting impurities into the semiconductor portion 10 and using the upper part of the semiconductor portion 10 as the second semiconductor layer 10b of the second conductivity type; implanting impurities into the semiconductor portion 10 and using the upper part of the second semiconductor layer 10b, which is opposite to the oxidized portion in the gate electrode 12, as the first conductivity type. The process includes: forming a third semiconductor layer 10c; forming a silicon oxide film 73 on the third semiconductor layer 10c; exposing a silicon nitride film 71 by performing a planarization process; forming a resist pattern 74 with a first opening P1 between multiple trenches TR; etching the silicon oxide film 73 using the resist pattern 74 as a mask; in the process of forming the resist pattern 74, the resist pattern 74 does not cover the first connection portion 12a, and after the process of forming the resist pattern 74, the silicon nitride film disposed on the first connection portion 12a is... The process includes: removing the silicon nitride film 71; in the process of forming the resist pattern 74, the resist pattern does not cover the second connection portion 11a; in the process of removing the silicon nitride film 71, the silicon nitride film 71 disposed on the second connection portion 11a is also removed; after the process of removing the silicon nitride film 71, the process of removing the silicon oxide film 73 disposed on the second connection portion 11a; a process of providing a drain electrode 41 as a first electrode on the lower surface of the semiconductor portion 10; and a process of providing a source electrode 42 as a second electrode on the upper surface of the semiconductor portion 10.

[0088] By employing such a process, the silicon nitride film 71 is used as a barrier film in the CMP-based planarization process, improving the planarity of the interlayer film, thereby enabling the miniaturization of the semiconductor device 100 and suppressing the rise of Ron.

[0089] Specifically, by adopting the above structure, the focus margin can be improved and the width of the fourth opening P4 for arranging the source contact 51 can be narrowed during the process of forming the resist pattern 74, thereby enabling miniaturization of the semiconductor device 100. Furthermore, by adopting the above structure, the fourth opening P4 for arranging the source contact 51, the second opening P2 for arranging the gate contact 55, and the fifth opening P5 for arranging the field plate contact 57 can be formed in the same process. Moreover, since the first opening P1 is formed between the plurality of trenches TR by forming the resist pattern 74, alignment deviations caused by the self-alignment of the first opening P1 can be prevented.

[0090] The foregoing has described several embodiments of the present invention, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention and its equivalents as described in the claims.

[0091] The present invention includes the following methods.

[0092] (Postscript 1)

[0093] A semiconductor device comprising:

[0094] First electrode;

[0095] A semiconductor portion is disposed on the first electrode and has a trench extending along a first direction. The semiconductor portion includes: a first semiconductor layer of a first conductivity type connected to the first electrode, a second semiconductor layer of a second conductivity type disposed on the first semiconductor layer, and a third semiconductor layer of the first conductivity type disposed on the second semiconductor layer.

[0096] The gate electrode is disposed in the trench along a second direction orthogonal to the first direction, in a manner opposite to the second semiconductor layer and the third semiconductor layer, and has an opposing surface at the position opposite to the third semiconductor layer, which is formed in a manner that moves away from the third semiconductor layer as it faces upward.

[0097] A first insulating portion is continuously disposed on the semiconductor portion and within the trench;

[0098] A second insulating portion is disposed on the gate electrode and is made of a different material than the first insulating portion; and

[0099] The second electrode is disposed on the semiconductor portion and connected to the second semiconductor layer and the third semiconductor layer.

[0100] (Postscript 2)

[0101] According to the semiconductor device described in Appendix 1, wherein,

[0102] The gate electrode has the opposing surfaces at both ends along the second direction.

[0103] (Note 3)

[0104] According to the semiconductor device described in Appendix 1, wherein,

[0105] The semiconductor portion comprises silicon.

[0106] The first insulating portion comprises silicon oxide.

[0107] The second insulating portion comprises silicon nitride.

[0108] (Postscript 4)

[0109] A method for manufacturing a semiconductor device, comprising:

[0110] The process of forming a silicon nitride film on a structure, the structure comprising: a semiconductor portion having a trench extending along a first direction and containing silicon; a gate electrode disposed in the trench and containing silicon; and an insulating portion disposed between the semiconductor portion and the gate electrode, having a recess formed on the gate electrode.

[0111] The process of forming a silicon oxide film on the silicon nitride film;

[0112] The process of removing the silicon oxide film in areas other than the area directly above the recess by performing a planarization process;

[0113] The process of etching the silicon nitride film using the silicon oxide film above the recessed portion as a mask; and

[0114] The process of performing oxidation treatment on the gate electrode.

[0115] (Note 5)

[0116] According to the method for manufacturing a semiconductor device as described in Appendix 4, wherein,

[0117] The process of etching the silicon nitride film is followed by a process of etching the silicon oxide film.

[0118] (Note 6)

[0119] According to the method of manufacturing the semiconductor device described in Appendix 4 or 5, wherein,

[0120] The semiconductor portion is of the first conductivity type.

[0121] The method for manufacturing the semiconductor device further comprises, after the step of oxidizing the gate electrode:

[0122] The process of implanting impurities into the semiconductor portion to make the upper part of the semiconductor portion a second semiconductor layer of a second conductivity type;

[0123] The process of implanting impurities into the semiconductor portion, so that the upper part of the second semiconductor layer and the portion opposite to the oxidized portion in the gate electrode become the third semiconductor layer of the first conductivity type;

[0124] The process of forming a silicon oxide film on the third semiconductor layer; and

[0125] The process of exposing the silicon nitride film by performing a planarization process.

[0126] (Note 7)

[0127] According to the method for manufacturing a semiconductor device as described in Appendix 6, wherein,

[0128] Following the exposure process, the following is also included:

[0129] The process of forming a resist pattern with openings between the plurality of said trenches; and

[0130] The process of etching the silicon oxide film using the resist pattern as a mask.

[0131] (Postscript 8)

[0132] According to the method for manufacturing a semiconductor device as described in Appendix 7, wherein,

[0133] The gate electrode has a first connection portion that connects to a gate wiring disposed on the upper surface of the semiconductor device.

[0134] In the process of forming the resist pattern, the resist pattern does not cover the first connecting portion.

[0135] After the process of forming the resist pattern, there is also a process of removing the silicon nitride film disposed on the first connecting portion.

[0136] (Note 9)

[0137] According to the method for manufacturing a semiconductor device as described in Appendix 8, wherein,

[0138] A field plate electrode is disposed below the gate electrode within the trench.

[0139] The field plate electrode has a second connection portion that connects to the source electrode disposed on the upper surface of the semiconductor device.

[0140] In the process of forming the resist pattern, the resist pattern does not cover the second connecting portion.

[0141] In the process of removing the silicon nitride film, the silicon nitride film disposed on the second connection portion is also removed.

[0142] After the step of removing the silicon nitride film, there is also a step of removing the silicon oxide film disposed on the second connecting portion.

[0143] (Postscript 10)

[0144] The method for manufacturing a semiconductor device according to any one of Appendices 4 to 9 further comprises:

[0145] The process of forming a first electrode on the lower surface of the semiconductor portion; and

[0146] The process of setting a second electrode on the upper surface of the semiconductor part.

Claims

1. A semiconductor device comprising: First electrode; A semiconductor portion is disposed on the first electrode and has a trench extending along a first direction. The semiconductor portion includes: a first semiconductor layer of a first conductivity type connected to the first electrode, a second semiconductor layer of a second conductivity type disposed on the first semiconductor layer, and a third semiconductor layer of the first conductivity type disposed on the second semiconductor layer. The gate electrode is disposed in the trench along a second direction orthogonal to the first direction, in a manner opposite to the second semiconductor layer and the third semiconductor layer, and has an opposing surface at the position opposite to the third semiconductor layer, which is formed in a manner that moves away from the third semiconductor layer as it faces upward. A first insulating portion is continuously disposed on the semiconductor portion and within the trench; The second insulating portion is disposed on the gate electrode and is made of a different material than the first insulating portion. as well as The second electrode is disposed on the semiconductor portion and connected to the second semiconductor layer and the third semiconductor layer.

2. The semiconductor device according to claim 1, wherein, The gate electrode has the opposing surfaces at both ends along the second direction.

3. The semiconductor device according to claim 1, wherein, The semiconductor portion comprises silicon. The first insulating portion comprises silicon oxide. The second insulating portion comprises silicon nitride.

4. The semiconductor device according to claim 1, wherein, The distance in the second direction between the gate electrode and the third semiconductor layer is longer than the distance in the second direction between the gate electrode and the second semiconductor layer.

5. The semiconductor device according to claim 1, wherein, The length of the second insulating portion in the second direction is shorter than the length of the gate electrode in the second direction.

6. The semiconductor device according to claim 1, wherein, A portion of the second insulating portion is aligned with a portion of the third semiconductor layer in the second direction.

7. The semiconductor device according to claim 1, wherein, The distance in the second direction between the second insulating portion and the third semiconductor layer is longer than the distance in the second direction between the opposing surface and the third semiconductor layer.

8. The semiconductor device according to claim 1, wherein, The length of the opposing surface in the third direction orthogonal to the first direction and the second direction is shorter than the length of the third semiconductor layer in the third direction.

9. The semiconductor device according to claim 1, wherein, It also includes a field plate electrode disposed below the gate electrode. The first insulating portion is provided between the field plate electrode and the semiconductor portion.

10. A method for manufacturing a semiconductor device, comprising the following steps: The process of forming a silicon nitride film on a structure, the structure comprising: The semiconductor section has a trench extending along a first direction and contains silicon; A gate electrode, disposed within the trench, comprises silicon; An insulating portion is disposed between the semiconductor portion and the gate electrode, and a recess is formed on the gate electrode; The process of forming a silicon oxide film on the silicon nitride film; The process of removing the silicon oxide film in areas other than the area directly above the recess by performing a planarization process; The process of etching the silicon nitride film using the silicon oxide film on the recessed portion as a mask; as well as The process of performing oxidation treatment on the gate electrode.

11. The method of manufacturing a semiconductor device according to claim 10, wherein, After the oxidation treatment, the length of the upper part of the gate electrode in the second direction orthogonal to the first direction is shorter than the length of the lower part of the gate electrode in the second direction.

12. The method of manufacturing a semiconductor device according to claim 10, wherein, After the etching process of the silicon nitride film, the length of the silicon oxide film in the second direction orthogonal to the first direction is longer than the length of the silicon nitride film in the second direction.

13. The method of manufacturing a semiconductor device according to claim 10, wherein, The process of etching the silicon nitride film is followed by a process of etching the silicon oxide film.

14. The method of manufacturing a semiconductor device according to claim 13, wherein, After the etching process of the silicon oxide film, the length of the silicon oxide film in the second direction orthogonal to the first direction is shorter than the length of the silicon nitride film in the second direction.

15. The method of manufacturing a semiconductor device according to claim 14, wherein, After the etching process of the silicon oxide film, the length of the silicon oxide film in the third direction orthogonal to the first direction and the second direction is less than the length of the silicon nitride film in the third direction.

16. The method of manufacturing a semiconductor device according to claim 10, wherein, The semiconductor portion is of the first conductivity type. The method for manufacturing the semiconductor device further includes the following steps after the step of oxidizing the gate electrode: The process of implanting impurities into the semiconductor portion to make the upper part of the semiconductor portion a second semiconductor layer of a second conductivity type; The process of implanting impurities into the semiconductor portion, so that the upper part of the second semiconductor layer and the portion opposite to the oxidized portion in the gate electrode become the third semiconductor layer of the first conductivity type; The process of forming a silicon oxide film on the third semiconductor layer; as well as The process of exposing the silicon nitride film by performing a planarization process.

17. The method of manufacturing a semiconductor device according to claim 16, wherein: Following the exposure process, the following process is also performed: The process of forming a resist pattern with openings between the plurality of said trenches; and The process of etching the silicon oxide film using the resist pattern as a mask.

18. The method of manufacturing a semiconductor device according to claim 17, wherein, The gate electrode has a first connection portion that connects to a gate wiring disposed on the upper surface of the semiconductor device. In the process of forming the resist pattern, the resist pattern does not cover the first connecting portion. After the process of forming the resist pattern, there is also a process of removing the silicon nitride film disposed on the first connecting portion.

19. The method of manufacturing a semiconductor device according to claim 18, wherein, A field plate electrode is disposed below the gate electrode within the trench. The field plate electrode has a second connection portion that connects to the source electrode disposed on the upper surface of the semiconductor device. In the process of forming the resist pattern, the resist pattern does not cover the second connecting portion. In the process of removing the silicon nitride film, the silicon nitride film disposed on the second connection portion is also removed. After the step of removing the silicon nitride film, there is also a step of removing the silicon oxide film disposed on the second connecting portion.

20. The method of manufacturing a semiconductor device according to claim 10, wherein, It also includes the following processes: The process of forming a first electrode on the lower surface of the semiconductor portion; and The process of setting a second electrode on the upper surface of the semiconductor part.

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