Semiconductor device and manufacturing method thereof, integrated circuit and electronic equipment

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, an integrated circuit and electronic equipment. The semiconductor device includes a vertical transistor including a first pole, a channel, a second pole, a gate, a first isolation structure and a second isolation structure. The channel comprises a first end face and a second end face which are oppositely arranged, the first pole is arranged on the first end face, the second pole is arranged on the second end face, and the first pole, the channel and the second pole are stacked. The grid electrode is arranged on the peripheral side face of the channel, the first isolation structure is arranged between the grid electrode and the first electrode, the second isolation structure is arranged between the grid electrode and the second electrode, and the second electrode and the first electrode are symmetrical along the plane where the center position of the channel is located, so that the conductivity of the semiconductor device is symmetrical. The electrical symmetry of the device is improved; and the conductivity of the device is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device, a method for manufacturing a semiconductor device, an integrated circuit, and an electronic device. Background Technology

[0002] With the development of advanced processes, the miniaturization of horizontally mounted transistors, such as FinFETs and Gate-all-around Field-Effect Transistors (GAAFETs), faces significant challenges. Due to physical limitations, the contacted gate pitch (CGP) of horizontally mounted transistors cannot be scaled below 40nm. Vertically mounted transistors (VFETs), with their source, gate, and drain stacked in space, can break the 40nm gate pitch limitation, extending Moore's Law. Furthermore, the gate of a VFET can be made longer, and the second isolation structures between the source and gate, and between the drain and gate, can be made thicker, better suppressing short-channel effects, reducing parasitic resistance and capacitance, and resulting in better performance.

[0003] In the prior art, the layer structure of vertical transistors is achieved by etching layer by layer, which is not conducive to improving the conductivity of vertical transistors. Summary of the Invention

[0004] This application provides a semiconductor device, a method for manufacturing a semiconductor device, an integrated circuit, and an electronic device, aimed at improving the conductivity of vertical transistors.

[0005] In a first aspect, embodiments of this application provide a semiconductor device including a vertical transistor. The vertical transistor includes a first electrode, a channel, a second electrode, a gate, a first isolation structure, and a second isolation structure. The channel includes a first end face and a second end face disposed opposite to each other. The first electrode is disposed on the first end face, and the second electrode is disposed on the second end face. The first electrode, the channel, and the second electrode are stacked. The gate is disposed on the peripheral side of the channel. The first isolation structure is disposed between the gate and the first electrode, and the second isolation structure is disposed between the gate and the second electrode. The second electrode and the first electrode are symmetrical along a plane containing the center of the channel.

[0006] In existing processes, the layer structure of semiconductor devices is etched and formed layer by layer from bottom to top. Specifically, the source is formed first, then the layer structure between the source and drain is formed, and then the drain is formed; or, the drain is formed first, then the layer structure between the source and drain is formed, and then the source is formed. This introduces errors in the symmetry between the source and drain, leading to electrical asymmetry in the semiconductor device. The semiconductor device provided in this application has its second electrode symmetrical to its first electrode along the plane containing the center of the channel, resulting in symmetrical conductivity and improved electrical symmetry and conductivity.

[0007] In one embodiment, the first electrode is symmetrical along the plane containing its own central axis, which helps to reduce errors in device performance.

[0008] In one embodiment, the second electrode is symmetrical along the plane containing its own central axis, which helps to reduce errors in device performance.

[0009] In one embodiment, the semiconductor device further includes a first insulating structure and a second insulating structure. The first insulating structure is disposed on the surface of the first isolation structure opposite to the gate, covering the first electrode. The second insulating structure is disposed on the surface of the second isolation structure opposite to the gate, covering the second electrode. The first insulating structure insulates adjacent first electrodes, and the second insulating structure insulates adjacent second electrodes. Furthermore, the semiconductor device eliminates the need for shallow trench isolation, P-well layers, and N-well layers, simplifying the device structure and saving on manufacturing processes. Simultaneously, the semiconductor device is substrate-free, avoiding substrate effects and improving its reliability.

[0010] In one embodiment, the semiconductor device further includes an interlayer dielectric structure disposed on the peripheral side surface of the gate and the peripheral side surface of the first isolation structure, and the interlayer dielectric structure is connected to the first insulating structure and the second insulating structure, respectively. The interlayer dielectric structure is used to insulate adjacent gates.

[0011] In one embodiment, the semiconductor device further includes a first conductive network structure and a second conductive network structure. The first conductive network structure is disposed on the surface of the first insulating structure opposite to the first isolation structure, and the second conductive network structure is disposed on the surface of the second insulating structure opposite to the second isolation structure. The first conductive network structure is electrically connected to both the first electrode and the second electrode, and the second conductive network structure is electrically connected to the gate; or, the first conductive network structure is electrically connected to the gate, and the second conductive network structure is electrically connected to both the first electrode and the second electrode. The first conductive network structure supplies power to the first electrode and the second electrode, and the second conductive network structure provides a signal to the gate; or, the first conductive network structure provides a signal to the gate, and the second conductive network structure supplies power to both the first electrode and the second electrode. This separates the signal-providing network structure from the power-supplying network structure, reducing the voltage drop of the power supply network structure and improving its power transmission efficiency, while also preventing interference with the signal transmitted by the signal-providing network structure.

[0012] In one embodiment, the first insulating structure has a first receiving hole penetrating through the first insulating structure, exposing the first electrode. A first contact is disposed within the first receiving hole, and the first contact is connected to the first electrode. The first electrode is electrically connected to the first conductive network structure through the first contact. Alternatively, the second insulating structure has a second receiving hole penetrating through the second insulating structure, exposing the second electrode. A second contact is disposed within the second receiving hole, and the second contact is connected to the second electrode. The second electrode is electrically connected to the second conductive network structure through the second contact. Direct electrical connection between the first electrode and the first conductive network structure via the first contact, or direct electrical connection between the second electrode and the second conductive network structure via the second contact, maximizes the use of the winding resources of the conductive network and improves the device integration.

[0013] Secondly, embodiments of this application provide a method for fabricating a semiconductor device. The method includes: sequentially forming an etch stop structure, a channel, and a second isolation structure on a surface of a substrate. The etch stop structure is located on one surface of the substrate, and the channel and the second isolation structure are both located on the surface of the etch stop structure facing away from the substrate. The second isolation structure connects to at least a portion of the peripheral side surface of the channel. The channel includes a first end face and a second end face disposed opposite to each other. The first end face extends out of the second isolation structure, and the second end face is connected to the etch stop structure. A gate is formed on the surface of the second isolation structure facing away from the etch stop structure, and the gate connects to at least a portion of the peripheral side surface of the channel. A first isolation structure is formed on the surface of the gate facing away from the second isolation structure, and the first end face of the channel exposes the first isolation structure. A first electrode is formed on the first end face of the channel. The substrate and the etch stop structure are removed, exposing the second isolation structure on the second end face of the channel. A second electrode is formed on the second end face of the channel. The second electrode is symmetrical to the first electrode along the plane where the center of the channel is located. The first electrode, the channel, the second electrode, the gate, the first isolation structure, and the second isolation structure constitute a vertical transistor.

[0014] In existing processes, the layer structure of semiconductor devices is etched and formed layer by layer from bottom to top. This involves forming the source electrode first, then the layer structure between the source and drain, and finally the drain electrode; or vice versa. This introduces errors in the symmetry between the source and drain, leading to electrical asymmetry in the semiconductor device. The semiconductor device fabrication method provided in this application exposes the first and second end faces of the channel, and forms the first electrode on the first end face and the second electrode on the second end face sequentially. This avoids forming the first and second electrodes layer by layer, meaning the layer structure between the first and second electrodes is not formed between the formation of the first and second electrodes. Therefore, the second electrode and the first electrode are symmetrical along the plane containing the center of the channel, resulting in symmetrical conductivity of the semiconductor device, improving both electrical symmetry and conductivity.

[0015] In one embodiment, a barrier structure is formed on the first end face of the channel, and forming a gate on the surface of the second isolation structure opposite to the etch stop structure includes: forming an oxide structure on the peripheral side surface of the channel. An alternative gate structure is formed on the surface of the second isolation structure opposite to the etch stop structure using the barrier structure as a mask, and the alternative gate structure connects to the peripheral side surface of the oxide structure. The surface of the alternative gate structure opposite to the second isolation structure is etched flat using a self-limiting reaction mechanism etching process. By forming the alternative gate structure using the barrier structure as a mask, the position of the alternative gate structure is not limited by photolithography, eliminating errors during photolithography definition and achieving a self-aligned alternative gate structure. Furthermore, the etching back process can maximize the elimination of etching load effects, which is beneficial for flattening the surface of the alternative gate structure opposite to the second isolation structure.

[0016] In one embodiment, forming a gate on the surface of the second isolation structure opposite to the etch stop structure further includes: forming a sidewall structure on the surface of the alternative gate structure opposite to the second isolation structure, the sidewall structure connecting the peripheral side surface of the channel and the peripheral side surface of the barrier structure. Removing the alternative gate structure and the oxide structure exposes the peripheral side surface of the channel. Forming a gate structure on the surface of the second isolation structure opposite to the etch stop structure, the gate structure connecting the exposed peripheral side surface of the channel and the peripheral side surface of the sidewall structure. Removing the gate structure on the periphery of the sidewall structure using the barrier structure and the sidewall structure as masks to form a gate transition structure, the gate transition structure connecting the peripheral side surface of the channel. Forming a shielding structure on a portion of the surface of the gate transition structure opposite to the second isolation structure, the shielding structure connecting to one side of the sidewall structure. Removing the portion of the gate transition structure that is offset from the sidewall structure and the shielding structure using the barrier structure, the sidewall structure, and the shielding structure as masks to form the gate. The gate is formed using the barrier structure, the sidewall structure, and the shielding structure as masks, eliminating the need for photolithography to limit the gate formation position, thus eliminating errors in photolithography definition, achieving a self-aligned gate formation, and improving device reliability. The shielding structure is used to occupy the position where the third contact is formed.

[0017] In one embodiment, forming a first isolation structure on the surface of the gate opposite to the second isolation structure includes: removing the shielding structure. An interlayer dielectric transition structure is formed on the surface of the second isolation structure opposite to the etch stop structure, the interlayer dielectric transition structure covering the gate, the shielding structure, and the blocking structure. The portion of the interlayer dielectric transition structure extending beyond the first end face is removed to form an interlayer dielectric structure; the portion of the sidewall structure extending beyond the first end face is removed to form the first isolation structure; and the blocking structure is removed, exposing the first end face. The interlayer dielectric transition structure covers the gate to prevent exposure and damage. Furthermore, since the interlayer dielectric transition structure covers both the shielding structure and the blocking structure, damage to the interlayer dielectric structure and the blocking structure during the polishing process can be effectively avoided.

[0018] In one embodiment, before removing the substrate and the etch stop structure, the method for fabricating the semiconductor device further includes: forming a first insulating structure on the peripheral side of the first electrode and on the surface of the first electrode opposite to the channel. A first conductive network structure is formed on the surface of the first insulating structure opposite to the first isolation structure. The first conductive network structure is electrically connected to the first electrode and the second electrode, or electrically connected to the gate. Forming the first electrode first and then the first conductive network structure avoids the high-temperature environment required for forming the first electrode from affecting the metal within the first conductive network structure, thus improving the reliability of the first conductive network structure.

[0019] In one embodiment, the method for fabricating the semiconductor device further includes: forming a second insulating structure on the surface of the second isolation structure opposite to the gate, the second insulating structure covering the second electrode; and forming a second conductive network structure on the surface of the second insulating structure opposite to the second isolation structure, the second conductive network structure being electrically connected to the first electrode and the second electrode, or the second conductive network structure being electrically connected to the gate. Forming the second electrode first and then the second conductive network structure avoids the high-temperature environment required for forming the second electrode from affecting the metal within the second conductive network structure, thus improving the reliability of the second conductive network structure.

[0020] In one embodiment, the first electrode is formed by selective epitaxy, and the second electrode is formed by selective epitaxy. Forming the first and second electrodes by selective epitaxy restricts the locations where the first and second electrodes are formed, thereby improving the symmetry between the first and second electrodes.

[0021] In one embodiment, the material of the first electrode comprises boron-doped germanium silicon; or, the material of the first electrode comprises arsenic-doped silicon or phosphorus-doped silicon.

[0022] In one embodiment, the material of the second electrode comprises boron-doped germanium silicon; or, the material of the second electrode comprises arsenic-doped silicon or phosphorus-doped silicon.

[0023] Thirdly, embodiments of this application also provide an integrated circuit, the integrated circuit including an electronic device and the aforementioned semiconductor device, the semiconductor device being electrically connected to the electronic device. The semiconductor device includes a vertical transistor, the vertical transistor including a first electrode, a channel, and a second electrode, the channel including a first end face and a second end face disposed opposite to each other. The first electrode is disposed on the first end face, the second electrode is disposed on the second end face, and the first electrode, the channel, and the second electrode are stacked. The gate is disposed on the peripheral side of the channel. The second electrode and the first electrode are symmetrical along the plane containing the center of the channel, making the conductivity of the semiconductor device symmetrical as well, improving the electrical symmetry of the device and improving the conductivity performance of the device.

[0024] Fourthly, embodiments of this application also provide an electronic device, the electronic device including a circuit board and the aforementioned integrated circuit, the integrated circuit being electrically connected to the circuit board. The integrated circuit includes an electronic device and a semiconductor device, the semiconductor device being electrically connected to the electronic device. The semiconductor device includes a vertical transistor, the vertical transistor including a first electrode, a channel, and a second electrode, the channel including a first end face and a second end face disposed opposite to each other. The first electrode is disposed on the first end face, the second electrode is disposed on the second end face, and the first electrode, the channel, and the second electrode are stacked. The gate is disposed on the peripheral side of the channel. The second electrode and the first electrode are symmetrical along the plane where the center position of the channel is located, making the conductivity of the semiconductor device symmetrical as well, improving the electrical symmetry of the device and improving the conductivity performance of the device. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application or the background art, the accompanying drawings used in the embodiments of this application or the background art will be described below.

[0026] Figure 1 This is a schematic diagram of the structure of the first electronic device disclosed in the embodiments of this application;

[0027] Figure 2 This is a schematic diagram of the structure of the second electronic device disclosed in the embodiments of this application;

[0028] Figure 3This is a schematic diagram of a specific layer structure of the semiconductor device disclosed in an embodiment of this application;

[0029] Figure 4 This is a bottom view of the semiconductor device disclosed in the embodiments of this application;

[0030] Figure 5 for Figure 4 A schematic cross-sectional view of the semiconductor device shown along the VV direction;

[0031] Figure 6 for Figure 5 An enlarged schematic diagram of structure VI in the semiconductor device shown;

[0032] Figure 7 for Figure 4 A schematic cross-sectional view of the semiconductor device shown along the VII-VII direction;

[0033] Figure 8 This is a schematic flowchart of the method for fabricating a semiconductor device disclosed in an embodiment of this application;

[0034] Figure 9 This is a schematic flowchart of step S100 of the semiconductor device fabrication method disclosed in the embodiments of this application;

[0035] Figure 10 for Figure 9 The schematic diagram of the layer structure formed corresponding to step S110 is shown below;

[0036] Figure 11 for Figure 9 The schematic diagram of the layer structure formed corresponding to step S120 is shown below;

[0037] Figure 12 for Figure 9 A top view of the structure formed corresponding to step S130 shown;

[0038] Figure 13 for Figure 12 The diagram shows a cross-sectional view of the structure along the S1-S1 direction;

[0039] Figure 14 for Figure 12 The diagram shows a cross-sectional view of the structure along the S2-S2 direction;

[0040] Figure 15 for Figure 9 A top view of the structure formed corresponding to step S140 shown;

[0041] Figure 16 for Figure 15 The diagram shows a cross-sectional view of the structure along the S1-S1 direction;

[0042] Figure 17 for Figure 15 The diagram shows a cross-sectional view of the structure along the S2-S2 direction;

[0043] Figure 18 This is a schematic flowchart of step S100 of the semiconductor device fabrication method disclosed in the embodiments of this application;

[0044] Figure 19 for Figure 18 A top view of the structure formed corresponding to step S220 is shown below;

[0045] Figure 20 for Figure 19 The diagram shows a cross-sectional view of the structure along the S1-S1 direction;

[0046] Figure 21 for Figure 19 The diagram shows a cross-sectional view of the structure along the S2-S2 direction;

[0047] Figure 22 for Figure 18 A top view of the structure formed corresponding to step S240 shown;

[0048] Figure 23 for Figure 22 The diagram shows a cross-sectional view of the structure along the S1-S1 direction;

[0049] Figure 24 for Figure 22 The diagram shows a cross-sectional view of the structure along the S2-S2 direction;

[0050] Figure 25 for Figure 18 A top view of the structure formed corresponding to step S250 shown;

[0051] Figure 26 for Figure 25 The diagram shows a cross-sectional view of the structure along the S1-S1 direction;

[0052] Figure 27 for Figure 25 The diagram shows a cross-sectional view of the structure along the S2-S2 direction;

[0053] Figure 28 for Figure 18 A top view of the structure formed corresponding to step S260 shown;

[0054] Figure 29 for Figure 28 The diagram shows a cross-sectional view of the structure along the S1-S1 direction;

[0055] Figure 30 for Figure 28The diagram shows a cross-sectional view of the structure along the S2-S2 direction;

[0056] Figure 31 for Figure 18 A top view of the structure formed corresponding to step S270 shown;

[0057] Figure 32 for Figure 31 The diagram shows a cross-sectional view of the structure along the S1-S1 direction;

[0058] Figure 33 for Figure 31 The diagram shows a cross-sectional view of the structure along the S2-S2 direction;

[0059] Figure 34 for Figure 18 A top view of the structure formed corresponding to step S280 shown;

[0060] Figure 35 for Figure 34 The diagram shows a cross-sectional view of the structure along the S1-S1 direction;

[0061] Figure 36 for Figure 34 The diagram shows a cross-sectional view of the structure along the S2-S2 direction;

[0062] Figure 37 for Figure 18 A top view of the structure formed corresponding to step S290 shown;

[0063] Figure 38 for Figure 37 The diagram shows a cross-sectional view of the structure along the S1-S1 direction;

[0064] Figure 39 for Figure 37 The diagram shows a cross-sectional view of the structure along the S2-S2 direction;

[0065] Figure 40 This is a schematic flowchart of step S300 of the semiconductor device fabrication method disclosed in the embodiments of this application;

[0066] Figure 41 for Figure 40 A top view of the structure formed corresponding to step S320 shown;

[0067] Figure 42 for Figure 41 The diagram shows a cross-sectional view of the structure along the S1-S1 direction;

[0068] Figure 43 for Figure 41 The diagram shows a cross-sectional view of the structure along the S2-S2 direction;

[0069] Figure 44 for Figure 40 A top view of the structure formed corresponding to step S330 shown;

[0070] Figure 45 for Figure 44 The diagram shows a cross-sectional view of the structure along the S1-S1 direction;

[0071] Figure 46 for Figure 44 The diagram shows a cross-sectional view of the structure along the S2-S2 direction;

[0072] Figure 47 for Figure 8 A top view of the structure formed corresponding to step S400 of the semiconductor device fabrication method shown;

[0073] Figure 48 for Figure 47 The diagram shows a cross-sectional view of the structure along the S1-S1 direction;

[0074] Figure 49 for Figure 47 The diagram shows a cross-sectional view of the structure along the S2-S2 direction;

[0075] Figure 50 for Figure 8 A top view of the structure formed corresponding to step S500 of the semiconductor device fabrication method shown;

[0076] Figure 51 for Figure 50 The diagram shows a cross-sectional view of the structure along the S1-S1 direction;

[0077] Figure 52 for Figure 50 The diagram shows a cross-sectional view of the structure along the S2-S2 direction;

[0078] Figure 53 for Figure 8 A top view of the structure formed corresponding to step S600 of the semiconductor device fabrication method shown;

[0079] Figure 54 for Figure 53 The diagram shows a cross-sectional view of the structure along the S1-S1 direction;

[0080] Figure 55 for Figure 53 The diagram shows a cross-sectional view of the structure along the S2-S2 direction;

[0081] Figure 56 for Figure 8A top view of the structure formed corresponding to step S700 of the semiconductor device fabrication method shown;

[0082] Figure 57 for Figure 56 The diagram shows a cross-sectional view of the structure along the S1-S1 direction;

[0083] Figure 58 for Figure 56 The diagram shows a cross-sectional view of the structure along the S2-S2 direction;

[0084] Figure 59 for Figure 8 A top view of the structure formed corresponding to step S800 of the semiconductor device fabrication method shown;

[0085] Figure 60 for Figure 59 The diagram shows a cross-sectional view of the structure along the S1-S1 direction;

[0086] Figure 61 for Figure 59 The diagram shows a cross-sectional view of the structure along the S2-S2 direction;

[0087] Figure 62 for Figure 8 A top view of the structure formed corresponding to step S900 of the semiconductor device fabrication method shown;

[0088] Figure 63 for Figure 62 The diagram shows a cross-sectional view of the structure along the S1-S1 direction;

[0089] Figure 64 for Figure 62 The diagram shows a cross-sectional view of the structure along the S2-S2 direction;

[0090] Figure 65 for Figure 8 A top view of the structure formed corresponding to step S1000 of the semiconductor device fabrication method shown;

[0091] Figure 66 for Figure 65 The diagram shows a cross-sectional view of the structure along the S1-S1 direction;

[0092] Figure 67 for Figure 65 The diagram shows a cross-sectional view of the structure along the S2-S2 direction. Detailed Implementation

[0093] This application provides an electronic device, which can be a mobile phone, laptop computer, tablet computer, smart TV, augmented reality (AR) device, virtual reality (VR) device, artificial intelligence (AI) device, smart wearable device (e.g., smartwatch, smart bracelet, smart glasses), in-vehicle device, smart home device, smart city device, terminal device, and other electronic products. This application does not impose any special limitations on the specific type of this electronic device. Please refer to... Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the structure of the first electronic device disclosed in the embodiments of this application. Figure 2 This is a schematic diagram of the structure of the second electronic device disclosed in the embodiments of this application. Figure 1 The electronic device shown is a mobile phone. Figure 2 The electronic device shown is a laptop computer. For ease of explanation, a mobile phone will be used as an example below.

[0094] The aforementioned electronic devices include components such as integrated circuits and circuit boards. Integrated circuits are electrically connected to circuit boards via pins, and integrated circuits can be electrically connected to external circuits through circuit boards to achieve signal exchange. Integrated circuits can be used to perform logical operations, process digital signals, or store data and instructions.

[0095] The aforementioned integrated circuit includes electronic devices and semiconductor devices, which are electrically connected to transmit electrical signals. The electronic devices include resistors, capacitors, and controllers, etc., which are not specifically limited in this application.

[0096] Based on this, embodiments of this application provide a semiconductor device, which may be a CoreLogic chip, Static Random Access Memory (SRAM), Memory Selector, Image Signal Processor (ISP), Digital Signal Processor (DSP), or Graphics Processing Unit (GPU), etc. Embodiments of this application do not impose any special limitations on the specific type of this semiconductor device.

[0097] In the embodiments of this application, please refer to Figure 3 , Figure 3This is a schematic diagram of a specific layer structure of the semiconductor device disclosed in an embodiment of this application. The semiconductor device 1 includes a first conductive network structure 110 and a second conductive network structure 120, which are spaced apart. A transistor is located between the first conductive network structure 110 and the second conductive network structure 120. The first conductive network structure 110 includes a first conductive line and a first insulator, and the second conductive network structure 120 includes a second conductive line and a second insulator. Figure 3 In the structure shown, the gray parts in the first conductive network structure 110 and the second conductive network structure 120 are conductive lines, and the insulator is disposed on the surface of the conductive lines.

[0098] Please see Figures 4 to 7 , Figure 4 This is a bottom view of the semiconductor device disclosed in an embodiment of this application. Figure 5 for Figure 4 The diagram shows a cross-sectional view of the semiconductor device along the VV direction. Figure 6 for Figure 5 The diagram shows an enlarged view of structure VI in the semiconductor device. Figure 7 for Figure 4 The diagram shows a cross-sectional view of the semiconductor device along the VII-VII direction. The semiconductor device 1 includes a first electrode 10, a channel 20, a second electrode 30, a gate 40, a second isolation structure 50, a first isolation structure 60, an interlayer dielectric structure 70, a first insulating structure 80 and a second insulating structure 90, a first conductive network structure 110, a second conductive network structure 120, a first contact 130, a second contact 140, a bonding structure 150 and a substrate 160, a third contact 170 and a connector 180. Figure 4 The dashed lines in the diagram represent the outline of channel 20. Channel 20 is in Figure 4The structure is not visible in the middle. A substrate 160, a bonding structure 150, a first conductive network structure 110, a first contact 130, a first electrode 10, a channel 20, a second electrode 30, a second contact 140, and a second conductive network structure 120 are sequentially stacked. The channel 20 includes a first end face 20a and a second end face 20b disposed opposite to each other. The first electrode 10 is disposed on the first end face 20a, and the second electrode 30 is disposed on the second end face 20b. A gate 40 is disposed on the peripheral side of the channel 20. A first isolation structure 60 is disposed between the gate 40 and the first electrode 10, a second isolation structure 50 is disposed between the gate 40 and the second electrode 30, and an interlayer dielectric structure 70 is disposed on the peripheral side of the gate 40. A first insulating structure 80 is disposed on the peripheral side of the first electrode 10 and the peripheral side of the first contact 130, and a second insulating structure 90 is disposed on the peripheral side of the second electrode 30 and the peripheral side of the second contact 140. A first isolation structure 60 is used to insulate the gate 40 from the first electrode 10, and a second isolation structure 50 is used to insulate the gate 40 from the second electrode 30. A first insulation structure 80 is used to insulate between two adjacent first electrodes 10 and between two adjacent first contacts 130, and a second insulation structure 90 is used to insulate between two adjacent second electrodes 30 and between two adjacent second contacts 140. The gate 40 is used to control the magnitude of the current passing through the first electrode 10 and the second electrode 30.

[0099] It should be noted that the first electrode 10 can be the source and the second electrode 30 can be the drain; or, the first electrode 10 can be the drain and the second electrode 30 can be the source. The embodiments of this application do not limit the specific types of the first electrode 10 and the second electrode 30.

[0100] For ease of description, define Figure 4 The width direction of the semiconductor device 1 shown is the X-axis direction, the length direction is the Y-axis direction, and the height direction is the Z-axis direction. The X-axis, Y-axis, and Z-axis directions are all perpendicular to each other. The directional terms such as "upper" and "lower" used in the description of the embodiments in this application are based on the orientation shown in the accompanying drawings. "Up" or "top" refers to the direction towards the positive Z-axis, and "lower" or "bottom" refers to the direction towards the negative Z-axis. These terms do not constitute a limitation on the actual application scenario of the semiconductor device 1.

[0101] Specifically, please refer to Figures 5 to 7 The first electrode 10, the channel 20, and the second electrode 30 are stacked sequentially along the Z-axis. That is, the channel 20 is disposed on the surface of the first electrode 10 facing the Z-axis, and the second electrode 30 is disposed on the surface of the channel 20 facing away from the first electrode 10.

[0102] Understandably, the second electrode 30 and the first electrode 10 are mirror images of each other along the plane containing the center of the channel 20, and the plane containing the center of the channel 20 is perpendicular to the height direction (extension direction) of the channel 20. The center of the channel 20 is its geometric center point, and the plane containing the center of the channel 20 is perpendicular to the Z-axis. That is, please refer to... Figure 6 and Figure 7 Assume there exists a plane A perpendicular to the Z-axis, where the distance between the first electrode 10 and plane A is equal to the distance between the second electrode 30 and plane A. This plane A is the plane containing the center of the channel 20. The second electrode 30 and the first electrode 10 are mirror-symmetric along this plane A. This mirror symmetry between the second electrode 30 and the first electrode 10 ensures that the conductivity of the semiconductor device 1 is also symmetrical, thus improving the electrical symmetry of the device.

[0103] In this application, please refer to Figure 6 and Figure 7 The plane containing the central axis of the first electrode 10 includes a first plane S1 and a second plane S2, which are perpendicular to each other. The first plane S1 is perpendicular to the X-axis, and the second plane S2 is perpendicular to the Y-axis. The geometric center point of the first electrode 10 is located on both the first plane S1 and the second plane S2. The first electrode 10 is symmetrical along the plane containing its own central axis, that is, it is symmetrical along the first plane S1 and along the second plane S2, which improves the accuracy of the first electrode 10 and reduces the error in device performance.

[0104] In this application, please refer to Figure 6 and Figure 7 The plane containing the central axis of the second electrode 30 includes a third plane S3 and a fourth plane S4, which are perpendicular to each other. The third plane S3 is perpendicular to the X-axis, and the fourth plane S4 is perpendicular to the Y-axis. The geometric center of the second electrode 30 lies on both the third plane S3 and the fourth plane S4. The second electrode 30 is symmetrical along its central axis, that is, symmetrical along both the third plane S3 and the fourth plane S4, which improves the accuracy of the second electrode 30 and reduces errors in device performance.

[0105] It should be noted that both the first electrode 10 and the second electrode 30 are formed by a self-alignment process, which can reduce the error of the first electrode 10 and the error of the second electrode 30.

[0106] Please see Figure 5 and Figure 7A gate 40 is disposed on the peripheral side surface of the channel 20, wherein the gate 40 may surround or partially surround the peripheral side surface of the channel 20. A first isolation structure 60 is disposed on the surface of the gate 40 facing the first electrode 10, and the first isolation structure 60 connects the peripheral side surface of the gate 40 and a portion of the peripheral side surface of the first electrode 10.

[0107] Please see Figure 6 and Figure 7 The first isolation structure 60 includes a first side surface 60a, a second side surface 60b, a third side surface 60c, and a fourth side surface 60d, which together form the peripheral surfaces of the first isolation structure 60. The first side surface 60a and the second side surface 60b are arranged opposite to each other along the X-axis, and the third side surface 60c and the fourth side surface 60d are arranged opposite to each other along the Y-axis. The first side surface 60a is connected to both the third side surface 60c and the fourth side surface 60d, and the second side surface 60b is connected to both the third side surface 60c and the fourth side surface 60d.

[0108] Please see Figure 6 and Figure 7 The gate 40 includes a first surface 40a, a second surface 40b, a third surface 40c, and a fourth surface 40d, which together form the peripheral surface of the gate 40. The first surface 40a and the second surface 40b are arranged opposite each other along the X-axis, and the third surface 40c and the fourth surface 40d are arranged opposite each other along the Y-axis. The first surface 40a is connected to both the third surface 40c and the fourth surface 40d, and the second surface 40b is also connected to both the third surface 40c and the fourth surface 40d. The first surface 40a is connected to a first side surface 60a, and the first surface 40a and the first side surface 60a are aligned in the Z-axis direction. The second surface 40b is connected to a second side surface 60b, and the second surface 40b and the second side surface 60b are aligned in the Z-axis direction. The third surface 40c is connected to a third side surface 60c, and the third surface 40c and the third side surface 60c are aligned in the Z-axis direction. The fourth face 40d is not aligned with the fourth side face 60d. The length of the side where the fourth face 40d of the gate 40 is located is longer than the length of the side where the fourth side face 60d of the first isolation structure 60 is located. That is, the fourth face 40d of the gate 40 extends out of the fourth side face 60d of the first isolation structure 60.

[0109] Please see Figure 5 and Figure 7An interlayer dielectric structure 70 is disposed on the peripheral side surface of the gate 40 and the peripheral side surface of the first isolation structure 60. Specifically, the interlayer dielectric structure 70 connects the first side surface 60a, the second side surface 60b, the third side surface 60c, and the fourth side surface 60d of the first isolation structure 60, and connects the first side surface 40a, the second side surface 40b, and the third side surface 40c of the gate 40. The surface of the interlayer dielectric structure 70 facing away from the second electrode 30 is aligned with the surface of the first isolation structure 60 facing away from the gate 40.

[0110] It should be noted that if the fourth surface 40d of the gate 40 is connected to other layer structures, the interlayer dielectric structure 70 is not connected to the fourth surface 40d of the gate 40; if the fourth surface 40d of the gate 40 is not connected to other layer structures, the interlayer dielectric structure 70 is connected to the fourth surface 40d of the gate 40.

[0111] Please see Figure 5 and Figure 7 The first insulating structure 80 is disposed on the surface of the interlayer dielectric structure 70 facing away from the second electrode 30 and the surface of the first isolation structure 60 facing away from the gate 40. The first insulating structure 80 connects to the peripheral side surface of the first electrode 10 and covers the surface of the first electrode 10 facing away from the channel 20. The surface of the first electrode 10 connected to the channel 20 may extend beyond the surface of the first insulating structure 80 facing the first isolation structure 60, or the surface of the first electrode 10 connected to the channel 20 may be aligned with the surface of the first insulating structure 80 facing the first isolation structure 60. Figures 5 to 7 In the first electrode 10, the surface of the first electrode 10 connected to the channel 20 extends out of the first insulating structure 80 toward the surface of the first isolation structure 60. The part of the first electrode 10 extending out of the first insulating structure 80 is the extension region, which can improve the electrical performance of the device.

[0112] Please see Figure 6 and Figure 7 The first insulating structure 80 has a first receiving hole 80a extending through the first insulating structure 80 along the Z-axis direction. The first receiving hole 80a is located in the direction opposite to the channel 20 of the first electrode 10, and the first receiving hole 80a exposes the surface of the first electrode 10 opposite to the channel 20. The first contact 130 is disposed in the first receiving hole 80a and is connected to the surface of the first electrode 10 opposite to the channel 20, so that the first contact 130 is electrically connected to the first electrode 10.

[0113] Please see Figure 7 The first insulating structure 80 also has a first through hole 80b and a second through hole 80c that penetrate the first insulating structure 80 along the Z-axis direction. The first through hole 80b and the second through hole 80c are respectively arranged on opposite sides of the first pole 10 along the Y-axis direction. The first through hole 80b is spaced apart from the first pole 10, and the second through hole 80c is spaced apart from the first pole 10.

[0114] The interlayer dielectric structure 70 has a third through-hole 70a and a fourth through-hole 70b extending through the interlayer dielectric structure 70 along the Z-axis. The third through-hole 70a and the fourth through-hole 70b are respectively disposed on opposite sides of the first isolation structure 60 along the Y-axis. The third through-hole 70a is spaced apart from the first isolation structure 60, and the fourth through-hole 70b is spaced apart from the first isolation structure 60. The third through-hole 70a is located in the direction opposite to the third side surface 60d, and the portion of the gate 40 facing the first insulating structure 80 exposes the third through-hole 70a. The fourth through-hole 70b is disposed in the direction opposite to the third side surface 60d.

[0115] A first through-hole 80b and a third through-hole 70a are stacked in the Z-axis direction and are connected. A second through-hole 80c and a fourth through-hole 70b are stacked in the Z-axis direction and are connected. A third contact 170 is disposed within the first through-hole 80b and the third through-hole 70a and is connected to the gate 40, thereby electrically connecting the gate 40 and the third contact 170.

[0116] Please see Figure 7 The connector 180 includes a first connector 181, a second connector 182, and a third connector 183 connected in sequence. The first connector 181 is disposed within the second through hole 80c and the fourth through hole 70b.

[0117] The first conductive network structure 110 is disposed on the surface of the first insulating structure 80 facing away from the first isolation structure 60, and the first conductive network structure 110 is connected to the third contact 170, the first contact 130, and the first connecting sub-component 181, respectively, so that the first conductive network structure 110 is electrically connected to the third contact 170, the first contact 130, and the first connecting sub-component 181, respectively. The gate 40 is electrically connected to the first conductive network structure 110 through the third contact 170, and the first electrode 10 is electrically connected to the first conductive network structure 110 through the first contact 130.

[0118] Please see Figure 5 and Figure 7 A bonding structure 150 is disposed on the surface of the first conductive network structure 110 opposite to the first insulating structure 80, and a substrate 160 is disposed on the surface of the bonding structure 150 opposite to the first conductive network structure 110. The bonding structure 150 is used to bond the first conductive network structure 110 to the substrate 160.

[0119] Please see Figure 5 and Figure 7The second isolation structure 50 is disposed on the surface of the interlayer dielectric structure 70 opposite to the first insulating structure 80 and the surface of the gate 40 opposite to the first isolation structure 60, and the second isolation structure 50 connects the peripheral side surface of the channel 20 and the peripheral side surface of the second electrode 30. The second isolation structure 50 includes a first isolation substructure 51 and a second isolation substructure 52. The first isolation substructure 51 is disposed on the surface of the gate 40 opposite to the first isolation structure 60 and is connected to the peripheral side surface of the channel 20. The second isolation substructure 52 is disposed on the surface of the interlayer dielectric structure 70 opposite to the first insulating structure 80 and the surface of the first isolation substructure 51 opposite to the gate 40, and is connected to the peripheral side surface of the channel 20.

[0120] Please see Figure 6 and Figure 7 The first isolation substructure 51 includes a first connecting surface 51a, a second connecting surface 51b, and a third connecting surface 51c, which together form part of the peripheral surface of the first isolation substructure 51. The first connecting surface 51a and the second connecting surface 51b are arranged opposite to each other along the X-axis direction, and the third connecting surface 51c is connected to both the first connecting surface 51a and the second connecting surface 51b. The first connecting surface 51a is connected to and aligned with the first surface 40a. The second connecting surface 51b is connected to and aligned with the second surface 40b. The third connecting surface 51c is connected to and aligned with the third surface 40c.

[0121] Please see Figure 5 and Figure 7 The second insulating structure 90 is disposed on the surface of the second insulating structure 50 facing away from the interlayer dielectric structure 70. The second insulating structure 90 connects to and covers the peripheral side surface of the second electrode 30. The surface of the second electrode 30 facing the channel 20 may extend beyond the surface of the second insulating structure 90 facing the second insulating structure 50, or the surface of the second electrode 30 facing the channel 20 may be aligned with the surface of the second insulating structure 90 facing the second insulating structure 50. Figures 5 to 7 In the second electrode 30, the surface of the second electrode 30 facing away from the second contact 140 extends out of the surface of the second insulating structure 90 toward the second isolation structure 50. The portion of the second electrode 30 extending out of the second insulating structure 90 is an extension region, which can improve the electrical performance of the device.

[0122] The second insulating structure 90 has a second receiving hole 90a extending through the second insulating structure 90 along the Z-axis. The second receiving hole 90a is located in the direction opposite to the channel 20 of the second electrode 30, and the second receiving hole 90a exposes the surface of the second electrode 30 opposite to the channel 20. The second contact 140 is disposed in the second receiving hole 90a and is connected to the second electrode 30, so that the second contact 140 and the second electrode 30 are electrically connected.

[0123] Please see Figure 7 The second isolation structure 50 has a fifth through hole 50a extending through it along the Z-axis, and the second insulating structure 90 has a sixth through hole 90b extending through it along the Z-axis. The fifth through hole 50a is located in the direction opposite to the fourth through hole 70b and the second through hole 80c, and the sixth through hole 90b is located in the direction opposite to the fifth through hole 50a and the fourth through hole 70b, and the fifth through hole 50a communicates with both the sixth through hole 90b and the second through hole. A connecting groove 90c is also provided on the side of the second insulating structure 90 opposite to the second isolation structure 50. The connecting groove 90c is located between the second receiving hole 90a and the sixth through hole 90b, and the connecting groove 90c communicates with both the second receiving hole 90a and the sixth through hole 90b.

[0124] The second connecting component 182 of the connector 180 is disposed within the fifth through hole 50a and the sixth through hole 90b, and the second connecting component 182 is connected to the surface of the first connecting component 181 facing away from the first conductive network structure 110. The third connecting component 183 is disposed within the connecting groove 90c, and the third connecting component 183 is connected to the second contact 140 and the second connecting component 182 respectively. The second electrode 30 is electrically connected to the first conductive network structure 110 through the second contact 140 and the connector 180.

[0125] Please see Figure 5 and Figure 7 The second conductive network structure 120 is disposed on the surface of the second insulating structure 90 facing away from the second isolation structure 50.

[0126] Understandably, the first insulating structure 80 insulates adjacent first electrodes 10, and the second insulating structure 90 insulates adjacent second electrodes 30. Furthermore, the semiconductor device 1 eliminates the need for shallow trench isolation, P-well layers, and N-well layers, simplifying its structure and saving on manufacturing processes. Simultaneously, the semiconductor device 1 does not require a substrate, avoiding substrate effects and improving its reliability.

[0127] It should be noted that, Figures 5 to 7In the example, the first conductive network structure 110 is electrically connected to the first electrode 10, the second electrode 30, and the gate 40, respectively. In one possible embodiment, the first conductive network structure 110 is electrically connected to the first electrode 10 and the second electrode 30, respectively, and the second conductive network structure 120 is electrically connected to the gate 40. In another possible embodiment, the first conductive network structure 110 is electrically connected to the gate 40, and the second conductive network structure 120 is electrically connected to the first electrode 10 and the second electrode 30, respectively.

[0128] Understandably, the first conductive network structure 110 supplies power to the first electrode 10 and the second electrode 30, while the second conductive network structure 120 provides a signal to the gate 40; alternatively, the first conductive network structure 110 provides a signal to the gate 40, and the second conductive network structure 120 supplies power to the first electrode 10 and the second electrode 30. This separates the signal-providing network structure from the power-supplying network structure, reducing the voltage drop of the power supply network structure and improving its power transmission efficiency. It also prevents interference with the signal transmitted by the signal-providing network structure. Furthermore, the first conductive network structure 110, the first electrode 10, the second electrode 30, and the second conductive network structure 120 are arranged along the vertical direction (Z-axis direction). The electrical connection between the first electrode 10 and the first conductive network structure 110 is not on the same plane as the electrical connection between the gate 40 and the first conductive network structure 110, thus avoiding the risk of short circuits or breakdowns between the first electrode 10 and the gate 40. The electrical connection between the second electrode 30 and the first conductive network structure 110 is not on the same plane as the electrical connection between the gate 40 and the first conductive network structure 110, thus avoiding the risk of short circuit or breakdown between the second electrode 30 and the gate 40.

[0129] It should also be noted that, Figures 5 to 7 In this configuration, the first electrode 10 is electrically connected to the first conductive network structure 110 via the first contact 130, and the second electrode 30 is connected to the first conductive network structure 110 via the second contact 140 and the connector 180. In one possible embodiment, the second electrode 30 is electrically connected to the second conductive network structure 120 via the second contact 140.

[0130] Understandably, the first electrode 10 is directly electrically connected to the first conductive network structure 110 through the first contact 130, which helps to maximize the use of the winding resources of the conductive network and improve the integration of the device. The second electrode 30 is directly electrically connected to the second conductive network structure 120 through the second contact 140, which helps to maximize the use of the winding resources of the conductive network and improve the integration of the device.

[0131] Please see Figure 5 and Figure 7A channel 20, together with its connected first electrode 10, second electrode 30, gate 40, first isolation structure 60, and second isolation structure 50, constitutes a vertical transistor. This vertical transistor can be either an N-type or P-type transistor. For ease of demonstration and description, Figure 5 The example shows two vertical transistors. Figure 7 An example of a vertical transistor is provided. The number of vertical transistors is referred to as "multiple" below. "Multiple" can mean several, dozens, thousands, tens of thousands, ..., hundreds of millions. This application does not impose any specific limitation on this.

[0132] In an exemplary embodiment, the number of channels 20, the number of first electrodes 10, and the number of second electrodes 30 are the same as the number of first isolation structures 60. One first isolation structure 60 is connected to the peripheral side of one channel 20, and one second isolation structure 50 can connect to the peripheral side of the channels 20 of multiple vertical transistors. The number of first contacts 130 is the same as the number of vertical transistors, and one first contact 130 is connected to the first electrode 10 of one vertical transistor. The number of second contacts 140 is the same as the number of vertical transistors, and one second contact 140 is connected to the second electrode 30 of one vertical transistor. The number of third contacts 170 is the same as the number of vertical transistors, and one third contact 170 is connected to the gate 40 of one vertical transistor.

[0133] A first insulating structure 80 connects the peripheral surfaces of the first electrodes 10 of a plurality of vertical transistors, the surfaces of a plurality of first isolation structures 60 opposite to the gate 40, and the peripheral surfaces of a plurality of first contacts 130. A second insulating structure 90 connects the peripheral surfaces of the second electrodes 30 of a plurality of vertical transistors, the peripheral surfaces of a plurality of second contacts 140, and the surface of the first isolation structures 60 opposite to the gate 40. An interlayer dielectric structure 70 connects the peripheral surfaces of the gates 40 of a plurality of vertical transistors and the peripheral surfaces of the plurality of first isolation structures 60. A first conductive network structure 110 and a second conductive network structure 120 are electrically connected to a plurality of vertical transistors.

[0134] Based on the same inventive concept, embodiments of this application also provide a method for fabricating a semiconductor device. Please refer to [link to relevant documentation]. Figure 8 , Figure 8 This is a schematic flowchart illustrating the method for fabricating a semiconductor device disclosed in an embodiment of this application. The method for fabricating the semiconductor device is used to form the aforementioned semiconductor device 1. For a description of the similarities between the structure involved in the method for fabricating the semiconductor device and the structure of semiconductor device 1, please refer to the relevant description of semiconductor device 1 above; it will not be repeated here. Please refer to... Figure 5 , Figure 7 and Figure 8 The method for fabricating semiconductor devices includes the following steps.

[0135] S100. An etch stop structure 220, a channel 20, and a second isolation structure 50 are sequentially formed on one surface of the substrate 210. The etch stop structure 220 is located on one surface of the substrate 210. The channel 20 and the second isolation structure 50 are both located on the surface of the etch stop structure 220 facing away from the substrate 210. The second isolation structure 50 connects at least a portion of the peripheral side surface of the channel 20. The channel 20 includes a first end face 20a and a second end face 20b disposed opposite to each other. The first end face 20a extends out of the second isolation structure 50, and the second end face 20b is connected to the etch stop structure 220.

[0136] S200, a gate 40 is formed on the surface of the second isolation structure 50 opposite to the etch stop structure 220, and the gate 40 is connected to at least a portion of the peripheral side surface of the channel 20.

[0137] S300, A first isolation structure 60 is formed on the surface of the gate 40 opposite to the second isolation structure 50, and the first end face 20a of the channel 20 exposes the first isolation structure 60.

[0138] S400, a first pole 10 is formed on the first end face 20a of the channel 20.

[0139] S500, a first insulating structure 80 is formed on the peripheral side of the first electrode 10 and on the surface of the first electrode 10 facing away from the channel 20.

[0140] S600, a first conductive network structure 110 is formed on the surface of the first insulating structure 80 opposite to the first isolation structure 60.

[0141] S700, removing substrate 210 and etch stop structure 220, the second end face 20b of channel 20 exposes second isolation structure 50.

[0142] S800, a second electrode 30 is formed on the second end face 20b of the channel 20. The second electrode 30 and the first electrode 10 are symmetrical along the plane where the center of the channel 20 is located. The first electrode 10, the channel 20, the second electrode 30, the gate 40, the first isolation structure 60 and the second isolation structure 50 constitute a vertical transistor.

[0143] S900, a second insulating structure 90 is formed on the surface of the second isolation structure 50 opposite to the gate 40, and the second insulating structure 90 covers the second electrode 30.

[0144] S1000, a second conductive network structure 120 is formed on the surface of the second insulating structure 90 opposite to the second isolation structure 50.

[0145] Understandably, the semiconductor device fabrication method provided in this application exposes the first end face 20a and the second end face 20b of the channel 20 respectively, and forms the first electrode 10 on the first end face 20a and the second electrode 30 on the second end face 20b in sequence. This avoids forming the first electrode 10 and the second electrode 30 layer by layer, making the second electrode 30 and the first electrode 10 symmetrical along the corresponding planes around the channel 20. The conductivity of the semiconductor device 1 is also symmetrical, thus improving the electrical symmetry of the device.

[0146] Please see Figure 9 , Figure 9 This is a flowchart illustrating step S100 of the semiconductor device fabrication method disclosed in this application embodiment. Step S100 includes the following steps.

[0147] S110, a substrate 210 is provided, and an etch stop structure 220 and an epitaxial structure 320 are sequentially formed on one surface of the substrate 210.

[0148] Specifically, please refer to Figure 10 , Figure 10 for Figure 9 The diagram shows the layer structure formed corresponding to step S110. An etch stop structure 220 is formed on one surface of the substrate 210, and an epitaxial structure 320 is formed on the surface of the etch stop structure 220 opposite to the substrate 210. The material of the etch stop structure 220 includes germanium silicon (SiGe) or boron-doped silicon (B-doped Si).

[0149] S120, a barrier structure 230 is formed on the surface of the epitaxial structure 320 opposite to the etch stop structure 220, and the barrier structure 230 is exposed on a portion of the surface of the epitaxial structure 320 opposite to the etch stop structure 220.

[0150] Specifically, please refer to Figure 11 , Figure 11 for Figure 9 The diagram shows the layer structure formed in step S120. A barrier structure 230 is formed on the surface of the epitaxial structure 320 opposite to the etch stop structure 220 using a deposition process. The portion of the surface of the epitaxial structure 320 opposite to the etch stop structure 220 is not covered by the barrier structure 230. The material of the barrier structure 230 includes silicon nitride (SiN).

[0151] S130, Remove the portion of the epitaxial structure 320 that is offset from the barrier structure 230 to form the channel 20. The portion of the surface of the etch stop structure 220 facing away from the substrate 210 exposes the barrier structure 230. The peripheral side surface of the channel 20 is exposed. The first end face 20a of the channel 20 is connected to the barrier structure 230, and the second end face 20b of the channel 20 is connected to the etch stop structure 220.

[0152] Specifically, please refer to Figures 12 to 14 , Figure 12 for Figure 9 The diagram shows a top view of the structure formed in step S130. Figure 13 for Figure 12 The diagram shows a cross-sectional view of the structure along the S1-S1 direction. Figure 14 for Figure 12 The diagram shows a cross-sectional view of the structure along the S2-S2 direction. For ease of illustration, Figure 13 Only the cross-section along the S1-S1 direction is shown in the previous section. All subsequent sections along the S1-S1 direction will be shown in part and will not be repeated here. The location of the channel 20 is defined using FinSelf-align Multiple Patterning (SAMP) with the barrier structure 230 as a mask. The channel 20 is located below the barrier structure 230. A dry etching process is used, with the barrier structure 230 as a mask, to remove the portion of the epitaxial structure 320 that is misaligned with the barrier structure 230, retaining the epitaxial structure 320 below the barrier structure 230 to form the channel 20, exposing the peripheral side of the channel 20. The dry etching process continues until the etching stop structure 220 is reached, exposing the portion of the etching stop structure 220 facing away from the substrate 210.

[0153] S140, A second isolation structure 50 is formed on the surface of the etch stop structure 220 facing away from the substrate 210, and the second isolation structure 50 is connected to the peripheral side surface of the channel 20.

[0154] Specifically, please refer to Figures 15 to 17 , Figure 15 for Figure 9 The diagram shows a top view of the structure formed in step S140. Figure 16 for Figure 15 The diagram shows a cross-sectional view of the structure along the S1-S1 direction. Figure 17 for Figure 15The diagram shows a cross-sectional view of the structure along the S2-S2 direction. A second isolation structure 50 is formed on the surface of the etch stop structure 220 opposite to the substrate 210 using either Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD). The second isolation structure 50 surrounds and connects to the peripheral side surface of the channel 20. The height of the second isolation structure 50 is lower than the height of the channel 20; that is, one end of the channel 20 opposite to the etch stop structure 220 extends beyond the surface of the second isolation structure 50 opposite to the etch stop structure 220. The material of the second isolation structure 50 includes silicon dioxide (SiO2) or silicon oxycarbonate (SiOC). After the second isolation structure 50 is formed, the surface of the second isolation structure 50 facing away from the etch stop structure 220 is etched flat by an etching process with a self-limiting reaction mechanism, such as etch back process and atomic layer etching process, so as to maximize the elimination of the etch loading effect of the second isolation structure 50.

[0155] It should be noted that when the second isolation structure 50 is formed, an isolation film is also formed on the surface of the barrier structure 230 facing away from the channel 20. The isolation film on the barrier structure 230 can be removed by chemical mechanical planarization (CMP) process, so that the surface of the barrier structure 230 facing away from the channel 20 is exposed.

[0156] Please see Figure 18 , Figure 18 This is a flowchart illustrating step S100 of the semiconductor device fabrication method disclosed in the embodiments of this application. Step S200 includes the following steps.

[0157] S210 forms an oxide structure on the peripheral side of the channel 20.

[0158] S220, using the blocking structure 230 as a mask, a substitute gate structure 240 is formed on the surface of the second isolation structure 50 opposite to the etching stop structure 220, and the substitute gate structure 240 is connected to the peripheral side of the oxide structure.

[0159] Specifically. Please see Figures 19 to 21 , Figure 19 for Figure 18 The diagram shows a top view of the structure formed in step S220. Figure 20 for Figure 19 The diagram shows a cross-sectional view of the structure along the S1-S1 direction. Figure 21 for Figure 19The diagram shows a cross-sectional view of the structure along the S2-S2 direction. The oxide structure is relatively thin and is not shown in the example structure of the semiconductor device fabrication method. The thickness of the oxide structure is 2nm to 3nm. The oxide structure is used to isolate the channel 20 from the alternative gate structure 240, preventing the alternative gate structure 240 from affecting the channel 20. The height of the alternative gate structure 240 is lower than the height of the channel 20, that is, one end of the channel 20 facing away from the etch stop structure 220 extends beyond the surface of the alternative gate structure 240 facing away from the second isolation structure 50. The alternative gate structure 240 comprises amorphous silicon (A-Si).

[0160] It should be noted that when the alternative gate structure 240 is formed, a layer of alternative gate film is also formed on the surface of the barrier structure 230 facing away from the channel 20. The alternative gate film on the barrier structure 230 can be removed by chemical mechanical planarization (CMP) process, so that the surface of the barrier structure 230 facing away from the channel 20 is exposed.

[0161] Understandably, by using the blocking structure 230 as a mask to form the alternative gate structure 240, the position of the alternative gate structure 240 is not limited by the photolithography process, thus eliminating the error during photolithography definition, realizing the self-aligned formation of the alternative gate structure 240, and reducing the complexity of the process.

[0162] S230, The surface of the replacement gate structure 240 facing away from the second isolation structure 50 is etched smooth by an etching process based on a self-limiting reaction mechanism.

[0163] Specifically, after the replacement gate structure 240 is formed, the surface of the replacement gate structure 240 facing away from the second isolation structure 50 is etched flat by a self-limiting reaction mechanism etching process, such as etch back process and atomic layer etching process, in order to maximize the elimination of the etch loading effect of the replacement gate structure 240 and facilitate the flattening of the surface of the replacement gate structure 240 facing away from the second isolation structure 50.

[0164] S240, a sidewall structure 260 is formed on the surface of the alternative gate structure 240 facing away from the second isolation structure 50. The sidewall structure 260 connects the peripheral side surface of the channel 20 and the peripheral side surface of the barrier structure 230.

[0165] Specifically, please refer to Figures 22 to 24 , Figure 22 for Figure 18 The diagram shows a top view of the structure formed in step S240. Figure 23 for Figure 22 The diagram shows a cross-sectional view of the structure along the S1-S1 direction. Figure 24 for Figure 22The diagram shows a cross-sectional view of the structure along the S2-S2 direction. A sidewall structure 260 is formed on a portion of the surface of the second isolation structure 50 opposite to the replacement gate structure 240 using atomic layer deposition. The sidewall structure 260 connects the peripheral side surface of the channel 20 and the peripheral side surface of the barrier structure 230. The portion of the surface of the replacement gate structure 240 opposite to the second isolation structure 50 is not covered by the sidewall structure 260. Adjacent sidewall structures 260 are spaced apart. The material of the sidewall structure 260 includes silicon oxynitride (SiOCN).

[0166] It should be noted that during the formation of the sidewall structure 260, other parts of the replacement gate structure 240 are also formed with a sidewall film. The sidewall film is removed by anisotropic etching process, leaving the sidewall structure 260 of the peripheral side surface of the channel 20 and the peripheral side surface of the barrier structure 230 intact.

[0167] S250, Remove the replacement gate structure 240 and the oxide structure, and expose the peripheral side of the channel 20.

[0168] Specifically, please refer to Figures 25 to 27 , Figure 25 for Figure 18 The diagram shows a top view of the structure formed corresponding to step S250. Figure 26 for Figure 25 The diagram shows a cross-sectional view of the structure along the S1-S1 direction. Figure 27 for Figure 25 The diagram shows a cross-sectional view of the structure along the S2-S2 direction. The replacement gate structure 240 is removed by a wet etching process, and then the oxide structure is removed by a wet etching process, exposing the peripheral side of the channel 20 and the surface of the second isolation structure 50 facing away from the etching stop structure 220.

[0169] S260, a gate structure 340 is formed on the surface of the second isolation structure 50 opposite to the etch stop structure 220. The gate structure 340 connects the exposed peripheral side surface of the channel 20 and the peripheral side surface of the sidewall structure 260.

[0170] Specifically, please refer to Figures 28 to 30 , Figure 28 for Figure 18 The diagram shows a top view of the structure formed in step S260. Figure 29 for Figure 28 The diagram shows a cross-sectional view of the structure along the S1-S1 direction. Figure 30 for Figure 28The diagram shows a cross-sectional view of the structure along the S2-S2 direction. An interface structure, a dielectric structure, and a work function metal structure are sequentially formed on the exposed peripheral side of the gate structure 340 connecting to the channel 20. That is, the interface structure is first formed on the exposed peripheral side of the gate structure 340 connecting to the channel 20, then the dielectric structure is formed on the peripheral side of the interface structure, and finally the work function metal structure is formed on the peripheral side of the dielectric structure. The interface structure, dielectric structure, and work function metal structure constitute the gate structure 340. The thickness of the interface structure is less than 1 nm. The material of the interface structure includes silicon dioxide, the material of the dielectric structure includes hafnium oxide (HfO2), and the material of the work function metal structure includes titanium nitride (TiN), aluminum titanium carbide (TiAlC), or tungsten nitride (WN). Figures 28 to 30 Only the entire gate structure 340 is shown; the specific interface structure, dielectric structure, and work function metal structure are not shown.

[0171] S270, using the blocking structure 230 and the sidewall structure 260 as a mask, the gate structure 340 on the periphery of the sidewall structure 260 is removed to form a gate transition structure 341, which connects to the periphery of the channel 20.

[0172] Specifically, please refer to Figures 31 to 33 , Figure 31 for Figure 18 The diagram shown is a top view of the structure formed in step S270. Figure 32 for Figure 31 The diagram shows a cross-sectional view of the structure along the S1-S1 direction. Figure 33 for Figure 31 The diagram shows a cross-sectional view of the structure along the S2-S2 direction. The gate structure 340 around the sidewall structure 260 is removed by a dry etching process using the barrier structure 230 and the sidewall structure 260 as masks to form a gate transition structure 341. The surface of the gate transition structure 341 facing away from the second isolation structure 50 is aligned with the surface of the sidewall structure 260 facing the second isolation structure 50.

[0173] Understandably, by using the barrier structure 230 and the sidewall structure 260 as masks to form the gate transition structure 341, the position of the gate transition structure 341 is not limited by the photolithography process, thus eliminating the error during photolithography definition and realizing the self-aligned formation of the gate transition structure 341.

[0174] S280, a shielding structure 280 is formed on a portion of the surface of the gate transition structure 341 facing away from the second isolation structure 50, and the shielding structure 280 is connected to one side of the sidewall structure 260.

[0175] Specifically, please refer to Figures 34 to 36 , Figure 34 for Figure 18The diagram shows a top view of the structure formed in step S280. Figure 35 for Figure 34 The diagram shows a cross-sectional view of the structure along the S1-S1 direction. Figure 36 for Figure 34 The diagram shows a cross-sectional view of the structure along the S2-S2 direction. A shielding structure 280 is formed on the portion of the gate transition structure 341 facing away from the second isolation structure 50. The surface of the shielding structure 280 facing away from the gate transition structure 341 is aligned with the surface of the sidewall structure 260 facing away from the gate transition structure 341. The peripheral sidewall structure 260 includes four sides, and the shielding structure 280 connects to one of these four sides. The shielding structure 280 can be photoresist.

[0176] S290, using the blocking structure 230, sidewall structure 260 and shielding structure 280 as masks, remove the portion of the gate transition structure 341 that is offset from the sidewall structure 260 and shielding structure 280 to form the gate 40.

[0177] Specifically, please refer to Figures 37 to 39 , Figure 37 for Figure 18 The diagram shows a top view of the structure formed in step S290. Figure 38 for Figure 37 The diagram shows a cross-sectional view of the structure along the S1-S1 direction. Figure 39 for Figure 37 The diagram shows a cross-sectional view of the structure along the S2-S2 direction. The portion of the gate transition structure 341 that is offset from the sidewall structure 260 and the shielding structure 280 is removed by an etching process using the barrier structure 230, sidewall structure 260, and shielding structure 280 as masks. The gate transition structure 341 below the sidewall structure 260 and shielding structure 280 is retained to form the gate 40.

[0178] It should be noted that, in order to ensure the complete removal of the portion of the gate transition structure 341 that is offset from the sidewall structure 260 and the shielding structure 280, the second isolation structure 50 can be etched downwards. The downward etching of the second isolation structure 50 forms the first isolation substructure 51 and the second isolation substructure 52. For a description of the first isolation substructure 51 and the second isolation substructure 52, please refer to the relevant description of semiconductor device 1, which will not be repeated here.

[0179] Understandably, by using the barrier structure 230, sidewall structure 260, and shielding structure 280 as masks to form the gate 40, the position of the gate 40 is not limited by photolithography, eliminating errors during photolithography definition and achieving a self-aligned gate 40, thus improving device reliability. The shielding structure 280 is used to occupy the position where the third contact is formed.

[0180] Please see Figure 40 , Figure 40 This is a flowchart illustrating step S300 of the semiconductor device fabrication method disclosed in this application embodiment. Step S300 includes the following steps.

[0181] S310, Remove occlusion structure 280.

[0182] S320, an interlayer dielectric transition structure 270 is formed on the surface of the second isolation structure 50 opposite to the etch stop structure 220. The interlayer dielectric transition structure 270 covers the gate 40, the shielding structure 280 and the blocking structure 230.

[0183] Specifically, please refer to Figures 41 to 43 , Figure 41 for Figure 40 The diagram shown is a top view of the structure formed in step S320. Figure 42 for Figure 41 The diagram shows a cross-sectional view of the structure along the S1-S1 direction. Figure 43 for Figure 41 The diagram shows a cross-sectional view of the structure along the S2-S2 direction. An interlayer dielectric transition structure 270 is formed on the surface of the second isolation structure 50 opposite to the etch stop structure 220 and on the surface of the gate 40 opposite to the second isolation structure 50. The interlayer dielectric transition structure 270 connects the peripheral side surface of the gate 40, the peripheral side surface of the sidewall structure 260, the surface of the sidewall structure 260 opposite to the gate 40, and the surface of the barrier structure 230 opposite to the channel 20. The material of the interlayer dielectric transition structure 270 includes silicon dioxide (SiO2) or silicon oxycarbonate (SiOC).

[0184] Understandably, the interlayer dielectric transition structure 270 covers the gate 40 to prevent the gate 40 from being exposed or damaged. Moreover, the interlayer dielectric transition structure 270 covers both the shielding structure 280 and the blocking structure 230, which can effectively prevent damage to the interlayer dielectric structure 70 and the blocking structure 230 during the polishing process in step S330.

[0185] S330, remove the portion of the interlayer medium transition structure 270 extending out of the first end face 20a to form the interlayer medium structure 70, remove the portion of the sidewall structure 260 extending out of the first end face 20a to form the first isolation structure 60, and remove the blocking structure 230, exposing the first end face 20a of the channel 20 to the first isolation structure 60.

[0186] Specifically, please refer to Figures 44 to 46 , Figure 44 for Figure 40 The diagram shown is a top view of the structure formed corresponding to step S330. Figure 45 for Figure 44 The diagram shows a cross-sectional view of the structure along the S1-S1 direction. Figure 46 for Figure 44 The diagram shows a cross-sectional view of the structure along the S2-S2 direction. The blocking structure 230 above the plane containing the first end face 20a of the channel 20, the sidewall structure 260 above the plane containing the first end face 20a, are removed using a chemical mechanical polishing process to form the first isolation structure 60, and the interlayer dielectric transition structure 270 above the plane containing the first end face 20a is removed to form the interlayer dielectric structure 70. The first isolation structure 60 connects to the peripheral side surface of the channel 20, and the interlayer dielectric structure 70 connects to the peripheral side surface of the gate 40 and the peripheral side surface of the first isolation structure 60. The first end face 20a of the channel 20, the surface of the first isolation structure 60 facing away from the gate 40, and the surface of the interlayer dielectric structure 70 facing away from the second isolation structure 50 are aligned with each other. The first end face 20a of the channel 20 exposing the first isolation structure 60 means that the first isolation structure 60 does not obstruct the first end face 20a; the first end face 20a can be flush with the surface of the first isolation structure 60 facing away from the gate 40 or extend beyond the first isolation structure 60.

[0187] Please see Figures 47 to 49 , Figure 47 for Figure 8 The diagram shows a top view of the structure formed corresponding to step S400 of the semiconductor device fabrication method. Figure 48 for Figure 47 The diagram shows a cross-sectional view of the structure along the S1-S1 direction. Figure 49 for Figure 47 The diagram shows a cross-sectional view of the structure along the S2-S2 direction. The first electrode 10 is formed on the first end face 20a using a selective epitaxial process. The epitaxy can be low-temperature vapor phase epitaxy.

[0188] The material of the first electrode 10 includes boron-doped germanium-silicon; or, the material of the first electrode 10 includes arsenic-doped silicon or phosphorus-doped silicon. This allows the doped material of the first electrode 10 to diffuse into the channel 20, improving the electrical performance of the device. It should be noted that if the material of the first electrode 10 is boron-doped germanium-silicon, the overall shape of the first electrode 10 is prism, and the cross-sectional shapes along the S1-S1 direction and along the S2-S2 direction are both polygonal. If the material of the first electrode 10 is phosphorus-doped silicon, the overall shape of the first electrode 10 is cylindrical, and the cross-sectional shapes along the S1-S1 direction and along the S2-S2 direction are both circular or similarly circular.

[0189] Please see Figures 50 to 52 , Figure 50 for Figure 8 The diagram shows a top view of the structure formed corresponding to step S500 of the semiconductor device fabrication method. Figure 51 for Figure 50 The diagram shows a cross-sectional view of the structure along the S1-S1 direction. Figure 52 for Figure 50 The diagram shows a cross-sectional view of the structure along the S2-S2 direction. A first insulating structure 80 is formed on the surface of the second insulating structure 50 opposite to the interlayer dielectric structure 70. The first insulating structure 80 connects to the peripheral side surface of the first electrode 10 and covers the surface of the first electrode 10 opposite to the channel 20.

[0190] After forming the first insulating structure 80, a first receiving hole 80a is formed through the first insulating structure 80 by etching. A first through-hole 80b and a second through-hole 80c are also formed through the first insulating structure 80 by etching. A third through-hole 70a and a fourth through-hole 70b are formed through the interlayer dielectric structure 70 by etching. The first through-hole 80b and the third through-hole 70a are connected, and the second through-hole 80c and the fourth through-hole 70b are connected. The portion of the surface of the first electrode 10 facing away from the channel 20 exposes the first receiving hole 80a. The portion of the gate 40 facing away from the second isolation structure 50 exposes the first through-hole 80b and the third through-hole 70a. The portion of the second isolation structure 50 facing away from the etch stop structure 220 exposes the second through-hole 80c and the fourth through-hole 70b.

[0191] After opening the first receiving hole 80a, the first through hole 80b, the second through hole 80c, the third through hole 70a and the fourth through hole 70b, a first contact 130 is formed in the first receiving hole 80a, a third contact 170 is formed in the first through hole 80b and the third through hole 70a, and a first connecting part 181 is formed in the second through hole 80c and the fourth through hole 70b.

[0192] For further descriptions of the first receiving hole 80a, the first through hole 80b, the second through hole 80c, the third through hole 70a, the fourth through hole 70b, the first contact 130, the third contact 170, and the first connecting sub-component 181, please refer to the relevant descriptions of the semiconductor device 1 above, which will not be repeated here.

[0193] Please see Figures 53 to 55 , Figure 53 for Figure 8 The diagram shows a top view of the structure formed corresponding to step S600 of the semiconductor device fabrication method. Figure 54 for Figure 53 The diagram shows a cross-sectional view of the structure along the S1-S1 direction. Figure 55 for Figure 53The diagram shows a cross-sectional view of the structure along the S2-S2 direction. A first conductive network structure 110 is formed on the surface of the first insulating structure 80 opposite to the interlayer dielectric structure 70. The first conductive network structure 110 is connected to the first contact 130, the third contact 170, and the first connecting sub-component 181, respectively, so that the first conductive network structure 110 is electrically connected to the first contact 130, the third contact 170, and the first connecting sub-component 181, respectively.

[0194] A substrate 160 is provided. After the first conductive network structure 110 is formed, it is bonded to the substrate 160 by a low-temperature bonding process. The surface of the first conductive network structure 110 facing away from the first insulating structure 80 is connected to the substrate 160 through a bonding structure 150.

[0195] Understandably, forming the first electrode 10 before forming the first conductive network structure 110 avoids the high-temperature environment required to form the first electrode 10 from affecting the metal in the first conductive network structure 110, thereby improving the reliability of the first conductive network structure 110.

[0196] Please see Figures 56 to 58 , Figure 56 for Figure 8 The diagram shows a top view of the structure formed corresponding to step S700 of the semiconductor device fabrication method. Figure 57 for Figure 56 The diagram shows a cross-sectional view of the structure along the S1-S1 direction. Figure 58 for Figure 56 The diagram shows a cross-sectional view of the structure along the S2-S2 direction. The formed portion of the semiconductor device is inverted, and the substrate 210 and etch stop structure 220 are removed, exposing the second end face 20b of the channel 20 and the surface of the second isolation structure 50 facing away from the interlayer dielectric structure 70.

[0197] Please see Figures 59 to 61 , Figure 59 for Figure 8 The diagram shows a top view of the structure formed corresponding to step S800 of the semiconductor device fabrication method. Figure 60 for Figure 59 The diagram shows a cross-sectional view of the structure along the S1-S1 direction. Figure 61 for Figure 59 The diagram shows a cross-sectional view of the structure along the S2-S2 direction. A second electrode 30 is formed on the second end face 20b of the channel 20 using a selective epitaxial process. The second electrode 30 is symmetrical to the first electrode 10 along the corresponding planes around the channel 20. The epitaxy can be low-temperature vapor phase epitaxy. "Exposed second end face 20b" means that the second end face 20b is not obstructed; it can be flush with the surface of the second isolation structure 50 opposite to the gate 40, or it can extend beyond the second isolation structure 50.

[0198] Understandably, by selectively epitaxially forming the first electrode 10 and the second electrode 30, the formation positions of the first electrode 10 and the second electrode 30 can be restricted, thereby improving the symmetry of the first electrode 10 and the second electrode 30.

[0199] The material of the second electrode 30 includes boron-doped germanium-silicon; or, the material of the second electrode 30 includes arsenic-doped silicon or phosphorus-doped silicon. This allows the doped material of the second electrode 30 to diffuse into the channel 20, improving the electrical performance of the second electrode 30. It should be noted that if the material of the second electrode 30 is boron-doped germanium-silicon, the overall shape of the second electrode 30 is prism, and the cross-sectional shapes along the S1-S1 direction and along the S2-S2 direction are both polygonal. If the material of the second electrode 30 is phosphorus-doped silicon, the overall shape of the second electrode 30 is cylindrical, and the cross-sectional shapes along the S1-S1 direction and along the S2-S2 direction are both circular or similarly circular.

[0200] Please see Figures 62 to 64 , Figure 62 for Figure 8 The diagram shows a top view of the structure formed corresponding to step S900 of the semiconductor device fabrication method. Figure 63 for Figure 62 The diagram shows a cross-sectional view of the structure along the S1-S1 direction. Figure 64 for Figure 62 The diagram shows a cross-sectional view of the structure along the S2-S2 direction. A second insulating structure 90 is formed on the surface of the second isolation structure 50 opposite to the gate 40. The second insulating structure 90 connects to the peripheral side surface of the second electrode 30 and covers the surface of the second electrode 30 opposite to the channel 20.

[0201] After the second insulating structure 90 is formed, a connecting groove 90c, a second receiving hole 90a penetrating the second insulating structure 90, and a sixth through hole 90b penetrating the second insulating structure 90 are formed on the side of the second insulating structure 90 opposite to the second isolation structure 50 by etching. A fifth through hole 50a penetrating the second isolation structure 50 is also formed by etching. The fifth through hole 50a communicates with both the fourth through hole 70b and the sixth through hole 90b, and the connecting groove 90c communicates with both the second receiving hole 90a and the sixth through hole 90b.

[0202] After forming the connecting groove 90c, the second receiving hole 90a, the sixth through hole 90b, and the fifth through hole 50a, a second contact 140 is formed in the second receiving hole 90a, a second connecting component 182 is formed in the fifth through hole 50a and the sixth through hole 90b, and a third connecting component 183 is formed in the connecting groove 90c. The second connecting component 182 is connected to the first connecting component 181 and the third connecting component 183, respectively, and the second contact 140 is connected to the third connecting component 183 and the second electrode 30, respectively. The first connecting component 181, the second connecting component 182, and the third connecting component 183 constitute the connecting component 180, and the second electrode 30 is electrically connected to the first conductive network structure 110 through the second contact 140 and the connecting component 180.

[0203] For further descriptions of the connecting groove 90c, the second receiving hole 90a, the sixth through hole 90b, the fifth through hole 50a, the second connecting sub-component 182, and the third connecting sub-component 183, please refer to the relevant description of the semiconductor device 1 above, which will not be repeated here.

[0204] Please see Figures 65 to 67 , Figure 65 for Figure 8 The diagram shows a top view of the structure formed corresponding to step S1000 of the semiconductor device fabrication method. Figure 66 for Figure 65 The diagram shows a cross-sectional view of the structure along the S1-S1 direction. Figure 67 for Figure 65 The diagram shows a cross-sectional view of the structure along the S2-S2 direction. A second conductive network structure 120 is formed on the surface of the second insulating structure 90 opposite to the second insulating structure 50.

[0205] Understandably, forming the second electrode 30 before forming the second conductive network structure 120 avoids the high-temperature environment required to form the second electrode 30 from affecting the metal in the second conductive network structure 120, thereby improving the reliability of the second conductive network structure 120.

[0206] It should be noted that, Figures 55 to 67 In the first electrode 10, the first electrode 10 is electrically connected to the first conductive network structure 110 through the first contact 130, the second electrode 30 is electrically connected to the first conductive network structure 110 through the second contact 140 and the connector 180, and the gate electrode 40 is electrically connected to the first conductive network structure 110 through the third contact 170.

[0207] In one possible embodiment, the second conductive network structure 120 is electrically connected to the first electrode 10, the second electrode 30, and the gate 40, respectively.

[0208] In one possible embodiment, the first conductive network structure 110 is electrically connected to the first electrode 10 and the second electrode 30, respectively, and the second conductive network structure 120 is electrically connected to the gate 40.

[0209] In one possible embodiment, the second conductive network structure 120 is electrically connected to the first electrode 10 and the second electrode 30, respectively, and the first conductive network structure 110 is electrically connected to the gate 40.

[0210] In summary, the method for fabricating a semiconductor device disclosed in this application includes: sequentially forming an etch stop structure 220, a channel 20, and a second isolation structure 50 on a surface of a substrate 210. The etch stop structure 220 is located on a surface of the substrate 210, and both the channel 20 and the second isolation structure 50 are located on the surface of the etch stop structure 220 facing away from the substrate 210. The second isolation structure 50 is connected to the peripheral side surface of the channel 20. The channel 20 includes a first end face 20a and a second end face 20b disposed opposite to each other. The first end face 20a extends out of the second isolation structure 50, and the second end face 20b is connected to the etch stop structure 220. A gate 40 is formed on the surface of the second isolation structure 50 facing away from the etch stop structure 220. The gate 40 is located on the surface of the second isolation structure 50 facing away from the etch stop structure 220 and is connected to the peripheral side surface of the channel 20. A first isolation structure 60 is formed on the surface of the gate 40 facing away from the second isolation structure 50, and the first end face 20a of the channel 20 is exposed to the first isolation structure 60. A first electrode 10 is formed on the first end face 20a of the channel 20. The substrate 210 and the etch stop structure 220 are removed, exposing the second end face 20b of the channel 20. A second electrode 30 is formed on the second end face 20b of the channel 20, and the second electrode 30 is symmetrical to the first electrode 10 along the corresponding planes around the periphery of the channel 20. Therefore, by exposing the first end face 20a and the second end face 20b of the channel 20 respectively, and forming the first electrode 10 on the first end face 20a and the second electrode 30 on the second end face 20b sequentially, the layer-by-layer formation of the first electrode 10 and the second electrode 30 is avoided. This ensures that the second electrode 30 and the first electrode 10 are symmetrical along the corresponding planes around the periphery of the channel 20, and the conductivity of the semiconductor device 1 is also symmetrical, improving the electrical symmetry and conductivity of the device.

[0211] It should be understood that the application of this application is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims. Those skilled in the art will understand that implementing all or part of the processes of the above embodiments, and making equivalent changes according to the claims of this application, still falls within the scope of this application.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes a vertical transistor, which includes a first electrode, a channel, a second electrode, a gate, a first isolation structure, and a second isolation structure. The channel includes a first end face and a second end face disposed opposite to each other. The first electrode is disposed on the first end face, and the second electrode is disposed on the second end face. The first electrode, the channel, and the second electrode are stacked. The gate is disposed on the peripheral side of the channel. The first isolation structure is disposed between the gate and the first electrode, and the second isolation structure is disposed between the gate and the second electrode. The second electrode and the first electrode are symmetrical along the plane where the center of the channel is located.

2. The semiconductor device as claimed in claim 1, characterized in that, The first pole is symmetrical along the plane containing its own central axis.

3. The semiconductor device as described in claim 1, characterized in that, The second pole is symmetrical along the plane containing its own central axis.

4. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor device further includes a first insulating structure and a second insulating structure. The first insulating structure is disposed on the surface of the first isolation structure opposite to the gate and covers the first electrode. The second insulating structure is disposed on the surface of the second isolation structure opposite to the gate and covers the second electrode.

5. The semiconductor device as claimed in claim 4, characterized in that, The semiconductor device further includes an interlayer dielectric structure disposed on the peripheral side of the gate and the peripheral side of the first isolation structure, and the interlayer dielectric structure is connected to the first insulating structure and the second insulating structure, respectively.

6. The semiconductor device as claimed in claim 4, characterized in that, The semiconductor device further includes a first conductive network structure and a second conductive network structure. The first conductive network structure is disposed on the surface of the first insulating structure opposite to the first isolation structure, and the second conductive network structure is disposed on the surface of the second insulating structure opposite to the second isolation structure. The first conductive network structure is electrically connected to both the first electrode and the second electrode, and the second conductive network structure is electrically connected to the gate electrode; or... The first conductive network structure is electrically connected to the gate, and the second conductive network structure is electrically connected to the first electrode and the second electrode, respectively.

7. The semiconductor device as claimed in claim 6, characterized in that, The first insulating structure has a first receiving hole that penetrates the first insulating structure, exposing the first electrode. A first contact is disposed within the first receiving hole, and the first contact is connected to the first electrode. The first electrode is electrically connected to the first conductive network structure through the first contact; or... The second insulating structure has a second receiving hole that penetrates the second insulating structure, the second receiving hole exposes the second electrode, a second contact is provided in the second receiving hole, the second contact is connected to the second electrode, and the second electrode is electrically connected to the second conductive network structure through the second contact.

8. A method for fabricating a semiconductor device, characterized in that, The method for fabricating the semiconductor device includes: An etch stop structure, a channel, and a second isolation structure are sequentially formed on one surface of a substrate. The etch stop structure is located on one surface of the substrate, and the channel and the second isolation structure are both located on the surface of the etch stop structure opposite to the substrate. The second isolation structure connects at least a portion of the peripheral side surface of the channel. The channel includes a first end face and a second end face disposed opposite to each other. The first end face extends out of the second isolation structure, and the second end face is connected to the etch stop structure. A gate is formed on the surface of the second isolation structure opposite to the etch stop structure, the gate being connected to at least a portion of the peripheral side surface of the channel; A first isolation structure is formed on the surface of the gate opposite to the second isolation structure, and the first end face of the channel exposes the first isolation structure; A first pole is formed at the first end face of the channel; Remove the substrate and the etch stop structure, and the second end face of the trench exposes the second isolation structure; A second electrode is formed on the second end face of the channel. The second electrode is symmetrical to the first electrode along the plane where the center of the channel is located. The first electrode, the channel, the second electrode, the gate, the first isolation structure, and the second isolation structure constitute a vertical transistor.

9. The method for fabricating a semiconductor device as described in claim 8, characterized in that, The first end face of the channel is formed with a blocking structure, and the formation of a gate on the surface of the second isolation structure opposite to the etch stop structure includes: An oxide structure is formed on the peripheral surface of the channel; Using the blocking structure as a mask, an alternative gate structure is formed on the surface of the second isolation structure opposite to the etching stop structure, and the alternative gate structure is connected to the peripheral side surface of the oxide structure; The surface of the alternative gate structure facing away from the second isolation structure is etched flat using an etching process based on a self-limiting reaction mechanism.

10. The method for fabricating a semiconductor device as described in claim 9, characterized in that, The step of forming a gate on the surface of the second isolation structure opposite to the etch stop structure further includes: A sidewall structure is formed on the surface of the alternative gate structure opposite to the second isolation structure, the sidewall structure connecting the peripheral side surface of the channel and the peripheral side surface of the blocking structure; Remove the alternative gate structure and the oxide structure, exposing the peripheral side surface of the channel; A gate structure is formed on the surface of the second isolation structure opposite to the etch stop structure, the gate structure connecting the exposed peripheral side surface of the channel and the peripheral side surface of the sidewall structure; Using the blocking structure and the sidewall structure as a mask, the gate structure on the periphery of the sidewall structure is removed to form a gate transition structure, which connects to the periphery of the channel. A shielding structure is formed on a portion of the surface of the gate transition structure opposite to the second isolation structure, and the shielding structure is connected to one side of the sidewall structure; The gate is formed by removing the portion of the gate transition structure that is offset from the sidewall structure and the shielding structure using the blocking structure, the sidewall structure and the shielding structure as a mask.

11. The method for fabricating a semiconductor device as described in claim 10, characterized in that, The formation of the first isolation structure on the surface of the gate opposite to the second isolation structure includes: Remove the obstructing structure; An interlayer dielectric transition structure is formed on the surface of the second isolation structure opposite to the etch stop structure, and the interlayer dielectric transition structure covers the gate, the shielding structure and the blocking structure. The portion of the interlayer medium transition structure extending beyond the first end face is removed to form an interlayer medium structure; the portion of the sidewall structure extending beyond the first end face is removed to form the first isolation structure; and the blocking structure is removed, exposing the first end face.

12. The method for fabricating a semiconductor device according to any one of claims 8-11, characterized in that, Before removing the substrate and the etch stop structure, the method for fabricating the semiconductor device further includes: A first insulating structure is formed on the peripheral side of the first electrode and on the surface of the first electrode opposite to the channel; A first conductive network structure is formed on the surface of the first insulating structure opposite to the first isolation structure. The first conductive network structure is electrically connected to the first electrode and the second electrode, or the first conductive network structure is electrically connected to the gate.

13. The method for fabricating a semiconductor device according to any one of claims 8-11, characterized in that, The method for manufacturing the semiconductor device further includes: A second insulating structure is formed on the surface of the second isolation structure opposite to the gate, and the second insulating structure covers the second electrode; A second conductive network structure is formed on the surface of the second insulating structure opposite to the second isolation structure. The second conductive network structure is electrically connected to the first electrode and the second electrode, or the second conductive network structure is electrically connected to the gate.

14. A method for fabricating a semiconductor device as described in any one of claims 8-11, characterized in that, The first electrode is formed by selective epitaxy, and the second electrode is formed by selective epitaxy.

15. A method for fabricating a semiconductor device as described in any one of claims 8-11, characterized in that, The material of the first electrode includes boron-doped germanium silicon; or, the material of the first electrode includes arsenic-doped silicon or phosphorus-doped silicon.

16. A method for fabricating a semiconductor device as described in any one of claims 8-11, characterized in that, The material of the second electrode includes boron-doped germanium silicon; or, the material of the second electrode includes arsenic-doped silicon or phosphorus-doped silicon.

17. An integrated circuit, characterized in that, It includes electronic devices and semiconductor devices as described in any one of claims 1-7, wherein the semiconductor device is electrically connected to the electronic device.

18. An electronic device, characterized in that, The electronic device includes a circuit board and an integrated circuit as described in claim 17, wherein the integrated circuit is electrically connected to the circuit board.

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