Semiconductor device

Abstract

The invention relates to a semiconductor device comprising: a source region; the conduction type of the drain electrode region is the same as that of the source electrode region; the field oxide layer is located between the source electrode region and the drain electrode region; the grid electrode is located between the source electrode region and the drain electrode region and extends to the field oxide layer from the edge of the source electrode region; the resistive field plate is located on the field oxide layer, a plurality of series diodes obtained through N-type doping and / or P-type doping are formed on the resistive field plate, and the conduction direction of one part of the series diodes is opposite to the conduction direction of the other part of the series diodes; the resistive field plate is electrically connected with the drain electrode region and the grid electrode. When a potential difference exists between the grid electrode and the drain electrode, a part of diodes of the resistive field plate are reversely biased, so that electric leakage is blocked.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor device. Background Technology

[0002] Field plate structures are the mainstream technology for preventing high-voltage cross-lines and terminal charge concentration. Ideally, floating field plates offer better coupling. However, floating field plates actually manufactured in current fabs (semiconductor wafer foundries) cannot achieve perfectly ideal coupling, resulting in significant discrepancies between actual test results and simulation results.

[0003] The theoretical and experimental results of resistive field plates (i.e., resistive field plates) are closer; however, resistive field plates have leakage problems. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor device that can improve the leakage current problem of resistive field plates.

[0005] A semiconductor device includes: a source region; a drain region having the same conductivity type as the source region; a field oxide layer located between the source region and the drain region; a gate located between the source region and the drain region and extending from the edge of the source region onto the field oxide layer; and a resistive field plate located on the field oxide layer, wherein the resistive field plate has a plurality of series diodes formed by N-type doping and / or P-type doping, and a portion of these series diodes have opposite conduction directions to the other portion; the resistive field plate is electrically connected to the drain region and the gate, respectively.

[0006] In the aforementioned semiconductor device, the resistive field plate is formed with multiple series diodes through N-type doping and / or P-type doping, and some of these series diodes have opposite conduction directions to the others. Thus, when there is a potential difference between the gate and the drain, some of the diodes will be reverse biased, thereby blocking leakage current.

[0007] In one embodiment, the semiconductor device further includes: a drift region, at least partially located between the source region and the drain region; a diode region, including an N-type doped region and a P-type doped region, the N-type doped region and the P-type doped region forming a target diode; an isolation structure located between the drift region and the diode region for electrical isolation between the drift region and the diode region; a metal layer located above the N-type doped region and above the gate, the N-type doped region and the gate being electrically connected through the metal layer; a gate lead electrically connected to the P-type doped region; the gate lead and the gate being connected through the target diode.

[0008] In one embodiment, the semiconductor device further includes: an interlayer dielectric layer covering the source region, drain region, diode region, isolation structure, field oxide layer, gate, and resistive field plate; a metal layer located on the interlayer dielectric layer, the metal layer including a first metal interconnect electrically connected to the N-type doped region through a conductive material in a contact hole above the N-type doped region, and electrically connected to the gate through a conductive material in a contact hole above the gate; the gate is led out and electrically connected to the P-type doped region through a conductive material in a contact hole above the P-type doped region.

[0009] In one embodiment, the metal layer includes a second metal interconnect that is electrically connected to the resistive field plate through a conductive material in a contact hole above the resistive field plate, and electrically connected to the drain region through a conductive material in a contact hole above the drain region.

[0010] In one embodiment, the diode region further includes: an N-type region, wherein the N-type doped region is located within the N-type region and the doping concentration of the N-type doped region is greater than the doping concentration of the N-type region; and a P-well, wherein the P-type doped region is located within the P-well and the doping concentration of the P-type doped region is greater than the doping concentration of the P-well.

[0011] In one embodiment, the resistive field plate is made of high-resistivity polycrystalline silicon or semi-insulating polycrystalline silicon.

[0012] In one embodiment, the resistive field plate includes an outer ring and a spiral portion located inside the outer ring, the spiral portion being connected to the outer ring, and the ring width of the outer ring being greater than the strip width of the spiral portion.

[0013] In one embodiment, the resistive field plate is doped using the same photomask as the source and drain regions.

[0014] In one embodiment, the semiconductor device further includes: a second conductivity type buried region located in a drift region between the source region and the drain region; the source region, drain region, and drift region having a first conductivity type, wherein the first conductivity type and the second conductivity type are opposite conductivity types; and a top doping layer located above the second conductivity type buried region and below the field oxide layer in the drift region, comprising at least one first conductivity type doped layer, wherein the doping concentration of the first conductivity type doped layer is greater than the doping concentration of the drift region.

[0015] In one embodiment, the top doping includes at least two first conductivity type doped layers with different junction depths, and the doping concentration of the top first conductivity type doped layer is greater than the doping concentration of the remaining first conductivity type doped layers, with adjacent first conductivity type doped layers separated by a portion of a drift region.

[0016] In one embodiment, the top surface of the first conductivity type doped layer of the top layer is in direct contact with the bottom surface of the field oxide layer.

[0017] In one embodiment, the semiconductor device is a lateral device.

[0018] In one embodiment, the lateral device is a silicon-on-insulator lateral device, comprising a substrate and an insulating buried layer on the substrate.

[0019] In one embodiment, the substrate is a silicon substrate, and the insulating buried layer is made of silicon oxide.

[0020] In one embodiment, the lateral device is a laterally diffused metal-oxide-semiconductor field-effect transistor, and the lateral device further includes a first conductivity type well region and a second conductivity type well region, the drain region is located in the first conductivity type well region, and the source region is located in the second conductivity type well region; the first conductivity type and the second conductivity type are opposite conductivity types.

[0021] In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

[0022] In one embodiment, the isolation structure is made of silicon oxide, and the bottom of the isolation structure extends to the insulating buried layer of the silicon lateral device on the insulator. Attached Figure Description

[0023] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0024] Figure 1 This is a schematic diagram of the structure of a semiconductor device in one embodiment of this application.

[0025] Figure 2 This is an equivalent circuit diagram of the resistive field plate 140 in one embodiment of this application.

[0026] Figure 3 This is a layout of the resistive field plate 140 in one embodiment of this application.

[0027] Figure 4 This is a layout of a resistive field plate doped to form a series diode in one embodiment of this application.

[0028] Figure 5 This is a layout of a resistive field plate doped to form a series diode in another embodiment of this application.

[0029] Figure 6 This is a schematic diagram of the structure of a semiconductor device in another embodiment of this application. Detailed Implementation

[0030] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0032] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0033] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0035] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0036] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0037] The materials of resistive field plates are usually semi-insulating polycrystalline silicon or high-resistivity polycrystalline silicon. The leakage problem of resistive field plates using high-resistivity polycrystalline silicon is more serious than that of semi-insulating polycrystalline silicon.

[0038] This application proposes a semiconductor device that can improve the leakage current problem of resistive field plates. Figure 1 This is a schematic diagram of a semiconductor device structure according to an embodiment of this application, including a source region 134, a drain region 132, a gate 138, a field oxide layer 150, and a resistive field plate 140. The drain region 132 and the source region 134 have the same conductivity type (meaning both are N-type or both are P-type). The field oxide layer 150 is located between the source region 134 and the drain region 132. The gate 138 is located above the region between the source region 134 and the drain region 132, and extends from the edge of the source region 134 onto the field oxide layer 150. The resistive field plate 140 is located on the field oxide layer 150. The resistive field plate 140 has multiple series diodes formed thereon. These series diodes are obtained through N-type doping, or through P-type doping, or through a combination of N-type and P-type doping. A portion of these series diodes have opposite conduction directions to the other portions. Figure 2 This is an equivalent circuit diagram of a resistive field plate 140 in one embodiment of this application. The drain side of the resistive field plate 140 is electrically connected to the drain region 132, and the gate side is electrically connected to the gate 138.

[0039] In the aforementioned semiconductor device, the resistive field plate 140 is formed with multiple series diodes through N-type doping and / or P-type doping, and some of these series diodes have opposite conduction directions to the others. Thus, when there is a potential difference between the gate and drain of the device, some of the diodes will be reverse biased, thereby isolating leakage current.

[0040] Figure 3 This is a layout (photolithography layout) of a resistive field plate 140 in one embodiment of this application, which does not show the doping forming the series diodes. Figure 3 In the illustrated embodiment, the resistive field plate 140 includes an outer ring 342 and a spiral portion 344 located inside the outer ring 342. The spiral portion 344 is connected to the outer ring 342, and the ring width of the outer ring 342 is greater than the strip width of the spiral portion 344. Figure 4 This is a layout of a resistive field plate doped to form a series diode in one embodiment of this application. Figure 4 Layout of a medium resistive field plate and Figure 3 same. Figure 5 This is a layout of a resistive field plate doped to form a series diode, according to another embodiment of this application. Figure 5 Layout of a medium resistive field plate and Figure 3 Same. Figure 5In the embodiment shown, the doping of the resistive field plate and the doping of the drain region 132 and the source region 134 are lithographically patterned using the same photomask to save photomasks. Therefore, in the spiral section 344 ( Figure 5 The innermost part (not marked in the text) and the outermost ring 342 ( Figure 5 The outer side of the region (not shown in the text) is also provided with doped regions, corresponding to the doping of the drain region 132 and the doping of the source region 134, respectively.

[0041] In one embodiment of this application, the semiconductor device further includes a drift region 110 located at least partially between the source region 134 and the drain region 132. The conductivity type of the drift region 110 is the same as that of the source region 134 and the drain region 132.

[0042] In one embodiment of this application, the semiconductor device further includes a second conductivity type buried region 112 and a top doping layer 120. The second conductivity type buried region 112 is located in a drift region 110 between a source region 134 and a drain region 132. The top doping layer 120 includes at least one first conductivity type doped layer. Figure 1 In the illustrated embodiment, the first conductivity type is N-type and the second conductivity type is P-type. Therefore, the second conductivity type buried region 112 is a P-bury region within the N-type drift region (drift region 110), and the top doping 120 is an N-top. The top doping 120 includes two first conductivity type doped layers (N-type layer 122 and N-type layer 124). The doping concentration of the first conductivity type doped layers is greater than the doping concentration of the drift region 110. In other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type.

[0043] In one embodiment of this application, the top doping 120 includes at least two first conductivity type doped layers with different junction depths, i.e., one first conductivity type doped layer is disposed above another first conductivity type doped layer, and these first conductivity type doped layers are arranged from top to bottom in the drift region 110 on the second conductivity type buried region 112. The top first conductivity type doped layer in the top doping 120 (e.g., Figure 1 The doping concentration of the N-type layer 122 is greater than that of the other first conductivity type doped layers (e.g., ...). Figure 1 The doping concentration of the N-type layer 124 in the middle is such that adjacent first conductivity type doped layers are separated by a portion of the drift region 110. Figure 1 In the illustrated embodiment, the top surface of the first conductivity type doped layer (N-type layer 122) in the top doping layer 120 is in direct contact with the bottom surface of the field oxide layer 150.

[0044] exist Figure 1In the illustrated embodiment, the drain side of the resistive field plate 140 is electrically connected to the drain region 132 via a metal layer 160. Specifically, the semiconductor device further includes an interlayer dielectric (ILD) layer covering the source region 134, drain region 132, field oxide layer 140, gate 138, and resistive field plate 140. Figure 1 (Not shown in the image). The metal layer 160 is located on the interlayer dielectric layer. The metal layer 160 is electrically connected to the resistive field plate 140 through the conductive material in the contact hole (the contact hole penetrates the interlayer dielectric layer) above the resistive field plate 140, and is electrically connected to the drain region 132 through the conductive material in the contact hole above the drain region 132.

[0045] exist Figure 1 In the illustrated embodiment, the semiconductor device is a silicon-on-insulator (SOI) device. The device includes a substrate 10 and a buried insulating layer 20 on the substrate 10. A drift region 110 is located on the buried insulating layer 20. Figure 1 In the illustrated embodiment, substrate 10 is a P-type silicon substrate, and the insulating buried layer 20 is made of silicon oxide, such as silicon dioxide. Further, Figure 1 The semiconductor device shown is an LDMOSFET.

[0046] In one embodiment of this application, the gate 138 is made of polysilicon. In other embodiments, metals, metal nitrides, metal silicides, or similar compounds may also be used as the material of the gate 138.

[0047] In one embodiment of this application, a gate dielectric layer is further provided below the gate 138. Figure 1 (Not shown). The gate dielectric layer may comprise conventional dielectric materials such as silicon oxides, nitrides, and oxynitrides having a dielectric constant from about 4 to about 20 (measured in vacuum), or the gate dielectric layer may comprise a dielectric material with a generally higher dielectric constant having a dielectric constant from about 20 to at least about 100. Such a higher dielectric constant dielectric material may include, but is not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).

[0048] exist Figure 1In the illustrated embodiment, the semiconductor device further includes a first conductivity type well region 114 and a second conductivity type well region 116. A drain region 132 is located in the first conductivity type well region 114, and a source region 134 is located in the second conductivity type well region 116. A drift region 110 is at least partially located between the first conductivity type well region 114 and the second conductivity type well region 116. A second conductivity type buried region 112 is located between the first conductivity type well region 114 and the second conductivity type well region 116. The doping concentration of the source region 134 and the drain region 132 is greater than the doping concentration of the first conductivity type well region 114. In one embodiment of this application, the doping concentration of the first conductivity type well region 114 is greater than the doping concentration of the drift region 110. Figure 1 In the embodiment shown, source region 134 and drain region 132 are N+ regions.

[0049] exist Figure 1 In the illustrated embodiment, the semiconductor device further includes a body lead-out region 136 located in the second conductivity type well region 116. The doping concentration of the body lead-out region 136 is greater than the doping concentration of the second conductivity type well region 116. Figure 1 In the embodiment shown, the body lead-out region 136 is a P+ region.

[0050] exist Figure 1 In the illustrated embodiment, the resistive field plate 140 is made of high-resistivity polycrystalline silicon. In another embodiment, the resistive field plate 140 may also be made of semi-insulating polycrystalline silicon.

[0051] Figure 1 The semiconductor device of the illustrated embodiment exhibits good leakage current isolation performance of its resistive field plate 140 in ultra-high voltage semiconductor devices with operating voltages above 500V, and also in semiconductor devices with long drift regions. However, for semiconductor devices with lower operating voltages (e.g., 300V) and shorter drift regions, this application proposes a further improved semiconductor device structure that isolates leakage current by connecting a medium-to-low voltage diode in series between the gate and drain.

[0052] Figure 6 This is a schematic diagram of the structure of a semiconductor device in another embodiment of this application. Figure 6In the illustrated embodiment, the semiconductor device further includes an isolation structure 152, a diode region, and a metal layer 160. The diode region includes an N-type doped region 172 and a P-type doped region 174, which form the target diode. The isolation structure 152 is located between the drift region 110 and the diode region, providing electrical isolation between the drift region 110 and the diode region. The metal layer 160 is located above the N-type doped region 172 and the gate 138, which are electrically connected through the metal layer 160. The gate lead 166 above the P-type doped region 174 is electrically connected to the P-type doped region 174, thereby connecting the gate lead 166 and the gate 138 through the target diode. When an operating voltage is applied to the gate lead 166, the target diode is forward-biased. When a high voltage is applied to the drain, if the resistive field plate 140 cannot completely isolate the leakage current, the target diode can further isolate the leakage current.

[0053] In one embodiment of this application, the isolation structure 152 is made of silicon oxide. The bottom of the isolation structure 152 extends to the buried insulating layer 20, and the top extends to the top of the top silicon on the buried insulating layer 20, thereby laterally isolating the current between the drift region 110 and the diode region.

[0054] exist Figure 6 In the illustrated embodiment, the semiconductor device further includes an interlayer dielectric layer covering the source region 134, drain region 132, diode region, isolation structure 152, field oxide layer 150, gate 138, and resistive field plate 140. Figure 6 (Not shown in the image). Metal layer 160 includes a first metal interconnect 162, which is electrically connected to the N-type doped region 172 via a conductive material in a contact hole (the contact hole penetrates the interlayer dielectric layer) above the N-type doped region 172, and electrically connected to the gate 138 via a conductive material in a contact hole above the gate 138. Gate lead-out 166 is electrically connected to the P-type doped region 174 via a conductive material in a contact hole above the P-type doped region 174. In one embodiment of this application, gate lead-out 166 is also part of metal layer 160.

[0055] exist Figure 6 In the illustrated embodiment, the semiconductor device metal layer 160 further includes a second metal interconnect 164. The second metal interconnect 164 is electrically connected to the resistive field plate 140 through a conductive material in a contact hole above the resistive field plate 140, and is electrically connected to the drain region 132 through a conductive material in a contact hole above the drain region 132.

[0056] exist Figure 6In the illustrated embodiment, the diode region further includes an N-type region 171 and a P-well 173. An N-type doped region 172 is located within the N-type region 171, and the doping concentration of the N-type doped region 172 is greater than that of the N-type region 171. A P-type doped region 174 is located within the P-well 173, and the doping concentration of the P-type doped region 174 is greater than that of the P-well 173. In one embodiment of this application, the P-well 173 is located within the N-type region 171.

[0057] In one embodiment of this application, the drift region 110 and the N-type region 171 are part of the N-type epitaxial layer on the insulating buried layer 20.

[0058] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0059] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0060] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Source region; Drain region, wherein the drain region has the same conductivity type as the source region; A field oxygen layer is located between the source region and the drain region; A gate is located between the source region and the drain region, and extends from the edge of the source region to the field oxide layer; A resistive field plate is located on the field oxide layer. The resistive field plate is formed with a plurality of series diodes obtained by N-type doping and / or P-type doping, and some of these series diodes have opposite conduction directions to the others. The resistive field plate is electrically connected to the drain region and the gate, respectively.

2. The semiconductor device according to claim 1, characterized in that, Also includes: The drift region is at least partially located between the source region and the drain region; The diode region includes an N-type doped region and a P-type doped region, wherein the N-type doped region and the P-type doped region form the target diode; An isolation structure is located between the drift region and the diode region for electrical isolation between the drift region and the diode region; A metal layer is located above the N-type doped region and above the gate, and the N-type doped region and the gate are electrically connected through the metal layer; The gate is led out and electrically connected to the P-type doped region; the gate lead out and the gate are connected through the target diode.

3. The semiconductor device according to claim 2, characterized in that, Also includes: An interlayer dielectric layer covers the source region, drain region, diode region, isolation structure, field oxide layer, gate, and resistive field plate; The metal layer is located on the interlayer dielectric layer. The metal layer includes a first metal interconnect. The first metal interconnect is electrically connected to the N-type doped region through a conductive material in a contact hole above the N-type doped region, and is electrically connected to the gate through a conductive material in a contact hole above the gate. The gate is led out and electrically connected to the P-type doped region through a conductive material in a contact hole above the P-type doped region.

4. The semiconductor device according to claim 3, characterized in that, The metal layer includes a second metal interconnect, which is electrically connected to the resistive field plate through a conductive material in a contact hole above the resistive field plate, and electrically connected to the drain region through a conductive material in a contact hole above the drain region.

5. The semiconductor device according to claim 2, characterized in that, The diode region also includes: The N-type region is located within the N-type region, and the doping concentration of the N-type doped region is greater than that of the N-type region. The P-well has a P-type doped region located within it, and the doping concentration of the P-type doped region is greater than the doping concentration of the P-well.

6. The semiconductor device according to claim 1, characterized in that, The resistive field plate is made of high-resistivity polycrystalline silicon or semi-insulating polycrystalline silicon.

7. The semiconductor device according to claim 1, characterized in that, The resistive field plate includes an outer ring and a spiral portion located inside the outer ring. The spiral portion is connected to the outer ring, and the ring width of the outer ring is greater than the strip width of the spiral portion.

8. The semiconductor device according to claim 1, characterized in that, The resistive field plate is doped using the same photomask as the source and drain regions.

9. The semiconductor device according to claim 1, characterized in that, The semiconductor device is a lateral device.

10. The semiconductor device according to claim 9, characterized in that, The lateral device is a silicon-on-insulator lateral device; and / or The lateral device is a laterally diffused metal-oxide-semiconductor field-effect transistor. The lateral device further includes a first conductivity type well region and a second conductivity type well region. The drain region is located in the first conductivity type well region, and the source region is located in the second conductivity type well region. The first conductivity type and the second conductivity type are opposite conductivity types.

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