Lateral device

Abstract

The invention relates to a lateral device comprising: a source region having a first conductivity type; a drain region having the first conductivity type; the drift region is of the first conduction type, and at least part of the drift region is located between the source region and the drain region; a second conductivity type buried region located in the drift region between the source region and the drain region; the field oxide layer is located on the drift region; the top doping is located in the drift region above the second conduction type buried region and below the field oxide layer and comprises at least one first conduction type doping layer, and the doping concentration of the first conduction type doping layer is larger than that of the drift region; and the field plate is located on the field oxide layer. According to the invention, the field plate is utilized to assist in depleting the first conductive type doping layer above the second conductive type buried region, so that the first conductive type doping layer can adopt higher doping concentration, and the on-resistance of the device is further reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a lateral device. Background Technology

[0002] As a core device in BCD (Bipolar-CMOS-DMOS) technology, alleviating the contradiction between specific on-resistance and breakdown voltage in high-voltage LDMOS (Laterally Diffused Metal-Oxide-Semiconductor Field-Effect Transistor) has always been a major way to save chip costs. The development of RESURF (Reduced Surface Electric Field) technology, D (Dual)-RESURF and T (Triple)-RESURF technology has continuously reduced the specific on-resistance of the device.

[0003] The industry hopes for the emergence of RESURF structures that can further improve voltage withstand and reduce on-resistance. Summary of the Invention

[0004] Therefore, it is necessary to provide a lateral device that can further reduce on-resistance.

[0005] A lateral device includes: a source region having a first conductivity type; a drain region having a first conductivity type; a drift region having a first conductivity type and at least partially located between the source region and the drain region; a second conductivity type buried region located in the drift region between the source region and the drain region; the first conductivity type and the second conductivity type are opposite conductivity types; a field oxide layer located on the drift region; a top doping layer located above the second conductivity type buried region and below the field oxide layer in the drift region, including at least one first conductivity type doped layer, the doping concentration of the first conductivity type doped layer being greater than the doping concentration of the drift region; and a field plate located on the field oxide layer.

[0006] The aforementioned lateral device utilizes a field plate to assist in depleting the first conductivity type doped layer above the second conductivity type buried region. Therefore, the first conductivity type doped layer can adopt a higher doping concentration, thereby further reducing the on-resistance of the device.

[0007] In one embodiment, the field plate is used to assist in depleting the top doping.

[0008] In one embodiment, the top doping includes at least two first conductivity type doped layers with different junction depths, and the doping concentration of the top first conductivity type doped layer is greater than the doping concentration of the remaining first conductivity type doped layers, with adjacent first conductivity type doped layers separated by a portion of a drift region.

[0009] In one embodiment, the doping concentration of the first conductivity type doped layer at the top is 1e15-5e17 / cm². 3.

[0010] In one embodiment, the field plate is a floating field plate.

[0011] In one embodiment, the field plate includes an outer ring and a spiral portion located inside the outer ring, the spiral portion being connected to the outer ring, and the ring width of the outer ring being greater than the strip width of the spiral portion.

[0012] In one embodiment, the field plate includes an outer ring, multiple ring structures located inside the outer ring, and multiple strip sections, each strip section being located between two adjacent ring structures, and the ring width of the outer ring is greater than the strip width of each ring structure and the strip width of each strip section.

[0013] In one embodiment, the strips are located on both sides of the long axis of the field plate, while no strips are provided on both sides of the short axis of the field plate.

[0014] In one embodiment, the field plate is a polycrystalline silicon field plate.

[0015] In one embodiment, the field plate is a perforated field plate, with the bottom of the perforated field plate penetrating the field oxide layer downwards. The perforated field plate includes conductive material disposed in a plurality of contact holes. The lateral device further includes a metal interconnect layer located on the perforated field plate. The metal interconnect layer connects at least a portion of the contact holes of the perforated field plate into at least one group, and the conductive material in each group of contact holes is electrically connected together by the metal interconnect layer.

[0016] In one embodiment, the lateral device further includes: a gate disposed above the region between the source region and the drain region, and extending from the edge of the source region to the field oxide layer; an interlayer dielectric layer covering the source region, drain region, gate and field oxide layer; wherein the metal interconnect layer is disposed on the interlayer dielectric layer, and each contact hole of the orifice field plate penetrates the interlayer dielectric layer and extends downward into the field oxide layer.

[0017] In one embodiment, the lateral device is a silicon-on-insulator (SiI) lateral device; the SiI lateral device includes a substrate and an insulating buried layer on the substrate, with the drift region located on the insulating buried layer.

[0018] In one embodiment, the substrate is a silicon substrate, and the insulating buried layer is made of silicon oxide.

[0019] In one embodiment, the lateral device is a laterally diffused metal-oxide-semiconductor field-effect transistor, and the lateral device further includes a first conductivity type well region and a second conductivity type well region, the drain region is disposed in the first conductivity type well region, and the source region is disposed in the second conductivity type well region.

[0020] In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

[0021] In one embodiment, the top surface of the first conductivity type doped layer of the top layer is in direct contact with the bottom surface of the field oxide layer. Attached Figure Description

[0022] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0023] Figure 1 This is a schematic diagram of the structure of the lateral device in one embodiment of this application.

[0024] Figure 2 This is a partial layout of the field plate 140 in one embodiment of this application.

[0025] Figure 3 This is a layout of field plate 140 in another embodiment of this application.

[0026] Figure 4 This is a schematic diagram of the structure of the lateral device in another embodiment of this application.

[0027] Figure 5 This is a top view of the perforated plate 142 in one embodiment of this application. Detailed Implementation

[0028] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0030] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0031] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0032] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0033] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0034] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0035] The Qiao Ming group at the University of Electronic Science and Technology of China proposed a substrate termination and Ntop (i.e., N-type doped region near the top of the drift region) structure based on the T-RESURF structure, which respectively solved the problems of termination voltage and low specific on-resistance of the interdigitated structure. However, although the interdigitated structure avoids high voltage cross-line, the termination area of ​​the source-packet-drain junction is too large and isolation is inconvenient. Conventional Ntop structures are only depleted by Pbury (P-type buried layer), and the doping concentration of Ntop is difficult to increase further, thus limiting the on-resistance. At present, there is no suitable technology for enriching the surface of the drift region except for Ntop. Although surface superjunctions can increase the doping concentration, the requirements for charge balance are too stringent. In special lateral integrated devices, under the conditions of high-energy injection Gaussian distribution and substrate-assisted depletion effect, there is currently no suitable solution to increase the surface concentration of the drift region.

[0036] This application proposes an innovative lateral device with a RESURF structure that utilizes a field plate to assist in the depletion of the Ntop. Figure 1 This is a schematic diagram of the structure of a lateral device in one embodiment of this application, including a source region 134, a drain region 132, a drift region 110, a second conductivity type buried region 112, a top doped region 120, a field oxide layer 150, and a field plate 140. The source region 134, drain region 132, and drift region 110 have a first conductivity type. Figure 1In the illustrated embodiment, the first conductivity type is N-type and the second conductivity type is P-type. Therefore, the second conductivity type buried region 112 is a P-bury region in the N-type drift region (drift region 110), and the top doping 120 is an N-top. In other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type.

[0037] Drift region 110 is at least partially located between source region 134 and drain region 132. A second conductivity type buried region 112 is located within drift region 110 between source region 134 and drain region 132. Field oxide layer 150 is located on drift region 110. Top doping 120 is located above the second conductivity type buried region 112 and below field oxide layer 150 in drift region 110, and top doping 120 includes at least one first conductivity type doped layer. Figure 1 In the illustrated embodiment, the top doping 120 comprises two first conductivity type doped layers (N-type layer 122 and N-type layer 124). The doping concentration of the first conductivity type doped layers is greater than the doping concentration of the drift region 110. A field plate 140 is located on the field oxide layer 150 and is used to assist in the depletion of the top doping 120.

[0038] The aforementioned lateral device utilizes the field plate 140 to assist in depleting the first conductivity type doped layer above the second conductivity type buried region 112. Therefore, the first conductivity type doped layer can adopt a higher doping concentration, thereby further reducing the on-resistance of the device.

[0039] In one embodiment of this application, the top doping 120 includes at least two first conductivity type doped layers with different junction depths, i.e., one first conductivity type doped layer is disposed above another first conductivity type doped layer, and these first conductivity type doped layers are arranged from top to bottom in the drift region 110 on the second conductivity type buried region 112. The top first conductivity type doped layer in the top doping 120 (e.g., Figure 1 The doping concentration of the N-type layer 122 is greater than that of the other first conductivity type doped layers (e.g., ...). Figure 1 The doping concentration of the N-type layer 124 in the middle is such that adjacent first conductivity type doped layers are separated by a portion of the drift region 110. Figure 1 In the illustrated embodiment, the top surface of the first conductivity type doped layer (N-type layer 122) in the top doping layer 120 is in direct contact with the bottom surface of the field oxide layer 150. Figure 1 In the embodiment shown, the doping concentration of the N-type layer 122 is 1e15-5e17 / cm². 3 The implantation dose of N-type ions for forming N-type layer 122 was 0.5e12-3e12 / cm. 2Since this application utilizes the field plate 140 to assist in the depletion of the N-type layer 122, the doping concentration of the N-type layer 122 can be increased by 2-3 times compared to conventional Ntop, thereby enabling the device to achieve a lower on-resistance.

[0040] exist Figure 1 In the illustrated embodiment, the field plate 140 is a floating field plate, i.e., a field plate not connected to the electrodes. In one embodiment of this application, the floating field plate is a floating polycrystalline silicon field plate; in other embodiments, the floating field plate may also be made of other materials.

[0041] Figure 2 This is a partial layout (photolithography layout) of the field plate 140 in one embodiment of this application. Figure 2 In the illustrated embodiment, the field plate 140 includes an outer ring 242, multiple annular structures 244 located inside the outer ring 242, and multiple strip-shaped portions 246, each strip-shaped portion 246 being located between two adjacent annular structures 244. The width of the outer ring 242 is greater than the width of each annular structure 244 and the width of each strip-shaped portion 246. Because... Figure 2 The field plate 140 shown is an axisymmetric figure (symmetrical left and right, and also symmetrical up and down), therefore Figure 2 Its lower structure (which is symmetrical to the upper structure) has been omitted. Figure 2 In the embodiment shown, the strip portion 246 is located on both sides of the long axis of the field plate 140, while the strip portion 246 is not provided on both sides of the short axis of the field plate 140.

[0042] Figure 3 This is a layout of the field plate 140 in another embodiment of this application. Figure 3 In the illustrated embodiment, the field plate 140 includes an outer ring 342 and a spiral portion 344 located inside the outer ring 342. The spiral portion 344 is connected to the outer ring 342, and the ring width of the outer ring 342 is greater than the strip width of the spiral portion 344.

[0043] It should be pointed out that, Figure 2 and Figure 3 Only two structural shapes of the field plate 140 are shown. In other embodiments, the field plate 140 may also take other shapes.

[0044] exist Figure 1 In the illustrated embodiment, the lateral device is a silicon-on-insulator (SOI) device. The device includes a substrate 10 and a buried insulating layer 20 on the substrate 10. A drift region 110 is located on the buried insulating layer 20. Figure 1 In the embodiment shown, the substrate 10 is a P-type silicon substrate, and the insulating buried layer 20 is made of silicon oxide, such as silicon dioxide.

[0045] In one embodiment of this application, the lateral device further includes a gate 138. The gate 138 is disposed above the region between the source region 134 and the drain region 132, and extends from the edge of the source region 134 onto the field oxide layer 150. In one embodiment of this application, the gate 138 is made of polysilicon; in other embodiments, metals, metal nitrides, metal silicides, or similar compounds may also be used as the material of the gate 138. Figure 1 The lateral device shown is an LDMOSFET.

[0046] In one embodiment of this application, the gate 138 and the field plate 140 are formed by depositing polysilicon in the same step, and then photolithography and etching the polysilicon in the same step.

[0047] In one embodiment of this application, a gate dielectric layer is further provided below the gate 138. Figure 1 (Not shown). The gate dielectric layer may comprise conventional dielectric materials such as silicon oxides, nitrides, and oxynitrides having a dielectric constant from about 4 to about 20 (measured in vacuum), or the gate dielectric layer may comprise a dielectric material with a generally higher dielectric constant having a dielectric constant from about 20 to at least about 100. Such a higher dielectric constant dielectric material may include, but is not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).

[0048] Figure 4 This is a schematic diagram of the structure of a lateral device in another embodiment of this application, which also includes a source region 134, a drain region 132, a drift region 110, a second conductivity type buried region 112, a top doped layer 120 (including an N-type layer 122 and an N-type layer 124), and a field oxide layer 150. The source region 134, drain region 132, and drift region 110 have a first conductivity type. The drift region 110 is at least partially located between the source region 134 and the drain region 132. The second conductivity type buried region 112 is located in the drift region 110 between the source region 134 and the drain region 132. The field oxide layer 150 is located on the drift region 110. The top doped layer 120 is located in the drift region 110 above the second conductivity type buried region 112 and below the field oxide layer 150, and includes at least one first conductivity type doped layer. Figure 4 In the illustrated embodiment, the top doping 120 comprises two first conductivity type doped layers (N-type layer 122 and N-type layer 124). The doping concentration of the first conductivity type doped layers is greater than the doping concentration of the drift region 110. A field plate 140 is located on the field oxide layer 150 and is used to assist in the depletion of the top doping 120.

[0049] and Figure 1 The field plate shown is different from 140. Figure 4The field plate in the illustrated embodiment is a perforated field plate 142. A field oxide layer 150 extends downwards from the bottom of the perforated field plate 142, and the perforated field plate 142 includes conductive material disposed in a plurality of contact holes. The lateral device also includes a metal interconnect layer 160 located on the perforated field plate 142. The metal interconnect layer 160 connects at least a portion of the contact holes of the perforated field plate 142 into one or more groups, and the conductive material in each group of contact holes is electrically connected together by the metal interconnect layer 160. For example, the contact holes are connected in alternate rows, with odd-numbered rows of contact holes connected to the metal interconnect layer 160 (even-numbered rows of contact holes not connected to the metal interconnect layer 160), or even-numbered rows of contact holes connected to the metal interconnect layer 160 (odd-numbered rows of contact holes not connected to the metal interconnect layer 160). In one embodiment of this application, the conductive material used in the perforated field plate 142 can be a metal or an alloy; in other embodiments, the perforated field plate 142 can also use other conductive materials.

[0050] exist Figure 4 In the illustrated embodiment, the lateral device further includes an interlayer dielectric layer 154. The interlayer dielectric layer 154 covers the source region 134, drain region 132, gate 138, and field oxide layer 150. A metal interconnect layer 160 is disposed on the interlayer dielectric layer 154, and each contact hole of the aperture field plate 142 penetrates the interlayer dielectric layer 154 and extends downward into the field oxide layer 150.

[0051] Figure 5 This is a top view of the perforated plate 142 in one embodiment of this application. The position of the perforated plate 142 is shown for clarity. Figure 5 The metal interconnect layer 160 was made transparent. It should be noted that... Figure 5 Only one distribution structure of the perforated plate 142 is shown. In other embodiments, the perforated plate 142 may also be constructed in other shapes.

[0052] exist Figure 4 In the illustrated embodiment, the lateral device further includes an etch stop layer 152 located between the field oxide layer 150 and the N-type layer 122, which serves as an etch stop layer when forming contact holes for the aperture field plate 142 in the interlayer dielectric layer 154. The etch stop layer 152 can be made of silicon nitride or other materials that can serve as an etch stop layer when etching silicon dioxide.

[0053] exist Figure 1 and Figure 4In the illustrated embodiment, the lateral device further includes a first conductivity type well region 114 and a second conductivity type well region 116. A drain region 132 is located in the first conductivity type well region 114, and a source region 134 is located in the second conductivity type well region 116. A drift region 110 is at least partially located between the first conductivity type well region 114 and the second conductivity type well region 116. A second conductivity type buried region 112 is located between the first conductivity type well region 114 and the second conductivity type well region 116. The doping concentration of the source region 134 and the drain region 132 is greater than the doping concentration of the first conductivity type well region 114. In one embodiment of this application, the doping concentration of the first conductivity type well region 114 is greater than the doping concentration of the drift region 110. Figure 1 and Figure 4 In the embodiment shown, source region 134 and drain region 132 are N+ regions.

[0054] exist Figure 1 and Figure 4 In the illustrated embodiment, the lateral device further includes a body lead-out region 136 located in the second conductivity type well region 116. The doping concentration of the body lead-out region 136 is greater than the doping concentration of the second conductivity type well region 116. Figure 1 and Figure 4 In the embodiment shown, the body lead-out region 136 is a P+ region.

[0055] exist Figure 4 In the embodiment shown, the lateral device is further provided with a through-layer dielectric layer 154, and the source region 134, drain region 132, gate 138 and body lead-out region 136 are electrically connected to the contact holes of the metal interconnect layer 160.

[0056] Based on all the above embodiments, this application has an additional field plate resurfacing effect compared to conventional P-bury auxiliary depletion. The first conductivity type doped layer (N-type layer 122) in the top doped layer 120 can achieve a doping concentration 2-3 times higher than that of the conventional Ntop. Furthermore, conventional field plates are only used in high-voltage lateral devices to shield high-voltage cross-lines. This application is the first to utilize a field plate to assist the depletion surface Ntop, which significantly improves the implantation dose and doping concentration of Ntop.

[0057] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0058] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0059] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A lateral device, characterized in that, include: The source region has the first type of conductivity. The drain region has the first conductivity type; The drift region has a first conductivity type and is at least partially located between the source region and the drain region; The second conductivity type buried region is located in the drift region between the source region and the drain region; The first conductivity type and the second conductivity type are opposite conductivity types; An oxygen layer is located on the drift region; The top doping, located above the second conductivity type buried region and below the field oxygen layer in the drift region, includes at least one first conductivity type doped layer, wherein the doping concentration of the first conductivity type doped layer is greater than the doping concentration of the drift region; The field plate is located on the field oxygen layer.

2. The lateral device according to claim 1, characterized in that, The field plate is used to assist in depleting the top doping.

3. The lateral device according to claim 1 or 2, characterized in that, The top doping includes at least two first conductivity type doped layers with different junction depths, and the doping concentration of the top first conductivity type doped layer is greater than the doping concentration of the other first conductivity type doped layers, with adjacent first conductivity type doped layers separated by a portion of a drift region.

4. The lateral device according to claim 1 or 2, characterized in that, The field plate is a floating field plate.

5. The lateral device according to claim 4, characterized in that, The field plate includes an outer ring and a spiral portion located inside the outer ring, the spiral portion being connected to the outer ring, and the ring width of the outer ring being greater than the width of the spiral portion; or The field plate includes an outer ring, multiple ring structures located inside the outer ring, and multiple strip sections. Each strip section is located between two adjacent ring structures. The ring width of the outer ring is greater than the strip width of each ring structure and the strip width of each strip section.

6. The lateral device according to claim 4, characterized in that, The field plate is a polycrystalline silicon field plate.

7. The lateral device according to claim 1 or 2, characterized in that, The field plate is a perforated field plate, with the bottom of the perforated field plate penetrating the field oxide layer downwards. The perforated field plate includes conductive material disposed in a plurality of contact holes. The lateral device also includes a metal interconnect layer located on the perforated field plate. The metal interconnect layer connects at least a portion of the contact holes of the perforated field plate into at least one group, and the conductive material in each group of contact holes is electrically connected together by the metal interconnect layer.

8. The lateral device according to claim 7, characterized in that, Also includes: A gate is disposed above the region between the source region and the drain region, and extends from the edge of the source region to the field oxide layer; An interlayer dielectric layer covers the source region, drain region, gate, and field oxide layer; The metal interconnect layer is disposed on the interlayer dielectric layer, and each contact hole of the orifice plate penetrates the interlayer dielectric layer and extends downward into the field oxygen layer.

9. The lateral device according to claim 1 or 2, characterized in that, The lateral device is a silicon-on-insulator lateral device; and / or The lateral device is a laterally diffused metal-oxide-semiconductor field-effect transistor. The lateral device further includes a first conductivity type well region and a second conductivity type well region. The drain region is located in the first conductivity type well region, and the source region is located in the second conductivity type well region.

10. The lateral device according to claim 1 or 2, characterized in that, The first conductivity type is N-type, and the second conductivity type is P-type.

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