Semiconductor device

Abstract

Embodiments of the invention generally relate to a semiconductor device. According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a semiconductor layer, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third electrode, and a third semiconductor region of the first conductivity type. The semiconductor layer is arranged between the first electrode and the second electrode. The first semiconductor region is arranged in the semiconductor layer. The second semiconductor region is over the first semiconductor region. The third electrode is provided in the second semiconductor region via the first insulating region. The third semiconductor region is located between the second semiconductor region and the second electrode. The semiconductor layer includes a first portion in which the third electrode extends in the second direction with a first width and a second portion in which the third electrode is configured with a second width larger than the first width, and a length of the second portion in the second direction is smaller than that of the first portion.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2024-157683 (filed on September 11, 2024). This application incorporates all contents of the basic application by reference to that basic application. Technical Field

[0003] The embodiments of the present invention generally relate to a semiconductor device. Background Technology

[0004] In semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), low on-resistance is desirable. However, attempts to reduce on-resistance, such as by minimizing cell spacing or shortening channel length, can lead to increased cross-conductance and a narrowing of the Safe Operating Area (SOA). In other words, there is a trade-off between on-resistance and the safe operating area. Summary of the Invention

[0005] The semiconductor device of the embodiment includes a first electrode, a second electrode, a semiconductor layer, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third electrode, and a third semiconductor region of the first conductivity type. The semiconductor layer is disposed between the first electrode and the second electrode. The first semiconductor region is disposed within the semiconductor layer and located above the first electrode. The second semiconductor region is disposed within the semiconductor layer and located above the first semiconductor region. The third electrode is disposed within the second semiconductor region via a first insulating region and extends along a second direction orthogonal to a first direction from the first electrode toward the second electrode. The third semiconductor region is disposed within the semiconductor layer and located between the second semiconductor region and the second electrode. The semiconductor layer includes a first portion of the third electrode extending along the second direction with a first width and a second portion of the third electrode formed by a second width greater than the first width. The length of the second portion in the second direction is smaller than the length of the first portion in the second direction.

[0006] According to this embodiment, a semiconductor device capable of improving the trade-off between on-resistance and safe operating region can be provided. Attached Figure Description

[0007] Figure 1 This is a top view of the semiconductor device according to the embodiment.

[0008] Figure 2AThis is a cross-sectional view of the typical width portion of the gate in a semiconductor device according to an embodiment.

[0009] Figure 2B This is a cross-sectional view of the gate width portion in the semiconductor device according to the embodiment.

[0010] Figure 3 It is a graph showing the simulation results of the relationship between the mesa width and the threshold voltage in the semiconductor device of the embodiment.

[0011] Figure 4 This is a cross-sectional view of the gate's typical width portion and the gate's width portion, which is an example of a manufacturing process of a semiconductor device used to illustrate an embodiment.

[0012] Figure 5 It continues Figure 4 A cross-sectional view of the gate's typical width portion and the gate's width portion, used to illustrate an example of the manufacturing process of a semiconductor device for implementing an embodiment.

[0013] Figure 6A It continues Figure 5 A cross-sectional view of the gate, typically the width portion, of an example of a manufacturing process of a semiconductor device used to illustrate an embodiment.

[0014] Figure 6B It continues Figure 5 A cross-sectional view of the gate width portion of an example of a manufacturing process of a semiconductor device used to illustrate an embodiment.

[0015] Figure 7A It continues Figure 6A A cross-sectional view of the gate, typically the width portion, of an example of a manufacturing process of a semiconductor device used to illustrate an embodiment.

[0016] Figure 7B It continues Figure 6B A cross-sectional view of the gate width portion of an example of a manufacturing process of a semiconductor device used to illustrate an embodiment.

[0017] Figure 8A It continues Figure 7A A cross-sectional view of the gate, typically the width portion, of an example of a manufacturing process of a semiconductor device used to illustrate an embodiment.

[0018] Figure 8B It continues Figure 7B A cross-sectional view of the gate width portion of an example of a manufacturing process of a semiconductor device used to illustrate an embodiment.

[0019] Figure 9A It continues Figure 8AA cross-sectional view of the gate, typically the width portion, of an example of a manufacturing process of a semiconductor device used to illustrate an embodiment.

[0020] Figure 9B It continues Figure 8B A cross-sectional view of the gate width portion of an example of a manufacturing process of a semiconductor device used to illustrate an embodiment.

[0021] Figure 10 This is a top view of the semiconductor device in Modified Example 1.

[0022] Figure 11 This is a top view of the semiconductor device in Variation Example 2. Detailed Implementation

[0023] The embodiments of the present invention will now be described with reference to the accompanying drawings. These embodiments do not limit the scope of the invention. The drawings are schematic or conceptual, and the proportions of the parts are not necessarily identical to reality. In the specification and drawings, elements identical to those described in existing drawings are labeled with the same reference numerals, and detailed descriptions are appropriately omitted.

[0024] Additionally, for ease of explanation, such as Figure 1 As shown, an XYZ orthogonal coordinate system is used. The Z-axis direction is the stacking direction (thickness direction) of the semiconductor device. Additionally, the source electrode side in the Z-axis direction is referred to as "upper," and the drain electrode side as "lower." However, this expression is used for convenience and is independent of the direction of gravity. The Z-axis direction is the first direction in the claims. The Y-axis direction is the second direction in the claims. The X-axis direction is the third direction in the claims.

[0025] Additionally, in the following explanation, to indicate the relative levels of impurity concentration in each conductivity type, n is sometimes used. + n, n － and p + p, p － The marker. That is, n + This indicates that the impurity concentration of type n is relatively high compared to type n. － This indicates that the impurity concentration of the n-type is relatively low compared to the n-type. Additionally, p... + This indicates that the impurity concentration of p-type is relatively high compared to p-type. － This indicates that the concentration of p-type impurities is relatively low compared to p-type impurities. When these markings include both p-type and n-type impurities in their respective regions, they indicate the relative relative levels of net impurity concentration after these impurities compensate for each other. n-type, n... + type and n － The p-type is an example of the first conductivity type in the claims. + Type and p－ The n-type is an example of the second conductivity type in the claims. Furthermore, in the following description, the n-type and p-type can be reversed. That is, the first conductivity type can be p-type.

[0026] Furthermore, the impurity concentration in the semiconductor region can be measured, for example, by Secondary Ion Mass Spectrometry (SIMS). Additionally, the relative level of impurity concentration can also be determined, for example, by the level of carrier concentration obtained through Scanning Capacitance Microscopy (SCM).

[0027] In addition, dimensions such as the width of semiconductor regions can also be determined by analyzing the surface and / or cross-section using instruments such as Transmission Electron Microscope (TEM), Energy Dispersive X-ray spectroscopy (EDX), and Scanning Electron Microscope (SEM).

[0028] Furthermore, the terms used in this specification, such as “same,” “identical,” “equal,” etc., regarding the determination of shape, geometry, and physical properties and their degree, as well as the values ​​of dimensions and physical properties, are not strictly limited in meaning, but are interpreted in the general sense to include the range of degrees to which the same function can be expected.

[0029] Reference Figure 1 , Figure 2A as well as Figure 2B The semiconductor device 1 of the embodiment will be described. Figure 1 This is a top view of the semiconductor device 1 according to the embodiment, and is Figure 2A as well as Figure 2B A top view of position I at height. Figure 2A This is a cross-sectional view of the gate's typically wide portion 3 in the semiconductor device 1 of the embodiment, and it is along... Figure 1 A cross-sectional view of line A-A. Figure 2B This is a cross-sectional view of the gate width portion 4 in the semiconductor device 1 of the embodiment, and it is along... Figure 1 A cross-sectional view of the B-B line.

[0030] Semiconductor device 1 is, for example, a vertically oriented MOSFET. More specifically, semiconductor device 1 is a vertically oriented MOSFET having a structure in which the field plate electrode (FP electrode) and the gate electrode are buried in the same trench. Alternatively, semiconductor device 1 may also be a vertically oriented MOSFET having a structure in which the FP electrode and the gate electrode are buried in different trenches. Or, semiconductor device 1 may also be a vertically oriented transistor such as an IGBT (Insulated Gate Bipolar Transistor).

[0031] like Figure 2A as well as Figure 2B As shown, the semiconductor device 1 of this embodiment includes a semiconductor layer 2, a drain electrode 11, a source electrode 12, a gate electrode 13, an FP electrode 14, an insulating region (gate insulating film) 51, an insulating region (interlayer insulating film) 52, an insulating region (FP insulating film) 53, a conductive portion 61, and a conductive portion 62.

[0032] Semiconductor layer 2 is disposed between drain electrode 11 and source electrode 12. Semiconductor layer 2 has a lower surface 2a and an upper surface 2b opposite to the lower surface 2a.

[0033] In addition, such as Figure 1 As shown, semiconductor layer 2 has a gate general width portion 3 and a gate width portion 4. The gate general width portion 3 is the portion of the gate electrode 13 extending along the Y-axis direction with a width (first width) w1. The gate width portion 4 is the portion of the gate electrode 13 formed by a width (second width) w2. Width w2 is larger than width w1. That is, the length of the gate electrode 13 in the X-axis direction in the gate width portion 4 is greater than the length of the gate electrode 13 in the X-axis direction in the gate general width portion 3. The gate general width portion 3 is an example of the first part of the claims. The gate width portion 4 is an example of the second part of the claims. Figure 1 As shown, the gate width portion 3 and the gate width portion 4 are alternately arranged along the Y-axis direction.

[0034] Furthermore, the length of the gate width portion 4 in the Y-axis direction is smaller than the length of the gate normal width portion 3 in the Y-axis direction. That is, the gate electrode 13 is locally configured to be wide in the gate width portion 4. Additionally, in the gate width portion 4, the gate electrode 13 has a protrusion 13a that protrudes into the base region 23 via the insulating region 51. Furthermore, the ratio of the gate width portion 4 to the gate normal width portion 3 in the Y-axis direction is not limited to... Figure 1 For example, the ratio of the gate width portion 4 to the typical gate width portion 3 in the Y-axis direction can also be greater than... Figure 1 The examples are large, and can also be larger than Figure 1 The example is smaller. Or, the gate width portion 4 can be set to be smaller than... Figure 1 The examples can be made denser, or they can be made sparser.

[0035] like Figure 1 As shown, a plurality of gate electrodes 13 are provided, each extending along the Y-axis direction. That is, the semiconductor device 1 has a so-called stripe structure. In this embodiment, the center of the gate general width portion 3 between adjacent gate electrodes 13 in the Y-axis direction is along the X-axis direction, and the center of the gate width portion 4 between adjacent gate electrodes 13 in the Y-axis direction is along the X-axis direction. That is, a plurality of gate general width portions 3 are continuously provided along the X-axis direction, and a plurality of gate width portions 4 are continuously provided along the X-axis direction.

[0036] Semiconductor layer 2 can be an epitaxial layer, a semiconductor substrate, or a semiconductor substrate with an epitaxial layer disposed thereon. In this embodiment, semiconductor layer 2 is silicon (Si). In this case, arsenic (As), phosphorus (P), or antimony (Sb) is used as an n-type impurity, and boron (B) is used as a p-type impurity. Furthermore, semiconductor layer 2 can also be composed of compound semiconductors such as silicon carbide (SiC) or gallium nitride (GaN).

[0037] like Figure 2A as well as Figure 2B As shown, the semiconductor layer 2 includes, for example, a drift region 21, a drain region 22, a base region 23, a source region 24, and a high-concentration region 25. Details about these regions will be explained later.

[0038] The drain electrode 11 functions as the drain electrode of the MOSFET. The drain electrode 11 is disposed on the lower surface 2a of the semiconductor layer 2. The drain electrode 11 is connected to and electrically connected to the drain region 22. The drain electrode 11 is an example of the first electrode in the claims. The drain electrode 11 is, for example, made of copper (Cu), titanium (Ti), tungsten (W), aluminum (Al), etc.

[0039] The source electrode 12 functions as the source electrode of the MOSFET. The source electrode 12 is disposed on the upper surface 2b of the semiconductor layer 2, separated by an insulating region 52. Figure 2A As shown, the source electrode 12 is electrically connected to the source region 24 and the high-concentration region 25 via a conductive portion 61 in the normal width portion 3 of the gate. Additionally, as... Figure 2B As shown, the source electrode 12 is electrically connected to the source region 24 via the conductive portion 62 in the wide portion 4 of the gate. The source electrode 12 is an example of the second electrode in the claims. The source electrode 12 is made of, for example, copper (Cu), titanium (Ti), tungsten (W), aluminum (Al), etc. In addition, the insulating region 52 contains, for example, silicon oxide or silicon nitride.

[0040] The gate electrode 13 functions as the gate electrode of the MOSFET. The gate electrode 13 is disposed within the base region 23, separated by an insulating region 51. The gate electrode 13 is electrically insulated from the semiconductor layer 2 by the insulating region 51. The gate electrode 13 is an example of the third electrode as claimed in the claims. The gate electrode 13 is, for example, made of polysilicon containing p-type or n-type impurities. When a voltage is applied to the gate electrode 13, a channel is formed in the base region 23, and charge carriers flow between the drift region 21 and the source region 24. Thus, the MOSFET becomes in the on state.

[0041] like Figure 2A as well as Figure 2B As shown, in this embodiment, the distance d1 between the gate electrode 13 and the base region 23 along the X-axis in the gate general width portion 3 is equal to the distance d2 between the gate electrode 13 and the base region 23 along the X-axis in the gate width portion 4. Here, distance d1 corresponds to the thickness of the insulating region 51 in the gate general width portion 3, and distance d2 corresponds to the thickness of the insulating region 51 in the gate width portion 4. Alternatively, distance d1 may be different from distance d2.

[0042] The FP electrode 14 is disposed within the gate general width portion 3 and the gate width portion 4 of the semiconductor layer 2, separated by an insulating region 53. The FP electrode 14 is electrically insulated from the semiconductor layer 2 by the insulating region 53, and is electrically connected to the source electrode 12, for example, at the end of the semiconductor layer 2 in the Y-axis direction (not shown). The FP electrode 14 is an example of the fourth electrode in the claims. In this embodiment, the FP electrode 14 is located below the gate electrode 13 and extends along the Y-axis direction. The FP electrode 14 is, for example, made of polysilicon containing p-type or n-type impurities. Alternatively, the FP electrode 14 may be disposed within the semiconductor layer 2 separated by an insulating region different from the insulating region 53. Furthermore, the FP electrode 14 may extend in a direction other than the Y-axis direction (e.g., the X-axis direction).

[0043] like Figure 2A as well as Figure 2B As shown, the FP electrode 14 has a width w3 in the gate normal width portion 3 and a width w4 in the gate width portion 4. In this embodiment, the width w3 and the width w4 are equal. Alternatively, the width w3 may be different from the width w4.

[0044] Insulating regions 51 and 53 are configured to cover the sidewalls of a plurality of trenches disposed on the upper surface 2b of the semiconductor layer 2. Insulating regions 51 and 53 are examples of the first and second insulating regions, respectively, as described in the claims. Insulating regions 51 and 53 respectively comprise, for example, silicon oxide or silicon nitride.

[0045] A conductive portion 61 is disposed in the normal width portion 3 of the gate electrode, penetrating the source region 24 and electrically connecting the source region 24 and the high-concentration region 25 to the source electrode 12. The conductive portion 61 is an example of the first conductive portion described in the claims. The conductive portion 61 may, for example, be made of the same material as the source electrode 12. Alternatively, the conductive portion 61 may be made of a different material than the source electrode 12.

[0046] A conductive portion 62 is disposed on the wide portion 4 of the gate electrode, electrically connecting the source region 24 to the source electrode 12. The lower end of the conductive portion 62 is located slightly above the upper end of the base region 23. In this embodiment, the conductive portion 62 does not penetrate the source region 24. More specifically, in this embodiment, the lower end of the conductive portion 62 is located at the same height as the upper surface 2b of the semiconductor layer 2. The conductive portion 62 is an example of the second conductive portion in the claims. The conductive portion 62 is, for example, made of the same material as the source electrode 12. Alternatively, the conductive portion 62 may be made of a different material than the source electrode 12.

[0047] Next, the various regions within semiconductor layer 2 will be described in detail.

[0048] The drift region 21 functions as the drift region of the MOSFET. The drift region 21 is located within the gate width portion 3 and the gate width portion 4 of the semiconductor layer 2, and is positioned above the drain region 22 (above the drain electrode 11). The drift region 21 is, for example, n... － The n-type semiconductor region. The n-type impurity concentration in drift region 21 is, for example, 1 × 10⁻⁶. 15 cm －3 Above and 2×10 16 cm －3 the following.

[0049] The drain region 22 functions as the drain region of the MOSFET. The drain region 22 is located within the gate width portion 3 and the gate width portion 4 of the semiconductor layer 2, situated above the drain electrode 11, and positioned between the drift region 21 and the drain electrode 11. The drain region 22 is connected to the drain electrode 11, making an ohmic contact with it. The drain region 22 is, for example, n... + The n-type semiconductor region. The n-type impurity concentration in the drain region 22 is, for example, 1 × 10⁻⁶. 18 cm －3 Above and 1×10 21 cm －3 the following.

[0050] Drift region 21 and drain region 22 are examples of the first semiconductor region in the claims. Alternatively, drain region 22 may not be provided. In this case, drift region 21 is directly disposed on drain electrode 11, and drain electrode 11 is electrically connected to drift region 21. Alternatively, drift region 21 may not be provided. In this case, drain region 22 may also be disposed at the location of drift region 21.

[0051] The base region 23 functions as the base region of the MOSFET. The base region 23 is located within the gate width portion 3 and the gate width portion 4 of the semiconductor layer 2, above the drift region 21. Figure 1 As shown, the base region 23 extends along the Y-axis. Figure 2A as well as Figure 2B As shown, the base region 23 has a width w5 in the gate width portion 3 and a width w6 in the gate width portion 4. Widths w5 and w6 are so-called mesa widths. In this embodiment, width w6 is smaller than width w5. Width w6 is, for example, less than 0.1 μm. The base region 23 is, for example, a p-type semiconductor region. The p-type impurity concentration of the base region 23 is, for example, 1 × 10⁻⁶. 16 cm －3 Above 1×10 20 cm －3 Below, base region 23 is an example of a second semiconductor region in the claims.

[0052] The source region 24 functions as the source region of the MOSFET. The source region 24 is located within the gate width portion 3 and the gate width portion 4 of the semiconductor layer 2, between the base region 23 and the source electrode 12. The source region 24 has ohmic contact with the conductive portions 61 and 62. The source region 24 extends along the Y-axis. The source region 24 is, for example, n... + The source region 24 is a type of semiconductor region. The n-type impurity concentration is, for example, 1 × 10⁻⁶. 18 cm －3 Above 1×10 22 cm －3 Below, source region 24 is an example of a third semiconductor region in the claims.

[0053] like Figure 2A As shown, the high-concentration region 25 is disposed within the base region 23 in the gate's normal width portion 3. The high-concentration region 25 is electrically connected to the source electrode 12 via a conductive portion 61. The high-concentration region 25 is, for example, a p-type electrode. + This refers to a p-type semiconductor region. Specifically, the impurity concentration in the high-concentration region 25 is higher than that in the base region 23. The p-type impurity concentration in the high-concentration region 25 is, for example, 1 × 10⁻⁶. 18 cm－3 Above 1×10 21 cm －3 The high-concentration region 25 is an example of the fourth semiconductor region in the claims.

[0054] like Figure 1 As shown, the high-concentration region 25 does not extend into the gate width portion 4. That is, the high-concentration region 25 is not located within the gate width portion 4. In this embodiment, the high-concentration region 25 is not located at the boundary between the normal gate width portion 3 and the gate width portion 4. Furthermore, the high-concentration region 25 is located away from this boundary. Figure 1 In this example, the length l1 of the base region 23 between the high-concentration region 25 and the insulating region 51 in the X-axis direction is equal to the length l2 of the base region 23 between the high-concentration region 25 and the insulating region 51 in the Y-axis direction. Alternatively, the length l1 may be different from the length l2. Furthermore, the high-concentration region 25 may also be located at the boundary between the gate's normal width portion 3 and the gate width portion 4.

[0055] As described above, the semiconductor device 1 of this embodiment includes a drain electrode 11, a source electrode 12, a semiconductor layer 2, a drift region 21 and a drain region 22 of a first conductivity type, a base region 23 of a second conductivity type, a gate electrode 13, and a source region 24 of the first conductivity type. The semiconductor layer 2 is disposed between the drain electrode 11 and the source electrode 12. The drift region 21 and the drain region 22 are disposed within the semiconductor layer 2 and located above the drain electrode 11. The base region 23 is disposed within the semiconductor layer 2 and located above the drift region 21. The gate electrode 13 is disposed within the base region 23 via an insulating region 51 and extends along a Y-axis direction orthogonal to the Z-axis direction from the drain electrode 11 toward the source electrode 12. The source region 24 is disposed within the semiconductor layer 2 and located between the base region 23 and the source electrode 12. The semiconductor layer 2 includes: a gate normal width portion 3 extending along the Y-axis direction with a width w1 of the gate electrode 13; and a gate width portion 4 of the gate electrode 13 consisting of a width w2 that is larger than the width w1. The length of the gate width portion 4 in the Y-axis direction is smaller than the length of the gate normal width portion 3 in the Y-axis direction.

[0056] In this embodiment, the gate electrodes 13 sandwiching the base region 23 are closer to each other in the gate width portion 4 than in the gate normal width portion 3. Therefore, an inversion layer is easily formed in the base region 23 in the gate width portion 4. As a result, the threshold voltage of the gate width portion 4 is smaller than that of the gate normal width portion 3. For example, if a driving voltage is applied to the gate electrode 13, the channel is first turned on in the gate width portion 4 when the voltage is low, while the channel remains off in the gate normal width portion 3. Then, if the voltage increases, the channel is also turned on in the gate normal width portion 3. Thus, the cross-conductance of the semiconductor device 1 is reduced, and a safe operating region can be ensured even when the on-resistance is reduced. For example, even when the cell spacing of the semiconductor device 1 is miniaturized or the channel length is shortened to reduce the on-resistance, a safe operating region can still be ensured. Thus, according to this embodiment, the trade-off between on-resistance and the safe operating region can be improved.

[0057] Furthermore, in this embodiment, the width w6 of the base region 23 in the gate width portion 4 is smaller than the width w5 of the base region 23 in the gate normal width portion 3. As a result, the channel mobility in the base region 23 of the gate width portion 4 is improved, and the on-resistance of the semiconductor device 1 can be reduced compared to the case where the gate width portion 4 is not provided.

[0058] Furthermore, in this embodiment, the gate electrode 13 has a protrusion 13a that protrudes into the base region 23. For example... Figure 1 As shown, in the base region 23 of the gate's typical width portion 3, near the protrusion 13a (gate corner region), the gate electrode 13 approaches from two directions (X-axis direction and Y-axis direction), applying an electric field to the gate from both directions. As a result, an inversion layer is more easily formed in this gate corner region. This further reduces the transconductance of the semiconductor device 1.

[0059] Furthermore, according to this embodiment, by increasing or decreasing the number of protrusions 13a, the on-resistance and mutual conduction of the semiconductor device 1 can be controlled, thereby increasing the design freedom of the semiconductor device 1.

[0060] Furthermore, the semiconductor device 1 of this embodiment also includes a high-concentration region 25 disposed within the base region 23 in the gate normal width portion 3 and electrically connected to the source electrode 12 via a conductive portion 61. On the other hand, the high-concentration region 25 does not extend into the gate width portion 4. As a result, the avalanche tolerance of the semiconductor device 1 can be improved while maintaining the channel mobility in the gate width portion 4.

[0061] Furthermore, in this embodiment, the high-concentration region 25 is disposed away from the boundary between the gate normal width portion 3 and the gate width portion 4. This promotes the formation of an inversion layer near this boundary, further reducing the cross-conductivity of the semiconductor device 1. Alternatively, the high-concentration region 25 may be disposed at the boundary between the gate normal width portion 3 and the gate width portion 4. In this case, the avalanche tolerance of the semiconductor device 1 can be further improved.

[0062] Furthermore, the semiconductor device 1 of this embodiment also includes a conductive portion 62 disposed in the gate width portion 4 for electrically connecting the source region 24 and the source electrode 12. This ensures sufficient contact area with the source region 24 in the gate width portion 4, further reducing the on-resistance of the semiconductor device 1. Additionally, the lower end of the conductive portion 62 is located above the upper end of the base region 23. Therefore, the base region 23 is not eroded by the conductive portion 62 in the gate width portion 4, thus suppressing the rise in the threshold voltage of the gate width portion 4.

[0063] Furthermore, the semiconductor device 1 of this embodiment also includes an FP electrode 14 disposed within the semiconductor layer 2 with an insulating region 53 and electrically connected to the source electrode 12. Thus, in the MOSFET off state, the depletion layer extends from the FP electrode 14 to the surrounding drift region 21 using the voltage applied between the drain electrode 11 and the source electrode 12. This depletion layer is connected to the depletion layer of the adjacent FP electrode 14, thereby improving the withstand voltage of the semiconductor device 1.

[0064] Furthermore, in this embodiment, the width w6 of the base region 23 in the gate width portion 4 can also be 0.1 μm or less. This allows for a further reduction in the threshold voltage of the gate width portion 4. For this purpose, see [reference needed]. Figure 3 A detailed explanation. Figure 3 This is a graph showing the simulation results of the relationship between the mesa width (w6) and the threshold voltage (Vth) in the semiconductor device 1 of the embodiment.

[0065] like Figure 3 As shown, when the width w6 is 0.1 μm or less, the threshold voltage is significantly reduced compared to when the width w6 is larger than 0.1 μm. Therefore, by making the width w6 0.1 μm or less, the threshold voltage of the gate width portion 4 can be significantly reduced. Furthermore, by adjusting the width w6, the threshold voltage of the gate width portion 4 can be controlled, thus increasing the design freedom of the semiconductor device 1.

[0066] <Method for Manufacturing Semiconductor Device 1>

[0067] Next, refer to Figures 4 to 9B An example of a method for manufacturing the semiconductor device 1 according to this embodiment will be described. Figure 4as well as Figure 5 This is a cross-sectional view of the gate general width portion 3 and the gate width portion 4, which is used to illustrate an example of the manufacturing process of the semiconductor device 1 in the embodiment. Figure 6A , Figure 7A , Figure 8A as well as Figure 9A This is a cross-sectional view of the gate's typical width portion 3, which is an example of the manufacturing process of the semiconductor device 1 used to illustrate the implementation method. Figure 6B , Figure 7B , Figure 8B as well as Figure 9B This is a cross-sectional view of the gate width portion 4, which is used to illustrate an example of the manufacturing process of the semiconductor device 1 in the embodiment.

[0068] First, such as Figure 4 As shown, a semiconductor layer having a lower surface 2a and an upper surface 2b opposite to the lower surface 2a is prepared. The semiconductor layer is, for example, an n-type semiconductor substrate. A drift region 21 is provided within the semiconductor layer. In addition, a trench T1 is formed on the upper surface 2b of the semiconductor layer by means of Reactive Ion Etching (RIE) or the like.

[0069] Next, as Figure 5 As shown, an FP electrode 14 and an insulating region 53 are formed within a trench T1. More specifically, firstly, an insulating region covering the inner wall of the trench T1 and the upper surface 2b of the semiconductor layer is formed by thermal oxidation or the like. Then, a conductive material such as polycrystalline silicon is deposited within the insulating region by chemical vapor deposition (CVD) to form the FP electrode 14. Next, the portion of the insulating region above the FP electrode 14 is removed. Then, silicon oxide or the like is deposited on the upper surface of the FP electrode 14 by CVD or the like to form an insulating region 53a (buried film). Furthermore, in the following description, the insulating region 53a is considered as part of the insulating region 53.

[0070] Next, as Figure 6A as well as Figure 6B As shown, in the gate's normal width portion 3, a resist 70 is formed covering the upper surface 2b of the semiconductor layer and filling the trench T1. However, the resist 70 is not formed in the gate width portion 4. Subsequently, the upper sidewall portion of the trench T1 in the semiconductor layer of the gate width portion 4 is removed by chemical dry etching (CDE) or the like. As a result, in the gate width portion 4, the trench T1 is widened, forming a trench T2 that is wider than the trench T1. Then, the resist 70 in the gate's normal width portion 3 is removed.

[0071] Next, as Figure 7A as well as Figure 7BAs shown, a gate electrode 13, a base region 23, and an insulating region 51 are formed. More specifically, firstly, an insulating region is formed by thermal oxidation or the like, covering the sidewalls of the trench T1 in the gate normal width portion 3, the sidewalls of the trench T2 in the gate width portion 4, and the upper surface 2b of the semiconductor layer in both the gate normal width portion 3 and the gate width portion 4. Then, a conductive material such as polysilicon is deposited in the insulating region by CVD or the like to form the gate electrode 13. The width of the gate electrode 13 in the gate width portion 4 is larger than the width of the gate electrode 13 in the gate normal width portion 3. Next, p-type impurities are ion-implanted into the upper surface 2b of the semiconductor layer to form the base region 23. Then, an insulating region 51a is formed on the upper surface of the gate electrode 13. Furthermore, in the following description, the insulating region 51a is considered as part of the insulating region 51. Additionally, the portion of the insulating region formed on the upper surface 2b of the semiconductor layer (the insulating region 51b) is considered as part of the insulating region 52 after the formation of the insulating region 52 described later.

[0072] Next, as Figure 8A as well as Figure 8B As shown, a source region 24 and an insulating region 52 are formed. More specifically, firstly, n-type impurities are implanted into the upper surface 2b of the semiconductor layer to form the source region 24. Then, silicon oxide or the like is deposited on the upper surface 2b of the semiconductor layer by CVD or the like to form the insulating region 52.

[0073] Next, as Figure 9A as well as Figure 9B As shown, a high-concentration region 25, an opening H1, and an opening H2 are formed. More specifically, firstly, using a RIE (Rail Interchange Electrode) or the like, an opening reaching the upper end of the source region 24 is formed in the gate normal width portion 3 and the gate width portion 4. Thus, the upper portion of opening H1 is formed in the gate normal width portion 3, and opening H2 is formed in the gate width portion 4. Next, a resist is formed in the gate width portion 4, covering at least a portion of the upper surface 2b of the semiconductor layer and filling the opening H2. This resist is not formed in the gate normal width portion 3. Then, using a silicon RIE or the like, a trench penetrating the source region 24 and reaching the base region 23 is formed in the gate normal width portion 3. Thus, the lower portion of opening H1 is formed in the gate normal width portion 3. Then, p-type impurities are ion-implanted into the upper surface 2b of the semiconductor layer, forming a high-concentration region 25 at the bottom of opening H1. Finally, the resist formed in the gate width portion 4 is removed.

[0074] Subsequently, although not shown, n-type impurities are ion-implanted into the lower surface 2a of the semiconductor layer to form a drain region 22. Then, conductive portions 61 and 62, as well as a source electrode 12, are formed on the upper surface 2b of the semiconductor layer, and a drain electrode 11 is formed on the lower surface 2a of the conductor layer. Furthermore, conductive portion 61 fills opening H1, and conductive portion 62 fills opening H2.

[0075] Semiconductor device 1 is manufactured through the above processes.

[0076] According to the manufacturing method of this embodiment, the FP electrode 14 can be formed together in the gate normal width portion 3 and the gate width portion 4. In this case, the width w3 of the FP electrode 14 in the gate normal width portion 3 is equal to the width w4 of the FP electrode 14 in the gate width portion 4.

[0077] Furthermore, according to the manufacturing method of this embodiment, the insulating region 51 covering the sidewall of the trench T1 in the gate normal width portion 3 and the insulating region 51 covering the sidewall of the trench T2 in the gate width portion 4 can be formed simultaneously. In this case, the distance d1 between the gate electrode 13 and the base region 23 along the X-axis in the gate normal width portion 3 and the distance d2 between the gate electrode 13 and the base region 23 along the X-axis in the gate width portion 4 are equal.

[0078] Hereinafter, several variations of the above-described embodiments will be described, focusing on the differences between the embodiments. According to the variations described below, the trade-off between the on-resistance and the safe operating range of the semiconductor device can also be improved, similar to the embodiments.

[0079] (Variation Example 1)

[0080] Reference Figure 10 The semiconductor device 1A of the modified example 1 of the embodiment will be described. Figure 10 This is a top view of semiconductor device 1A in Modified Example 1.

[0081] like Figure 10 As shown, in this modified example, a gate width portion 3 and a gate width portion 4 are alternately arranged along the X-axis direction. Figure 10In this example, the gate width portions 4 are arranged in an alternating pattern within the semiconductor layer 2. More specifically, the center of the gate width portion 3 in the Y-axis direction of one gate electrode 13 is aligned with the center of the gate width portion 4 in the Y-axis direction of its adjacent gate electrode 13 along the X-axis direction. In other words, the position of the center of the gate width portion 4 in the Y-axis direction is offset from the adjacent gate electrodes 13 by half the length of the gate width portion 3 in the Y-axis direction. However, this is not a limitation; the position of the center of the gate width portion 4 in the Y-axis direction can also be offset from the adjacent gate electrodes 13 by one-third the length of the gate width portion 3 in the Y-axis direction.

[0082] According to this variation, the gate width portion 4 with a lower threshold voltage is more evenly distributed within the semiconductor device 1A, so that, for example, when a drive voltage is applied to the gate electrode 13, the current that begins to flow through the semiconductor device 1A can be uniformized.

[0083] (Variation Example 2)

[0084] Reference Figure 11 The semiconductor device 1B of the modified embodiment 2 will be described. Figure 11 This is a top view of semiconductor device 1B in Modified Example 2.

[0085] like Figure 11 As shown, in this modified example, the gate electrode 13 replaces the protrusion 13a and has a protrusion 13b. The protrusion 13b has a shape with rounded corners at the front end and the root. According to the manufacturing method of the semiconductor device 1B, the protrusion 13b is sometimes made in this shape.

[0086] According to this variation, the degree of freedom in the manufacturing process of semiconductor device 1B can be increased.

[0087] While several embodiments of the invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention as set forth in the claims and its equivalents.

Claims

1. A semiconductor device, characterized in that, have: First electrode; Second electrode; A semiconductor layer is disposed between the first electrode and the second electrode; A first semiconductor region of a first conductivity type is disposed within the semiconductor layer and located above the first electrode; A second semiconductor region of a second conductivity type is disposed within the semiconductor layer and located above the first semiconductor region; The third electrode is disposed in the second semiconductor region, separated by the first insulating region, and extends along a second direction orthogonal to the first direction from the first electrode toward the second electrode; A third semiconductor region of a first conductivity type is disposed within the semiconductor layer, located between the second semiconductor region and the second electrode. The semiconductor layer includes a first portion of the third electrode extending along the second direction with a first width and a second portion of the third electrode consisting of a second width larger than the first width. The length of the second part in the second direction is smaller than the length of the first part in the second direction.

2. The semiconductor device according to claim 1, characterized in that, In the second part, the third electrode has a protrusion that extends into the second semiconductor region.

3. The semiconductor device according to claim 2, characterized in that, It also includes a fourth electrode, which is disposed within the semiconductor layer through a second insulating region and is electrically connected to the second electrode. The width of the fourth electrode in the first part is equal to the width of the fourth electrode in the second part.

4. The semiconductor device according to claim 2, characterized in that, The width of the second semiconductor region in the second part is smaller than the width of the second semiconductor region in the first part.

5. The semiconductor device according to claim 1, characterized in that, It also includes a fourth semiconductor region, which is disposed within the second semiconductor region in the first portion, electrically connected to the second electrode via a first conductive portion, and has a higher impurity concentration than the second semiconductor region. The fourth semiconductor region does not extend into the second portion.

6. The semiconductor device according to claim 5, characterized in that, It also includes a fourth electrode, which is disposed within the semiconductor layer through a second insulating region and is electrically connected to the second electrode. The width of the fourth electrode in the first part is equal to the width of the fourth electrode in the second part.

7. The semiconductor device according to claim 5, characterized in that, The width of the second semiconductor region in the second part is smaller than the width of the second semiconductor region in the first part.

8. The semiconductor device according to claim 5, characterized in that, The fourth semiconductor region is positioned away from the boundary between the first portion and the second portion.

9. The semiconductor device according to claim 8, characterized in that, It also includes a fourth electrode, which is disposed within the semiconductor layer through a second insulating region and is electrically connected to the second electrode. The width of the fourth electrode in the first part is equal to the width of the fourth electrode in the second part.

10. The semiconductor device according to claim 8, characterized in that, The width of the second semiconductor region in the second part is smaller than the width of the second semiconductor region in the first part.

11. The semiconductor device according to claim 5, characterized in that, It also includes a second conductive portion disposed in the second portion, which is used to electrically connect the third semiconductor region to the second electrode. The lower end of the second conductive portion is located above the upper end of the second semiconductor region.

12. The semiconductor device according to claim 11, characterized in that, It also includes a fourth electrode, which is disposed within the semiconductor layer through a second insulating region and is electrically connected to the second electrode. The width of the fourth electrode in the first part is equal to the width of the fourth electrode in the second part.

13. The semiconductor device according to claim 11, characterized in that, The width of the second semiconductor region in the second part is smaller than the width of the second semiconductor region in the first part.

14. The semiconductor device according to claim 1, characterized in that, It also includes a fourth electrode, which is disposed within the semiconductor layer through a second insulating region and is electrically connected to the second electrode. The width of the fourth electrode in the first part is equal to the width of the fourth electrode in the second part.

15. The semiconductor device according to claim 14, characterized in that, The width of the second semiconductor region in the second part is smaller than the width of the second semiconductor region in the first part.

16. The semiconductor device according to claim 1, characterized in that, The width of the second semiconductor region in the second part is smaller than the width of the second semiconductor region in the first part.

17. The semiconductor device according to claim 16, characterized in that, The width of the second semiconductor region in the second part is less than 0.1 μm.

18. The semiconductor device according to claim 1, characterized in that, The distance between the third electrode in the first part and the second semiconductor region along a third direction orthogonal to the first direction and the second direction is equal to the distance between the third electrode in the second part and the second semiconductor region along the third direction.

19. The semiconductor device according to claim 1, characterized in that, The center of the second portion of the second direction between adjacent third electrodes is along a third direction orthogonal to both the first and second directions.

20. The semiconductor device according to claim 1, characterized in that, The first portion and the second portion are alternately provided along a third direction orthogonal to the first direction and the second direction.

Images