Semiconductor device and preparation method thereof

Abstract

The invention discloses a semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors, the semiconductor device comprises a substrate, an N-type drift layer, a source electrode layer and a grid electrode layer, the substrate is N-type doping, and one side of the substrate is a drain electrode layer; the N-type drift layer is arranged on the other side of the substrate, at least two P-type regions arranged at intervals are arranged in the N-type drift layer, the P-type regions extend in the direction perpendicular to the substrate and make contact with the substrate, and the P-type regions and the N-type drift layer form a transverse NPNPN structure; the source electrode layer is arranged on the side, away from the substrate, of the N-type drift layer; the gate layer is used for controlling opening or closing of a conductive channel from the source layer to the drain layer. According to the invention, the P-type region and the N-type drift layer form a transverse NPNPN structure to realize simultaneous transverse and longitudinal distribution of the space charge region, so that the doping concentration of the drift region is improved and the on-resistance is reduced while the voltage endurance capability is ensured.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] Compared to SiVDMOS devices, SiC VDMOS devices have a wider bandgap and higher breakdown voltage, and are widely used in high breakdown voltage, high temperature and even high power electronic devices.

[0003] However, in some high-voltage applications (such as radar), SiC VDMOS devices cannot simultaneously meet the requirements of high voltage and low on-resistance by relying solely on their wide bandgap characteristics. This is because increasing the voltage usually requires reducing the doping concentration of the N-type drift region or increasing its thickness, which in turn leads to an increase in on-resistance. Therefore, this limits the application of SiC VDMOS devices in devices with high voltage and low on-resistance. Summary of the Invention

[0004] The main objective of this invention is to propose a semiconductor device and its fabrication method, aiming to address the limitations of existing SiCVDMOS devices in applications requiring high voltage withstand capability and low on-resistance.

[0005] To achieve the above objectives, the present invention provides a semiconductor device comprising: The substrate is N-type doped, and one side of the substrate is a drain layer; An N-type drift layer is disposed on the other side of the substrate. The N-type drift layer contains at least two spaced P-type regions that extend in a direction perpendicular to the substrate and are in contact with the substrate. The P-type regions and the N-type drift layer form a transverse NPNPN structure. A source layer, wherein the source layer is disposed on the side of the N-type drift layer opposite to the substrate; and A gate layer, which is used to control the opening or closing of the conductive channel from the source layer to the drain layer.

[0006] In one embodiment of the present invention, the semiconductor device further includes a P-type shielding layer and an insulating dielectric layer; One end of the gate layer is connected to the source layer, and the other end extends toward the N-type drift layer. The insulating dielectric layer is disposed on the outer peripheral surface of the gate layer, and the P-type shielding layer is disposed on the side of the insulating dielectric layer facing the substrate.

[0007] In one embodiment of the present invention, the semiconductor device further includes an N-type region, and two of each of the gate layer, the insulating dielectric layer and the P-type shielding layer are provided, with each of the gate layer, the insulating dielectric layer and the P-type shielding layer being sequentially provided with a P-type region along a direction perpendicular to the substrate; The N-type region includes a first layer and a second layer. The first layer is located between the P-type shielding layer and the P-type region, and the second layer is located between the two P-type shielding layers.

[0008] In one embodiment of the present invention, the semiconductor device further includes an N+ source region, a P-type well region, and a P+ region; The N+ source region and the P-type well region are stacked between the source layer and the N-type drift layer. The N+ source region is connected to the source layer. The P+ region is located outside the N+ source region and the P-type well region and is connected to the source layer. The P+ region, the N+ source region, and the P-type well region form a body diode from the source metal to the N-type drift layer.

[0009] In one embodiment of the present invention, the substrate is a silicon carbide substrate, and the doping concentration of the substrate is 2-8e. 18 cm -3 ; And / or, the doping concentration of the N-type drift layer is 6-10e 16 cm -3 ; And / or, the doping concentration of the P-type region is 1-5e 17 cm -3 ; And / or, the doping concentration of the P-type shielding layer is 1-5e 17 cm -3 ; And / or, the doping concentration of the P-type well region is 1-5e 16 cm -3 ; And / or, the doping concentration of the N-type region is 6-10e1. 7 cm -3 ; And / or, the doping concentration of the N+ source region is 2-8e 18 cm -3 ; And / or, the doping concentration of the P+ region is 1-5e 19 cm -3 .

[0010] In one embodiment of the present invention, the thickness of the substrate is 1.5 μm; And / or, the thickness of the N-type drift layer is 40 μm; And / or, the width of the P-type region is 1 μm and the thickness is 35 μm; And / or, the width of the P-type shielding layer is 1 μm and the thickness is 300 nm; And / or, the width of the P-type well region is 1-2 μm and the thickness is 200 nm; And / or, the thickness of the first layer of the N-type region is 3.7 μm, and the width of the second layer of the N-type region is 2 μm; And / or, the width of the N+ source region is 1 μm and the thickness is 300 nm; And / or, the width of the P+ region is 2μm and the thickness is 1μm.

[0011] The present invention also proposes a method for fabricating a semiconductor device as described in any of the above descriptions, the method comprising the steps of: An N-type drift layer is formed on the substrate; A first barrier layer is formed on the N-type drift layer, and at least two first vias are etched in the first barrier layer to expose the N-type drift layer; Ion implantation is performed on the region of the N-type drift layer exposed to the first via to form a P-type region, which is connected to the substrate; Remove the first blocking layer to form an N-type drift layer covering the P-type region; A second barrier layer is formed on the N-type drift layer, and a second via is formed by etching the second barrier layer; The N-type drift layer is etched to form a gate trench; A gate layer is deposited within the gate trench to form a gate layer; Remove the second barrier layer and form a third barrier layer on the N-type drift layer; A third via is formed by etching the third barrier layer, and the N-type drift layer is etched to form a source trench; A source layer is deposited within the source trench to form a source layer.

[0012] In one embodiment of the present invention, after the step of forming the N-type drift layer covering the P-type region and before the step of forming the second barrier layer on the N-type drift layer, the method further includes: A fourth barrier layer is formed on the N-type drift layer, and a fourth via is etched in the fourth barrier layer; An N-type region is formed by ion implantation in the region of the N-type drift layer exposed to the fourth via, and the N-type region is located on the P-type region; Remove the fourth barrier layer and form a fifth barrier layer on the N-type drift layer, and etch a fifth via in the fifth barrier layer; Ion implantation is performed on the region of the N-type drift layer exposed to the fifth via to form a P-type shielding layer, and the fifth barrier layer is removed.

[0013] In one embodiment of the present invention, after the step of forming the P-type shielding layer and before the step of forming the second barrier layer on the N-type drift layer, the method further includes: A sixth barrier layer is formed on the N-type drift layer, and a sixth via is etched in the sixth barrier layer; Ion implantation is performed on the region of the N-type drift layer exposed to the sixth via to form a P+ region; Remove the sixth barrier layer and form a seventh barrier layer on the N-type drift layer; A seventh through-hole is formed by etching the seventh barrier layer; Ion implantation is performed to form a P-type well region in the area of ​​the N-type drift layer exposed to the seventh via. Remove the seventh barrier layer and form an eighth barrier layer on the N-type drift layer; An eighth through-hole is formed by etching the eighth barrier layer; An N+ source region is formed by ion implantation in the region of the N-type drift layer exposed to the eighth via.

[0014] In one embodiment of the present invention, after the step of forming the N-type drift layer covering the P-type region and before the step of forming the second barrier layer on the N-type drift layer, the method further includes: A ninth barrier layer is formed on the N-type drift layer, and a ninth via is etched in the ninth barrier layer; The N-type drift layer is etched to form an insulating trench; An insulating dielectric layer is deposited within the insulating trench to form an insulating dielectric layer.

[0015] The semiconductor device proposed in this invention includes a substrate, an N-type drift layer, a source layer, and a gate layer. The substrate is N-type doped, and a drain layer is located on one side of the substrate. The N-type drift layer is disposed on the other side of the substrate, and at least two spaced-apart P-type regions are disposed within the N-type drift layer. The P-type regions extend in a direction perpendicular to the substrate and contact the substrate, forming a lateral NPNPN structure with the N-type drift layer. The source layer is located on the side of the N-type drift layer facing away from the substrate. The gate layer is used to control the opening or closing of the conductive channel from the source layer to the drain layer. By forming a lateral NPNPN structure with the P-type regions and the N-type drift layer, the space charge region is simultaneously distributed laterally and longitudinally. This improves the drift region doping concentration and reduces the on-resistance while ensuring the breakdown voltage. This has the advantage of optimizing the switching and conduction characteristics of the device, enabling the semiconductor device to be used in devices with high breakdown voltage and low on-resistance. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0017] Figure 1 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure for forming an N-type drift layer on a substrate; Figure 3 A schematic diagram of the structure used to prepare the P-type region; Figure 4 A schematic diagram of a structure covering an N-type drift layer on a P-type region; Figure 5 A schematic diagram of the structure used to prepare the N-type region; Figure 6 A schematic diagram of the structure used to prepare the P-type shielding layer; Figure 7 A schematic diagram of the structure forming the P+ region; Figure 8 A schematic diagram of the structure used to prepare the P-type well region; Figure 9 A schematic diagram of the structure used to prepare the N+ source region; Figure 10 A schematic diagram of the structure used to prepare the insulating dielectric layer; Figure 11 A schematic diagram of the structure for forming the gate layer; Figure 12 A schematic diagram of the structure for forming the source layer; Figure 13 This is a flowchart illustrating the steps of a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 14 This is a flowchart illustrating the steps of another embodiment of the method for fabricating the semiconductor device of the present invention; Figure 15 This is a flowchart of the steps in another embodiment of the method for fabricating the semiconductor device of the present invention.

[0018] Explanation of icon numbers: 10. Substrate; 20. Drain layer; 30. N-type drift layer; 40. P-type region; 50. N-type region; 60. P-type shielding layer; 70. Gate layer; 71. Insulating dielectric layer; 81. N+ source region; 82. P-type well region; 83. P+ region; 90. Source layer; 101. First barrier layer; 101a. First via; 102. Second barrier layer; 102a. Second via; 103. Third barrier layer; 103a. Third via; 104. Fourth barrier layer; 104a. Fourth via; 105. Fifth barrier layer; 105a. Fifth via; 106. Sixth barrier layer; 106a. Sixth via; 107. Seventh barrier layer; 107a. Seventh via; 108. Eighth barrier layer; 108a. Eighth via; 109. Ninth barrier layer; 109a. Ninth via.

[0019] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0021] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0022] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0023] This invention proposes a semiconductor device.

[0024] Combination Figure 1 As shown, in one embodiment of the present invention, the semiconductor device includes: Substrate 10 is N-type doped, and one side of substrate 10 is a drain layer 20; An N-type drift layer 30 is disposed on the other side of the substrate 10. At least two spaced P-type regions 40 are disposed within the N-type drift layer 30. The P-type regions 40 extend in a direction perpendicular to the substrate 10 and are in contact with the substrate 10. The P-type regions 40 and the N-type drift layer 30 form a transverse NPNPN structure. Source layer 90, the source layer 90 is disposed on the side of the N-type drift layer 30 opposite to the substrate 10; and Gate layer 70 is used to control the opening or closing of the conductive channels from source layer 90 to drain layer 20.

[0025] In this embodiment, the substrate 10 is made of silicon carbide (SiC) material with a thickness of 1.5 μm and a doping concentration of 2-8e. 18 cm -3 For example, the doping concentration can be 6e 18 cm -3 The thickness of substrate 10 ensures mechanical support during the subsequent epitaxial growth of N-type drift layer 30, and its high doping concentration enables it to form a low-resistance ohmic contact with drain metal (such as nickel), effectively reducing the overall on-resistance of the device.

[0026] The N-type drift layer 30 is formed by epitaxial growth, with a thickness of 40 μm and a doping concentration of 6-10e. 16 cm -3 For example, the doping concentration can be 8e 16 cm -3 There are at least two P-type regions 40, preferably periodically arranged strip structures with a width of 1 μm, a depth (thickness) of 35 μm, and a doping concentration of 1-5e. 17 cm -3 For example, the doping concentration can be 3e 17 cm -3 .

[0027] Increasing the doping concentration of the N-type drift layer 30 decreases the on-resistance; conversely, decreasing the doping concentration increases the on-resistance. The doping concentration of the P-type region 40 must match that of the N-type drift layer 30. Increasing the doping concentration of the N-type drift layer 30 necessitates a corresponding increase in the doping concentration of the P-type region 40 to achieve lateral PN junction breakdown voltage. Therefore, the doping concentrations of the N-type drift layer 30 and the P-type region 40 represent a trade-off between reverse breakdown voltage and on-resistance. This concentration relationship ensures the lateral and longitudinal diffusion of the space charge region in the PN junction, achieving a superjunction structure and thus guaranteeing both high breakdown voltage and low on-resistance.

[0028] Specifically, the P-type region 40 extends upward from and directly contacts the N+SiC substrate 10, forming a vertical PN junction together with the surrounding N-type drift layer 30. Simultaneously, adjacent P-type regions 40 form lateral PN junctions with the N-type drift layer 30, thus constructing a unique "lateral NPNPN" superjunction structure. This structure allows the space charge region to be distributed simultaneously in both the lateral and vertical directions during reverse breakdown, with the voltage evenly distributed across multiple PN junction interfaces. This significantly reduces the electric field peak of a single PN junction, preventing premature local breakdown. Because the voltage is shared by multiple PN junctions, the electric field strength experienced by each PN junction is significantly reduced. Therefore, the doping concentration of the N-type drift layer 30 can be safely increased, thereby greatly reducing the on-resistance and achieving a balance between high breakdown voltage and low on-resistance.

[0029] Combination Figure 1 As shown, in one embodiment of the present invention, the semiconductor device further includes a P-type shielding layer 60 and an insulating dielectric layer 71; One end of the gate layer 70 is connected to the source layer 90, and the other end extends toward the N-type drift layer 30. The insulating dielectric layer 71 is disposed on the outer peripheral surface of the gate layer 70, and the P-type shielding layer 60 is disposed on the side of the insulating dielectric layer 71 facing the substrate 10.

[0030] In this embodiment, the gate layer 70 can be made of polysilicon or metal, and a trench structure extending into the N-type drift layer 30, i.e., a "split trench gate," is formed through an etching process. An insulating dielectric layer 71 fills the gate trench, enclosing the outer periphery of the gate layer 70. The insulating dielectric layer 71 can be a silicon dioxide (SiO2) layer with a bottom thickness of 200 nm and sidewall thicknesses of 50 nm. A P-type shielding layer 60 is provided at the bottom of the insulating dielectric layer 71, near the substrate 10. This P-type shielding layer 60 has a width of 1 μm, a thickness of 300 nm, and a doping concentration of 1-5e. 17 cm -3 For example, the doping concentration can be 3e 17 cm -3 Its top is in direct contact with the insulating dielectric layer 71.

[0031] The P-type shielding layer 60 optimizes the switching characteristics of the semiconductor device. When the semiconductor device is turned off, a high voltage is applied to the drain, which generates a large electric field between the gate and the drain, leading to an increase in parasitic gate-drain capacitance (Cgd) and consequently, an increase in Miller capacitance (Crss). The P-type shielding layer 60 acts like an electrostatic shield, located below the gate, effectively isolating the gate metal from the high-potential drain region below, greatly weakening the electric field coupling between them, and thus significantly reducing Cgd and Crss.

[0032] Therefore, the P-type shielding layer 60 in this embodiment produces two major benefits: first, it improves the switching speed of the device because the amount of charge required for the drive circuit is reduced; second, it significantly reduces switching losses and improves power conversion efficiency, which is crucial for high-frequency applications. Meanwhile, the doping concentration of the P-type shielding layer 60 affects the performance of the semiconductor device. Excessive doping concentration increases on-resistance, while insufficient doping concentration weakens the shielding effect. This embodiment selects a doping concentration of 1-5e... 17 cm -3 Concentration achieves a balance between switching and conduction characteristics.

[0033] Combination Figure 1 As shown, in one embodiment of the present invention, the semiconductor device further includes an N-type region 50, and two gate layers 70, insulating dielectric layers 71 and P-type shielding layers 60 are provided. Each gate layer 70, insulating dielectric layer 71 and P-type shielding layer 60 are arranged sequentially with a P-type region 40 in a direction perpendicular to the substrate 10. The N-type region 50 includes a first layer and a second layer. The first layer is located between the P-type shielding layer 60 and the P-type region 40, and the second layer is located between the two P-type shielding layers 60.

[0034] In this embodiment, the device includes two symmetrically arranged trench gate structures. Each gate layer 70 corresponds to a P-type region 40, a P-type shielding layer 60, and an insulating dielectric layer 71. The N-type region 50 consists of two parts: a first layer and a second layer, which together form an inverted T-shaped cross-section. The maximum thickness of the N-type region 50 is 4.2 μm, and the maximum width is 4 μm. The first N-type region 50 is located in the gap between the P-type shielding layer 60 and the corresponding P-type region 40, and its thickness is 3.7 μm. The second N-type region 50 is located between the two P-type shielding layers 60, and its width between the P-type shielding layers 60 is 2 μm. This size design of the N-type region 50 ensures the functionality of the P-type region 40 and the P-type shielding layer 60 while redistributing the intermediate current of the device's separated gates, thereby reducing the device's on-resistance.

[0035] The doping concentration of N-type region 50 is 6-10e. 17 cm -3 For example, the doping concentration can be 8e 17 cm -3The N-type region 50 of this invention, particularly the second N-type region 50 located below the middle region of the gate, provides an additional, low-on-resistance current conduction path. It redistributes and redirects the current originally concentrated on both sides of the gate layer 70 to the middle region of the gate layer 70, achieving current homogenization. The first N-type region 50 connects the P-type region 40 and the P-type shielding layer 60, contributing to charge balance. This current redistribution mechanism effectively avoids excessively high local current density, reducing not only the overall on-resistance of the device but also improving its thermal stability and preventing reliability degradation caused by local overheating.

[0036] Combination Figure 1 As shown, in one embodiment of the present invention, the semiconductor device further includes an N+ source region 81, a P-type well region 82, and a P+ region 83. The N+ source region 81 and the P-type well region 82 are stacked between the source layer 90 and the N-type drift layer 30. The N+ source region 81 is connected to the source layer 90. The P+ region 83 is located outside the N+ source region 81 and the P-type well region 82. The P+ region 83 is connected to the source layer 90. The P+ region 83, the N+ source region 81, and the P-type well region 82 form a body diode from the source metal to the N-type drift layer 30.

[0037] In this embodiment, the width of the P-type well region 82 is 1-2 μm. For example, the width of the P-type well regions 82 on the left and right sides of the semiconductor device is 1 μm, and the width of the P-type well region 82 in the middle of the separation gate is 2 μm. The thickness of the P-type well region 82 is 200 nm, and the doping concentration is 1-5e. 16 cm -3 For example, the doping concentration can be 3e 16 cm -3 The N+ source region 81 is located on the side of the P-type well region 82 facing the source layer 90. The N+ source region 81 is in direct contact with the source layer 90 (source metal), and its width is 1 μm, its thickness is 300 nm, and its doping concentration is 2-8e. 18 cm -3 For example, the doping concentration can be 5e 18 cm -3 This ensures a low-resistance ohmic contact with the source metal. The P+ region 83 is located outside the P-type well region 82 and the N+ source region 81, adjacent to the device edge. It has a width of 2 μm, a thickness of 1 μm, and a doping concentration as high as 1-5e⁻¹. 19 cm -3 For example, the doping concentration can be 4e 19 cm -3 The doping concentration is much higher than that of the P-type well region 82.

[0038] The P+ region 83, N+ source region 81, and P-type well region 82 together form a parasitic PN junction, i.e., a body diode. In inductive load applications, this body diode provides a freewheeling path when the main switch is off, ensuring normal system operation. More importantly, the introduction of the P+ region 83 greatly enhances the reliability of the source. In the conventional structure, the contact area between the bottom of the P-type well region 82 and the N-type drift layer 30 is small. When the drain is subjected to a high voltage, space charge diffuses towards the source layer 90, easily causing electric field concentration at the edge of the P-type well region 82, leading to device breakdown.

[0039] Due to its extremely high doping concentration, the P+ region 83 of this invention suppresses the diffusion rate of the space charge region at its interface with the N-type drift layer 30. Furthermore, the high doping gradient between the P+ region 83 and the P-type well region 82 makes the diffusion of the space charge region at their contact area slower and narrower. These two effects work together to force the space charge to diffuse towards the gate layer 70 at the center of the device, away from the source layer 90 and the edge of the P-type well region 82, thereby effectively preventing the breakdown of the source layer 90 and significantly improving the long-term reliability of the device under high-voltage stress.

[0040] In one embodiment of the present invention, the substrate 10 is a silicon carbide substrate 10, and the doping concentration of the substrate 10 is 2-8e. 18 cm -3 ; And / or, the doping concentration of the N-type drift layer 30 is 6-10e 16 cm -3 ; And / or, the doping concentration of the p-type region 40 is 1-5e 17 cm -3 ; And / or, the doping concentration of the P-type shielding layer is 1-5e. 17 cm -3 ; And / or, the doping concentration of the P-type well region 82 is 1-5e 16 cm -3 ; And / or, the doping concentration of the N-type region 50 is 6-10e 17 cm -3 ; And / or, the doping concentration of the N+ source region 81 is 2-8e 18 cm -3 ; And / or, the doping concentration of P+ region 83 is 1-5e 19 cm -3 .

[0041] In this embodiment, the key material parameters involved in the foregoing embodiments are specifically quantified. The substrate 10 is made of SiC material, and its doping concentration can be selected as 6e. 18 cm -3 This concentration ensures excellent ohmic contact with the drain metal without compromising the epitaxial layer quality due to excessive concentration. The doping concentration of the N-type drift layer can be selected as 8e. 16 cm -3 To achieve a balance between 5kV withstand voltage and low on-resistance, the doping concentration of both the P-type region 40 and the P-type shielding layer 60 can be selected as 3e. 17 cm -3 This concentration ensures both charge balance in the superjunction structure and provides sufficient shielding. The doping concentration for the P-type well region can be selected as 3e⁻¹. 16 cm -3 This value takes into account the gate threshold voltage, conduction characteristics, and compatibility with the P+ region 83. The doping concentration of the N-type region 50 can be selected as 8e. 17 cm -3 To provide a current redistribution path. The doping concentration of the N+ source region 81 can be selected as 5e. 18 cm -3 This ensures low contact resistance. The P+ region has a high doping concentration of 83, which can be selected as 4e. 19 cm -3 To achieve source protection.

[0042] The present invention also proposes a method for fabricating a semiconductor device as described in any of the above embodiments.

[0043] Combination Figures 2 to 4 , Figures 11 to 13 As shown, in one embodiment of the present invention, the preparation method includes the following steps: S100: An N-type drift layer 30 is formed on the substrate 10; S200: A first barrier layer 101 is formed on the N-type drift layer 30, and at least two first vias 101a are etched in the first barrier layer 101 to expose the N-type drift layer 30; S300: Ion implantation is performed on the region of the N-type drift layer 30 exposed to the first via 101a to form a P-type region 40, and the P-type region 40 is connected to the substrate 10; S400: Remove the first blocking layer 101 to form an N-type drift layer 30 covering the P-type region 40; S500: A second barrier layer 102 is formed on the N-type drift layer 30, and a second through-hole 102a is formed by etching the second barrier layer 102; S600: Etch the N-type drift layer 30 to form a gate trench, and deposit the gate layer 70 within the gate trench; S700: Remove the second barrier layer 102 and form a third barrier layer 103 on the N-type drift layer 30; S800: A third via 103a is formed by etching the third barrier layer 103, and an N-type drift layer 30 is etched to form a source trench, and a source layer 90 is deposited in the source trench.

[0044] In this embodiment, the substrate 10 is an n+ type SiC substrate 10. First, an N-type drift layer 30 is formed through an epitaxial growth process. Then, a photoresist layer is coated as a first barrier layer 101. A first via 101a is formed on the first barrier layer 101 through photolithography and etching processes. The position, shape, and size of the first via 101a correspond to the position, cross-sectional shape, and size of the P-type region 40. Then, ions are implanted into the N-type drift layer 30 using the first barrier layer 101 as a barrier structure to form the P-type region 40 connecting the substrate 10. In one embodiment, an ion implanter is used with aluminum (Al) as the ion source, and the implantation energy (e.g., 300 keV) and dose (e.g., 5eV) are precisely controlled. 13 cm -3 Aluminum ions are implanted into the exposed N-type drift layer 30 region, penetrating to contact the n+ substrate 10, forming a P-type region 40 with a depth of approximately 35 μm. Then, the first barrier layer 101 is removed, and epitaxial growth is performed again to grow a new N-type drift layer 30 to cover the formed P-type region 40.

[0045] In fabricating the gate layer 70, photoresist is first coated to form a second barrier layer 102, followed by photolithography and etching processes to form a second via 102a. Then, a gate trench with a depth of approximately 1.5 μm is etched in the N-type drift layer 30 using dry etching (such as ICP-RIE). A 200 nm thick SiO2 layer is thermally grown within the trench as an insulating dielectric layer 71, and then filled with polysilicon or metal material by chemical vapor deposition (CVD) to form the gate layer 70.

[0046] In the preparation of the source layer 90, a third barrier layer 103 is first formed, then the source trench is etched, and metals such as titanium / nickel are sputtered to form the source layer 90.

[0047] Combination Figure 5 , Figure 6 as well as Figure 14 As shown, in one embodiment of the present invention, after the step of forming the N-type drift layer 30 covering the P-type region 40 and before the step of forming the second barrier layer 102 on the N-type drift layer 30, the method further includes: S410: A fourth barrier layer 104 is formed on the N-type drift layer 30, and a fourth through hole 104a is formed by etching the fourth barrier layer 104. S420: Ion implantation is performed on the region of the N-type drift layer 30 exposed to the fourth via 104a to form an N-type region 50, which is located on the P-type region 40; S430: Remove the fourth barrier layer 104 and form a fifth barrier layer 105 on the N-type drift layer 30. Etch the fifth barrier layer 105 to form a fifth via 105a. S440: Ion implantation is performed on the region of the N-type drift layer 30 exposed to the fifth via 105a to form a P-type shielding layer 60, and the fifth barrier layer 105 is removed.

[0048] In this embodiment, after the epitaxial growth of the N-type drift layer 30 covering the P-type region 40 is completed, the N-type region 50 and the P-type shielding layer 60 are prepared.

[0049] First, photoresist is coated as the fourth barrier layer 104. A fourth via 104a is defined using photolithography, corresponding to the position of the N-type region 50 (i.e., the area directly above the P-type region 40 and between the two P-type regions 40). Then, using an ion implantation process, with the fourth barrier layer 104 as the barrier structure, ions are implanted into the N-type drift layer 30 to form the N-type region 50. For example, nitrogen (N) or phosphorus (P) is used as the ion source, and the implantation energy (e.g., 180 keV) and dose (e.g., 2e) are controlled through the ion implantation process. 14 cm -2 A doping concentration of 8e is formed in the N-type drift layer 30 above the P-type region 40. 17 cm -3 The N-type region 50. After implantation, the fourth barrier layer 104 (photoresist) is removed.

[0050] Next, photoresist is recoated as the fifth barrier layer 105, and a fifth via 105a is formed at the position corresponding to the P-type shielding layer 60 by photolithography and etching. Then, a doping concentration of 3e is formed below the predetermined position of the insulating dielectric layer 71 by ion implantation. 17 cm -3 A 300nm thick P-type shielding layer 60 is applied. Finally, the fifth barrier layer 105 is removed.

[0051] Combination Figures 7 to 9 as well as Figure 15 As shown, in one embodiment of the present invention, after the step of forming the P-type shielding layer 60 and before the step of forming the second barrier layer 102 on the N-type drift layer 30, the following steps are further included: S441: A sixth barrier layer 106 is formed on the N-type drift layer 30, and a sixth through-hole 106a is formed by etching the sixth barrier layer 106. S442: Ion implantation is performed on the region of the N-type drift layer 30 exposed to the sixth via 106a to form a P+ region 83; S443: Remove the sixth barrier layer 106 and form the seventh barrier layer 107 on the N-type drift layer 30; S444: A seventh through-hole 107a is formed by etching the seventh barrier layer 107; S445: Ion implantation is performed in the region of the N-type drift layer 30 exposed to the seventh via 107a to form a P-type well region 82; S446: Remove the seventh barrier layer 107 and form the eighth barrier layer 108 on the N-type drift layer 30; S447: An eighth through-hole 108a is formed by etching the eighth barrier layer 108; S448: An N+ source region 81 is formed by ion implantation in the region of the N-type drift layer 30 exposed to the eighth via 108a.

[0052] In this embodiment, after forming the P-type shielding layer 60, the P+ region 83, the P-type well region 82, and the N+ source region 81 are prepared sequentially.

[0053] First, photoresist is coated as the sixth barrier layer 106. A sixth via 106a, corresponding to the P+ region 83, is defined in the sixth barrier layer 106 using photolithography and etching processes. Then, the P+ region 83 is formed using an ion implantation process. For example, a high dose of aluminum ions (e.g., 5e) is used. 15 cm -2 Ion implantation was performed to create a doping concentration as high as 4e. 19 cm -3 A P+ region 83 with a depth of approximately 1 μm was formed. Finally, the sixth barrier layer 106 was removed.

[0054] Then, a seventh barrier layer 107 (photoresist) is coated to form the seventh barrier layer 107. Through photolithography and etching processes, seventh vias 107a are defined on the seventh barrier layer 107, corresponding to the positions of the P-type well regions 82 (including the middle and both sides). A lower dose of aluminum ions (e.g., 1e) is used. 13 cm -2 Ion implantation was performed to form a doping concentration of 3e. 16 cm -3 A P-type well region 82 with a depth of approximately 200 nm was formed. Finally, the seventh barrier layer 107 was removed.

[0055] An eighth barrier layer 108 (photoresist) is formed by coating, and an eighth via 108a corresponding to the N+ source region 81 is defined in the eighth barrier layer 108 by photolithography and etching processes. High-dose implantation (dose such as 5e) is then performed using nitrogen or phosphorus ions. 15 cm -2 ), forming a doping concentration of 5e 18 cm -3An N+ source region with a depth of approximately 300 nm was created. After all implantation was completed, a high-temperature annealing process was performed.

[0056] Combination Figure 10 As shown, in one embodiment of the present invention, after the step of forming the N-type drift layer 30 covering the P-type region 40 and before the step of forming the second barrier layer 102 on the N-type drift layer 30, the method further includes: A ninth barrier layer 109 is formed on the N-type drift layer 30, and a ninth via 109a is formed by etching the ninth barrier layer 109. Etch the N-type drift layer 30 to form an insulating trench; An insulating dielectric layer 71 is deposited within the insulating trench to form an insulating dielectric layer.

[0057] In this embodiment, after the epitaxial growth of the N-type drift layer 30 covering the P-type region 40 is completed, an insulating dielectric layer 71 is first prepared. Photoresist is coated as a ninth barrier layer 109, and a ninth via 109a corresponding to the positions of the P-type shielding layer 60 and the insulating dielectric layer 71 is defined on the ninth barrier layer 109 using photolithography and etching processes. Then, an insulating trench with a depth of approximately 300 nm is etched in the N-type drift layer 30 using dry etching (such as ICP-RIE). The bottom of this insulating trench is the location of the subsequent P-type shielding layer 60. A silicon dioxide (SiO2) layer with a thickness of 200 nm is grown in the insulating trench using thermal oxidation or CVD processes as the insulating dielectric layer 71. After this step, the gate layer 70 is prepared, i.e., the insulating dielectric layer 71 is etched to form a gate trench, and the gate material is deposited in the gate trench to form the gate layer 70, such that the insulating dielectric layer 71 covers the outer periphery of the gate layer 70.

[0058] The above description is merely an exemplary embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention specification and drawings under the technical concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: The substrate is N-type doped, and one side of the substrate is a drain layer; An N-type drift layer is disposed on the other side of the substrate. The N-type drift layer contains at least two spaced P-type regions that extend in a direction perpendicular to the substrate and are in contact with the substrate. The P-type regions and the N-type drift layer form a transverse NPNPN structure. A source layer, wherein the source layer is disposed on the side of the N-type drift layer opposite to the substrate; and A gate layer, which is used to control the opening or closing of the conductive channel from the source layer to the drain layer.

2. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor device further includes a P-type shielding layer and an insulating dielectric layer; One end of the gate layer is connected to the source layer, and the other end extends toward the N-type drift layer. The insulating dielectric layer is disposed on the outer peripheral surface of the gate layer, and the P-type shielding layer is disposed on the side of the insulating dielectric layer facing the substrate.

3. The semiconductor device as described in claim 2, characterized in that, The semiconductor device further includes an N-type region. Two gate layers, two insulating dielectric layers, and two P-type shielding layers are provided. Each gate layer, one insulating dielectric layer, and one P-type shielding layer are sequentially provided with a P-type region along a direction perpendicular to the substrate. The N-type region includes a first layer and a second layer. The first layer is located between the P-type shielding layer and the P-type region, and the second layer is located between the two P-type shielding layers.

4. The semiconductor device as described in claim 3, characterized in that, The semiconductor device further includes an N+ source region, a P-type well region, and a P+ region; The N+ source region and the P-type well region are stacked between the source layer and the N-type drift layer. The N+ source region is connected to the source layer. The P+ region is located outside the N+ source region and the P-type well region and is connected to the source layer. The P+ region, the N+ source region, and the P-type well region form a body diode from the source metal to the N-type drift layer.

5. The semiconductor device as claimed in claim 4, characterized in that, The substrate is a silicon carbide substrate, and the doping concentration of the substrate is 2-8e. 18 cm -3 ; And / or, the doping concentration of the N-type drift layer is 6-10e 16 cm -3 ; And / or, the doping concentration of the P-type region is 1-5e 17 cm -3 ; And / or, the doping concentration of the P-type shielding layer is 1-5e 17 cm -3 ; And / or, the doping concentration of the P-type well region is 1-5e 16 cm -3 ; And / or, the doping concentration of the N-type region is 6-10e 17 cm -3 ; And / or, the doping concentration of the N+ source region is 2-8e 18 cm -3 ; And / or, the doping concentration of the P+ region is 1-5e 19 cm -3 .

6. The semiconductor device as claimed in claim 4, characterized in that, The thickness of the substrate is 1.5 μm; And / or, the thickness of the N-type drift layer is 40 μm; And / or, the width of the P-type region is 1 μm and the thickness is 35 μm; And / or, the width of the P-type shielding layer is 1 μm and the thickness is 300 nm; And / or, the width of the P-type well region is 1-2 μm and the thickness is 200 nm; And / or, the thickness of the first layer of the N-type region is 3.7 μm, and the width of the second layer of the N-type region is 2 μm; And / or, the width of the N+ source region is 1 μm and the thickness is 300 nm; And / or, the width of the P+ region is 2μm and the thickness is 1μm.

7. A method for fabricating a semiconductor device as described in any one of claims 1 to 6, characterized in that, The preparation method includes the following steps: An N-type drift layer is formed on the substrate; A first barrier layer is formed on the N-type drift layer, and at least two first vias are etched in the first barrier layer to expose the N-type drift layer; Ion implantation is performed on the region of the N-type drift layer exposed to the first via to form a P-type region, which is connected to the substrate; Remove the first blocking layer to form an N-type drift layer covering the P-type region; A second barrier layer is formed on the N-type drift layer, and a second via is formed by etching the second barrier layer; The N-type drift layer is etched to form a gate trench, and a gate layer is deposited in the gate trench to form a gate layer. Remove the second barrier layer and form a third barrier layer on the N-type drift layer; A third via is formed by etching the third barrier layer, and the N-type drift layer is etched to form a source trench, and a source layer is deposited in the source trench.

8. The preparation method according to claim 7, characterized in that, After the step of forming the N-type drift layer covering the P-type region and before the step of forming the second barrier layer on the N-type drift layer, the method further includes: A fourth barrier layer is formed on the N-type drift layer, and a fourth via is etched in the fourth barrier layer; An N-type region is formed by ion implantation in the region of the N-type drift layer exposed to the fourth via, and the N-type region is located on the P-type region; Remove the fourth barrier layer and form a fifth barrier layer on the N-type drift layer, and etch a fifth via in the fifth barrier layer; Ion implantation is performed on the region of the N-type drift layer exposed to the fifth via to form a P-type shielding layer, and the fifth barrier layer is removed.

9. The preparation method according to claim 8, characterized in that, After the step of forming the P-type shielding layer and before the step of forming the second barrier layer on the N-type drift layer, the method further includes: A sixth barrier layer is formed on the N-type drift layer, and a sixth via is etched in the sixth barrier layer; Ion implantation is performed on the region of the N-type drift layer exposed to the sixth via to form a P+ region; Remove the sixth barrier layer and form a seventh barrier layer on the N-type drift layer; A seventh through-hole is formed by etching the seventh barrier layer; Ion implantation is performed to form a P-type well region in the area of ​​the N-type drift layer exposed to the seventh via. Remove the seventh barrier layer and form an eighth barrier layer on the N-type drift layer; An eighth through-hole is formed by etching the eighth barrier layer; An N+ source region is formed by ion implantation in the region of the N-type drift layer exposed to the eighth via.

10. The preparation method according to claim 7, characterized in that, After the step of forming the N-type drift layer covering the P-type region and before the step of forming the second barrier layer on the N-type drift layer, the method further includes: A ninth barrier layer is formed on the N-type drift layer, and a ninth via is etched in the ninth barrier layer; The N-type drift layer is etched to form an insulating trench; An insulating dielectric layer is deposited within the insulating trench to form an insulating dielectric layer.

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