Semiconductor device and preparation method thereof

Abstract

The invention discloses a semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors, and the semiconductor device comprises a substrate, an N-type drift layer, a source electrode layer and a grid electrode layer. A drain electrode layer is arranged on one side of the substrate; the N-type drift layer is arranged on the other side of the substrate, two P-type regions arranged at intervals are arranged in the N-type drift layer, and the P-type regions extend in the direction perpendicular to the substrate and make contact with the substrate; two P + regions extending in the direction perpendicular to the substrate are further arranged in the N-type drift layer, and the P + regions are arranged on the sides, away from the substrate, of the P-type regions at intervals in the direction perpendicular to the substrate; the source electrode layer is arranged on the N-type drift layer; the gate layer is used for controlling on-off of the device. According to the invention, the PN junction voltage-withstanding structure is formed in the longitudinal direction and the transverse PN junction voltage-withstanding structure is formed at the same time, so that the device has higher voltage-withstanding capability, and the semiconductor device can be applied to devices with high voltage-withstanding and low on-resistance by improving the doping concentration of the N-type drift layer and reducing the on-resistance of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] In the field of semiconductor technology, SiC VDMOS devices have the advantages of wide bandgap and high voltage withstand capability, which have led to their widespread application in high breakdown voltage, high temperature and high power electronic devices.

[0003] However, in some high-voltage power grid applications, high demands are placed on the low-resistance characteristics of devices. This requires not only high voltage withstand capability but also low on-resistance while maintaining high voltage withstand capability. However, existing SiCVDMOS devices are difficult to design and manufacture simultaneously to meet the requirements of high voltage withstand capability and low on-resistance. Therefore, this limits the application of SiCVDMOS devices in devices requiring high voltage withstand capability and low on-resistance. Summary of the Invention

[0004] The main objective of this invention is to propose a semiconductor device and its fabrication method, aiming to address the limitations of existing SiCVDMOS devices in applications requiring high voltage withstand capability and low on-resistance.

[0005] To achieve the above objectives, the present invention provides a semiconductor device comprising: The substrate is N-type doped, and one side of the substrate is a drain layer; An N-type drift layer is disposed on the other side of the substrate. The N-type drift layer contains two spaced-apart P-type regions that extend in a direction perpendicular to the substrate and are in contact with the substrate. The N-type drift layer also includes two P+ regions, which extend in a direction perpendicular to the substrate. Each P+ region is spaced apart from the P-type region on the side away from the substrate in a direction perpendicular to the substrate. A source layer, wherein the source layer is disposed on the side of the N-type drift layer opposite to the substrate; and A gate layer, which is used to control the opening or closing of the conductive channel from the source layer to the drain layer.

[0006] In one embodiment of the present invention, the semiconductor device further includes an N+ region located on the side of the gate layer facing the substrate layer and on the side of the N-type drift layer away from the substrate.

[0007] In one embodiment of the present invention, the semiconductor device further includes a P-type shielding layer disposed between the N+ layer and the N-type drift layer, the P-type shielding layer enclosing the N+ region.

[0008] In one embodiment of the present invention, the semiconductor device further includes an N+ source region and a P-type well region; The N+ source region is located between the source layer and the N-type drift layer. The N+ source region is connected to the source layer and is adjacent to the P+ region. The P-type well region surrounds the outer periphery of the N+ source region and is adjacent to the P-type shielding layer.

[0009] In one embodiment of the present invention, the substrate is a silicon carbide substrate, and the doping concentration of the substrate is 2-8e. 18 cm -3 ; And / or, the doping concentration of the N-type drift layer is 1-5e 17 cm -3 ; And / or, the doping concentration of the P-type region is 1-5e 17 cm -3 ; And / or, the doping concentration of the P-type shielding layer is 1-5e 17 cm -3 ; And / or, the doping concentration of the P-type well region is 6-10e 16 cm -3 ; And / or, the doping concentration of the N+ region is 6-10e 17 cm -3 ; And / or, the doping concentration of the N+ source region is 2-8e 18 cm -3 ; And / or, the doping concentration of the P+ region is 1-5e 19 cm -3 .

[0010] In one embodiment of the present invention, the thickness of the substrate is 0.6 μm; And / or, the thickness of the N-type drift layer is 30-40 μm; And / or, the width of the P-type region is 1 μm and the thickness is greater than 12 μm; And / or, the width of the P-type shielding layer is 1 μm and the thickness is 1.5 μm; And / or, the maximum width of the P-type well region is 1.3 μm and the maximum thickness is 1.5 μm; And / or, the maximum width of the N+ region is 2μm and the maximum thickness is 2μm; And / or, the width of the N+ source region is 1 μm and the thickness is 300 nm; And / or, the width of the P+ region is 1 μm and the thickness is 12 μm.

[0011] The present invention also proposes a method for fabricating a semiconductor device as described in any of the above descriptions, the method comprising the steps of: An N-type drift layer is formed on the substrate; A first barrier layer is formed on the N-type drift layer, and two first vias are etched in the first barrier layer to expose the N-type drift layer; Ion implantation is performed on the region of the N-type drift layer exposed to the first via to form a P-type region, which is connected to the substrate; Remove the first blocking layer to form an N-type drift layer covering the P-type region; A second barrier layer is formed on the N-type drift layer, and two second vias are etched in the second barrier layer; Ion implantation is performed on the region of the N-type drift layer exposed to the second via to form two P+ regions, the P+ regions being spaced apart in the direction perpendicular to the substrate from the P-type region, and the second barrier layer is removed. A third barrier layer is formed on the N-type drift layer, and a third via is etched into the third barrier layer; The N-type drift layer is etched to form a gate trench, and a gate layer is deposited in the gate trench to form a gate layer. Remove the third barrier layer and form a fourth barrier layer on the N-type drift layer; A fourth via is formed by etching the fourth barrier layer, and the N-type drift layer is etched to form a source trench, and a source layer is deposited in the source trench.

[0012] In one embodiment of the present invention, after the step of removing the second barrier layer and before the step of forming the third barrier layer on the N-type drift layer, the method further includes: A fifth barrier layer is formed on the N-type drift layer, and a fifth via is etched in the fifth barrier layer; Ion implantation is performed on the region of the N-type drift layer exposed to the fifth via to form a P-type well region, which is adjacent to the P+ region; Remove the fifth barrier layer and form a sixth barrier layer on the N-type drift layer, and etch a sixth through-hole in the sixth barrier layer; An N+ source region is formed by ion implantation in the area of ​​the N-type drift layer exposed to the sixth via. The N+ source region is located on the side of the P-type well region away from the substrate. The sixth barrier layer is then removed.

[0013] In one embodiment of the present invention, after the step of forming the N+ source region and before the step of forming the third barrier layer on the N-type drift layer, the method further includes: A seventh barrier layer is formed on the N-type drift layer, and a seventh via is etched in the seventh barrier layer; An N+ region is formed by ion implantation in the area of ​​the N-type drift layer exposed to the seventh via, and the N+ region is disposed adjacent to the P-type well region. Remove the seventh barrier layer and form an eighth barrier layer on the N-type drift layer; An eighth through-hole is formed by etching the eighth barrier layer; A P-type shielding layer is formed by ion implantation in the region of the N+ region exposed to the eighth via, the P-type shielding layer being located on the side of the N+ region away from the substrate, and the eighth barrier layer is removed.

[0014] In one embodiment of the present invention, after the step of forming the P-type shielding layer and before the step of forming the third barrier layer on the N-type drift layer, the method further includes: A ninth barrier layer is formed on the N-type drift layer, and a ninth via is etched in the ninth barrier layer; An insulating dielectric layer is deposited within the ninth through hole.

[0015] The semiconductor device proposed in this invention includes a substrate, an N-type drift layer, a source layer, and a gate layer. The substrate is N-type doped, and a drain layer is located on one side of the substrate. The N-type drift layer is disposed on the other side of the substrate. Two spaced-apart P-type regions are disposed within the N-type drift layer, extending perpendicular to the substrate and contacting it. Two P+ regions are also disposed within the N-type drift layer, extending perpendicular to the substrate. Each P+ region is spaced apart from the P-type region on the side away from the substrate, perpendicular to the substrate. Both the P-type and P+ regions are positioned close to the edge of the unit cell. Therefore, a bottom P-type region-N-type drift layer-P-type region structure and a top P+ region-N-type drift layer-P+ region structure are constructed in the lateral structure of the device. This forms a lateral PN junction breakdown structure while simultaneously creating a vertical PN junction breakdown structure, thereby improving the breakdown voltage capability of the device through a combination of lateral and vertical structures. Because semiconductor devices have higher withstand voltage, the doping concentration of the N-type drift layer can be increased, thereby reducing the on-resistance of the device. This allows semiconductor devices to be used in devices with high withstand voltage and low on-resistance. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0017] Figure 1 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure for forming an N-type drift layer on a substrate; Figure 3 A schematic diagram of the structure used to prepare the P-type region; Figure 4 A schematic diagram of a structure covering an N-type drift layer on a P-type region; Figure 5 A schematic diagram of the structure forming the P+ region; Figure 6 A schematic diagram of the structure used to form the P-type well region; Figure 7 A schematic diagram of the structure used to prepare the N+ source region; Figure 8 A schematic diagram of the structure used to form the N+ region; Figure 9 A schematic diagram of the structure used to prepare the P-type shielding layer; Figure 10 A schematic diagram of the structure used to prepare the insulating dielectric layer; Figure 11 A schematic diagram of the structure for forming the gate layer; Figure 12 A schematic diagram of the structure for forming the source layer; Figure 13 A schematic diagram of the structure for forming a protective layer on the source layer; Figure 14 To be Figure 13 A schematic diagram of the flipped structure; Figure 15 A schematic diagram of the structure for forming the drain layer; Figure 16 This is a flowchart illustrating the steps of a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 17 This is a flowchart illustrating the steps of another embodiment of the method for fabricating the semiconductor device of the present invention; Figure 18 This is a flowchart illustrating the steps of another embodiment of the method for fabricating the semiconductor device of the present invention.

[0018] Explanation of icon numbers: 10. Substrate; 20. Drain layer; 30. N-type drift layer; 40. P-type region; 50. P+ region; 60. P-type well region; 70. N+ source region; 81. P-type shielding layer; 82. N+ region; 91. Gate layer; 92. Source layer; 93. Insulating dielectric layer; 101. First barrier layer; 101a. First via; 102. Second barrier layer; 102a. Second via; 103. Third barrier layer; 103a. Third via; 104. Fourth barrier layer; 104a. Fourth via; 105. Fifth barrier layer; 105a. Fifth via; 106. Sixth barrier layer; 106a. Sixth via; 107. Seventh barrier layer; 107a. Seventh via; 108. Eighth barrier layer; 108a. Eighth via; 109. Ninth barrier layer; 109a. Ninth via.

[0019] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0021] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0022] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0023] This invention proposes a semiconductor device.

[0024] Combination Figure 1 As shown, in one embodiment of the present invention, the semiconductor device includes a substrate, an N-type drift layer, a source layer, and a gate layer; the substrate is N-type doped, and a drain layer is located on one side of the substrate; the N-type drift layer is disposed on the other side of the substrate, and two spaced-apart P-type regions are provided in the N-type drift layer, the P-type regions extending in a direction perpendicular to the substrate and contacting the substrate; the N-type drift layer also includes two P+ regions, the P+ regions extending in a direction perpendicular to the substrate, each P+ region being spaced apart from the P-type regions on the side away from the substrate in a direction perpendicular to the substrate; the source layer is disposed on the side of the N-type drift layer away from the substrate; the gate layer is used to control the opening or closing of the conductive channel from the source layer to the drain layer.

[0025] In this embodiment, the substrate 10 is made of silicon carbide (SiC) material, with a thickness of 0.6 μm after fabrication and an initial thickness of 1.5 μm, achieved through a thinning process after epitaxial growth. This thickness design ensures mechanical support during the epitaxial growth of the N-type drift layer and reduces the drain contact resistance through thinning, thereby effectively reducing the overall on-resistance of the device.

[0026] The substrate doping concentration is 2-8e 18 cm -3 For example, it could be 6e 18 cm -3 This forms a low-resistance ohmic contact with the drain layer metal (such as nickel). The N-type drift layer 30 is formed by epitaxial growth and has a thickness of 35 μm with a doping concentration of 1-5e. 17 cm -3 For example, it could be 3e 17 cm -3 The key structural feature of this application lies in the device's breakdown voltage design: at the bottom of the cell, two spaced-apart P-type regions (1 μm wide, 12 μm thick, doped with 1-5e⁻¹) are present. 17 cm -3 For example, it could be 3e 17 cm -3 The P-type region and the intermediate N-type drift layer together form a "P-type region-N-type drift layer-P-type region" structure; at the top of the cell, there are two P+ regions (1 μm wide, 12 μm thick, doped with 1-5e-e-T). 19 cm -3 For example, it could be 3e 19 cm -3The P-type well and the intermediate N-type drift layer form a "P+ region - N-type drift layer - P+ region" structure. This combined horizontal and vertical breakdown voltage structure allows the space charge region to expand not only vertically (between the P-type well and the N-type drift layer) but also horizontally (between the P-type regions and between the P+ regions) during reverse breakdown, creating a multi-dimensional electric field distribution. The voltage is shared by multiple PN junctions, significantly reducing the peak electric field and avoiding electric field concentration at a single PN junction, thus achieving a high breakdown voltage of over 3kV. Simultaneously, because the horizontal PN junctions share part of the breakdown voltage, the doping concentration of the N-type drift layer can be increased, further reducing the on-resistance and achieving synergistic optimization of high breakdown voltage and low on-resistance.

[0027] Combination Figure 1 and Figure 8 As shown, in one embodiment of the present invention, the semiconductor device further includes an N+ region, which is located on the side of the gate layer facing the substrate layer and on the side of the N-type drift layer away from the substrate.

[0028] In this embodiment, the N+ region is located on the side of the gate layer facing the substrate, with a maximum width of 2 μm, a maximum depth of 2 μm, and a doping concentration of 6-10e. 17 cm -3 For example, it could be 8e 17 cm -3 The N+ region is in contact with the N-type drift layer and is located directly below the planar gate (composed of gate metal and insulating dielectric). The introduction of the N+ region provides a low-resistance bypass for the current from the source layer to the N-type drift layer, effectively reducing the resistance of the traditional JFET region and thus significantly improving the low-resistance conduction characteristics of the device.

[0029] Combination Figure 1 and Figure 9 As shown, in one embodiment of the present invention, the semiconductor device further includes a P-type shielding layer, which is disposed between the N+ layer and the N-type drift layer, and the P-type shielding layer encloses the N+ region.

[0030] In this embodiment, the P-type shielding layer, enclosed by the N+ region, is located below the gate metal. The P-type shielding layer effectively shields the electric field coupling between the gate and drain. The P-type shielding layer has a width of 1 μm and a thickness of 1.5 μm; the doping concentration of the P-type shielding layer is 1-5e. 17 cm -3When the device is turned off, the electric field generated by the high drain voltage is blocked by the P-type shielding layer and cannot be directly coupled to the gate, thus significantly reducing the gate-drain capacitance (Cgd) and Miller capacitance (Crss). This directly improves the switching speed of the device and reduces switching losses, especially in high-frequency switching applications, significantly improving system efficiency. The size and doping concentration of the N+ region and the P-type shielding layer are optimized to ensure that the gate control capability is not sacrificed while reducing the JFET resistance, achieving the best balance between shielding effect and on-resistance.

[0031] Combination Figure 1 and Figure 7 As shown, in one embodiment of the present invention, the semiconductor device further includes an N+ source region and a P-type well region; The N+ source region is located between the source layer and the N-type drift layer. The N+ source region is connected to the source layer and is adjacent to the P+ region. The P-type well region surrounds the outer periphery of the N+ source region and is adjacent to the P-type shielding layer.

[0032] In this embodiment, the P+ region is located on the left and right sides of the device cell, and is a strip-shaped doped region with a width of 1 μm, a depth of 12 μm, and a doping concentration of 1-5e. 19 cm -3 The P+ region contacts the N-type drift layer, forming a PN junction. When the device is turned off, the depletion region formed by this PN junction not only bears the longitudinal breakdown voltage, but its lateral extension also effectively shields the electric field interference between adjacent cells, forming an "inter-cell electric field shielding" effect. This shielding effect makes the electric field distribution more uniform, avoiding electric field concentration at the cell edges, thus allowing for an appropriate increase in the doping concentration of the N-type drift layer while ensuring high breakdown voltage, further reducing the on-resistance.

[0033] Furthermore, the P+ region also has a dual function: firstly, as the P+ region forms a parasitic body diode with the N-type drift layer, its depth of 12 μm results in a large contact area with the N-type drift layer, significantly reducing the on-resistance of the body diode and improving its freewheeling capability; secondly, the high doping concentration (3e) of the P+ region... 19 cm -3 This creates a steep doping gradient between the doping layer and the adjacent P-type region, which helps to achieve electrical isolation between cells and prevent leakage current.

[0034] Additionally, the P+ region and N+ source region (width 1 μm, depth 300 nm, doping concentration 2-8e) 18 cm -3 For example, it could be 5e. 18 cm -3 ) and P-type well region (maximum width 1.3 μm, maximum thickness 1.5 μm, doping concentration 6-10e) 16 cm -3Together, these two elements form a parasitic PN junction, namely a body diode. In inductive load applications, this body diode provides a freewheeling path when the main switch is off, ensuring normal system operation. More importantly, the introduction of the P+ region greatly enhances the reliability of the source. In traditional structures, the contact area between the bottom of the P-type well region and the N-type drift layer is small. When the drain is subjected to a high voltage, space charge diffuses towards the source layer, easily causing electric field concentration at the edge of the P-type well region, leading to device breakdown.

[0035] Due to its extremely high doping concentration, the P+ region of this invention suppresses the diffusion rate of the space charge region at its interface with the N-type drift layer. Furthermore, the high doping gradient between the P+ region and the P-type well region makes the space charge diffusion in their contact area slower and narrower. These two effects work together to force the space charge to diffuse towards the gate layer at the center of the device, away from the source layer and the edge of the P-type well region, thereby effectively preventing source layer breakdown and significantly improving the long-term reliability of the device under high-voltage stress.

[0036] In one embodiment of the present invention, the substrate is a silicon carbide substrate, and the doping concentration of the substrate is 2-8e. 18 cm -3 ; And / or, the doping concentration of the N-type drift layer is 1-5e 17 cm -3 ; And / or, the doping concentration of the P-type region is 1-5e 17 cm -3 ; And / or, the doping concentration of the P-type shielding layer is 1-5e 17 cm -3 ; And / or, the doping concentration of the P-type well region is 6-10e 16 cm -3 ; And / or, the doping concentration of the N+ region is 6-10e 17 cm -3 ; And / or, the doping concentration of the N+ source region is 2-8e 18 cm -3 ; And / or, the doping concentration of the P+ region is 1-5e 19 cm -3 .

[0037] In this embodiment, the key material parameters involved in the foregoing embodiments are specifically quantified. The substrate 10 is made of SiC material, and its doping concentration can be selected as 6e. 18 cm -3This concentration ensures low-ohmic contact with the drain metal. The doping concentration of the N-type drift layer can be selected as 3e. 17 cm -3 This achieves a low on-resistance while maintaining a 3kV withstand voltage. The concentration of the P-type region and the P-type shielding layer can be selected as 3e. 17 cm -3 This matches the N-type drift layer, achieving charge balance. The 8eT of the P-type well region... 16 cm -3 The concentration ensures appropriate threshold voltage and gate control capability. The 8e in the N+ region... 17 cm -3 The concentration strikes a balance between reducing JFET resistance and avoiding interference with gate control. 5e in the N+ source region. 18 cm -3 The concentration ensures low-resistance contact with the source metal. The 3e in the P+ region... 19 cm -3 Ultra-high doping concentration is key to achieving low bulk diode forward voltage drop and strong electric field shielding. Silicon dioxide is chosen as the insulating dielectric layer due to its stable dielectric constant, good interface quality with SiC, and high reliability. The synergistic effect of these parameters ensures the high performance of the device.

[0038] The present invention also proposes a method for fabricating a semiconductor device as described above, the specific structure of which is described in the above embodiments.

[0039] Combination Figures 2 to 5 , Figure 11 , Figure 12 as well as Figure 16 As shown, in one embodiment of the present invention, the preparation method includes the following steps: S100: An N-type drift layer is formed on the substrate; S200: A first barrier layer is formed on the N-type drift layer, and two first through-holes exposing the N-type drift layer are etched in the first barrier layer; S300: Ion implantation is performed on the region of the N-type drift layer exposed to the first via to form a P-type region, which is connected to the substrate; S400: Remove the first blocking layer to form an N-type drift layer covering the P-type region; S500: A second barrier layer is formed on the N-type drift layer, and two second vias are etched in the second barrier layer; S600: Ion implantation is performed on the region of the N-type drift layer exposed to the second via to form two P+ regions, with the P+ regions separated by a direction perpendicular to the substrate in the P-type region, and the second barrier layer is removed. S700: A third barrier layer is formed on the N-type drift layer, a third via is etched in the third barrier layer, and a gate layer is deposited in the third via. S800: Remove the third barrier layer and form a fourth barrier layer on the N-type drift layer. Etch the fourth barrier layer to form a fourth via and deposit the source layer in the fourth via.

[0040] In this embodiment, the substrate is an N+ type SiC substrate. First, an N-type drift layer is formed through an epitaxial growth process. Then, a photoresist layer is coated as a first barrier layer. A first via is formed on the first barrier layer through photolithography and etching processes. The position, shape, and size of the first via correspond to the position, cross-sectional shape, and size of the P-type region. Then, ions are implanted into the N-type drift layer using the first barrier layer as a barrier structure to form a P-type region connecting to the substrate through an ion implantation process. In one embodiment, an ion implanter is used with aluminum (Al) as the ion source, and the implantation energy (e.g., 300 keV) and dose (e.g., 5eV) are precisely controlled. 13 cm -3 Aluminum ions are implanted into the exposed N-type drift layer region, penetrating to contact the N+ substrate and forming a P-type region with a depth of approximately 35 μm. Afterward, the first barrier layer is removed, and epitaxial growth is performed again to grow a new N-type drift layer to cover the formed P-type region.

[0041] Next, a photoresist layer is coated on the surface of the N-type drift layer as a second barrier layer. A second via is formed on the second barrier layer using photolithography and etching processes. The position, shape, and size of the second via correspond to the position, cross-sectional shape, and size of the P-type region. Then, ions are implanted into the N-type drift layer using the second barrier layer as a barrier structure to form the P+ region. The P+ region spacer is located above the P-type region.

[0042] In fabricating the gate layer, photoresist is first coated to form a third barrier layer, followed by photolithography and etching processes to form a third via. Then, a gate trench with a depth of approximately 1.5 μm is etched in the N-type drift layer using dry etching (such as ICP-RIE). A 200 nm thick SiO2 layer is thermally grown within the trench as an insulating dielectric layer, and then filled with polysilicon or metal material using chemical vapor deposition (CVD) to form the gate layer, which is a planar gate structure.

[0043] In the preparation of the source layer, a fourth barrier layer is first formed, then a fourth via is etched, and metals such as titanium / nickel are sputtered to form the source layer.

[0044] Combination Figure 6 , Figure 7 as well as Figure 17 As shown, in one embodiment of the present invention, after the step of removing the second barrier layer and before the step of forming the third barrier layer on the N-type drift layer, the method further includes: S610: A fifth barrier layer is formed on the N-type drift layer, and a fifth through-hole is formed by etching the fifth barrier layer; S620: Ion implantation is performed on the region of the N-type drift layer exposed to the fifth via to form a P-type well region, which is adjacent to the P+ region; S630: Remove the fifth barrier layer and form a sixth barrier layer on the N-type drift layer, and etch a sixth through-hole in the sixth barrier layer; S640: Ion implantation is performed on the region of the N-type drift layer exposed to the sixth via to form an N+ source region. The N+ source region is located on the side of the P-type well region away from the substrate, and the sixth barrier layer is removed.

[0045] In this embodiment, when fabricating the P-type well region, a layer of photoresist is first coated on the surface of the N-type drift layer as a fifth barrier layer. A fifth via is then formed on the fifth barrier layer using photolithography and etching processes. The position, shape, and size of the fifth via correspond to the position, cross-sectional shape, and size of the P-type well region. Then, ions are implanted into the N-type drift layer using the fifth barrier layer as a barrier structure to form the P-type well region. The P-type well region is arranged adjacent to both the P+ and N+ regions.

[0046] In fabricating the N+ source region, a photoresist layer is first coated on the surface of the N-type drift layer as a sixth barrier layer. A sixth via is then formed on the sixth barrier layer using photolithography and etching processes. The position, shape, and size of the sixth via correspond to the position, cross-sectional shape, and size of the N+ source region. Next, ions are implanted into the P-type well region using the sixth barrier layer as a barrier structure to form the N+ source region. The N+ source region is enclosed by the P-type well region and located on the side of the P-type well region facing away from the substrate, while simultaneously connecting to the source layer.

[0047] Combination Figure 8 , Figure 9 as well as Figure 18 As shown, in one embodiment of the present invention, after the step of forming the N+ source region and before the step of forming the third blocking layer on the N-type drift layer, the method further includes: S650: A seventh barrier layer is formed on the N-type drift layer, and a seventh via is formed by etching the seventh barrier layer; S660: Ion implantation is performed on the region of the N-type drift layer exposed to the seventh via to form an N+ region, which is adjacent to the P-type trap region; S670: Remove the seventh barrier layer and form an eighth barrier layer on the N-type drift layer; S680: An eighth through-hole is formed by etching the eighth barrier layer; S690: Ion implantation is performed in the N+ region exposed to the eighth via to form a P-type shielding layer. The P-type shielding layer is located on the side of the N+ region away from the substrate. The eighth barrier layer is then removed.

[0048] In this embodiment, after forming the N+ source region, the N+ region and the P-type shielding layer are fabricated. First, photoresist is coated as a seventh barrier layer. A seventh via is etched into the seventh barrier layer using photolithography and etching processes. The position, shape, and size of the seventh via correspond to the position, cross-sectional shape, and size of the N+ region. Then, using an ion implantation process, ions are implanted into the N-type drift layer, with the seventh barrier layer serving as the barrier structure, to form the N+ region.

[0049] For example, using nitrogen ions, the injection energy is controlled at 120 keV and the dose is 2e. 14 cm -2 Formed with a depth of approximately 2 μm and a doping concentration of 8e 17 cm -3 The N+ region is then de-photoresisted. Next, photoresist is recoated as the eighth barrier layer. The P-type shielding layer position is defined in the N+ region using photolithography and etching processes, and the eighth via is etched. Then, a P-type shielding layer is formed by ion implantation, for example using aluminum ions, with the implantation energy controlled at 100 keV and the dose at 8e. 13 cm -3 It forms a doping depth of approximately 1.5 μm and a doping concentration of 3e. 17 cm -3 The P-type shielding layer. The P-type shielding layer wraps the N+ region from the bottom and sides, with only the top in contact with the insulating dielectric layer.

[0050] Combination Figure 10 As shown, in one embodiment of the present invention, after the step of forming the P-type shielding layer and before the step of forming the third barrier layer on the N-type drift layer, the method further includes: A ninth barrier layer is formed on the N-type drift layer, and a ninth via is formed by etching the ninth barrier layer; An insulating dielectric layer is deposited within the ninth through hole.

[0051] In this embodiment, an insulating dielectric layer is prepared before fabricating the gate layer. Photoresist is coated as a ninth barrier layer, and a ninth via corresponding to the position of the insulating dielectric layer is etched onto the ninth barrier layer using photolithography and etching processes. Then, a 200nm thick silicon dioxide (SiO2) layer is grown as an insulating dielectric layer within the ninth via and above the N-type drift layer using thermal oxidation or CVD processes. After this step, the gate layer is fabricated, ensuring that the insulating dielectric layer covers the side of the gate layer facing the substrate.

[0052] Combination Figures 13 to 15As shown, after all front-side processes are completed, a photoresist or protective layer is first coated on one side of the source layer. Then, the wafer is flipped, and the substrate is thinned from the initial 1.5 μm to 0.6 μm using chemical mechanical polishing (CMP) or grinding. This thinning process is a key step in reducing the on-resistance of this invention. The thicker initial substrate (1.5 μm) ensures mechanical strength and thermal stability during the long epitaxial growth process (35 μm), preventing wafer warping or breakage. After epitaxy, the substrate thickness is reduced to 0.6 μm through the thinning process, significantly shortening the current path from the drain metal to the N-type drift layer, significantly reducing substrate resistance, and thus reducing the overall on-resistance of the device. After thinning, the back side of the substrate is cleaned and surface-treated, and then the drain metal is deposited to form the source layer using electron beam evaporation or sputtering. After deposition, a high-temperature alloying treatment is performed in a nitrogen or argon atmosphere at 800-1000°C, causing the drain metal to react with SiC to form a low-resistance ohmic contact. The resulting drain has extremely low contact resistance, ensuring the high performance of the device. This "thick-then-thin" process strategy cleverly resolves the contradiction between the support of thick epitaxial layers and low contact resistance.

[0053] The above description is merely an exemplary embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention specification and drawings under the technical concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: The substrate is N-type doped, and one side of the substrate is a drain layer; An N-type drift layer is disposed on the other side of the substrate. The N-type drift layer contains two spaced-apart P-type regions that extend in a direction perpendicular to the substrate and are in contact with the substrate. The N-type drift layer also includes two P+ regions, which extend in a direction perpendicular to the substrate. Each P+ region is spaced apart from the P-type region on the side away from the substrate in a direction perpendicular to the substrate. A source layer, wherein the source layer is disposed on the side of the N-type drift layer opposite to the substrate; and A gate layer, which is used to control the opening or closing of the conductive channel from the source layer to the drain layer.

2. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor device further includes an N+ region located on the side of the gate layer facing the substrate layer and on the side of the N-type drift layer away from the substrate.

3. The semiconductor device as described in claim 2, characterized in that, The semiconductor device further includes a P-type shielding layer disposed between the N+ layer and the N-type drift layer, the P-type shielding layer enclosing the N+ region.

4. The semiconductor device as described in claim 3, characterized in that, The semiconductor device further includes an N+ source region and a P-type well region; The N+ source region is located between the source layer and the N-type drift layer. The N+ source region is connected to the source layer and is adjacent to the P+ region. The P-type well region surrounds the outer periphery of the N+ source region and is adjacent to the P-type shielding layer.

5. The semiconductor device as claimed in claim 4, characterized in that, The substrate is a silicon carbide substrate, and the doping concentration of the substrate is 2-8e. 18 cm -3 ; And / or, the doping concentration of the N-type drift layer is 1-5e 17 cm -3 ; And / or, the doping concentration of the P-type region is 1-5e 17 cm -3 ; And / or, the doping concentration of the P-type shielding layer is 1-5e 17 cm -3 ; And / or, the doping concentration of the P-type well region is 6-10e 16 cm -3 ; And / or, the doping concentration of the N+ region is 6-10e 17 cm -3 ; And / or, the doping concentration of the N+ source region is 2-8e 18 cm -3 ; And / or, the doping concentration of the P+ region is 1-5e 19 cm -3 .

6. The semiconductor device as claimed in claim 4, characterized in that, The thickness of the substrate is 0.6 μm; And / or, the thickness of the N-type drift layer is 30-40 μm; And / or, the width of the P-type region is 1 μm and the thickness is greater than 12 μm; And / or, the width of the P-type shielding layer is 1 μm and the thickness is 1.5 μm; And / or, the maximum width of the P-type well region is 1.3 μm and the maximum thickness is 1.5 μm; And / or, the maximum width of the N+ region is 2μm and the maximum thickness is 2μm; And / or, the width of the N+ source region is 1 μm and the thickness is 300 nm; And / or, the width of the P+ region is 1 μm and the thickness is 12 μm.

7. A method for fabricating a semiconductor device as described in any one of claims 1 to 6, characterized in that, The preparation method includes the following steps: An N-type drift layer is formed on the substrate; A first barrier layer is formed on the N-type drift layer, and two first vias are etched in the first barrier layer to expose the N-type drift layer; Ion implantation is performed on the region of the N-type drift layer exposed to the first via to form a P-type region, which is connected to the substrate; Remove the first blocking layer to form an N-type drift layer covering the P-type region; A second barrier layer is formed on the N-type drift layer, and two second vias are etched in the second barrier layer; Ion implantation is performed on the region of the N-type drift layer exposed to the second via to form two P+ regions, the P+ regions being spaced apart in the direction perpendicular to the substrate from the P-type region, and the second barrier layer is removed. A third barrier layer is formed on the N-type drift layer, and a third via is etched into the third barrier layer; A gate layer is deposited within the third via; Remove the third barrier layer and form a fourth barrier layer on the N-type drift layer; A fourth via is formed by etching the fourth barrier layer, and a source layer is deposited within the fourth via.

8. The preparation method according to claim 7, characterized in that, After the step of removing the second barrier layer and before the step of forming the third barrier layer on the N-type drift layer, the method further includes: A fifth barrier layer is formed on the N-type drift layer, and a fifth via is etched into the fifth barrier layer; Ion implantation is performed on the region of the N-type drift layer exposed to the fifth via to form a P-type well region, which is adjacent to the P+ region; Remove the fifth barrier layer and form a sixth barrier layer on the N-type drift layer, and etch a sixth through-hole in the sixth barrier layer; An N+ source region is formed by ion implantation in the area of ​​the N-type drift layer exposed to the sixth via. The N+ source region is located on the side of the P-type well region away from the substrate. The sixth barrier layer is then removed.

9. The preparation method according to claim 8, characterized in that, After the step of forming the N+ source region and before the step of forming the third barrier layer on the N-type drift layer, the method further includes: A seventh barrier layer is formed on the N-type drift layer, and a seventh via is etched in the seventh barrier layer; An N+ region is formed by ion implantation in the area of ​​the N-type drift layer exposed to the seventh via, and the N+ region is disposed adjacent to the P-type well region. Remove the seventh barrier layer and form an eighth barrier layer on the N-type drift layer; An eighth through-hole is formed by etching the eighth barrier layer; A P-type shielding layer is formed by ion implantation in the region of the N+ region exposed to the eighth via, the P-type shielding layer being located on the side of the N+ region away from the substrate, and the eighth barrier layer is removed.

10. The preparation method according to claim 9, characterized in that, After the step of forming the P-type shielding layer and before the step of forming the third barrier layer on the N-type drift layer, the method further includes: A ninth barrier layer is formed on the N-type drift layer, and a ninth via is etched in the ninth barrier layer; An insulating dielectric layer is deposited within the ninth through hole.

Images