Silicon carbide semiconductor device and preparation method thereof
By employing a split gate structure and a thickened gate oxide layer in silicon carbide MOSFETs, the problems of high gate oxide electric field and high interface state density are solved, thereby improving the switching speed and reliability of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-10
- Publication Date
- 2026-03-13
AI Technical Summary
Silicon carbide MOSFETs generate a high gate oxide electric field region at the top of the JFET region, leading to gate oxide reliability issues, and the high interface state density limits the current carrying capacity of the device.
A split gate structure is adopted, including a first sub-gate oxide layer and a second sub-gate oxide layer. The second sub-gate oxide layer is located above the JFET region and coincides with the projection of the JFET region. The split gate is located on both sides of the second sub-gate oxide layer to reduce gate-drain parasitic capacitance and form a thickened gate oxide layer above the JFET region to avoid high gate oxide electric field.
This improves the switching speed of silicon carbide semiconductor devices, reduces switching losses, and enhances the reliability of gate oxide, thus solving the problem of poor device reliability.
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Figure CN121665636A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing, and more specifically, to a silicon carbide semiconductor device and a method for its fabrication. Background Technology
[0002] Currently, there are effective techniques for reducing the gate-drain parasitic capacitance of MOSFETs in silicon-based power devices, improving switching speed and reducing switching losses. However, these solutions for silicon-based devices have not yet been widely adopted in silicon carbide MOSFETs. This is because silicon carbide MOSFETs generate a high gate oxide electric field region at the top of the JFET region during operation, leading to gate oxide reliability issues. Furthermore, the interface state density of silicon carbide MOSFETs is two orders of magnitude higher than that of silicon-based MOSFETs, which limits the electron mobility of the inversion layer, resulting in reduced current carrying capacity.
[0003] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention
[0004] The main objective of this application is to provide a silicon carbide semiconductor device and its fabrication method, so as to solve the problem of poor reliability of silicon carbide semiconductor devices in the prior art.
[0005] To achieve the above objectives, according to one aspect of this application, a silicon carbide semiconductor device is provided, comprising: a substrate including a base and an epitaxial layer, the epitaxial layer being located on one side of the substrate, and the surface of the epitaxial layer facing away from the substrate being a first surface; a plurality of source region structures spaced apart in the epitaxial layer, and the surface of the source region structures facing away from the substrate being located in the first surface; a JFET region located in the epitaxial layer and between the plurality of source region structures; a gate structure and a plurality of first insulating layers, all located on the side of the epitaxial layer facing away from the substrate, the gate structure including a gate oxide layer and a split gate, and the plurality of... The first insulating layer is spaced apart and located on the side of the gate oxide layer away from the substrate. The gate oxide layer includes a first sub-gate oxide layer and a second sub-gate oxide layer. The second sub-gate oxide layer is located on the side of the first sub-gate oxide layer away from the epitaxial layer and coincides with the projection of the JFET region on the first surface. In a first direction, the width of the second sub-gate oxide layer is smaller than the width of the first sub-gate oxide layer. The split gate is located on both sides of the second sub-gate oxide layer and the first insulating layer located on the side of the second sub-gate oxide layer away from the substrate in the first direction. The first direction is perpendicular to the thickness direction of the silicon carbide semiconductor device.
[0006] Optionally, the source region structure includes a first doped region, a second doped region, a third doped region, and a fourth doped region, wherein the second doped region, the third doped region, and the fourth doped region are all located on the side of the first doped region away from the substrate, the third doped region is located between the second doped region and the fourth doped region, the second doped region is in contact with the JFET region, the first doped region and the fourth doped region have a first doping type, and the second doped region and the third doped region have a second doping type.
[0007] Optionally, the doping concentration of the second doped region is 5E15~1E16 cm⁻¹. -3 The doping concentration of the first doped region is 5E18~8E18 cm⁻¹ -3 .
[0008] Optionally, the JFET region includes a fifth doped region, and the silicon carbide semiconductor device further includes a fifth doped region, the fifth doped region being located in the JFET region and having a portion of the JFET region between it and the source region structure, the fifth doped region having a first doping type.
[0009] Optionally, the projection of the fifth doped region onto the first surface is located in the central region of the projection of the JFET region onto the first surface.
[0010] Optionally, the split gate contacts the side surface of the second sub-gate oxide layer opposite to the substrate and the side surface of the second sub-gate oxide layer in the first direction.
[0011] Optionally, the silicon carbide semiconductor device further includes a gate electrode, a source electrode, and a drain electrode, wherein the source electrode is located on both sides of the gate oxide layer in a first direction and is in contact with the source region structure, a portion of the first insulating layer is located between the source electrode and the split gate, the gate electrode is located on the side of the split gate away from the substrate, and the drain electrode is located on the side of the substrate away from the epitaxial layer.
[0012] According to another aspect of this application, a method for fabricating a silicon carbide semiconductor device is provided. The method includes: providing a substrate, the substrate comprising a substrate and an epitaxial layer, the epitaxial layer being located on one side of the substrate, and the surface of the epitaxial layer facing away from the substrate being a first surface; forming a plurality of spaced source region structures in the epitaxial layer, the surface of the source region structures facing away from the substrate being located in the first surface; forming JFET regions in the epitaxial layer between the plurality of source region structures; forming a gate structure and a plurality of first insulating layers on the side of the epitaxial layer facing away from the substrate, the gate structure comprising a gate oxide layer and a split gate, the plurality of first insulating layers being spaced apart on the side of the gate oxide layer facing away from the substrate. On one side of the substrate, the gate oxide layer includes a first sub-gate oxide layer and a second sub-gate oxide layer. The second sub-gate oxide layer is located on the side of the first sub-gate oxide layer away from the epitaxial layer and coincides with the projection of the JFET region on the first surface. The width of the second sub-gate oxide layer in a first direction is smaller than that of the first sub-gate oxide layer. The split gate is located on both sides of the second sub-gate oxide layer and the first insulating layer located on the side of the second sub-gate oxide layer away from the substrate in a first direction. The first direction is perpendicular to the thickness direction of the silicon carbide semiconductor device. Source electrodes are formed on both sides of the gate oxide layer in the first direction. The source electrodes are in contact with the source region structure, and a drain electrode is formed on the side of the substrate away from the epitaxial layer.
[0013] Optionally, the step of forming a plurality of spaced source region structures in the epitaxial layer includes: performing a first ion implantation in the epitaxial layer to form a plurality of spaced first doped regions; performing a second ion implantation in the first doped regions to form a fourth doped region; performing a third ion implantation in the second doped region and a portion of the first doped region to form a third doped region; and performing a fourth ion implantation in the second doped region and a portion of the first doped region to form a fourth doped region, wherein the first doped region, the second doped region, the third doped region, and the fourth doped region form the source region structure.
[0014] Optionally, the step of forming a gate structure on the side of the epitaxial layer away from the substrate includes: forming a first sub-gate oxide layer and a second sub-gate oxide layer on the epitaxial layer, and etching the second sub-gate oxide layer to retain the second sub-gate oxide layer located above the JFET region; forming the split gate on the side of the first sub-gate oxide layer and the second sub-gate oxide layer away from the substrate, wherein the split gate is in contact with the surface of the second sub-gate oxide layer away from the substrate.
[0015] Using the technical solution of this application, the gate structure of the silicon carbide semiconductor device is located on the side of the epitaxial layer away from the substrate. The gate structure includes a gate oxide layer and a split gate. The gate oxide layer includes a first sub-gate oxide layer and a second sub-gate oxide layer. The second sub-gate oxide layer is located on the side of the first sub-gate oxide layer away from the epitaxial layer and coincides with the projection of the JFET region on the first surface. The width of the second sub-gate oxide layer in the first direction is smaller than that of the first sub-gate oxide layer. The split gate is located on both sides of the first insulating layer in the first direction, which is located on the side of the second sub-gate oxide layer away from the substrate. By setting a split gate, the area of the gate and drain of the device can be reduced, thereby lowering the gate-drain parasitic capacitance of the silicon carbide semiconductor device, which improves the switching speed and reduces the switching loss of the device. Furthermore, a gate oxide layer structure with a first sub-gate oxide layer and a second sub-gate oxide layer is formed above the JFET region. The projection of the second sub-gate oxide layer coincides with the projection of the JFET region on the first surface. The thickened gate oxide layer can avoid the high gate oxide electric field problem caused by the high gate oxide electric field region above the JFET region without a split gate when the silicon carbide semiconductor device is working, which is a problem of poor gate oxide electric field in related technologies. This improves gate oxide reliability and solves the problem of poor reliability of silicon carbide semiconductor devices. Attached Figure Description
[0016] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:
[0017] Figure 1 A schematic cross-sectional view of a silicon carbide semiconductor device according to an embodiment of this application is shown.
[0018] Figure 2 A schematic flowchart of a method for fabricating a silicon carbide semiconductor device according to an embodiment of this application is shown;
[0019] Figure 3 It shows Figure 2 In the preparation method, a cross-sectional view of the substrate after the formation of the first doped region is shown.
[0020] Figure 4 It shows in Figure 3 A cross-sectional view of the substrate after the second doped region is formed in the first doped region;
[0021] Figure 5 It shows in Figure 4 A cross-sectional view of the substrate after the third and fourth doped regions are formed in the first and second doped regions;
[0022] Figure 6 It shows in Figure 5 A cross-sectional view of the substrate after the gate structure is formed on the structure;
[0023] Figure 7 It shows in Figure 6 A cross-sectional view of the substrate after the first insulating layer is formed on the gate structure;
[0024] Figure 8 It shows the Figure 7 Cross-sectional view of the substrate after etching the first insulating layer;
[0025] Figure 9 The output characteristic curves of this application and conventional silicon carbide semiconductor devices at a gate voltage of 18V are shown.
[0026] The above figures include the following reference numerals:
[0027] 10. Substrate; 11. Substrate; 12. Epitaxial layer; 20. Source region structure; 21. First doped region; 22. Second doped region; 23. Third doped region; 24. Fourth doped region; 30. JFET region; 31. Fifth doped region; 40. Gate structure; 41. Gate oxide layer; 411. First sub-gate oxide layer; 412. Second sub-gate oxide layer; 42. Split gate; 50. First insulating layer; 60. Gate electrode; 70. Source electrode; 80. Drain electrode. Detailed Implementation
[0028] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.
[0029] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.
[0030] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0031] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.
[0032] As described in the background section, if the existing technology for reducing gate-drain parasitic capacitance of silicon-based semiconductor devices is applied to silicon carbide semiconductor devices, a high gate oxide electric field region will be generated at the top of the JFET region when the silicon carbide semiconductor device is working, thereby causing gate oxide reliability problems. In order to solve the problem of poor reliability of silicon carbide semiconductor devices in the prior art, the embodiments of this application provide a silicon carbide semiconductor device and its fabrication method.
[0033] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
[0034] A silicon carbide semiconductor device according to an embodiment of this application, such as Figure 1As shown, it includes: a substrate 10, comprising a substrate 11 and an epitaxial layer 12, the epitaxial layer 12 being located on one side of the substrate 11, the surface of the epitaxial layer 12 facing away from the substrate 11 being a first surface; a plurality of source region structures 20, spaced apart within the epitaxial layer 12, the surface of the source region structures 20 facing away from the substrate 11 being located within the first surface; a JFET region 30, located within the epitaxial layer 12 and between the plurality of source region structures 20; a gate structure 40 and a plurality of first insulating layers 50, all located on the side of the epitaxial layer 12 facing away from the substrate 11, the gate structure 40 including a gate oxide layer 41 and a split gate 42, the plurality of first insulating layers 50 spaced apart. On the side of the gate oxide layer 41 away from the substrate 10, the gate oxide layer 41 includes a first sub-gate oxide layer 411 and a second sub-gate oxide layer 412. The second sub-gate oxide layer 412 is located on the side of the first sub-gate oxide layer 411 away from the epitaxial layer 12 and coincides with the projection of the JFET region 30 on the first surface. The width of the second sub-gate oxide layer 412 in the first direction X is smaller than the width of the first sub-gate oxide layer 411. The split gate 42 is located on both sides of the second sub-gate oxide layer 412 and the first insulating layer 50 located on the side of the second sub-gate oxide layer 412 away from the substrate 10 in the first direction X. The first direction X is perpendicular to the thickness direction of the silicon carbide semiconductor device.
[0035] By setting a split gate, the area of the gate and drain of the device can be reduced, thereby lowering the gate-drain parasitic capacitance of the silicon carbide semiconductor device, which improves the switching speed and reduces the switching loss of the device. Furthermore, a gate oxide layer structure with a first sub-gate oxide layer and a second sub-gate oxide layer is formed above the JFET region. The projection of the second sub-gate oxide layer coincides with the projection of the JFET region on the first surface. The thickened gate oxide layer can avoid the high gate oxide electric field problem caused by the high gate oxide electric field region above the JFET region without a split gate when the silicon carbide semiconductor device is working, which is a problem of poor gate oxide electric field in related technologies. This improves gate oxide reliability and solves the problem of poor reliability of silicon carbide semiconductor devices.
[0036] In the above embodiments, the thickness of the epitaxial layer can be 5~10 μm, and the doping concentration can be 8E15~2E16 cm⁻¹. -3 The substrate can be a silicon carbide substrate with a thickness of 3~5 μm and a doping concentration of 1E19~1E20 cm⁻¹. -3 The gate oxide layer can be made of silicon dioxide. The thickness of the first sub-gate oxide layer can be 40-50 nm, the thickness of the second sub-gate oxide layer can be 60-100 nm, and the thickness of the gate oxide layer formed directly above the JFET region can be 100-150 nm. The split gate can be made of polysilicon with a thickness of 600-800 nm.
[0037] In some alternative implementations, such as Figure 1As shown, the source region structure 20 includes a first doped region 21, a second doped region 22, a third doped region 23, and a fourth doped region 24. The second doped region 22, the third doped region 23, and the fourth doped region 24 are all located on the side of the first doped region 21 facing away from the substrate 11. The third doped region 23 is located between the second doped region 22 and the fourth doped region 24. The second doped region 22 is in contact with the JFET region 30. The first doped region 21 and the fourth doped region 24 have a first doping type, while the second doped region 22 and the third doped region 23 have a second doping type. Using the second doped region 22, which has the opposite doping type to the first doped region 21, as the device channel allows the channel to transition from an inversion layer electron to an accumulation layer electron, thus reducing the specific on-resistance and conduction loss during operation.
[0038] In the above optional embodiments, the second doped region 22 has a shallower doping concentration and the doping type is opposite to that of the first doped region 21. The first doped region 21 can be P-type, while the second doped region 22 can be N-type. The second doped region 22, as a shallow N-type doped region, converts the channel conducting electrons from P-type doped inversion layer electrons to N-type doped accumulation layer electrons, serving as the channel region of the silicon carbide semiconductor device. After applying a sufficient positive gate voltage, enough electrons accumulate on the surface of the second doped region 22, forming a channel connecting the drain and gate regions of the silicon carbide semiconductor device. At this time, the N-type accumulation layer electron mobility is 1.25 times that of the conventional P-type inversion layer electron mobility, effectively reducing the channel resistance. Due to Coulomb scattering and surface roughness scattering, the inversion layer electrons have an electron mobility approximately 25% lower than the accumulation layer electrons. Therefore, using the N-type shallow doped region as the channel can reduce the specific on-resistance and conduction loss during operation (by about 10%), thereby reducing the chip area and manufacturing cost, and avoiding the high cost problem of silicon carbide semiconductor device applications.
[0039] In the above embodiments, the first doping type can be N-type doping or P-type doping, and the second doping type can be P-type doping or N-type doping. For example, the first doping type is N-type doping and the second doping type is P-type doping, or the first doping type is P-type doping and the second doping type is N-type doping. The N-type doping element can be any one of pentavalent elements, including phosphorus (P), arsenic (As), and antimony (Sb), and the P-type doping element can be any one of trivalent elements, including boron (B), aluminum (Al), and gallium (Ga). This application does not impose specific limitations.
[0040] In some alternative embodiments, the doping concentration of the second doped region is 5E15~1E16 cm⁻¹. -3 The doping concentration of the first doped region is 5E18~8E18 cm⁻¹ -3By setting a first doped region (high-concentration P+ doped region) below the second doped region (shallow N-type doped region), the second doped region is pinched off by the depletion region when the device is not turned on, ensuring that the device remains normally off. This solves the leakage problem caused by the second doped region acting as a channel, ensuring that this solution meets the application requirements of conventional application scenarios. Setting the doping concentration of the first and second doped regions to the ranges mentioned above ensures that the PN junction distribution formed by the entire second and first doped regions is approximately a single-sided abrupt junction. At this point, setting the thickness of the second doped region to 0.1~0.3μm ensures that the second doped region is pinched off by the depletion region at zero bias.
[0041] In some alternative implementations, such as Figure 1 As shown, the silicon carbide semiconductor device also includes a fifth doped region 31, which is located within the JFET region 30 and partially intersects with the source region structure 20. The fifth doped region 31 has a first doping type. The fifth doped region 31 can pinch off the current path through the depletion region when the device is not turned on, ensuring the device remains normally off. This solves the normally-on problem caused by the second doped region acting as a channel, ensuring that the threshold voltage is positive during application. The doping concentration of the fifth doped region 31 can be 5E18~8E18 cm⁻¹. -3 The doping concentration in region 30 of the JFET can be 5E16~1E17 cm⁻¹ -3 Designing the spacing between the fifth doped region 31 and the second doped region 22 to be 0.1~0.3μm ensures that the current path is pinched off by the depletion region. Forming the fifth doped region 31 in the JFET region 30 can further shield the high gate oxide electric field generated by the split gate in the region above the JFET region 30 without a split gate, thus improving the gate oxide reliability of devices with split gate structures.
[0042] In the above optional embodiments, the width Y of the depletion region can be calculated by the relationship between the width of the depletion region of the single-sided abrupt junction and the doping concentration, the width of the fifth doped region is X, and the width of the JFET region in the first direction is X+2. Yμm.
[0043] In some alternative implementations, such as Figure 1 As shown, the projection of the fifth doped region 31 on the first surface is located in the central region of the projection of the JFET region 30 on the first surface. Placing the fifth doped region 31 in the central region of the JFET region 30 can better shield the high gate oxide electric field generated by setting the split gate in the region above the JFET region 30 without the split gate, and the distance from the two source region structures 20 is equal, which can ensure that the current path of both source region structures 20 is pinched off by the depletion region.
[0044] In some alternative implementations, such as Figure 1 As shown, the split gate 42 contacts the side surface of the second sub-gate oxide layer 412 facing away from the substrate 11 and the side surface of the second sub-gate oxide layer 412 in the first direction X. The width of the contact area above the split gate 42 and the second sub-gate oxide layer 412 is less than 0.2 μm. When the split gate 42 contacts both the upper surface and the side surface of the gate oxide layer 41, the charge can be distributed more uniformly, thereby reducing the local electric field strength below the thickened gate oxide layer 41 in the JFET region 30. This helps to improve gate oxide reliability, especially in high-voltage applications, effectively preventing gate oxide breakdown and degradation.
[0045] In some alternative implementations, such as Figure 1 As shown, the silicon carbide semiconductor device also includes a gate electrode 60, a source electrode 70, and a drain electrode 80. The source electrode 70 is located on both sides of the gate oxide layer 41 in the first direction X and contacts the source region structure 20. A portion of the first insulating layer 50 is located between the source electrode 70 and the split gate 42. The gate electrode 60 is located on the side of the split gate 42 facing away from the substrate 11, and the drain electrode 80 is located on the side of the substrate 11 facing away from the epitaxial layer 12. The first insulating layer 50 is used to prevent a source short circuit between the split gate 42 and the source electrode 70. When the voltage at the gate electrode 60 is lower than a threshold voltage, the channel disappears, preventing current flow and putting the device into a cutoff state. The source electrode 70 provides the source signal required for device operation. It forms a good ohmic contact with the source region structure 20 to reduce the contact resistance of the source electrode 70 and ensure that the source current can flow into or out of the device efficiently. The drain electrode 80 collects the current from the epitaxial layer 12 through the channel to the drain region, forming a drain current path. Similarly, the drain electrode 80 will form a good ohmic contact with the substrate 11 to ensure a low-impedance current path, thereby reducing the drain contact resistance and improving the overall efficiency of the device.
[0046] In the above optional embodiments, the second doped region is replaced with a lightly doped P-type implanted region, and the N-type accumulation layer is no longer used as the conductive channel; instead, a P-type inversion layer is used. The lightly doped P-type implanted region has a lower doping concentration than the first doped region, making it easier for the conductive channel to invert at the same gate voltage, thereby increasing the forward channel current. After introducing the lightly doped P-type implanted region, the device no longer needs to pinch off the current through a heavily doped P-region, so the fifth doped region can be removed. Removing the fifth doped region further reduces the JFET region resistance, improving the device's forward current capability. This structure simplifies the fabrication process while retaining the split gate.
[0047] In the above optional embodiments, N-type shallow doping is performed between the two source regions to form a JFET implantation region, and the doping concentration can be 7E15~1E16 cm⁻¹. -3This embodiment can effectively reduce the JFET region 30 resistance caused by the fifth doped region, thereby reducing the specific on-resistance and conduction loss of the device.
[0048] Figure 2 This is a flowchart of a method for fabricating a silicon carbide semiconductor device according to an embodiment of this application. Figures 2 to 9 As shown, the method includes the following steps:
[0049] Step S1, a substrate 10 is provided. The substrate 10 includes a substrate 11 and an epitaxial layer 12. The epitaxial layer 12 is located on one side of the substrate 11, and the surface of the epitaxial layer 12 facing away from the substrate 11 is the first surface.
[0050] Specifically, the thickness of the epitaxial layer 12 can be 5~10 μm, and the doping concentration can be 8E15~2E16 cm⁻¹. -3 The substrate 11 can be a silicon carbide substrate with a thickness of 3~5 μm and a doping concentration of 1E19~1E20 cm⁻¹. -3 The higher doping concentration of the epitaxial layer 12 compared to the substrate 11 can improve the device's breakdown voltage. Taking a 1200V SiC MOSFET as an example, the thickness of the epitaxial layer 12 can be set to 10μm, and the doping concentration can be 1E16cm⁻¹. -3 The calculated width Y of the small depletion region is 0.5 μm.
[0051] Step S2: A plurality of spaced source region structures 20 are formed in the epitaxial layer 12, and the surface of the source region structure 20 facing away from the substrate 11 is located in the first surface.
[0052] Specifically, the source region structure 20 includes a first doped region 21, a second doped region 22, a third doped region 23, and a fourth doped region 24. The second doped region 22 has a shallower doping concentration and the opposite doping type to the first doped region 21. As a shallow N-type doped region, the second doped region 22 converts the channel conducting electrons from the inversion layer electrons of the P-type doped region to the accumulation layer electrons of the N-type doped region, serving as the channel region of the silicon carbide semiconductor device. After applying a sufficient positive gate voltage, enough electrons accumulate on the surface of the second doped region 22, forming a channel connecting the drain and gate regions of the silicon carbide semiconductor device, which can reduce the specific on-resistance and conduction loss during operation.
[0053] Step S3: A JFET region 30 is formed in the epitaxial layer 12 between multiple source region structures 20;
[0054] Specifically, the doping concentration of JFET region 30 can be 5E16~1E17 cm⁻¹. -3The JFET region 30 has a fifth doped region 31 with the opposite doping type. By forming the JFET region 30 between the source region structures 20, the on-resistance of the device can be further reduced. At the same time, by adjusting the doping concentration of the fifth doped region 31 of the JFET region 30, the normally open problem caused by the second doped region 22 as a channel can be solved.
[0055] In step S4, a gate structure 40 and a plurality of first insulating layers 50 are formed on the side of the epitaxial layer 12 away from the substrate 11. The gate structure 40 includes a gate oxide layer 41 and a split gate 42. The plurality of first insulating layers 50 are spaced apart on the side of the gate oxide layer 41 away from the substrate 10. The gate oxide layer 41 includes a first sub-gate oxide layer 411 and a second sub-gate oxide layer 412. The second sub-gate oxide layer 412 is located on the side of the first sub-gate oxide layer 411 away from the epitaxial layer 12 and coincides with the projection of the JFET region 30 on the first surface. The width of the second sub-gate oxide layer 412 in the first direction X is smaller than the width of the first sub-gate oxide layer 411. At least a portion of the split gate 42 is located on both sides of the second sub-gate oxide layer 412 and the first insulating layer 50 located on the side of the second sub-gate oxide layer 412 away from the substrate 10 in the first direction X. The first direction X is perpendicular to the thickness direction of the silicon carbide semiconductor device.
[0056] Specifically, the gate oxide layer 41 can be made of silicon dioxide, the thickness of the first sub-gate oxide layer 411 can be 40-50 nm, the thickness of the second sub-gate oxide layer 412 can be 60-100 nm, and the thickness of the gate oxide layer 41 formed directly above the JFET region 30 can be 100-150 nm. The split gate 42 can be made of polysilicon and has a thickness of 600-800 nm. The use of the split gate structure reduces the face-to-face area between the split gate 42 and the drain, thereby reducing the gate-drain parasitic capacitance. The thickening of the second sub-gate oxide layer 412 can effectively shield the high electric field generated above the JFET region 30 due to the absence of the split gate 42, preventing the device from being damaged.
[0057] In step S5, source electrodes 70 are formed on both sides of the gate oxide layer 41 in the first direction X. The source electrodes 70 are in contact with the source region structure 20, and a drain electrode 80 is formed on the side of the substrate 11 away from the epitaxial layer 12.
[0058] Specifically, the source electrode 70 and the drain electrode 80 can be made of any one or more of Ag, Cu and Ti, which can give the device good conductivity.
[0059] The silicon carbide semiconductor device fabricated according to the above-described embodiments of this application has a split gate, which reduces the area of the gate drain, lowers the gate drain parasitic capacitance, thereby improving the switching speed and reducing the switching loss. Furthermore, a gate oxide layer structure with a first sub-gate oxide layer and a second sub-gate oxide layer is formed above the JFET region. The second sub-gate oxide layer coincides with the projection of the JFET region onto the first surface. This thickened gate oxide layer avoids the high gate oxide electric field problem caused by the high gate oxide electric field region above the JFET region where there is no split gate during operation, thus improving gate oxide reliability and solving the problem of poor reliability of silicon carbide semiconductor devices in related technologies.
[0060] like Figures 3 to 5 As shown, step S2 above, the step of forming multiple spaced source region structures 20 in the epitaxial layer 12, includes:
[0061] like Figure 3 As shown, a first ion implantation is performed in the epitaxial layer 12 to form multiple spaced first doped regions 21; the doping type of the first doped regions 21 is opposite to that of the epitaxial layer 12, and the doping concentration can be 5E18~8E18 cm⁻¹. -3 Before forming the first doped region 21, the same type of ion implantation can be performed in the central region of the epitaxial layer 12 to form the JFET region 30. The implantation concentration of the JFET region 30 can be 5E16~1E17 cm⁻¹. -3 Then, while forming the first doped region 21, a fifth doped region 31 can also be formed in the JFET region 30. Taking a 1200V SiC MOSFET as an example, the width X of the fifth doped region 31 can be 0.5μm, and the doping concentration can be 1E18cm³. -3 The spacing between the first doped regions 21 (the width of the JFET region 30) is 1.5 μm, and the first doped region 21 can be 1E18 cm. -3 .
[0062] like Figure 4 As shown, a second ion implantation is performed in the first doped region 21 to form the second doped region 22. Setting the thickness of the second doped region 22 to 0.1~0.3 μm ensures that the second doped region is pinched off by the depletion region at zero bias. The doping concentration of the second doped region 22 can be between 5E15 and 1E16 cm⁻¹. -3 This ensures that the entire PN junction distribution is approximately a single-sided abrupt junction; and the depth of the second doped region 22 can be calculated using the minimum depletion region width of the single-sided abrupt junction. Taking a 1200V SiC MOSFET as an example, if the doping concentration of the fifth doped region 31 is 1E18cm⁻¹ -3 The doping concentration of the second doped region 22 is 1E16cm.-3 The depth of the second doped region 22 is calculated to be 0.3 μm.
[0063] like Figure 5 As shown, a third ion implantation is performed in the second doped region 22 and part of the first doped region 21 to form the third doped region 23. A fourth ion implantation is performed in the second doped region 22 and part of the first doped region 21 to form the fourth doped region 24. The first doped region 21, the second doped region 22, the third doped region 23, and the fourth doped region 24 form the source region structure 20. A self-aligned process can be used for N-type heavy doping implantation to form the third doped region 23. The third doped region 23 is connected to the source point to form a current path. The fourth doped region 24 is used to prevent parasitic BJT transistor turn-on failure during operation. To form better N-type and P-type ohmic contacts, the doping concentration of the third doped region 23 can be 1E19~1E20 cm⁻¹. -3 The doping concentration of the third doped region 23 can be 1E19~1E20 cm⁻¹ -3 After the formation of the third doped region 23 and the fourth doped region 24, the remaining width of the first doped region 21 is 0.3~0.5μm, which is the final channel width. After all the above implantation processes are completed, ion implantation activation annealing is performed to prepare the gate oxide layer.
[0064] Taking a 1200V SiC MOSFET as an example, the N-type doping concentration in the third doped region 23 is 1E20cm⁻¹. -3 The doping concentration of the fourth doped region 24 is 1E19cm⁻¹. -3 The fourth doped region 24 and the third doped region 23 have a depth of 0.5 μm, and the remaining width of the first doped region 21 is 0.5 μm, which ensures that the channel will not be penetrated.
[0065] like Figure 6 As shown, the step of forming the gate structure 40 on the side of the epitaxial layer 12 away from the substrate 11 includes:
[0066] A first sub-gate oxide layer 411 and a second sub-gate oxide layer 412 are formed on the epitaxial layer 12, and the second sub-gate oxide layer 412 is etched to retain the second sub-gate oxide layer 412 located above the JFET region 30; at this time, the thickness of the gate oxide layer 41 (the total thickness of the first sub-gate oxide layer 411 and the second sub-gate oxide layer 412) is 100nm~150nm. The second sub-gate oxide layer 412 can be dry etched, and finally a gate oxide layer 41 with a thickness of 100~150nm is formed directly above the JFET region 30, serving as the gate oxide thickening region at the top of the JFET region 30. The thickness of the first sub-gate oxide layer 411 directly above the source structure can be 40~50nm.
[0067] Taking a 1200V SiC MOSFET as an example, in this embodiment, the thickness of the first sub-gate oxide layer 411 is 40nm, and the thickness of the gate oxide layer 41 directly above the JFET region 30 is 100nm.
[0068] A split gate 42 is formed on the side of the first sub-gate oxide layer 411 and the second sub-gate oxide layer 412 facing away from the substrate 11. The split gate 42 is in partial contact with the surface of the second sub-gate oxide layer 412 facing away from the substrate 11. After the top polysilicon is deposited, dry etching is performed to remove the polysilicon at the top of the JFET region 30, thereby breaking the top polysilicon to form the split gate 42. This structure helps to reduce the parasitic gate leakage capacitance of the device, thereby improving the switching speed of the device and reducing the switching loss of the device. The thickness of the split gate 42 can be 600nm~800nm, and the width of the split gate 42 over the second sub-gate oxide layer 412 does not exceed 0.2μm, which can reduce the leakage current of the device.
[0069] Taking a 1200V SiC MOSFET as an example, in this embodiment, the thickness of the split gate 42 is 600nm, and the width of the split gate 42 over the second sub-gate oxide layer 412 is 0.15μm.
[0070] like Figure 1 , Figure 7 and Figure 8 As shown, after forming the split gate 42, the fabrication method further includes: depositing an insulating material on the split gate 42 and the gate oxide layer 41 to form a first insulating layer 50. The first insulating layer 50 serves as an interlayer dielectric region to prevent gate-source short circuits. An opening is made in the region of the first insulating layer 50 used to fabricate the source electrode, followed by a front-side metallization process to finally form the gate electrode 60 and the source electrode 70. A back-side metallization process is then performed on the substrate 11 to form the drain electrode 80. The thicknesses of the gate electrode 60, the source electrode 70, and the drain electrode 80 can be 0.5 μm to 1 μm, ultimately forming a silicon carbide semiconductor device.
[0071] Taking a 1200V SiC MOSFET as an example, the thickness of the gate electrode 60 and the drain electrode 80 is 0.5μm, and the thickness of the source electrode 70 is 1μm.
[0072] In this embodiment, the output characteristic curve at a gate voltage of 18V is as follows: Figure 9 As shown, it can be observed that in the linear region, the output current of this embodiment (patent) is 10% to 15% higher than that of traditional silicon carbide semiconductor devices. This demonstrates that this embodiment can indeed reduce the on-resistance of the device.
[0073] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0074] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A silicon carbide semiconductor device, characterized in that, include: The substrate includes a substrate and an epitaxial layer, wherein the epitaxial layer is located on one side of the substrate, and the surface of the epitaxial layer facing away from the substrate is a first surface; Multiple source region structures are spaced apart in the epitaxial layer, and the surface of the source region structure facing away from the substrate is located in the first surface; The JFET region is located in the epitaxial layer and between the plurality of source region structures; A gate structure and multiple first insulating layers are located on the side of the epitaxial layer away from the substrate. The gate structure includes a gate oxide layer and a split gate. The multiple first insulating layers are spaced apart on the side of the gate oxide layer away from the substrate. The gate oxide layer includes a first sub-gate oxide layer and a second sub-gate oxide layer. The second sub-gate oxide layer is located on the side of the first sub-gate oxide layer away from the epitaxial layer and coincides with the projection of the JFET region on the first surface. In a first direction, the width of the second sub-gate oxide layer is smaller than the width of the first sub-gate oxide layer. The split gate is located on both sides of the second sub-gate oxide layer and the first insulating layer located on the side of the second sub-gate oxide layer away from the substrate in the first direction. The first direction is perpendicular to the thickness direction of the silicon carbide semiconductor device.
2. The silicon carbide semiconductor device according to claim 1, characterized in that, The source region structure includes a first doped region, a second doped region, a third doped region, and a fourth doped region. The second doped region, the third doped region, and the fourth doped region are all located on the side of the first doped region away from the substrate. The third doped region is located between the second doped region and the fourth doped region. The second doped region is in contact with the JFET region. The first doped region and the fourth doped region have a first doping type, and the second doped region and the third doped region have a second doping type.
3. The silicon carbide semiconductor device according to claim 2, characterized in that, The doping concentration of the second doped region is 5E15~1E16 cm⁻¹ -3 The doping concentration of the first doped region is 5E18~8E18 cm⁻¹ -3 .
4. The silicon carbide semiconductor device according to claim 1, characterized in that, The silicon carbide semiconductor device further includes a fifth doped region located within the JFET region and having a portion of the JFET region between it and the source region structure. The fifth doped region has a first doping type.
5. The silicon carbide semiconductor device according to claim 4, characterized in that, The projection of the fifth doped region onto the first surface is located in the central region of the projection of the JFET region onto the first surface.
6. The silicon carbide semiconductor device according to claim 1, characterized in that, The split gate contacts the side surface of the second sub-gate oxide layer opposite to the substrate and the side surface of the second sub-gate oxide layer in the first direction.
7. The silicon carbide semiconductor device according to claim 1, characterized in that, The silicon carbide semiconductor device further includes a gate electrode, a source electrode, and a drain electrode, wherein the source electrode is located on both sides of the gate oxide layer in a first direction and is in contact with the source region structure, a portion of the first insulating layer is located between the source electrode and the split gate, the gate electrode is located on the side of the split gate away from the substrate, and the drain electrode is located on the side of the substrate away from the epitaxial layer.
8. A method for fabricating a silicon carbide semiconductor device, characterized in that, The method for preparing the silicon carbide semiconductor device according to any one of claims 1 to 7 comprises: A substrate is provided, the substrate comprising a substrate and an epitaxial layer, the epitaxial layer being located on one side of the substrate, and the surface of the epitaxial layer facing away from the substrate being a first surface; Multiple spaced source region structures are formed in the epitaxial layer, and the surface of the source region structure facing away from the substrate is located in the first surface; A JFET region is formed in the epitaxial layer between the multiple source region structures; A gate structure and a plurality of first insulating layers are formed on the side of the epitaxial layer away from the substrate. The gate structure includes a gate oxide layer and a split gate. The plurality of first insulating layers are spaced apart on the side of the gate oxide layer away from the substrate. The gate oxide layer includes a first sub-gate oxide layer and a second sub-gate oxide layer. The second sub-gate oxide layer is located on the side of the first sub-gate oxide layer away from the epitaxial layer and coincides with the projection of the JFET region on the first surface. In a first direction, the width of the second sub-gate oxide layer is smaller than the width of the first sub-gate oxide layer. The split gate is located on both sides of the second sub-gate oxide layer and the first insulating layer located on the side of the second sub-gate oxide layer away from the substrate in the first direction. The first direction is perpendicular to the thickness direction of the silicon carbide semiconductor device. Source electrodes are formed on both sides of the gate oxide layer in the first direction, the source electrodes are in contact with the source region structure, and a drain electrode is formed on the side of the substrate away from the epitaxial layer.
9. The preparation method according to claim 8, characterized in that, The step of forming a plurality of spaced source region structures in the epitaxial layer includes: A first ion implantation is performed in the epitaxial layer to form multiple spaced first doped regions; A second ion implantation is performed in the first doped region to form a second doped region; A third ion implantation is performed in the second doped region and a portion of the first doped region to form a third doped region. A fourth ion implantation is performed in the second doped region and a portion of the first doped region to form a fourth doped region. The first doped region, the second doped region, the third doped region, and the fourth doped region form the source region structure.
10. The preparation method according to claim 8, characterized in that, The step of forming a gate structure on the side of the epitaxial layer opposite to the substrate includes: The first sub-gate oxide layer and the second sub-gate oxide layer are formed on the epitaxial layer, and the second sub-gate oxide layer is etched to retain the second sub-gate oxide layer located above the JFET region; The split gate is formed on the side of the first sub-gate oxide layer and the second sub-gate oxide layer away from the substrate, and the split gate is in contact with the surface of the second sub-gate oxide layer away from the substrate.