Embedded flash memory structure based on vertical auxiliary gate and dynamic programming method thereof
By adding an auxiliary gate and a high-K dielectric layer below the floating gate, the channel potential is dynamically modulated, solving the problems of low programming accuracy and high voltage erasure in traditional embedded flash memory structures, thus achieving more efficient programming and improved reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-23
- Publication Date
- 2026-03-13
AI Technical Summary
Traditional embedded flash memory structures suffer from low programming precision, the need for high voltage for erasure, and poor reliability, especially in terms of compatibility issues with advanced processes.
An auxiliary gate and a high-K dielectric layer are added below the floating gate. The channel potential is modulated by the auxiliary gate, which changes the effective electric field of the floating gate. A dynamic programming method is used to monitor the channel current in real time to adjust the voltage, thereby optimizing the programming accuracy and erase voltage.
It improves programming efficiency, reduces the operating voltage required for erasing, suppresses noise, and significantly enhances data retention and reliability.
Smart Images
Figure CN121665637A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of memory technology, and in particular to an embedded flash memory structure based on a vertical auxiliary gate and its dynamic programming method. Background Technology
[0002] Embedded flash memory (eFlash) is non-volatile memory integrated on a chip, used to store program code and process data in products such as microcontrollers (MCUs). Its typical characteristics include: targeting low-power and high-reliability scenarios; supporting wireless / firmware updates such as OTA / FOTA; and widespread use in IoT devices, smart cards, wearables, factory automation, and automotive electronics, providing space for processors to store program code, constant data, configuration parameters, and user data. The basic unit of eFlash is a floating-gate transistor.
[0003] With the development of logic technology, traditional floating-gate eFlash faces significant challenges. Traditional stacked-gate eFlash requires high voltage (>18V) for erasure, which is incompatible with advanced processes and results in low programming accuracy (wide Vth distribution, σ>0.15V). Separate-gate eFlash has a large cell area (>0.04μm² at the 22nm node), relies on sharp-corner electric fields for erasure, and has poor reliability (10...). 5 (Fails after one cycle).
[0004] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention
[0005] The purpose of this invention is to provide an embedded flash memory structure based on a vertical auxiliary gate and its dynamic programming method to solve the problem of low programming accuracy.
[0006] To address the aforementioned technical problems, this invention provides an embedded flash memory structure based on a vertical auxiliary gate, comprising a substrate, a channel oxide layer covering the top surface of the substrate, a floating gate distributed on the channel oxide layer, and a control gate disposed on the floating gate. The channel oxide layer and the floating gate are stacked sequentially from bottom to top with an auxiliary gate, a high-k dielectric layer, and an interlayer oxide layer. During programming and erasing, the channel potential is modulated by applying a voltage to the auxiliary gate, thereby changing the effective electric field of the floating gate.
[0007] Preferably, a gate oxide layer is further disposed between the floating gate and the control gate.
[0008] Preferably, it further includes a source region and a drain region disposed in the substrate, the source region and the drain region being disposed on both sides of the bottom of the channel oxide layer.
[0009] Preferably, the auxiliary gate is made of polycrystalline silicon.
[0010] Preferably, the material of the interlayer oxide layer is silicon oxide.
[0011] A dynamic programming method for an embedded flash memory structure based on a vertical auxiliary gate, employing the aforementioned embedded flash memory structure based on a vertical auxiliary gate.
[0012] Preferably, during programming, an initial voltage is applied to the control gate, the channel current of the auxiliary gate is monitored in real time, and the channel current is compared with the threshold current.
[0013] When the channel current is less than the threshold current, the voltage applied to the control gate is gradually reduced.
[0014] When the channel current is greater than or equal to the threshold current, the voltage applied to the control gate is maintained;
[0015] Programming is terminated when the channel current is less than or equal to the preset current.
[0016] Preferably, it includes:
[0017] Voltages are applied to the control gate, auxiliary gate, and drain region respectively to raise the potential of the drain region, thus performing programming operations;
[0018] Apply voltage to the auxiliary gate to pull down the floating gate potential, float the source region, drain region, and control gate, and perform the erase operation.
[0019] Preferably, an 8V voltage is applied to the control gate, a 1.5V voltage is applied to the auxiliary gate, and a 5V voltage is applied to the drain region for programming operations.
[0020] Preferably, a voltage of 2V is applied to the auxiliary gate to float the source region, drain region, and control gate for erasure operation.
[0021] In the embedded flash memory structure based on a vertical auxiliary gate provided by the present invention, an auxiliary gate and a high-K dielectric layer are added below the floating gate. The channel potential is modulated by the auxiliary gate, the effective electric field of the floating gate is changed, the programming efficiency is improved, the working voltage required for erasure is reduced, noise is suppressed, and the data retention capability is significantly improved.
[0022] During programming or writing, a voltage is applied to the auxiliary gate to raise the drain potential, enhance hot electron injection efficiency, and reduce hot carrier damage. During erasing, a voltage is applied to the auxiliary gate, and the auxiliary gate positively couples down the floating gate potential, achieving low-voltage FN tunneling (Fowler-Nordheim tunneling), reducing the erase voltage by 55%, and allowing for controllable erase depth. During reading, a micro-voltage on the auxiliary gate stabilizes the channel and suppresses noise. The introduced high-k dielectric layer also improves data retention.
[0023] The dynamic programming method for the embedded flash memory structure based on the vertical auxiliary gate provided by this invention belongs to the same inventive concept as the embedded flash memory structure based on the vertical auxiliary gate provided by this invention. Therefore, the dynamic programming method for the embedded flash memory structure based on the vertical auxiliary gate provided by this invention has at least all the advantages of the embedded flash memory structure based on the vertical auxiliary gate provided by this invention, which will not be repeated here. Attached Figure Description
[0024] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:
[0025] Figure 1 This is a schematic diagram of the gate structure programming and erasing of existing eFlash technology;
[0026] Figure 2 This is a schematic diagram of an embodiment of the present invention;
[0027] Figure 3 This is a schematic diagram of programming writing according to an embodiment of the present invention;
[0028] Figure 4 This is a schematic diagram of the erasure process according to an embodiment of the present invention;
[0029] Figure 5 This is a flowchart of dynamic voltage compensation according to an embodiment of the present invention.
[0030] In the picture,
[0031] 100, Substrate; 101, Source region; 102, Drain region; 200, Channel oxide layer; 300, Auxiliary gate; 400, High-K dielectric layer; 500, Interlayer oxide layer; 600, Floating gate; 700, Gate oxide layer; 800, Control gate. Detailed Implementation
[0032] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.
[0033] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; the term “at least two” is generally used to mean “two or more”; furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first," "second," and "third" may explicitly or implicitly include one or at least two of those features. The term "proximal" typically refers to the end closer to the operator, and the term "distal" typically refers to the end closer to the patient. "One end" and "the other end," as well as "proximal" and "distal," generally refer to two corresponding parts, including not only endpoints. The terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections or electrical connections; they can be direct connections or indirect connections through an intermediate medium; they can be internal connections between two elements or interactions between two elements. Furthermore, as used in this invention, the placement of one element on another element generally only indicates a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of another element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0034] The inventors discovered that the core principle of eFlash is to use the amount of charge stored in the floating gate 600 to change the threshold voltage of the transistor, thereby distinguishing between the "0" and "1" states. The operation is based on Fowler-Nordheim tunneling and hot electron injection. Conventional stacked-gate eFlash and split-gate eFlash both have certain problems during programming, writing, and erasing, such as... Figure 1 The stacked gate eFlash shown has the problems of requiring high voltage for erasure and low programming accuracy, while the discrete gate eFlash has the problems of large cell area and poor reliability.
[0035] Based on this, the core idea of the present invention is to add an auxiliary gate below the floating gate of the vertical gate structure, and to change the effective electric field of the floating gate by dynamically modulating the channel potential through the auxiliary gate, thereby improving programming efficiency, reducing the erase working voltage, suppressing noise, and significantly improving data retention capability.
[0036] For details, please refer to Figures 2-5 This is a schematic diagram of an embodiment of the present invention. Figure 2 As shown, an embedded flash memory structure based on a vertical auxiliary gate includes a substrate 100, the top surface of which is covered with a channel oxide layer 200. A floating gate 600 is also distributed on the channel oxide layer 200, and a control gate 800 is also disposed on the floating gate 600. An auxiliary gate 300, a high-k dielectric layer 400, and an interlayer oxide layer 500 are stacked sequentially from bottom to top on the channel oxide layer 200 and the floating gate 600. During programming and erasing, the channel potential is modulated by applying a voltage to the auxiliary gate 300, thereby changing the effective electric field of the floating gate 600.
[0037] This application proposes a novel dual-gate eFlash, which adopts a vertically stacked auxiliary gate configuration. An auxiliary gate 300 and a high-K dielectric layer 400 are added below the floating gate 600. The auxiliary gate 300 modulates the channel potential, changes the effective electric field of the floating gate 600, improves programming efficiency, reduces the operating voltage required for erasure, suppresses noise, and significantly improves data retention capability.
[0038] During programming or writing, a voltage is applied to the auxiliary gate 300 to raise the potential of the drain region 102, enhancing hot electron injection efficiency and reducing hot carrier damage. During erasing, a voltage is applied to the auxiliary gate 300, which positively couples down the floating gate 600 potential, achieving low-voltage FN tunneling (Fowler-Nordheim tunneling). The erase voltage is reduced by 55% (compared to the traditional 18V), and the erase depth is controllable. During reading, the auxiliary gate 300 uses a micro-voltage to stabilize the channel and suppress noise. The introduced high-k dielectric layer 400 also improves data retention.
[0039] Even better, during the reading process, a small voltage, i.e. a micro-voltage, can also be applied to the auxiliary gate 300 to stabilize the channel and suppress noise.
[0040] The interlayer oxide layer 500 and the high-K dielectric layer 400, which exist sequentially between the floating gate 600 and the auxiliary gate 300, form a double-protection isolation of charge barrier and potential decoupling: the interlayer oxide layer 500 is used to increase the potential barrier and prevent electrons from leaking from the floating gate 600 to the auxiliary gate 300, while the high-K dielectric layer 400 ensures that the charge state of the floating gate 600 is not directly affected by the voltage of the auxiliary gate 300.
[0041] The high-k dielectric layer 400 uses a high-k material (high dielectric constant material). High-k materials are insulating materials with a dielectric constant higher than that of traditional silicon dioxide (SiO2, k=3.9), and are mainly used to replace the gate dielectric layer and capacitor dielectric layer. The introduction of high-k materials can increase the physical thickness for the same capacitance (e.g., HfO2 has k=25, and its thickness can be 3-6 times that of SiO2), thereby suppressing leakage current and improving device reliability.
[0042] like Figure 2 As shown, a gate oxide layer 700 is also disposed between the floating gate 600 and the control gate 800. It also includes a source region 101 and a drain region 102 disposed in the substrate 100, the source region 101 and the drain region 102 being respectively disposed on both sides of the bottom of the channel oxide layer 200.
[0043] Specifically, the auxiliary gate 300 is made of polycrystalline silicon. The interlayer oxide layer 500 is made of silicon oxide. The channel oxide layer 200 is also made of silicon oxide.
[0044] Compared to traditional structures, this application adds a vertically stacked gate structure and a High-k dielectric layer. The channel potential is dynamically modulated by the auxiliary gate 300, which rises to +3.2V during erasure. A silicon oxide layer and a high-k dielectric layer 400 are sequentially located between the floating gate 600 and the auxiliary gate 300, forming a double-protection isolation: charge barrier: the high barrier (3.1eV) of silicon oxide prevents electrons from leaking from the floating gate 600 to the auxiliary gate 300; potential decoupling: the high-k dielectric layer 400 ensures that the charge state of the floating gate 600 is not directly affected by the voltage of the auxiliary gate 300.
[0045] Based on the same technical concept, this application also provides a dynamic programming method for an embedded flash memory structure based on a vertical auxiliary gate, employing the aforementioned embedded flash memory structure based on a vertical auxiliary gate. The embedded flash memory structure based on a vertical auxiliary gate includes a substrate 100, the top surface of which is covered with a channel oxide layer 200. A floating gate 600 is distributed on the channel oxide layer 200, and a control gate 800 is disposed on the floating gate 600. An auxiliary gate 300, a high-k dielectric layer 400, and an interlayer oxide layer 500 are stacked sequentially from bottom to top on the channel oxide layer 200 and the floating gate 600. During programming and erasing, the channel potential is modulated by applying a voltage to the auxiliary gate 300, thereby changing the effective electric field of the floating gate 600. The interlayer oxide layer 500 and the high-k dielectric layer 400, which exist sequentially between the floating gate 600 and the auxiliary gate 300, form a double-protection isolation of charge blocking and potential decoupling.
[0046] A gate oxide layer 700 is also disposed between the floating gate 600 and the control gate 800. It also includes a source region 101 and a drain region 102 disposed in the substrate 100, the source region 101 and the drain region 102 being respectively disposed on both sides of the bottom of the channel oxide layer 200.
[0047] Specifically, the auxiliary gate 300 is made of polycrystalline silicon. The interlayer oxide layer 500 is made of silicon oxide. The channel oxide layer 200 is also made of silicon oxide.
[0048] like Figure 5As shown, during the programming process, an initial voltage V is applied to the control gate 800. CG The channel current I_AG of the auxiliary gate 300 is monitored in real time, and the channel current I_AG is compared with the threshold current I_th:
[0049] When the channel current I_AG is less than the threshold current I_th, the voltage V applied to the control gate 800 is gradually reduced. CG ;
[0050] When the channel current I_AG is greater than or equal to the threshold current I_th, the voltage V applied to the control gate 800 is maintained. CG ;
[0051] Programming is terminated when the channel current I_AG is less than or equal to the preset current I_min.
[0052] Understandably, by monitoring the channel current I_AG of the auxiliary gate (AG) 300 in real time, the voltage of the control gate (CG) 800 can be intelligently adjusted to improve programming accuracy.
[0053] In one implementation, an initial voltage V is applied to the control gate 800. CG The voltage is 8V, the threshold current I_th (i.e., I_threshold) is set to 50µA, the preset current I_min is 10µA, and the voltage V applied to the control gate 800 is gradually decreased. CG The step decay value is 0.2V, and the voltage applied to the auxiliary gate 300 is 1.5V.
[0054] The steps for programming and erasing the aforementioned embedded flash memory structure include:
[0055] like Figure 3 As shown, voltages are applied to the control gate 800, the auxiliary gate 300 and the drain region 102 respectively to raise the potential of the drain region 102 and perform programming operations. At this time, the source region 101 emits hot electrons, and the auxiliary gate 300 raises the potential of the drain region 102 to enhance the hot electron injection efficiency.
[0056] like Figure 4 As shown, a voltage is applied to the auxiliary gate 300, and the potential of the floating gate 600 is pulled down, so that the source region 101, the drain region 102 and the control gate 800 are floated for erasure operation. At this time, the auxiliary gate 300 positively couples and pulls down the potential of the floating gate 600 to realize FN tunneling. Compared with the traditional 18V voltage, the erasure voltage is reduced by 55% and the erasure depth is controllable.
[0057] Even better, during the reading process, a small voltage, i.e. a micro-voltage, is also applied to the auxiliary gate 300 to stabilize the channel and suppress noise.
[0058] Specifically, an 8V voltage is applied to the control gate 800, a 1.5V voltage is applied to the auxiliary gate 300, and a 5V voltage is applied to the drain region 102 for programming operations. A 2V voltage is applied to the auxiliary gate 300 to float the source region 101, drain region 102, and control gate 800 for erasing operations.
[0059] In the embedded flash memory structure and dynamic programming method based on a vertical auxiliary gate provided by this invention, during programming or writing, a voltage is applied to the auxiliary gate 300 to raise the potential of the drain region 102, enhance the hot electron injection efficiency, and reduce hot carrier damage. During erasing, a voltage is applied to the auxiliary gate 300, and the auxiliary gate 300 positively couples down the floating gate 600 potential to achieve low-voltage FN tunneling (Fowler-Nordheim tunneling), reducing the erase voltage by 55% (compared to the traditional 18V), and the erase depth is controllable. During reading, a small voltage is applied to the auxiliary gate 300 to stabilize the channel and suppress noise. During the reading process, a small voltage can also be applied to the auxiliary gate 300 to stabilize the channel and suppress noise.
[0060] The interlayer oxide layer 500 and the high-K dielectric layer 400, which exist sequentially between the floating gate 600 and the auxiliary gate 300, form a double-protection isolation of charge barrier and potential decoupling: the interlayer oxide layer 500 is used to increase the potential barrier and prevent electrons from leaking from the floating gate 600 to the auxiliary gate 300, while the high-K dielectric layer 400 ensures that the charge state of the floating gate 600 is not directly affected by the voltage of the auxiliary gate 300.
[0061] Furthermore, by monitoring the channel current I_AG of the auxiliary gate (AG) 300 in real time, the voltage of the control gate (CG) 800 can be intelligently adjusted to improve programming accuracy.
[0062] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.
Claims
1. An embedded flash memory structure based on a vertical auxiliary gate, characterized in that, The device includes a substrate, the top surface of which is covered with a channel oxide layer. Floating gates are distributed on the channel oxide layer, and a control gate is disposed on the floating gates. An auxiliary gate, a high-k dielectric layer, and an interlayer oxide layer are stacked sequentially from bottom to top on the channel oxide layer and the floating gates. During programming and erasing, the channel potential is modulated by applying a voltage to the auxiliary gate, thereby changing the effective electric field of the floating gate.
2. The embedded flash memory structure based on a vertical auxiliary gate according to claim 1, characterized in that, A gate oxide layer is also disposed between the floating gate and the control gate.
3. The embedded flash memory structure based on a vertical auxiliary gate according to claim 1, characterized in that, It also includes a source region and a drain region disposed in the substrate, wherein the source region and the drain region are disposed on both sides of the bottom of the channel oxide layer.
4. The embedded flash memory structure based on a vertical auxiliary gate according to claim 1, characterized in that, The auxiliary gate is made of polycrystalline silicon.
5. The embedded flash memory structure based on a vertical auxiliary gate according to claim 1, characterized in that, The material of the interlayer oxide layer is silicon dioxide.
6. A dynamic programming method for an embedded flash memory structure based on a vertical auxiliary gate, characterized in that, The embedded flash memory structure based on a vertical auxiliary gate as described in any one of claims 1-5 is adopted.
7. The dynamic programming method for an embedded flash memory structure based on a vertical auxiliary gate according to claim 6, characterized in that, During programming, an initial voltage is applied to the control gate, the channel current of the auxiliary gate is monitored in real time, and the channel current is compared with the threshold current. When the channel current is less than the threshold current, the voltage applied to the control gate is gradually reduced. When the channel current is greater than or equal to the threshold current, the voltage applied to the control gate is maintained; Programming is terminated when the channel current is less than or equal to the preset current.
8. The dynamic programming method for an embedded flash memory structure based on a vertical auxiliary gate according to claim 6, characterized in that, include: Voltages are applied to the control gate, auxiliary gate, and drain region respectively to raise the potential of the drain region, thus performing programming operations; Apply voltage to the auxiliary gate to pull down the floating gate potential, float the source region, drain region, and control gate, and perform the erase operation.
9. The dynamic programming method for an embedded flash memory structure based on a vertical auxiliary gate according to claim 8, characterized in that, A voltage of 8V is applied to the control gate, a voltage of 1.5V is applied to the auxiliary gate, and a voltage of 5V is applied to the drain region to perform programming operations.
10. The dynamic programming method for an embedded flash memory structure based on a vertical auxiliary gate according to claim 8, characterized in that, A voltage of 2V is applied to the auxiliary gate to float the source region, drain region, and control gate for erasure operation.