Semiconductor device

Abstract

A semiconductor device includes a substrate, a semiconductor layer, a source electrode, a drain electrode, and a gate electrode. The semiconductor layer is disposed on the substrate. The source electrode directly contacts the semiconductor layer. The drain electrode directly contacts the semiconductor layer. The gate electrode is located between the source electrode and the drain electrode, wherein the gate electrode is in direct contact with the semiconductor layer. The semiconductor device is designed to be a breakdown type N-type metal semiconductor field effect transistor (Punch-Through nMES; according to the semiconductor device, the P-type metal semiconductor field effect transistor (PTnMES) is designed, and the source electrode and the drain electrode of the semiconductor device are designed to be Schottky contact, so that the semiconductor device can be a single carrier device without additional doping, and the semiconductor device can have current characteristics similar to those of a P-type metal semiconductor field effect transistor under the condition that the size does not need to be increased.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] Traditional metal semiconductor field effect transistors (MESFETs) are widely used in radio frequency (RF) and microwave applications. However, traditional MESFETs still face many limitations in their applications, such as submillimeter-wave and megahertz radiation. In recent years, broadband MESFETs have attracted much attention due to their high-temperature stability and low loss characteristics at high frequencies.

[0003] However, MESFETs with broadband materials still cannot solve the electron-hole carrier mobility mismatch between N-type and P-type metal-semiconductor field-effect transistors (nMES) in complementary metal-semiconductor (CMES), thus failing to improve CMES performance. Furthermore, since the hole mobility in pMES is much smaller than the electron mobility in nMES, CMES requires increased element width in pMES, leading to larger wiring and higher process costs. Therefore, providing a MES that solves these problems remains a key research goal for those in the field. Summary of the Invention

[0004] This disclosure provides a semiconductor device in some embodiments. By designing this semiconductor device as a punch-through nMES (PTnMES) and designing the source and drain electrodes of this semiconductor device as Schottky contacts, this semiconductor device can be a single-carrier device that does not require additional doping. Furthermore, by adjusting the Schottky barrier of the source and drain electrodes, this semiconductor device can have current characteristics similar to those of a p-type metal-semiconductor field-effect transistor without increasing its size. This semiconductor device can have good carrier mobility, and by combining the carrier mobility matching of nMES and PTnMES, the performance of the CMES is improved. Therefore, this semiconductor device can have good reliability and stability in RF applications and microwave circuit applications.

[0005] This disclosure provides a semiconductor device in some embodiments. The semiconductor device includes a substrate, a semiconductor layer, a source electrode, a drain electrode, and a gate electrode. The semiconductor layer is disposed on the substrate. The source electrode directly contacts the semiconductor layer. The drain electrode directly contacts the semiconductor layer. The gate electrode is located between the source electrode and the drain electrode, wherein the gate electrode directly contacts the semiconductor layer.

[0006] According to some embodiments disclosed herein, the gate electrode forms a Schottky contact with the semiconductor layer.

[0007] According to some embodiments disclosed herein, the Schottky barrier height between the gate electrode and the semiconductor layer is less than the Schottky barrier height between the source electrode and the semiconductor layer and the Schottky barrier height between the drain electrode and the semiconductor layer.

[0008] According to some embodiments disclosed herein, the semiconductor layer includes a first semiconductor region, a second semiconductor region, and a third semiconductor region. The first semiconductor region is adjacent to the source electrode. The second semiconductor region is adjacent to the drain electrode. The third semiconductor region is located between the first semiconductor region and the second semiconductor region, wherein a doping concentration of the first semiconductor region and the second semiconductor region is higher than a doping concentration of the third semiconductor region.

[0009] According to some embodiments disclosed herein, the first semiconductor region and the second semiconductor region have the same conductivity type.

[0010] According to some embodiments of this disclosure, the gate electrode overlaps the third semiconductor region in a direction perpendicular to the surface of the gate electrode.

[0011] According to some embodiments disclosed herein, the semiconductor device further includes a spacer layer. The spacer layer separates the source electrode or the drain electrode from the semiconductor layer, wherein the spacer layer comprises nanoparticles, semiconductor oxides, or nitrides.

[0012] According to some embodiments disclosed herein, the semiconductor device further includes a dielectric buffer layer. The dielectric buffer layer is located between the semiconductor layer and the gate electrode, wherein the dielectric buffer layer comprises nanoparticles, semiconductor oxides, or nitrides.

[0013] According to some embodiments disclosed herein, the gate electrode, source electrode, and drain electrode comprise the same material.

[0014] According to some embodiments disclosed herein, the material of the gate electrode is different from the material of the source electrode and the material of the drain electrode. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of a semiconductor device according to a partial embodiment of this disclosure;

[0016] Figure 2A for Figure 1 A schematic diagram illustrating the on-state operation of a semiconductor device.

[0017] Figure 2B for Figure 1 A schematic diagram illustrating the operation of a semiconductor device in its off-state;

[0018] Figure 3 This is a schematic diagram of a semiconductor device according to a partial embodiment of this disclosure;

[0019] Figures 4A to 4D A perspective view of various stages of manufacturing a semiconductor device according to a partial embodiment of the present disclosure;

[0020] Figure 5 This is a current relationship diagram of a semiconductor device according to a partial embodiment of the present disclosure.

[0021] [Symbol Explanation]

[0022] 100, 200, 300: Semiconductor devices

[0023] 110: Substrate

[0024] 120, 400: Oxide layer

[0025] 500: Spare layer

[0026] 600: Drain-Source Contact

[0027] 130: Semiconductor layer

[0028] 130A, 130B, 130C, 140A, 150A, 160A: Surface

[0029] 132, 134, 136: Areas

[0030] 140, 220: Source electrode

[0031] 150, 240: Drain electrode

[0032] 160: Gate electrode

[0033] DR1, DR2, DR3, DR23: Depletion Zones

[0034] L SG L G L DG L S :length

[0035] C1, C2, C3, C4, C5, C6: Conditions

[0036] TS :thickness

[0037] I p Breakdown current

[0038] X, Y: Direction Detailed Implementation

[0039] The embodiments disclosed herein are discussed in detail below. However, it should be understood that the embodiments provide many applicable concepts that can be implemented in a wide variety of specific situations. The embodiments discussed and disclosed are for illustrative purposes only and are not intended to limit the scope of this disclosure. The terms "first," "second," etc., used herein are not specifically intended to indicate order or sequence, but are merely used to distinguish components or operations described using the same technical terms.

[0040] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms are used herein to describe the relationship between one element or feature and another illustrated in the figures. Besides the orientation depicted in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly. As used herein, “approximately,” “about,” “nearly,” or “substantially” generally refers to within 20%, 10%, or 5% of a given value or range. The numerical quantities given herein are approximate, meaning that the terms “approximately,” “about,” “nearly,” or “substantially” may be conjectured unless explicitly specified.

[0041] Figure 1 This is a schematic diagram of a semiconductor device 100 according to a partial embodiment of the present disclosure. The semiconductor device 100 includes a substrate 110, an oxide layer 120, a semiconductor layer 130, a source electrode 140, a drain electrode 150, and a gate electrode 160. For ease of explanation, the direction parallel to the gate electric field is defined herein as direction Y, and the direction of the current from the source electrode 140 to the drain electrode 150 is defined as direction X, wherein direction X is perpendicular to direction Y. The substrate 110 may be any suitable substrate. For example, in some embodiments, the substrate 110 may be silicon (Si), silicon carbide (SiC), or a material with high electron mobility. In some embodiments, the oxide layer 120 may be selectively disposed on the substrate 110. For example, in this embodiment, the oxide layer 120 may be silicon dioxide (SiO2). However, it should be noted that the oxide layer 120 may be made of any suitable material, and is not limited thereto.

[0042] In some embodiments, the semiconductor layer 130 may be disposed on the substrate 110 and the oxide layer 120. The semiconductor layer 130 may be any suitable semiconductor layer. For example, in some embodiments, the semiconductor layer 130 may be silicon, germanium, oxide semiconductor, group III-V, group II-VI, or a combination thereof. Furthermore, the semiconductor layer 130 may be doped to different conductivity types using any suitable doping method. For example, in this embodiment, the semiconductor layer 130 may be doped to an N-type bulk semiconductor using in-situ doping, and only the bulk of the semiconductor layer 130 needs to be doped once or the already doped semiconductor material needs to be purchased. This design eliminates the need for any ion implantation process steps for the semiconductor layer 130, which can greatly reduce the number of process steps and thermal costs (e.g., thermal annealing), thereby giving the semiconductor device 100 advantages such as reduced process steps, reduced photomask usage, reduced thermal budget, avoidance of alignment errors, and reduced process costs.

[0043] In some embodiments, the source electrode 140 may comprise any suitable conductive material. For example, in this embodiment, the source electrode 140 may comprise palladium (Pd). In some other embodiments, the source electrode 140 may comprise platinum (Pt), rhodium (Rh), nickel (Ni), ruthenium (Ru), iridium (Ir), osmium (Os), Pd, similar metals, or combinations thereof. Thereby, the source electrode 140 can form a Schottky contact with the semiconductor layer 130 with different Schottky barrier heights to modulate the size of the depletion region DR2 induced by the source electrode 140 (see below). Figure 2A And 2B), wherein the height of the Schottky barrier is positively correlated with the size of the depletion region DR2 (i.e., the higher the height of the Schottky barrier, the larger the size of the depletion region DR2), and the size of the depletion region DR2 is also related to the voltage applied to the source electrode 140 (i.e., a positive bias voltage shrinks the depletion region DR2, and a negative bias voltage increases the depletion region DR2). Furthermore, the source electrode 140 can be positioned at different locations according to functional requirements. For example, in this embodiment, the source electrode 140 is disposed along direction X on surface 130A of the semiconductor layer 130. In some embodiments, the source electrode 140 may also have its endpoints surrounding the semiconductor layer 130 (e.g., the endpoints of the semiconductor layer 130, surfaces 130A, 130B, or 130C) and connected to the tail end of the semiconductor layer 130. For example, the source electrode 140 may directly contact surface 130A and surface 130C of the semiconductor layer 130 (see reference 130A). Figure 4DThe source electrode 140 has a surface 140A that directly contacts the surface 130A of the semiconductor layer 130, wherein the source electrode 140 overlaps the surface 130A of the semiconductor layer 130 in a direction perpendicular to the surface 140A of the source electrode 140. Therefore, this design reduces the impedance at the interface between the source electrode 140 and the semiconductor layer 130 (i.e., surfaces 130A and 140A) and increases the size of the depletion region DR2 induced by the source electrode 140 (see below). Figure 2A And 2B).

[0044] In some embodiments, the drain electrode 150 may comprise any suitable conductive material. For example, the drain electrode 150 may comprise Pd, Pt, Rh, Ni, Ru, Ir, Os, Pd, similar metals, or combinations thereof. In this embodiment, the drain electrode 150 may comprise the same material as the source electrode 140 (e.g., Pd, Pt, Ni, Rh, Ru, Ir, Os, Pd). In some other embodiments, the drain electrode 150 may comprise a different material than the source electrode 140. This allows the drain electrode 150 to form a Schottky contact with the semiconductor layer 130 with different Schottky barrier heights to modulate the size of the depletion region DR3 induced by the drain electrode 150 (see below). Figure 2A And 2B), wherein the size of the depletion region DR3 is positively correlated with the height of the Schottky barrier (i.e., the higher the height of the Schottky barrier, the larger the size of the depletion region DR3), and the size of the depletion region DR3 is also related to the voltage applied to the drain electrode 150 (i.e., a positive bias makes the depletion region DR3 smaller, and a negative bias makes the depletion region DR3 larger). Furthermore, the drain electrode 150 can be disposed at different locations according to functional requirements. For example, in this embodiment, the drain electrode 150 is disposed along direction X on surface 130B of the semiconductor layer 130 opposite to surface 130A. In this embodiment, the drain electrode 150 may also have its endpoints surrounding the semiconductor layer 130 (e.g., the endpoints of the semiconductor layer 130, surfaces 130A and 130B are connected to the tail end of the semiconductor layer 130). For example, in some embodiments, the drain electrode 150 may directly contact surface 130B and surface 130C of the semiconductor layer 130 (see reference 130B). Figure 4D The drain electrode 150 has a surface 150A that directly contacts the surface 130B of the semiconductor layer 130, wherein the drain electrode 150 overlaps the surface 130B of the semiconductor layer 130 in a direction perpendicular to the surface 150A of the drain electrode 150 (i.e., direction X). Therefore, this design reduces the impedance at the junction of the drain electrode 150 and the semiconductor layer 130 (i.e., surfaces 130B and 150A) and increases the size of the depletion region DR3 induced by the drain electrode 150 (see below). Figure 2A And 2B).

[0045] In some embodiments, the gate electrode 160 may comprise any suitable conductive material. For example, the gate electrode 160 may comprise Pd, Ni, Pt, Rh, Ru, Ir, Os, similar metals, or combinations thereof. In this embodiment, the gate electrode 160 may comprise the same material (e.g., Ni or Pd) as the source electrode 140 and the drain electrode 150. In some embodiments, the gate electrode 160 may comprise a different material than the source electrode 140 and the drain electrode 150. Thereby, the gate electrode 160 and the semiconductor layer 130 can form a Schottky contact with different Schottky barrier heights to modulate the size of the depletion region DR1 induced by the gate electrode 160 (see below). Figure 2B The height of the Schottky barrier and the depletion zone DR1 (see subsequent text) Figure 2B The size of DR1 in the depletion region is positively correlated with the height of the Schottky barrier (i.e., the higher the Schottky barrier, the greater the DR1 in the depletion region). Figure 2B The larger the size of the region (DR1), the better (see subsequent text). Figure 2B The size of ) is also related to the voltage applied to the gate electrode 160 (i.e., the positive bias makes the depletion region DR1 (see later) Figure 2B The negative bias reduces the depletion region DR1 (see subsequent text). Figure 2B (Increase). Furthermore, the gate electrode 160 can be positioned at different locations depending on functional requirements. For example, in this embodiment, the gate electrode 160 is disposed along the Y direction on the surface 130C of the semiconductor layer 130. Specifically, the gate electrode 160 is located between the source electrode 140 and the drain electrode 150, and the gate electrode 160 has a surface 160A that directly contacts the surface 130C of the semiconductor layer 130. Therefore, this design can reduce the impedance at the interface between the gate electrode 160 and the semiconductor layer 130 (i.e., surfaces 130C and 160A), and increase the size of the depletion region DR1 induced by the gate electrode 160 (see subsequent descriptions). Figure 2B ).

[0046] The Schottky barrier heights of the gate electrode 160, source electrode 140, and drain electrode 150 can be changed according to functional requirements. For example, in this embodiment, by designing the metal material of the gate electrode 160 to be different from the metal materials of the source electrode 140 and drain electrode 150, the Schottky barrier height of the gate electrode 160 and semiconductor layer 130 can be made smaller than the Schottky barrier heights of the source electrode 140 and semiconductor layer 130, and the Schottky barrier height of the drain electrode 150 and semiconductor layer 130.

[0047] In some embodiments, the gate electrode 160 may be separated from the source electrode 140 and the drain electrode 150. Specifically, in this embodiment, the gate electrode 160 and the source electrode 140 are separated by a length L. SGSeparated. The gate electrode 160 and the drain electrode 150 are separated by a length L. DG Separated. The length L of the gate electrode 160. G The length L between the gate electrode 160 and the source electrode 140 is greater than the length L between the gate electrode 160 and the source electrode 140. SG and the length L between the gate electrode 160 and the drain electrode 150 DG In this embodiment, the length L SG With length L DG Same. In some other embodiments, the length L SG It can be different from the length L DG .

[0048] In some embodiments, one or more spacer layers (not shown) may be selectively disposed between the source electrode 140 and the semiconductor layer 130. For example, in some embodiments, the spacer layer (not shown) may include nanoparticles, semiconductor oxides, or nitrides to enhance the functionality of the semiconductor device 100. In another embodiment, the spacer layer (not shown) may be a van der Waals layer between the semiconductor layer 130 and the gate electrode 160 to enhance the performance of the semiconductor device 100.

[0049] In some embodiments, one or more spacer layers (not shown) may be selectively disposed between the drain electrode 150 and the semiconductor layer 130. For example, in some embodiments, the spacer layer (not shown) may include nanoparticles, semiconductor oxides, or nitrides to enhance the functionality of the semiconductor device 100. In another embodiment, the spacer layer (not shown) may be a van der Waals layer between the semiconductor layer 130 and the drain electrode 150 to enhance the performance of the semiconductor device 100.

[0050] In some embodiments, one or more dielectric buffer layers (not shown) may be selectively disposed between the gate electrode 160 and the semiconductor layer 130. For example, in some embodiments, the dielectric buffer layer (not shown) may include nanoparticles, semiconductor oxides, or nitrides to improve the performance of the semiconductor device 100. In another embodiment, the dielectric buffer layer (not shown) may be a van der Waals layer between the semiconductor layer 130 and the gate electrode 160 to improve the performance of the semiconductor device 100.

[0051] Figure 2A for Figure 1 A schematic diagram of the operation of the semiconductor device 100 in the on-state. First, a negative bias voltage is applied to the gate electrode 160, and the depletion region DR1 induced by the gate electrode 160 (refer to...) Figure 2B The region gradually shrinks in both the X and Y directions, causing the depletion region DR2 induced by the source electrode 140 (refer to...) Figure 2BThe area gradually increases towards the drain electrode 150, causing the depletion region DR3 (refer to) induced by the drain electrode 150 to expand gradually. Figure 2B The voltage gradually increases towards the source electrode 140. Then, after continuously applying a negative bias voltage to the gate electrode 160 for a period of time, the depletion region DR2 induced by the source electrode 140 and the depletion region DR3 induced by the drain electrode 150 will contact and connect (e.g., overlap) to form an elongated depletion region DR23, causing a punch-through effect to occur in the depletion region DR23, thereby generating a breakdown current I. p The energy flows from the source electrode 140 to the drain electrode 150 through the elongated depletion region DR23. Furthermore, the Schottky barrier height of the gate electrode 160 can be set to be smaller than the Schottky barrier heights of the source electrode 140 and the drain electrode 150, so that the depletion region DR1 (refer to...) Figure 2B Smaller (e.g., vacancy region DR1 (reference)) Figure 2B The thickness of the depletion regions DR2 and DR3 in the Y direction is increased to make them larger (e.g., the thickness of the depletion regions DR2 and DR3 in the X direction), thereby achieving better performance of the semiconductor device 100. This allows the gate electrode 160 of the semiconductor device 100 to use a smaller negative bias voltage, facilitating contact (e.g., overlap) between the depletion regions DR2 induced by the source electrode 140 and DR3 induced by the drain electrode 150, thereby generating a breakdown effect during conduction, similar to the breakdown current I. p As indicated. Furthermore, through the breakdown effect, the semiconductor device 100 can possess characteristics similar to a p-type metal semiconductor (pMES) without adjusting the component size of the semiconductor device 100. Accordingly, wiring and manufacturing costs of the semiconductor device 100 can be reduced.

[0052] Figure 2B for Figure 1 This is a schematic diagram illustrating the operation of the semiconductor device 100 in its off state. First, a positive bias voltage is applied to the gate electrode 160, causing the depletion region DR1 induced by the gate electrode 160 to gradually increase along the X and Y directions. This causes the depletion region DR2 induced by the source electrode 140 to gradually decrease towards the source electrode 140, and the depletion region DR3 induced by the drain electrode 150 to gradually decrease towards the drain electrode 150. Next, the positive bias voltage of the gate electrode 160 is made greater than a pinch-off voltage. At this point, the depletion region DR1 induced by the gate electrode 160 separates the depletion region DR2 induced by the source electrode 140 from the depletion region DR3 induced by the drain electrode 150, thereby turning off the semiconductor device 100.

[0053] Furthermore, the length L of the semiconductor layer 130 can be changed.S (Refer to Figure 1 ) and thickness T S (Refer to Figure 1 This involves adjusting the contact between depletion regions DR2 and DR3. For example, in some embodiments, the length L of semiconductor layer 130 can be shortened. S (Refer to Figure 1 This makes it easier for the depletion regions DR2 and DR3 to make contact, and increases the conduction current (I). ON In the design, care should be taken to avoid making the length L of the semiconductor layer 130 too large. S (Refer to Figure 1 The thickness T of the semiconductor layer 130 can be increased to avoid increasing the leakage current of the semiconductor device 100. Alternatively, the thickness T of the semiconductor layer 130 can be increased. S (Refer to Figure 1 ), causing the semiconductor device 100 to conduct current (I) ON ) and shut-off current (I off Therefore, the thickness T of semiconductor layer 130 should be considered in the design. S The thickness should not be too large; an excessively large thickness (T) S This will make it difficult for the depletion region DR1 to separate the depletion regions DR2 and DR3, which will increase the sub-threshold swing of the semiconductor device 100 (e.g., reduce the turn-on and turn-off speed or sensitivity of the semiconductor device 100), and require a larger positive voltage to be applied to the gate electrode 160 to turn off the semiconductor device 100.

[0054] Figure 3 This is a schematic diagram of a semiconductor device 100 according to a partial embodiment of this disclosure. This embodiment is similar to the one described above. Figure 1 The embodiments are similar. Figure 3 and Figure 1The difference lies in that: semiconductor layer 130 includes regions 132, 134, and 136. Region 132 is adjacent to source electrode 140. Region 134 is adjacent to drain electrode 150. Region 136 is located between regions 132 and 134, and gate electrode 160 overlaps region 136 along a direction perpendicular to the surface 160A of gate electrode 160 (i.e., direction Y). Regions 132, 134, and 136 can be formed by any suitable doping method. For example, in some embodiments, regions 132 and 134 can be formed by ion implantation or vapor deposition, and region 136 can be formed by in-situ doping. Furthermore, the doping concentration and conductivity type of regions 132, 134, and 136 can be varied according to functional requirements. For example, in some embodiments, regions 132 and 134 have the same conductivity type, and the conductivity types of regions 132 and 134 are different from those of region 136. For example, region 136 is an N-type semiconductor, and regions 132 and 134 are P-type semiconductors. In some embodiments, the doping concentration of regions 132 and 134 is higher than that of region 136. Regions 132 and 134 with higher doping concentrations can serve as buffer layers for the semiconductor device 100 to improve its stability. In another embodiment, the doping concentration of regions 132 and 134 is lower than that of region 136, allowing the source electrode 140 and drain electrode 150 to form an ohmic contact. In this way, the highly doped region 136 of the semiconductor device 100 can have a larger breakdown current I. p .

[0055] Figures 4A to 4D This is a perspective view of various stages of manufacturing a semiconductor device 300 according to a partial embodiment of the present disclosure. In this embodiment, the semiconductor device 300 may include semiconductor device 100 and semiconductor device 200 to form a complementary metal semiconductor (CMES), wherein semiconductor device 100 is a PTnMES and semiconductor device 200 is an nMES.

[0056] Reference Figure 4A A semiconductor layer 130 is formed on the substrate 110 and the oxide layer 120. For example, in this embodiment, an oxide layer 400 is formed on the oxide layer 120. Then, the oxide layer 400 is etched to form a trench. Then, the semiconductor layer 130 is formed in the trench. For example, in this embodiment, the semiconductor layer 130 can be formed by a sidewall image transfer (SIT) process.

[0057] Receiver, reference Figure 4B A spacer layer 500 is formed on the surface 130C of the semiconductor layer 130, wherein the spacer layer 500 may be a nitride, such as silicon nitride (SiN). For example, in this embodiment, a hard mask (not shown) is formed on the surface 130C of the semiconductor layer 130. Next, an exposure and development process is performed on the hard mask to form an opening on the surface 130C of the semiconductor layer 130 and expose the surface 130C of the semiconductor layer 130, wherein the exposure and development process may include exposure, development, baking, or similar or combined steps. Next, the spacer layer 500 is deposited on the exposed surface 130C of the semiconductor layer 130. Next, a portion of the spacer layer 500 is removed.

[0058] Reference Figure 4C A metal electrode layer is formed on the semiconductor layer 130 using processes such as chemical vapor deposition (CVD). Next, regions for the gate electrode 160, source electrode 140, and drain electrode 150 are defined using a photomask. Then, a portion of the metal electrode layer is removed by etching or similar methods to form the gate electrode 160, source electrode 140, and drain electrode 150, with a spacer layer 500 separating them. In this embodiment, the source electrode 140 and drain electrode 150 may also have their endpoints surrounding the semiconductor layer 130 (e.g., the endpoints, surfaces 130A, 130B, or 130C of the semiconductor layer 130) and connected to the tail end of the semiconductor layer 130 (e.g., the source electrode 140 and drain electrode 150 may directly contact surfaces 130A and 130C of the semiconductor layer 130).

[0059] Furthermore, in this embodiment, the gate electrode 160, source electrode 140, and drain electrode 150 can be formed by patterning a identical metal electrode layer, so that the gate electrode 160, source electrode 140, and drain electrode 150 have the same metal material. In some other embodiments, the gate electrode 160 can be formed by depositing and patterning a first metal electrode layer, and then the source electrode 140 and drain electrode 150 can be formed by depositing and patterning a second metal electrode layer, so that the gate electrode 160 has a different metal material than the source electrode 140 and drain electrode 150. Here, the two gate electrodes 160 respectively form Schottky contacts with the two fin semiconductor layers 130. In this embodiment, the source electrode 140 and drain electrode 150 respectively form Schottky contacts with the fin semiconductor layers 130, thereby forming a semiconductor device 100 having gate Schottky contacts and source / drain Schottky contacts. Next, using processes such as CVD, vapor deposition, and PVD, source electrodes 220 and drain electrodes 240 are formed on both sides of another fin-shaped semiconductor layer 130. In this embodiment, source electrodes 220 and drain electrodes 240 may be made of a different material than source electrodes 140 and drain electrodes 150 (e.g., titanium (Ti)). In this embodiment, source electrodes 220 and drain electrodes 240 may also have their endpoints surrounding the semiconductor layer 130 (e.g., the endpoints, surfaces 130A, 130B, or 130C of the semiconductor layer 130) and connected to the tail end of the semiconductor layer 130 (e.g., source electrodes 220 and drain electrodes 240 may directly contact surfaces 130A and 130C of the semiconductor layer 130). In this way, the source electrode 220 and the drain electrode 240 respectively form ohmic contacts with the fin semiconductor layer 130, thereby forming a semiconductor device 200 having a gate Schottky contact and a source / drain ohmic contact. Next, referring to... Figure 4D A back-end ofline (BEOL) process is then performed to form the drain-source contact 600. In some embodiments, the drain-source contact 600 may be a metal line, wherein the drain-source contact 600 electrically connects the gate electrode 160, source electrode 140, drain electrode 150, source electrode 220, and drain electrode 240. Furthermore, in some embodiments, after the drain-source contact 600, a chemical mechanical polishing (CMP) process may be performed on the semiconductor device 300.

[0060] Figure 5 This is a current relationship diagram of a semiconductor device 300 according to a partial embodiment of this disclosure. Figure 5 In the process, the conduction current (I) of semiconductor device 100 and semiconductor device 200 are tested respectively. ON(PTnMES) / ION(nMES) The ratio is given by the equation, where the horizontal axis represents the Schottky barrier height of the source electrode 140 and drain electrode 150 of semiconductor device 100 and the Schottky barrier height of the gate electrode 160 of semiconductor device 200. In this embodiment, the magnitudes of the Schottky barrier are, in order, conditions C1, C2, C3, C4, C5, and C6. Figure 5 It can be seen that when the semiconductor device 300 operates under conditions C1, C2, C3, C4, C5, and C6, the conduction current (I) ON(PTnMES) / I ON(nMES) The ratio increases sequentially and reaches its maximum value under condition C6. Under condition C6, the current of semiconductor device 100 in semiconductor device 300 exceeds that of semiconductor device 200 in semiconductor device 300. In other words, semiconductor device 100 can have a larger current by adjusting only the Schottky barrier and without adjusting the size of semiconductor device 100, making semiconductor device 100 a replacement for pMES in conventional CMES.

[0061] This disclosure provides a semiconductor device in some embodiments. By designing this semiconductor device as an N-type breakdown metal-semiconductor field-effect transistor (Punch-Through nMES; PTnMES) and designing the source and drain electrodes of this semiconductor device as Schottky contacts, this semiconductor device can be a single-carrier device that does not require additional doping. Furthermore, by adjusting the Schottky barrier of the source and drain electrodes, this semiconductor device can have current characteristics similar to those of a P-type metal-semiconductor field-effect transistor without increasing its size. This semiconductor device can have good carrier mobility, and by matching the carrier mobility of nMES and PTnMES, the efficiency of the CMES is improved. Therefore, this semiconductor device can have good reliability and stability in RF applications and microwave circuit applications.

[0062] The foregoing summary outlines features of several embodiments, enabling those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: One substrate; A semiconductor layer is disposed on the substrate; One source electrode directly contacts the semiconductor layer; A drain electrode directly contacts the semiconductor layer; as well as A gate electrode is located between the source electrode and the drain electrode, wherein the gate electrode directly contacts the semiconductor layer.

2. The semiconductor device as claimed in claim 1, characterized in that, The gate electrode forms a Schottky contact with the semiconductor layer.

3. The semiconductor device as claimed in claim 1, characterized in that, The Schottky barrier height between the gate electrode and the semiconductor layer is less than the Schottky barrier height between the source electrode and the semiconductor layer and the Schottky barrier height between the drain electrode and the semiconductor layer.

4. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor layer includes: A first semiconductor region, adjacent to the source electrode; A second semiconductor region, adjacent to the drain electrode; and A third semiconductor region is located between the first semiconductor region and the second semiconductor region, wherein a doping concentration of the first semiconductor region and the second semiconductor region is higher than a doping concentration of the third semiconductor region.

5. The semiconductor device as claimed in claim 4, characterized in that, The first semiconductor region and the second semiconductor region have the same conductivity type.

6. The semiconductor device as claimed in claim 4, characterized in that, The gate electrode overlaps the third semiconductor region along a direction perpendicular to one surface of the gate electrode.

7. The semiconductor device as claimed in claim 1, characterized in that, It also includes a spacer layer that separates the source electrode or the drain electrode from the semiconductor layer, wherein the spacer layer includes a nanoparticle, a semiconductor oxide, or a nitride.

8. The semiconductor device as claimed in claim 1, characterized in that, It also includes a dielectric buffer layer located between the semiconductor layer and the gate electrode, wherein the dielectric buffer layer comprises a nanoparticle, a semiconductor oxide, or a nitride.

9. The semiconductor device as claimed in claim 1, characterized in that, The gate electrode, the source electrode, and the drain electrode are made of the same material.

10. The semiconductor device as claimed in claim 1, characterized in that, The material of the gate electrode is different from the material of the source electrode and the material of the drain electrode.

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