Semiconductor device and forming method thereof
By forming etching cavities with support structures and shallow trench isolation structures in semiconductor devices, the problem of etching non-uniformity caused by the increase in the depth of the process sealing ring trench is solved, thereby improving the performance of semiconductor devices and optimizing the etching shape.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-05
- Publication Date
- 2026-03-13
Smart Images
Figure CN121665643A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor device and a method for forming the same. Background Technology
[0002] The profile shape of the U-shaped process seal ring (PSR) trench affects the electrical performance of semiconductor devices. Increasing the depth of the PSR trench can improve its U-shaped profile. However, increasing the trench depth leads to larger defects in SiGe, affecting the uniformity of etching depth and ultimately degrading semiconductor device performance. Therefore, optimizing the etching shape of the PSR trench while improving semiconductor device performance has become a critical technical problem to be solved. Summary of the Invention
[0003] In view of this, embodiments of the present invention provide a semiconductor device and a method for forming the same, optimizing the etching shape of the process sealing ring trench.
[0004] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions.
[0005] In a first aspect, embodiments of the present invention provide a semiconductor device, comprising:
[0006] A substrate, the substrate comprising a substrate, a support structure located on the substrate, and fins located on the support structure;
[0007] A shallow trench isolation structure is located within an etched cavity formed between the substrate and the support structure, the bottom of the fin, and the top surface of the substrate;
[0008] A process sealing ring groove is located in the fin, and the bottom of the process sealing ring groove contacts the top surface of the shallow groove isolation structure.
[0009] In a second aspect, embodiments of the present invention provide a method for forming a semiconductor device, comprising:
[0010] A substrate is provided, the substrate including a substrate, a support structure located on the substrate, and a fin located on the support structure, wherein an etched cavity is formed between the support structure, the bottom of the fin, and the top surface of the substrate;
[0011] A shallow trench isolation structure is formed on the substrate and within the etched cavity;
[0012] A process sealing ring groove is formed on the fin, and the bottom of the process sealing ring groove contacts the top surface of the shallow groove isolation structure;
[0013] An epitaxial layer is grown within the process sealing ring trench to obtain the target semiconductor device.
[0014] The semiconductor device provided in this embodiment of the invention includes: a substrate, the substrate including a base, a support structure located on the base and a fin located on the support structure; a shallow trench isolation structure located in an etched cavity formed between the base and the support structure, the bottom of the fin and the top surface of the base; and a process sealing ring trench located in the fin, the bottom of the process sealing ring trench contacting the top surface of the shallow trench isolation structure.
[0015] As can be seen, in the semiconductor device provided by the embodiments of the present invention, since the fins of the substrate are formed on the substrate by a support structure, there is an etching cavity between the support structure, the bottom of the fins and the top surface of the substrate. The shallow trench isolation structure formed can be located not only on the substrate surface but also within the etching cavity. Furthermore, through the function of the shallow trench isolation structure within the etching cavity, the process sealing ring trench can be fully etched to form a process sealing ring trench with an ideal profile, while effectively preventing the deep etching of the process sealing ring trench. This ensures that the etching profile of the process sealing ring trench meets the requirements of the ideal profile (U-shaped profile), thereby improving the performance of the semiconductor device. Moreover, due to the influence of the shallow trench isolation structure, the etching depth of the process sealing ring trench is reduced, thereby achieving the goal of optimizing the etching shape of the process sealing ring trench while improving the performance of the semiconductor device. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0017] Figure 1 This is a top view of the semiconductor device provided in an embodiment of the present invention;
[0018] Figure 2 yes Figure 1 Cross-sectional view of the semiconductor device structure shown in the X direction;
[0019] Figure 3 yes Figure 1 A cross-sectional view of the semiconductor device structure shown in the Y direction;
[0020] Figure 4 This is a schematic flowchart of a semiconductor device formation method provided in an embodiment of the present invention;
[0021] Figure 5This is a top view of the substrate structure in the semiconductor device provided in the embodiment of the present invention;
[0022] Figure 6 yes Figure 5 Cross-sectional view of the substrate structure shown in the X direction;
[0023] Figure 7 yes Figure 5 A cross-sectional view of the substrate structure shown in the Y direction;
[0024] Figure 8 It is a top view of the original substrate structure formed during the semiconductor device manufacturing process;
[0025] Figure 9 yes Figure 8 Cross-sectional view of the original substrate structure in the X direction;
[0026] Figure 10 yes Figure 8 A cross-sectional view of the original substrate structure in the Y direction;
[0027] Figure 11 This is a top view of the structure of the semiconductor device after etching the sacrificial layer, provided in an embodiment of the present invention.
[0028] Figure 12 yes Figure 11 The X-direction cross-sectional view of the structure after etching the sacrificial layer is shown.
[0029] Figure 13 yes Figure 11 A cross-sectional view of the structure after etching the sacrificial layer is shown in the Y direction.
[0030] Figure 14 This is a top view of the support structure in the semiconductor device provided in the embodiment of the present invention;
[0031] Figure 15 yes Figure 14 Cross-sectional view of the supporting structure shown in the X direction;
[0032] Figure 16 yes Figure 14 A cross-sectional view of the supporting structure shown in the Y direction;
[0033] Figure 17 This is a top view of the shallow trench structure in the semiconductor device provided in the embodiment of the present invention;
[0034] Figure 18 yes Figure 17 Cross-sectional view of the shallow trench structure shown in the X direction;
[0035] Figure 19 yes Figure 17 A cross-sectional view of the shallow trench structure shown in the Y direction;
[0036] Figure 20 This is a top view of a semiconductor device with an etched cavity provided in an embodiment of the present invention;
[0037] Figure 21 yes Figure 20 A cross-sectional view of a semiconductor device with etched cavities shown in the X direction;
[0038] Figure 22 yes Figure 20 A cross-sectional view of a semiconductor device with etched cavities shown in the Y direction;
[0039] Figure 23 This is a top view of a semiconductor device that forms a shallow trench structure;
[0040] Figure 24 yes Figure 23 A cross-sectional view along the X direction of a semiconductor device forming a shallow trench structure;
[0041] Figure 25 yes Figure 23 A cross-sectional view along the Y direction of a semiconductor device forming a shallow trench structure;
[0042] Figure 26 This is a top view of the shallow trench isolation structure in the semiconductor device provided in the embodiment of the present invention;
[0043] Figure 27 yes Figure 26 Cross-sectional view of the shallow trench isolation structure shown in the X direction;
[0044] Figure 28 yes Figure 26 A cross-sectional view of the shallow trench isolation structure shown in the Y direction;
[0045] Figure 29 This is a top view of the original shallow trench isolation structure in a semiconductor device;
[0046] Figure 30 yes Figure 29 The X-direction sectional view of the original shallow trench isolation structure shown.
[0047] Figure 31 yes Figure 29 A cross-sectional view of the original shallow trench isolation structure in the Y direction, as shown.
[0048] Figure 32 This is a top view of the original process sealing ring trench with deep etching in a semiconductor device;
[0049] Figure 33 yes Figure 32 The image shows a cross-sectional view in the X direction of the original process sealing ring groove with a deep etch depth.
[0050] Figure 34 yes Figure 32 The image shows a cross-sectional view in the Y direction of the original process sealing ring groove with a deep etch depth. Detailed Implementation
[0051] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0052] In high-speed integrated circuit (IC) products, process seal ring trenches are created by embedding a SiGe thin film with compressive strain into the source and drain regions of a PMOS transistor. Process seal ring trenches utilize a technique used in semiconductor chip manufacturing to protect the chip edges. This technique forms a protective ring around the outermost edge of the chip to prevent damage during wafer dicing. Process seal ring trenches are typically composed of multiple layers of material, forming a protective band around the chip, which helps improve the chip's reliability and stability.
[0053] The technique of filling process seal ring trenches with strained silicon combines process seal ring and trench filling technologies to improve semiconductor device performance while ensuring chip edge protection. The addition of strained silicon (SiGe) to the process seal ring trenches provides a way to regulate the threshold voltage, significantly improving semiconductor device performance due to its improved hole mobility and reduced contact resistance.
[0054] The process seal ring trench filling strained silicon technique requires introducing process seal ring trench etching and selective epitaxial SiGe deposition into the source and drain regions of the PMOS immediately after sidewall formation. Process seal ring trench etching typically uses gas. During the etching process, the etching depth is positively correlated with the ideal profile of the process seal ring trench. The ideal profile of the process seal ring trench is a U-shape; the closer the formed profile of the process seal ring trench is to a U-shape, the more significant the performance improvement of the semiconductor device. However, a closer profile of the process seal ring trench to a U-shape also means a deeper etching depth and more deposited epitaxial SiGe, which can affect the variability of the semiconductor device and thus impact its performance.
[0055] Therefore, how to ensure that the process sealing ring trench has an ideal U-shaped profile while controlling the amount of epitaxial SiGe deposition, so as to ensure that the process sealing ring trench filling strained silicon technology can effectively improve the performance of semiconductor devices, is a technical problem that urgently needs to be solved by those in the field.
[0056] Based on this, embodiments of the present invention provide a semiconductor device that optimizes the etching shape of the process sealing ring trench while improving the performance of the semiconductor device.
[0057] Please refer to Figures 1-3 , Figure 1 This is a top view of the semiconductor device provided in an embodiment of the present invention. Figure 2 yes Figure 1 The image shows a cross-sectional view along the X direction of the semiconductor device structure. Figure 3 yes Figure 1 The diagram shows a cross-sectional view of the semiconductor device structure along the Y direction.
[0058] like Figures 1-3 As shown, the semiconductor device may include:
[0059] The substrate 1 includes a substrate 11, a support structure 12 located on the substrate 11, and a fin 13 located on the support structure 12;
[0060] The shallow trench isolation structure 2 is located in the etched cavity A formed between the substrate 11 and the support structure 12, the bottom of the fin 13 and the top surface of the substrate 11;
[0061] The process sealing ring groove 3 is located in the fin 13, and the bottom of the process sealing ring groove 3 is in contact with the top surface of the shallow groove isolation structure 2.
[0062] As can be seen, in the semiconductor device provided in the embodiments of the present invention, the fin 13 is formed on the substrate 11 by means of the support structure 12, so as to ensure the forming and stability of the overall structure of the fin 13. Meanwhile, in addition to forming the shallow trench isolation structure 2 on the surface of the substrate 11, the present invention also forms a shallow trench isolation structure 2 in the etching cavity A formed between the support structure 12, the bottom of the fin 13, and the top surface of the substrate 11. Since the shallow trench isolation structure 2 is deposited between the substrate 11 and the fin 13, during the process of etching the fin 13 to form the process sealing ring trench 3 using a process capable of forming an ideal U-shaped profile, the etching stops when the shallow trench isolation structure 2 is reached. When the process time for performing the process etching of the ideal U-shaped profile is met, the process sealing ring trench 3 with an ideal U-shaped profile can be formed. At the same time, the etching depth of the process sealing ring trench is not very deep (due to the obstruction of the shallow trench isolation structure 2), thereby enabling the semiconductor device provided by the present invention to effectively improve the etching profile of the process sealing ring trench while ensuring improved semiconductor device performance.
[0063] As can be seen, in the semiconductor device provided by the embodiments of the present invention, while fully etching the process sealing ring trench 3 to form a process sealing ring trench 3 with an ideal profile, the deep etching of the process sealing ring trench 3 can be effectively prevented, so as to achieve the requirement that the etching profile of the process sealing ring trench 3 meets the ideal profile (U-shaped profile) requirement, thereby improving the performance of the semiconductor device. Furthermore, due to the influence of the shallow trench isolation structure 2, the etching depth of the process sealing ring trench 3 is reduced, thereby achieving the purpose of optimizing the etching shape of the process sealing ring trench 3 while improving the performance of the semiconductor device.
[0064] Please continue to refer to this. Figures 1-3 ,like Figures 1-3 As shown, the semiconductor device may further include:
[0065] The grid structure 4 is located on the fin 13;
[0066] The epitaxial layer 5 is located within the process sealing ring groove 3.
[0067] An epitaxial layer 5 is deposited within the process sealing ring trench 3. The material of the epitaxial layer 5 can be SiGe. This is used to improve the performance of the semiconductor device, and the gate structure 4 is used to ensure that the semiconductor device can function properly.
[0068] This invention also provides a method for forming a semiconductor device, which is used to form the semiconductor device provided in the above embodiments.
[0069] Please refer to Figure 4 , Figure 4 This is a schematic flowchart of a semiconductor device formation method provided in an embodiment of the present invention.
[0070] like Figure 4 As shown, the method may include the following steps:
[0071] Step S100: Provide a substrate, the substrate including a substrate, a support structure located on the substrate, and fins located on the support structure.
[0072] An etched cavity is formed between the support structure, the bottom of the fin, and the top surface of the substrate.
[0073] The substrate mentioned in step S100 is a substrate including a support structure. That is, in this embodiment of the invention, before the deposition process of the shallow trench isolation structure, a support structure is formed on the substrate in advance to support the fins and form an etching cavity between the substrate top surface and the bottom surface of the fins. This facilitates the subsequent formation of a shallow trench isolation structure within the etching cavity. This ensures that the subsequently formed process sealing ring trench has an ideal etching profile and does not have a deep etching depth, thus fully ensuring the improvement of semiconductor device performance.
[0074] In order to successfully form the support structure, in one embodiment, the implementation steps of step S100 may include:
[0075] A substrate structure is provided, the substrate structure including a substrate structure layer, a sacrificial layer on the substrate structure layer, a fin structure layer on the sacrificial layer, and a hard mask structure layer on the fin structure layer; a portion of the sacrificial layer is removed; support structures are formed on the sidewalls of the remaining sacrificial layer; the hard mask structure layer, the fin structure layer, the remaining sacrificial layer, and a portion of the substrate structure layer are etched to form a substrate, the etched remaining sacrificial layer on the substrate, and the fins on the etched remaining sacrificial layer; the etched remaining sacrificial layer is removed to obtain a substrate.
[0076] As can be seen, in the substrate structure provided by the embodiments of the present invention, a sacrificial layer is formed between the substrate structure layer and the fin structure layer. Thus, by processing the sacrificial layer, a support structure for supporting the fin can be formed. At the same time, after removing the remaining sacrificial layer after etching, an etching cavity can be formed between the support structure, the top surface of the substrate, and the bottom surface of the fin, which satisfies the subsequent formation of a shallow trench isolation structure that can reduce the etching depth of the sealing ring trench in the process.
[0077] In one embodiment, the step of providing the substrate structure includes:
[0078] A substrate material layer is provided; a sacrificial material layer is formed on the substrate material layer, and a fin material layer is formed on the sacrificial material layer; a hard mask layer is formed on the fin material layer, the hard mask layer exposing a predetermined area for forming the fin; the fin material layer, the sacrificial material layer, and a portion of the substrate material layer exposed by the hard mask layer are etched to form the substrate structure.
[0079] In the process of forming the substrate structure, a sacrificial material layer is deposited on the substrate material layer in advance to obtain the sacrificial layer, which can then be used to form the support structure.
[0080] The substrate structure provided above can be referenced. Figures 5-7 , Figure 5 This is a top view of the substrate structure in the semiconductor device provided in the embodiment of the present invention. Figure 6 yes Figure 5 The X-direction cross-sectional view of the substrate structure shown is shown. Figure 7 yes Figure 5 The Y-direction cross-sectional view of the substrate structure shown.
[0081] like Figures 5-7As shown, the substrate structure 10 includes a substrate structure layer 110, a sacrificial layer 14 formed on the substrate structure layer 110, a fin structure layer 130 formed on the sacrificial layer 14, and a hard mask structure layer 150 formed on the fin structure layer 130. The sacrificial layer 14 is formed after etching a sacrificial material layer corresponding to a predetermined area exposed by the hard mask structure layer 150.
[0082] The sacrificial layer 14 facilitates the subsequent formation of a support structure. For example, the material of the sacrificial layer 14 can be SiGe.
[0083] After the supporting structure is formed, the remaining sacrificial layer can be released to obtain, as shown in the figure. Figure 3 The structure shown is such that an etched cavity A is formed between the bottom surface of the fin 13, the top surface of the substrate 11, and the support structure 12.
[0084] The formation process and structure of the original substrate structure differ from those in existing processes. For a better understanding of the formation process and structure of the original substrate structure in existing processes, please refer to [reference needed]. Figures 8-10 , Figure 8 This is a top view of the original substrate structure formed during the semiconductor device manufacturing process. Figure 9 yes Figure 8 The image shows a cross-sectional view of the original substrate structure along the X direction. Figure 10 yes Figure 8 The image shows a cross-sectional view of the original substrate structure along the Y direction.
[0085] like Figures 8-10 As shown, the formation process of the original substrate structure 20 is as follows: the original fin structure layer 131 and the hard mask structure layer 150 located on the original fin structure layer 131 are formed directly on the substrate structure layer 110. Since the sacrificial layer 14 is located between the fin structure layer 130 and the substrate structure layer 110 in the substrate structure 10 of the semiconductor device provided in this embodiment of the invention, the top view corresponding to the substrate structure 10 of this embodiment of the invention (…) Figure 5 () and a top view of the original substrate structure 20 formed in the existing process () Figure 8 The same as, but a cross-sectional view of the substrate structure 10 formed according to an embodiment of the present invention: Figure 6 , Figure 7 A cross-sectional view of the original substrate structure 20 formed in the existing process: Figure 9 and Figure 10 The comparison clearly shows that in this embodiment of the invention, a sacrificial layer 14 is also formed between the fin structure layer 130 and the substrate structure layer 110, so that the sacrificial layer 14 can be etched in the future to facilitate the formation of the support structure.
[0086] The structure obtained during the etching of the sacrificial layer 14 in this embodiment of the invention can be referred to Figures 11-13 As shown, Figure 11This is a top view of the structure of the semiconductor device after etching the sacrificial layer, provided in an embodiment of the present invention. Figure 12 yes Figure 11 The image shows a cross-sectional view of the structure after etching the sacrificial layer. Figure 13 yes Figure 11 The Y-direction cross-sectional view of the structure after etching the sacrificial layer is shown.
[0087] like Figures 11-13 As shown, partial etching is performed on the two sidewalls of the sacrificial layer 14, and the remaining two sides of the sacrificial layer 140 will form gap positions B, which are used to form the support structure 12 at the gap positions B.
[0088] The supporting structure can be referenced. Figures 14-16 As shown, Figure 14 This is a top view of the support structure in the semiconductor device provided in the embodiment of the present invention. Figure 15 yes Figure 14 The X-direction sectional view of the supporting structure shown. Figure 16 yes Figure 14 The Y-direction sectional view of the supporting structure shown.
[0089] like Figures 14-16 As shown, the support structure 12 is formed in Figure 13 At the notch location B formed after etching, a support structure 12 is formed on both sides of the remaining sacrificial layer 140. In subsequent processes, the remaining sacrificial layer 140, fin structure layer 130, hard mask structure layer 150 and part of the substrate structure layer can be etched to form a shallow trench structure on the substrate. The shallow trench structure is used to deposit a shallow trench isolation structure material layer formed on the substrate.
[0090] To facilitate the formation of shallow trench isolation structures, Figures 14-16 The structure shown is etched to form a shallow trench structure on the substrate. Please refer to [reference needed]. Figures 17-19 , Figure 17 This is a top view of the shallow trench structure in the semiconductor device provided in the embodiment of the present invention. Figure 18 yes Figure 17 The X-direction sectional view of the shallow trench structure shown. Figure 19 yes Figure 17 The Y-direction cross-sectional view of the shallow trench structure shown.
[0091] Etching Figures 14-16 After the hard mask structure layer 150, the fin structure layer 130 covered by the hard mask structure layer 150, the remaining sacrificial layer 140, and part of the substrate structure layer 110 are shown, a structure is formed as follows: Figures 17-19 The structure shown.
[0092] Etching Figures 14-16The hard mask structure layer 150, the fin structure layer 130, the remaining sacrificial layer 140, and part of the substrate structure layer 110 shown form a Figures 17-19 The substrate 11, the remaining sacrificial layer 141 after etching on the substrate 11, and the fins 13 on the remaining sacrificial layer 141 are shown; thereby forming a shallow trench structure 16 on the substrate 11. A shallow trench isolation material layer can then be deposited within the shallow trench structure 16 to obtain... Figures 1-3 The shallow trench isolation structure located on substrate 11 in the semiconductor device shown.
[0093] In order to deposit a shallow trench isolation material layer between the fins and the substrate, further... Figures 17-19 After etching the structure shown, the remaining sacrificial layer 141 is released to obtain the etched cavity A.
[0094] Please refer to Figures 20-22 , Figure 20 This is a top view of a semiconductor device with an etched cavity provided in an embodiment of the present invention. Figure 21 yes Figure 20 The image shows a cross-sectional view of a semiconductor device with etched cavities along the X direction. Figure 22 yes Figure 20 The image shows a cross-sectional view of a semiconductor device with an etched cavity in the Y direction.
[0095] like Figures 20-22 As shown, after forming the support structure 12, the remaining sacrificial layer 141 after etching is removed, creating an etching cavity A between the bottom of the fin 13, the top surface of the substrate 11, and the support structure 12. This facilitates the subsequent deposition of a shallow trench isolation material layer within the etching cavity A, ultimately resulting in... Figures 1-3 The shallow trench isolation structure 2 is shown. That is, in this embodiment of the invention, shallow trench isolation material layers are deposited in both the shallow trench structure 16 on the substrate and the etched cavity A, thereby forming the trench isolation structure 2 located between the fin 13 and the substrate 11, rather than simply forming a shallow trench isolation structure located in the shallow trench structure 16 on the substrate as in the prior art. This allows the shallow trench isolation structure provided by this embodiment of the invention to have the ability to prevent deep etching of the fin.
[0096] In the existing shallow trench structure manufacturing process, the resulting semiconductor devices can be referenced. Figures 23-25 , Figure 23 This is a top view of a semiconductor device that forms a shallow trench structure. Figure 24 yes Figure 23 The image shows a cross-sectional view along the X direction of a semiconductor device forming a shallow trench structure. Figure 25 yes Figure 23 The image shows a cross-sectional view along the Y direction of a semiconductor device forming a shallow trench structure.
[0097] In existing processes, when forming shallow trench structures, the material is directly applied to... Figures 8-10 The structure shown is etched, specifically the original fin structure layer 131, the hard mask structure layer 150, and part of the substrate structure layer, to obtain the structure shown. Figures 23-25 The structure shown is as follows: a shallow trench structure 16 is formed on the substrate 11, while the original fin 132 is formed directly on the substrate 11. When the original process sealing ring trench is subsequently formed on the original fin 132, there is no structure with the ability to stop etching for the original fin 132. Therefore, under the etching conditions for forming a process sealing ring trench with a good U-shaped profile, the etching depth of the original process sealing ring trench also increases, affecting the performance of the semiconductor device.
[0098] Please continue to refer to this. Figure 4 The method includes:
[0099] Step S101: A shallow trench isolation structure is formed on the substrate and within the etched cavity.
[0100] Based on a structure with etched cavities between the top surface of the substrate, the bottom surface of the fin, and the support structure, a shallow trench isolation structure is deposited. This allows shallow trench isolation structures to be formed in both the substrate and the etched cavities. The shallow trench isolation structure has the ability to prevent etching, meaning it can be considered an etch stop layer for etching the fin. Thus, under etching conditions that aim to form a process sealing ring trench with a good U-shaped profile, the etching of the fin is not affected, thus preventing the deep etching of the process sealing ring trench. This allows for the formation of a process sealing ring trench with an ideal U-shaped profile while improving the performance of the semiconductor device, thereby significantly enhancing the performance of the semiconductor device.
[0101] In one implementation, step S101 may include:
[0102] A shallow trench isolation material layer is deposited on the substrate and within the etched cavity; a portion of the shallow trench isolation material layer is etched to form a shallow trench isolation structure.
[0103] Shallow trench isolation structures can be referenced. Figures 26-28 , Figure 26 This is a top view of the shallow trench isolation structure in the semiconductor device provided in the embodiment of the present invention. Figure 27 yes Figure 26 The X-direction sectional view of the shallow trench isolation structure shown. Figure 28 yes Figure 26 The Y-direction cross-sectional view of the shallow trench isolation structure shown.
[0104] exist Figures 20-22 Based on the structure shown, form Figures 26-28The shallow trench isolation structure 2 is shown. As can be seen, the shallow trench isolation structure 2 is formed in the etched cavity A and the shallow trench structure 16 on the substrate 11. Since the shallow trench isolation structure 2 can prevent the fin 13 from being etched to a depth along the direction perpendicular to the substrate 11, it is possible to continue etching the fin located above the shallow trench isolation structure 2, while preventing the downward etching of the fin 13. This ensures that the formed process sealing ring trench has an ideal U-shaped profile and that the process sealing ring trench 3 has a shallow etching depth.
[0105] In other words, the shallow trench isolation structure 2 formed in the embodiments of the present invention can be used as a bottom dielectric isolation structure (BDI). The shallow trench isolation structure 2 has the function of a bottom dielectric isolation structure, which can prevent leakage of the fin 13 and reduce the etching depth of the process sealing ring trench, thereby ensuring that the process sealing ring trench can have an ideal U-shaped profile while effectively improving the performance of the semiconductor device.
[0106] In one embodiment, prior to the step of depositing a shallow trench isolation material layer on the substrate and within the etched cavity, the method further includes: removing a fin hard mask layer located on the fin to expose the top of the fin.
[0107] like Figures 26-28 As shown, the hard mask layer located on the fin 13 has been removed when the shallow trench isolation structure 2 is formed.
[0108] In the existing process, since no shallow trench isolation structure is formed between the substrate 11 and the original fin 132 (there is no basis for forming the etched cavity A), the original shallow trench isolation structure 170 in the existing process is only formed in the shallow trench structure 16. Please refer to... Figures 29-31 As shown, Figure 29 This is a top view of the original shallow trench isolation structure in semiconductor devices. Figure 30 yes Figure 29 The image shows a cross-sectional view along the X direction of the original shallow trench isolation structure. Figure 31 yes Figure 29 The original shallow trench isolation structure is shown in the Y-direction cross-sectional view.
[0109] like Figures 29-31 As shown, the original shallow trench isolation structure 170 is formed in the shallow trench structure 16, that is, on the substrate 11. It can only achieve isolation between the active regions of the semiconductor device, that is, conventional functional use, and cannot have the function of BDI (preventing leakage of the original fin 132 and reducing the etching depth of the process sealing ring trench).
[0110] Please continue to refer to this. Figure 4 The method includes:
[0111] Step S102: A process sealing ring groove is formed on the fin, and the bottom of the process sealing ring groove contacts the top surface of the shallow groove isolation structure.
[0112] Because a shallow trench isolation structure is formed between the fin and the substrate, when forming the process sealing ring trench, under etching conditions that can form an ideal U-shaped process sealing ring trench (e.g., using a certain etching rate to etch the fin within a certain time to form a process sealing ring trench with an ideal U-shaped profile), it is possible to both satisfy the formation of an ideal U-shaped profile process sealing ring trench and reduce the etching depth of the process sealing ring trench. This improves the performance of the semiconductor device while avoiding excessive filler strained silicon material due to a deeper etching depth of the process sealing ring trench, which would otherwise affect the performance improvement of the semiconductor device.
[0113] In one implementation, step S102 may include:
[0114] A grid structure is formed on the fin; a portion of the fin located between adjacent grid structures is removed to form a process sealing ring groove.
[0115] The grid structure can be referenced further. Figures 1-3 A gate structure 4 is formed on the fin 13 in a direction perpendicular to the extension direction of the fin 13 to ensure the normal operation of the semiconductor device.
[0116] In one embodiment, the step of removing a portion of the fin located between adjacent gate structures to form a process sealing ring groove includes:
[0117] The fins located between adjacent gate structures are etched until the top surface of the shallow trench isolation structure is reached, at which point the etching stops to form a process sealing ring trench.
[0118] As can be seen, the shallow trench isolation structure has the function of a bottom dielectric isolation structure. It can be used as an etching stop layer for etching the fin to prevent further etching of the fin. This results in the process sealing ring trench formed on the fin having a smaller etching depth, which will not affect the effect of process sealing ring trench filled strained silicon technology on improving the performance of semiconductor devices.
[0119] Please continue to refer to this. Figure 4 The method includes:
[0120] Step S103: An epitaxial layer is grown in the process sealing ring trench to obtain the target semiconductor device.
[0121] Growing an epitaxial layer (strained silicon material) within the process sealing ring trench can ensure an effective improvement in the performance of semiconductor devices.
[0122] After step S103 is performed, the resulting semiconductor structure can be referenced. Figures 1-3 As shown.
[0123] In existing processes, because a shallow trench isolation structure capable of preventing the etching of the original fin is not formed between the original fin and the substrate, the original process sealing ring trench formed will have a deeper etching depth under the same etching conditions that can form an ideal U-shaped process sealing ring trench. This will increase the amount of strained silicon material deposited subsequently, affecting the effectiveness and feasibility of improving the performance of semiconductor devices.
[0124] The original sealing ring groove formed by the existing process can be referenced. Figures 32-34 As shown, Figure 32 This is a top view of a pre-process sealing ring trench with deep etching in a semiconductor device. Figure 33 yes Figure 32 The image shown is a cross-sectional view along the X direction of the original process sealing ring groove with a deep etch depth. Figure 34 yes Figure 32 The image shows a cross-sectional view in the Y direction of the original process sealing ring groove with a deep etch depth.
[0125] and Figures 1-3 In comparison, it is obvious that Figures 32-34 In the original process sealing ring trench 19, it can have an ideal U-shaped profile. However, compared with the process sealing ring trench 3 formed in the embodiment of the present invention, the original process sealing ring trench 19 has a deeper etching depth. As a result, the deposited original epitaxial layer 51 is more than the epitaxial layer 5 that needs to be filled in the embodiment of the present invention, which affects the improvement of semiconductor device performance.
[0126] As can be seen, in the semiconductor device formation method provided by the embodiments of the present invention, since the fins of the substrate are formed on the substrate by a support structure, there is an etching cavity between the support structure, the bottom of the fins and the top surface of the substrate. The shallow trench isolation structure formed can be located not only on the substrate surface but also within the etching cavity. Furthermore, through the function of the shallow trench isolation structure within the etching cavity, the process sealing ring trench can be fully etched to form a process sealing ring trench with an ideal profile, while effectively preventing the deep etching of the process sealing ring trench. This ensures that the etching profile of the process sealing ring trench meets the requirements of the ideal profile (U-shaped profile), thereby improving the performance of the semiconductor device. Moreover, due to the influence of the shallow trench isolation structure, the etching depth of the process sealing ring trench is reduced, thereby achieving the goal of optimizing the etching shape of the process sealing ring trench while improving the performance of the semiconductor device.
[0127] The foregoing describes multiple embodiment schemes provided by the embodiments of this application. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and published by the embodiments of this application.
[0128] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.
Claims
1. A semiconductor device, characterized in that, include: A substrate, the substrate comprising a substrate, a support structure located on the substrate, and fins located on the support structure; A shallow trench isolation structure is located within an etched cavity formed between the substrate and the support structure, the bottom of the fin, and the top surface of the substrate; A process sealing ring groove is located in the fin, and the bottom of the process sealing ring groove contacts the top surface of the shallow groove isolation structure.
2. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A grid structure is located on the fin. The epitaxial layer is located within the process sealing ring groove.
3. A method for forming a semiconductor device, characterized in that, include: A substrate is provided, the substrate including a substrate, a support structure located on the substrate, and a fin located on the support structure, wherein an etched cavity is formed between the support structure, the bottom of the fin, and the top surface of the substrate; A shallow trench isolation structure is formed on the substrate and within the etched cavity; A process sealing ring groove is formed on the fin, and the bottom of the process sealing ring groove contacts the top surface of the shallow groove isolation structure; An epitaxial layer is grown within the process sealing ring trench to obtain the target semiconductor device.
4. The semiconductor device formation method according to claim 3, characterized in that, The step of providing the substrate includes: A substrate structure is provided, the substrate structure including a substrate structure layer, a sacrificial layer on the substrate structure layer, a fin structure layer on the sacrificial layer, and a hard mask structure layer on the fin structure layer; Remove part of the sacrificial layer; Supporting structures are formed on the side walls of the remaining sacrificial layer; The hard mask structure layer, the fin structure layer, the remaining sacrificial layer, and a portion of the substrate structure layer are etched to form a substrate, the remaining sacrificial layer after etching on the substrate, and the fins on the remaining sacrificial layer after etching. Remove the remaining sacrificial layer after etching to obtain the substrate.
5. The semiconductor device formation method as described in claim 4, characterized in that, The step of providing the substrate structure includes: Provide a substrate material layer; A sacrificial material layer is formed on the substrate material layer, and a fin material layer is formed on the sacrificial material layer; A hard mask layer is formed on the fin material layer, the hard mask layer exposing a predetermined area for forming the fin; The substrate structure is formed by etching the fin material layer, sacrificial material layer, and a portion of the substrate material layer exposed by the hard mask layer.
6. The semiconductor device formation method according to claim 4, characterized in that, The step of forming a shallow trench isolation structure on the substrate and within the etched cavity includes: A shallow trench isolation material layer is deposited on the substrate and within the etched cavity; The shallow trench isolation material layer is etched to form a shallow trench isolation structure.
7. The semiconductor device formation method according to claim 5, characterized in that, Prior to the step of depositing a shallow trench isolation material layer on the substrate and within the etched cavity, the method further includes: Remove the fin hard mask layer located on the fin to expose the top of the fin.
8. The method for forming a semiconductor device according to any one of claims 3-7, characterized in that, The step of forming a process sealing ring groove on the fin includes: A grid structure is formed on the fin; Remove a portion of the fin located between adjacent gate structures to form a process sealing ring groove.
9. The semiconductor device formation method according to claim 8, characterized in that, The step of removing a portion of the fin located between adjacent gate structures to form a process sealing ring groove includes: The fins located between adjacent gate structures are etched until the top surface of the shallow trench isolation structure is reached, at which point the etching stops to form a process sealing ring trench.