Semiconductor device

Abstract

A semiconductor device according to an embodiment includes: a substrate; a nitride semiconductor layer provided on the substrate, the nitride semiconductor layer having a first layer and a second layer provided on the first layer and having a band gap wider than that of the first layer; a source electrode; a drain electrode; a gate electrode between the source electrode and the drain electrode in the first direction; and an insulating film provided between the gate electrode and the nitride semiconductor layer, the nitride semiconductor layer having a p-type semiconductor layer, the p-type semiconductor layer having: a connection portion connected to the source electrode; and an extension portion extending in the first direction from the connection portion within the nitride semiconductor layer, the extension portion being located between a first interface between the first layer and the second layer and a second interface between the substrate and the nitride semiconductor layer, and not in contact with the first interface and the second interface. An end portion of the extension portion away from the connection portion in the first direction is located between a position of an end portion of the gate electrode on the drain electrode side and a position of an end portion of the drain electrode on the gate electrode side in the first direction.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2024-159372 (filed on September 13, 2024). This application incorporates all contents of the basic application by reference to that basic application. Technical Field

[0003] The implementation involves a semiconductor device. Background Technology

[0004] As a power device, HEMT (High Electron Mobility Transistor) using gallium nitride-based materials is known. Summary of the Invention

[0005] Embodiments of the present invention provide a semiconductor device capable of reducing leakage current.

[0006] According to this embodiment, a semiconductor device includes: a substrate; a nitride semiconductor layer disposed on the substrate, having a first layer and a second layer disposed on the first layer and having a band gap wider than the first layer; a source electrode disposed on the nitride semiconductor layer and in contact with the nitride semiconductor layer; a drain electrode disposed on the nitride semiconductor layer and in contact with the nitride semiconductor layer, located at a position separate from the source electrode in a first direction; a gate electrode located between the source electrode and the drain electrode in the first direction; and an insulating film disposed between the gate electrode and the nitride semiconductor layer, wherein the nitride... The semiconductor layer has a p-type semiconductor layer, the p-type semiconductor layer having: a connection portion connected to the source electrode; and an extension portion extending from the connection portion within the nitride semiconductor layer along a first direction, the extension portion being located between a first interface between the first layer and the second layer and a second interface between the substrate and the nitride semiconductor layer, and not in contact with the first interface and the second interface, the end of the extension portion in the first direction away from the connection portion being located between the end of the gate electrode on the drain electrode side and the end of the drain electrode on the gate electrode side in the first direction. Attached Figure Description

[0007] Figure 1 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0008] Figure 2 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment.

[0009] Figure 3 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment.

[0010] Figure 4 This is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment.

[0011] Figure 5 This is a schematic cross-sectional view of the semiconductor device according to the fifth embodiment.

[0012] Figure 6 This is a schematic top view showing the configuration of the main components in the semiconductor device according to the fifth embodiment. Detailed Implementation

[0013] Hereinafter, the embodiments will be described with reference to the accompanying drawings. Furthermore, in each of the drawings, the same reference numerals are used to label the same components.

[0014] [First Implementation Method]

[0015] like Figure 1 As shown, the semiconductor device 1 of the first embodiment includes a substrate 100 and a nitride semiconductor layer 10 disposed on the substrate 100.

[0016] As substrate 100, for example, a p-type silicon substrate can be used. A potential of, for example, 0V can also be applied to substrate 100.

[0017] Two directions intersecting each other within a plane parallel to the surface of the substrate 100 are designated as the first direction X and the second direction Y. In this example, the first direction X and the second direction Y are orthogonal to each other. A direction orthogonal to the first direction X and the second direction Y is designated as the third direction Z. In the third direction Z, the direction from the substrate 100 toward the nitride semiconductor layer 10 is designated as upward. The direction from the nitride semiconductor layer 10 toward the substrate 100 is designated as downward.

[0018] The nitride semiconductor layer 10 has a first layer 11 and a second layer 12 disposed on the first layer 11. In the third direction Z, the first layer 11 is located between the substrate 100 and the second layer 12. The band gap of the second layer 12 is wider than that of the first layer 11. For example, the first layer 11 is an n-type gallium nitride (GaN) layer, and the second layer 12 is an undoped aluminum gallium nitride (AlGaN) layer. A two-dimensional electron gas 200 is distributed near the interface (first interface) S1 between the first layer 11 and the second layer 12 through piezoelectric polarization. The thickness of the second layer 12 is thinner than that of the first layer 11. The first layer 11 can also be an undoped GaN layer. The Al to Ga composition ratio in the AlGaN layer of the second layer 12 is arbitrary.

[0019] The nitride semiconductor layer 10 may also have a buffer layer 13. The buffer layer 13 is located between the substrate 100 and the first layer 11 in the third direction Z. The buffer layer 13 mitigates the lattice mismatch between the substrate 100 and the first layer 11. The buffer layer 13 may, for example, be a GaN layer doped with carbon or iron, a superlattice of GaN and AlGaN layers, or a combination thereof.

[0020] The semiconductor device 1 also includes a source electrode 31, a drain electrode 32, and a gate electrode 33 disposed on the nitride semiconductor layer 10. The source electrode 31, the gate electrode 33, and the drain electrode 32 extend in the third direction Y.

[0021] The source electrode 31 and drain electrode 32 are connected to the nitride semiconductor layer 10. The source electrode 31 and drain electrode 32 are in ohmic contact with the nitride semiconductor layer 10. Figure 1 In the example shown, the source electrode 31 and the drain electrode 32 are connected to the second layer 12.

[0022] The source electrode 31 and drain electrode 32 are located separately in the first direction X. The gate electrode 33 is located between the source electrode 31 and the drain electrode 32 in the first direction X. The distance in the first direction X between the end 32A of the drain electrode 32 on the gate electrode 33 side and the end 33B of the gate electrode 33 on the drain electrode 32 side is longer than the distance in the first direction X between the end 31A of the source electrode 31 on the gate electrode 33 side and the end 33A of the gate electrode 33 on the source electrode 31 side.

[0023] The semiconductor device 1 also includes an insulating film 41 disposed on a nitride semiconductor layer 10 between the source electrode 31 and the drain electrode 32. The insulating film 41 is disposed between the gate electrode 33 and the nitride semiconductor layer 10, and the gate electrode 33 is not in contact with the nitride semiconductor layer 10. For example, a silicon nitride film can be used as the insulating film 41.

[0024] The semiconductor device 1 also includes a protective film 42. The protective film 42 is disposed on the insulating film 41 and covers a portion of the source electrode 31 and a portion of the drain electrode 32. In addition, the protective film 42 covers the gate electrode 33. As the protective film 42, for example, a silicon oxide film or a silicon nitride film can be used.

[0025] The semiconductor device 1 further includes a gate field plate electrode 36 and a source field plate electrode 35. The gate field plate electrode 36 is connected to a portion of the upper surface of the gate electrode 33 and extends toward the drain electrode 32 in the protective film 42. The source field plate electrode 35 is connected to the upper surface of the source electrode 31 and extends toward the drain electrode 32 in the protective film 42. The gate field plate electrode 36 and the source field plate electrode 35 suppress current collapse.

[0026] In the first direction X, the position of the end 36A of the gate field plate electrode 36 on the drain electrode 32 side is located between the position of the end 33B of the gate electrode 33 on the drain electrode 32 side and the end 32A of the drain electrode 32 on the gate electrode 33 side. In the first direction X, the position of the end 35A of the source field plate electrode 35 on the drain electrode 32 side is located between the position of the end 36A of the gate field plate electrode 36 on the drain electrode 32 side and the end 32A of the drain electrode 32 on the gate electrode 33 side.

[0027] The nitride semiconductor layer 10 has, for example, a p-type semiconductor layer 20 containing magnesium (Mg) as a p-type impurity. The p-type semiconductor layer 20 has a connection portion 21 connected to the source electrode 31 and an extension portion 22 extending from the connection portion 21 within the nitride semiconductor layer 10 along a first direction X.

[0028] The connecting portion 21 is in contact with the lower surface of the source electrode 31 and extends downward from the lower surface of the source electrode 31 within the nitride semiconductor layer 10.

[0029] The extension 22 is located between the first interface S1 of the first layer 11 and the second layer 12 and the second interface S2 of the substrate 100 and the nitride semiconductor layer 10. Figure 1 In the example shown, the extension 22 is located in the first layer 11. The extension 22 is not in contact with the two-dimensional electron gas 200 distributed in the first interface S1 and the first layer 11. The extension 22 is not in contact with the second interface S2 between the substrate 100 and the nitride semiconductor layer 10.

[0030] The extension 22 extends from the connection 21 across the gate electrode 33 in the first direction X toward the drain electrode 32. The end portion 23 of the extension 22 in the first direction X, away from the connection 21, is located between the end portion 33B of the gate electrode 33 on the drain electrode 32 side and the end portion 32A of the drain electrode 32 on the gate electrode 33 side. The position of the end portion 23 of the extension 22 in the first direction X is located between the position of the end portion 33B of the gate electrode 33 on the drain electrode 32 side and the position of the end portion 32A of the drain electrode 32 on the gate electrode 33 side. In the first direction X, the end portion 23 of the extension 22 is located in the nitride semiconductor layer 10 below the region between the gate electrode 33 and the drain electrode 32.

[0031] If a first potential (e.g., several hundred V) is applied to the drain electrode 32, a second potential (e.g., 0 V) ​​lower than the first potential is applied to the source electrode 31, and a gate voltage above the threshold is applied to the gate electrode 33, then current flows through the two-dimensional electron gas 200 between the drain electrode 32 and the source electrode 31, and the semiconductor device 1 becomes conductive.

[0032] If a potential lower than the threshold (e.g., around -10V) is applied to the gate electrode 33, the two-dimensional electron gas 200 below the gate electrode 33 is blocked, and the semiconductor device 1 becomes cut off.

[0033] In the aforementioned cutoff state, near the end 32A of the drain electrode 32 where the electric field is strengthened, a large number of holes are easily generated in the nitride semiconductor layer 10 due to impact ionization. These holes flow in the nitride semiconductor layer 10 towards the source electrode 31 and the gate electrode 33. In particular, the potential of the gate electrode 33 in the cutoff state (e.g., around -10V) is lower than the potential of the source electrode 31 (e.g., 0V), so holes tend to accumulate below the gate electrode 33. This reduces the effect of the gate electrode 33, which is used to block the two-dimensional electron gas 200, on the potential, and electrons flow from the source electrode 31 to the drain electrode 32, generating positive feedback that promotes impact ionization near the drain electrode 32. As a result, the leakage current increases. In addition, a large number of hot carriers are generated due to the above feedback, which reduces reliability.

[0034] According to this embodiment, by providing a p-type semiconductor layer 20 connected to the source electrode 31 in the nitride semiconductor layer 10, holes generated by impact ionization can be easily discharged to the source electrode 31 via the p-type semiconductor layer 20. This suppresses the accumulation of holes generated by impact ionization below the gate electrode 33, reduces leakage current, and improves reliability.

[0035] In this embodiment, the extension 22 of the p-type semiconductor layer 20 is located in the first layer 11 and is not in contact with the first interface S1 between the first layer 11 and the second layer 12. Furthermore, the extension 22 is not in contact with the two-dimensional electron gas 200 distributed in the first layer 11. Therefore, the p-type semiconductor layer 20 does not affect the on-resistance.

[0036] Furthermore, the extension 22 of the p-type semiconductor layer 20 is not disposed on the substrate 100, but is located within the nitride semiconductor layer 10. As a result, compared to the case where the p-type semiconductor layer 20 is located on the substrate 100, holes generated near the end 32A of the drain electrode 32 due to impact ionization can be easily discharged to the source electrode 31 via the p-type semiconductor layer 20.

[0037] If the end portion 23 of the extension portion 22 extends to a position overlapping below the drain electrode 32, it will lead to a decrease in breakdown voltage. Furthermore, if the end portion 23 of the extension portion 22 does not extend closer to the drain electrode 32 side than the end portion 33B on the drain electrode 32 side of the gate electrode 33, holes generated due to impact ionization will easily flow to the gate electrode 33 and easily accumulate below the gate electrode 33. According to this embodiment, the end portion 23 of the extension portion 22 is located in the first direction X between the position of the end portion 33B on the drain electrode 32 side of the gate electrode 33 and the position of the end portion 32A on the gate electrode 33 side of the drain electrode 32. Therefore, the decrease in breakdown voltage can be suppressed, and holes generated due to impact ionization can be easily discharged to the source electrode 31 via the p-type semiconductor layer 20.

[0038] To facilitate the removal of holes generated by collisional ionization, the p-type impurity concentration of the p-type semiconductor layer 20 is preferably 1×10¹⁵ cm⁻³ or higher.

[0039] The following describes other embodiments. Regarding these other embodiments, the description mainly focuses on configurations that differ from the first embodiment described above.

[0040] [Second Implementation]

[0041] like Figure 2 As with the semiconductor device 2 of the second embodiment shown, the extension 22 of the p-type semiconductor layer 20 can also be located in the buffer layer 13. The buffer layer 13 is located further away from the end 32A of the drain electrode 32 in the third direction Z than the first layer 11. Therefore, the end 23 of the extension 22 located in the buffer layer 13 is preferably located on the side closer to the drain electrode 32 in the first direction X than the end 23 of the extension 22 located in the first layer 11. As a result, holes generated near the end 32A of the drain electrode 32 due to impact ionization can be easily discharged to the source electrode 31 via the p-type semiconductor layer 20.

[0042] [Third Implementation Method]

[0043] like Figure 3 As with the semiconductor device 3 of the third embodiment shown, the extension of the p-type semiconductor layer 20 may also have a first extension 22A located in the first layer 11 and a second extension 22B located in the buffer layer 13. The first extension 22A extends from the connection portion 21 in the first layer 11 along the first direction X, and the second extension 22B extends from the connection portion 21 in the buffer layer 13 along the first direction X.

[0044] The end 23B of the second extension 22B, located away from the connecting portion 21 in the first direction X, is positioned closer to the drain electrode 32 in the first direction X than the end 23A of the first extension 22A, located away from the connecting portion 21. Therefore, holes generated near the end 32A of the drain electrode 32 due to impact ionization can be easily discharged to the source electrode 31 via the first extension 22A and the second extension 22B.

[0045] [Fourth Implementation Method]

[0046] like Figure 4 As shown in the semiconductor device 4 of the fourth embodiment, the extension 22 of the p-type semiconductor layer 20 can also be located in the second layer 12. The extension 22 extends from the connection portion 21 within the second layer 12 along the first direction X. The extension 22 is not in contact with the first interface S1 between the first layer 11 and the second layer 12. Furthermore, the extension 22 is not in contact with the two-dimensional electron gas 200. Therefore, the p-type semiconductor layer 20 does not affect the on-resistance.

[0047] Furthermore, the end portion 23 of the extension portion 22, located away from the connection portion 21 in the first direction X, lies between the end portion 31A of the source electrode 31 on the gate electrode 33 side and the end portion 33A of the gate electrode 33 on the source electrode 31 side. The position of the end portion 23 of the extension portion 22 in the first direction X lies between the position of the end portion 31A of the source electrode 31 on the gate electrode 33 side and the position of the end portion 33A of the gate electrode 33 on the source electrode 31 side. In the first direction X, the end portion 23 of the extension portion 22 is located in the nitride semiconductor layer 10 below the region between the source electrode 31 and the gate electrode 33.

[0048] The second layer 12 is the uppermost layer of the nitride semiconductor layer 10, and it is closer to the gate electrode 33 in the third direction Z than other layers. By positioning the end 23 of the extension 22 at the aforementioned position, the extension 22 located in the second layer 12 can maintain the potential effect of the gate electrode 33 used to block the two-dimensional electron gas 200. Thus, by controlling the gate electrode 33, the semiconductor device 4 can be turned off.

[0049] [Fifth Implementation]

[0050] Figure 5 The semiconductor device 5 of the fifth embodiment shown also includes a negative electrode 34 disposed on the nitride semiconductor layer 10. The negative electrode 34 is disposed, for example, on the second layer 12. A negative potential, which is different from the potential of the source electrode 31, is applied to the negative electrode 34.

[0051] The connection portion 21 of the p-type semiconductor layer 20 is connected to the source electrode 31, but to the negative electrode 34. A lower potential (e.g., -20V) can be applied to the negative electrode 34 than the potential applied to the gate electrode 33 in the off state. This further facilitates the discharge of holes generated by impact ionization through the p-type semiconductor layer 20 to the negative electrode 34.

[0052] like Figure 6 As shown, for example, the negative electrode 34 is located in the terminal region 302 outside the cell region 301, where the source electrode 31, gate electrode 33, and drain electrode 32 are disposed. Therefore, the negative electrode 34 does not affect the arrangement of the source electrode 31, gate electrode 33, and drain electrode 32 in the cell region 301. For example, two terminal regions 302 located in the third direction Y, separated from the cell region 301, are respectively disposed with negative electrodes 34. The connection portion 21 of the p-type semiconductor layer 20 connects to the lower surface of the two negative electrodes 34 in the terminal region 302 and extends along the third direction Y. The extension portion 22 of the p-type semiconductor layer 20 extends from the connection portion 21 along the first direction X and is disposed in the cell region 301.

[0053] Alternatively, the negative electrode 34 can also be disposed on the nitride semiconductor layer 10 of the cell region 301.

[0054] The above-described embodiments can be appropriately combined with two or more embodiments within the scope of technical non-contradiction.

[0055] For example, any of the p-type semiconductor layers 20 in the first to fourth embodiments can also be used as the p-type semiconductor layer 20 connected to the negative electrode 34 in the fifth embodiment.

[0056] While several embodiments of the invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention as set forth in the claims and its equivalents.

[0057] Explanation of reference numerals in the attached figures

[0058] 1-5… Semiconductor device, 10… Nitride semiconductor layer, 11… First layer, 12… Second layer, 13… Buffer layer, 20… P-type semiconductor layer, 21… Connector, 22… Extension, 22A… First extension, 22B… Second extension, 31… Source electrode, 32… Drain electrode, 33… Gate electrode, 34… Negative electrode, 35… Source field plate electrode, 36… Gate field plate electrode, 41… Insulating film, 42… Protective film, 100… Substrate, 200… Two-dimensional electron gas, 301… Cell region, 302… Terminal region, S1… First interface, S2… Second interface

Claims

1. A semiconductor device, characterized in that, have: substrate; A nitride semiconductor layer is disposed on the substrate, having a first layer and a second layer disposed on the first layer and having a band gap wider than that of the first layer; The source electrode is disposed on the nitride semiconductor layer and is connected to the nitride semiconductor layer; The drain electrode is located in a first direction at a position separate from the source electrode, and is disposed on the nitride semiconductor layer and connected to the nitride semiconductor layer; A gate electrode is located between the source electrode and the drain electrode in the first direction; as well as An insulating film is disposed between the gate electrode and the nitride semiconductor layer. The nitride semiconductor layer has a p-type semiconductor layer. The p-type semiconductor layer has: a connection portion connected to the source electrode; and an extension portion extending from the connection portion within the nitride semiconductor layer along the first direction. The extension is located between the first interface and the second interface, and is not in contact with either the first interface or the second interface. The first interface is the interface between the first layer and the second layer, and the second interface is the interface between the substrate and the nitride semiconductor layer. The end of the extension in the first direction away from the connection portion is located between the end of the gate electrode on the drain electrode side and the end of the drain electrode on the gate electrode side in the first direction.

2. The semiconductor device according to claim 1, characterized in that, The extension is located in the first layer.

3. The semiconductor device according to claim 1, characterized in that, The nitride semiconductor layer further comprises a buffer layer disposed between the substrate and the first layer. The extension is located within the buffer layer.

4. The semiconductor device according to claim 1, characterized in that, The nitride semiconductor layer further includes a buffer layer disposed between the substrate and the first layer. The extension has a first extension located in the first layer and a second extension located in the buffer layer. The end of the second extension in the first direction that is away from the connection portion is located closer to the drain electrode in the first direction than the end of the first extension in the first direction that is away from the connection portion.

5. The semiconductor device according to claim 5, characterized in that, The extension is not in contact with the two-dimensional electron gas distributed in the first layer.

6. A semiconductor device, characterized in that, have: substrate; A nitride semiconductor layer is disposed on the substrate, having a first layer and a second layer disposed on the first layer and having a band gap wider than that of the first layer; The source electrode is disposed on the nitride semiconductor layer and is connected to the nitride semiconductor layer; The drain electrode is located in a first direction at a position separate from the source electrode, and is disposed on the nitride semiconductor layer and connected to the nitride semiconductor layer; A gate electrode is located between the source electrode and the drain electrode in the first direction; as well as An insulating film is disposed between the gate electrode and the nitride semiconductor layer. The nitride semiconductor layer has a p-type semiconductor layer. The p-type semiconductor layer has: a connection portion connected to the source electrode; and an extension portion extending from the connection portion within the nitride semiconductor layer along the first direction. The extension is located in the second layer. The end of the extension away from the connection portion in the first direction is located between the end of the source electrode on the gate electrode side and the end of the gate electrode on the source electrode side in the first direction.

7. The semiconductor device according to claim 6, characterized in that, The extension is not in contact with the two-dimensional electron gas distributed in the first layer.

8. A semiconductor device, characterized in that, have: substrate; A nitride semiconductor layer is disposed on the substrate, having a first layer and a second layer disposed on the first layer and having a band gap wider than that of the first layer; The source electrode is disposed on the nitride semiconductor layer and is connected to the nitride semiconductor layer; The drain electrode is located in a first direction at a position separate from the source electrode, and is disposed on the nitride semiconductor layer and connected to the nitride semiconductor layer; A gate electrode is located between the source electrode and the drain electrode in the first direction; An insulating film is disposed between the gate electrode and the nitride semiconductor layer, and The negative electrode is disposed on the nitride semiconductor layer and is given a negative potential. The nitride semiconductor layer has a p-type semiconductor layer connected to the negative electrode.

9. The semiconductor device according to claim 8, characterized in that, The p-type semiconductor layer has: a connection portion connected to the negative electrode; and an extension portion extending from the connection portion within the nitride semiconductor layer along the first direction. The extension is located between the first interface and the second interface, and is not in contact with either the first interface or the second interface. The first interface is the interface between the first layer and the second layer, and the second interface is the interface between the substrate and the nitride semiconductor layer. The region between the end of the extension away from the connection portion in the first direction and the end of the drain electrode side of the gate electrode in the first direction.

10. The semiconductor device according to claim 8, characterized in that, The negative electrode is located in the terminal region outside the cell region where the source electrode, the gate electrode, and the drain electrode are disposed.

11. The semiconductor device according to claim 8, characterized in that, The extension is not in contact with the two-dimensional electron gas distributed in the first layer.

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