Planar structure for improving short circuit endurance capability of power device and device thereof

Abstract

The invention belongs to the technical field of power semiconductors, and particularly provides a gate protection structure of a trench gate power device surface integrated reverse biased diode and a device thereof. A reverse biased diode cathode is connected with a polysilicon gate (7), an anode conductor is connected with a source electrode metal (12), active protection for a short circuit event is realized through an electric heating feedback gate voltage regulation mechanism, the short circuit endurance capability of the device is remarkably improved, and meanwhile, the problem of gate reliability caused by serious gate voltage negative oscillation in the rapid turn-off process of an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and an IGBT (Insulated Gate Bipolar Transistor) is solved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power device technology, specifically relating to a novel power device that integrates a reverse-biased polysilicon diode or a Schottky diode on the surface of a trench gate power device to improve the short-circuit withstand capability of the device. It is mainly applicable to improving the short-circuit capability of IGBTs and MOSFETs. Background Technology

[0002] As power semiconductor devices evolve towards higher voltage, higher frequency, and higher power density, the drain saturation current during short circuits is often very large. The simultaneous occurrence of high voltage and high current leads to a rapid increase in junction temperature, which can easily trigger thermal runaway and seriously threaten system reliability. Especially for high-power devices such as IGBTs and wide-bandgap semiconductors like MOSFETs, their extremely high saturation current density significantly shortens the short-circuit withstand time, typically to the order of microseconds, limiting their application in power electronic systems requiring high reliability.

[0003] To improve the short-circuit robustness of devices, existing technologies mostly focus on reducing saturation current to limit power consumption during faults. However, these methods often involve increased on-resistance, making it difficult to achieve comprehensive performance optimization without sacrificing other electrical characteristics. Therefore, there is an urgent need for a novel structure that can effectively improve the short-circuit withstand capability of devices without affecting their static and dynamic performance. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention proposes a gate protection structure for surface-integrated reverse-biased polysilicon diodes or Schottky diodes in trench-gate power devices. This structure can be widely applied to various power devices such as MOSFETs and IGBTs constructed from silicon-based, SiC-based, GaN-based, and other semiconductor materials with trench gate structures. The technical solution adopted by this invention is as follows:

[0005] 1. A MOSFET device cell with a trench gate surface integrated reverse-biased diode to improve short-circuit withstand capability, comprising:

[0006] The substrate (1) is an N-type heavily doped substrate (1) made of a first type of semiconductor, an N-type withstand voltage layer (2) made of a first type of semiconductor is disposed on the substrate (1), and a trench gate region is disposed at the middle position of the cell surface; an N-type current extension region (5) made of a first type of semiconductor is disposed on the N-type withstand voltage layer (2); a P-type base region (6) made of a first type of semiconductor is disposed on the N-type current extension region (5), a P-type heavily doped source ohmic contact region (3) made of a first type of semiconductor and an N-type heavily doped source ohmic contact region (4) made of a first type of semiconductor are disposed on the P-type base region (6), and a source ohmic contact metal (12) is disposed on the P-type heavily doped source ohmic contact region (3) and the N-type heavily doped source ohmic contact region (4), and a drain ohmic contact metal (13) is disposed at the bottom of the substrate (1); the trench gate region includes a trench wall dielectric layer (10) and an N-type heavily doped polysilicon gate region (7) located in the trench.

[0007] The feature is that a reverse bias diode with the cathode connected to the polysilicon gate (7) and the anode conductor connected to the source metal (12) is disposed between the polysilicon gate (7) and the source electrode (12); the reverse bias diode is composed of a cathode N-type heavily doped polysilicon (8), a polysilicon withstand voltage layer (9) and an anode conductor (14); the reverse bias diode is covered with a dielectric passivation layer (11).

[0008] The feature is that, when the reverse-biased diode is a PN junction diode, the polysilicon withstand voltage layer (9) can be composed of N-type or P-type lightly doped polysilicon, and its doping is generally 1×10⁻⁶. 17 cm -3 The anode conductor (14) is P-type heavily doped polycrystalline silicon.

[0009] Furthermore, when the reverse-biased diode is a Schottky diode, the polycrystalline silicon withstand voltage layer (9) is composed of N-type polycrystalline silicon, and its doping is generally 1×10⁻⁶. 17 cm -3 The anode conductor (14) is a Schottky contact metal, typically a common metal such as Al, Ti, Ni, or W, which forms a Schottky contact with the polycrystalline silicon withstand layer (9).

[0010] Furthermore, the first semiconductor material is silicon, SiC, Ga2O3, GaN, AlGaN, AlN, or diamond.

[0011] Furthermore, a P-type electric field shielding region (16) is provided at the bottom of the slot grid region within the N-type current extension region (5), and the P-type electric field shielding region (16) is in contact with the source ohmic contact metal (12) in the three-dimensional layout design.

[0012] Furthermore, electric field shielding regions (15) that penetrate deep into the semiconductor region are respectively provided on both sides of the trench gate below the P-type heavily doped source ohmic contact region (3), and the electric field shielding regions (15) penetrate deep into and are close to the bottom of the N-type current extension region (5).

[0013] Furthermore, a P-type electric field shielding region (16) is provided at the bottom of the slot grid region within the N-type current extension region (5), and the P-type electric field shielding region (16) is in contact with the source ohmic contact metal (12) in the three-dimensional layout design.

[0014] Furthermore, deep trenches are respectively provided on both sides of the trench gate, and P-type heavily doped electric field shielding regions (17) are provided on the sidewalls and bottom of the deep trenches within the semiconductor. The P-type heavily doped electric field shielding regions (17) are in contact with the P-type heavily doped source ohmic contact regions (3). Source metal (12) is provided in the deep trenches, and the source metal (12) in the deep trenches is in direct contact with the P-type heavily doped electric field shielding regions (17).

[0015] Furthermore, a P-type electric field shielding region (16) is provided at the bottom of the slot grid region within the N-type current extension region (5), and the P-type electric field shielding region (16) is in contact with the source ohmic contact metal (12) in the three-dimensional layout design.

[0016] Furthermore, deep trenches are respectively provided on both sides of the trench gate, and P-type heavily doped electric field shielding region (17) is provided in the semiconductor on the sidewall and bottom of the deep trench. The P-type heavily doped electric field shielding region (17) is in contact with the P-type heavily doped source ohmic contact region (3). A dielectric layer (10) and an N-type heavily doped polysilicon gate region (7) are sequentially provided in the deep trench. The N-type heavily doped polysilicon gate region (7) is connected to the source metal (12).

[0017] Furthermore, a P-type electric field shielding region (16) is provided at the bottom of the slot grid region within the N-type current extension region (5), and the P-type electric field shielding region (16) is in contact with the source ohmic contact metal (12) in the three-dimensional layout design.

[0018] 2. An IGBT device cell with a trench gate surface integrated reverse-biased diode to improve short-circuit withstand capability, comprising:

[0019] A P-type collector region (1) of the first semiconductor is disposed on the collector region (1), an N-type buffer layer (19) of the first semiconductor is disposed on the collector region (1), an N-type withstand voltage layer (2) of the first semiconductor is disposed on the buffer layer (19), and a trench gate region is disposed at the middle position of the cell surface; an N-type implantation enhancement region (5) of the first semiconductor is disposed on both sides of the trench gate above the N-type withstand voltage layer (2); a P-type base region (6) of the first semiconductor is disposed on the N-type implantation enhancement region (5), and a P-type base region (6) of the first semiconductor is disposed on the P-type base region (6). The device comprises a P-type heavily doped emitter ohmic contact region (3) made of a first type of semiconductor and an N-type heavily doped emitter ohmic contact region (4) made of the first type of semiconductor adjacent to the trench gate region. Emitter ohmic contact metal (12) is provided on the P-type heavily doped emitter ohmic contact region (3) and the N-type heavily doped emitter ohmic contact region (4). Collector ohmic contact metal (13) is provided at the bottom of the collector region (1). The trench gate region includes a trench wall dielectric layer (10) and an N-type heavily doped polysilicon gate region (7) located in the trench.

[0020] The feature is that a reverse bias diode with the cathode connected to the polysilicon gate (7) and the anode connected to the emitter metal (12) is disposed between the polysilicon gate (7) and the emitter metal (12); the reverse bias diode is composed of a cathode N-type heavily doped polysilicon (8), a polysilicon withstand voltage layer (9) and an anode conductor (14); the reverse bias diode is covered with a dielectric passivation layer (11).

[0021] Furthermore, when the reverse-biased diode is a PN junction diode, the polysilicon withstand voltage layer (9) can be composed of N-type or P-type lightly doped polysilicon, with a doping level typically between 1×10⁻⁶. 17 cm -3 The anode conductor (14) is P-type heavily doped polycrystalline silicon.

[0022] Furthermore, when the reverse-biased diode is a Schottky diode, the polycrystalline silicon withstand voltage layer (9) is composed of N-type polycrystalline silicon, and its doping is generally 1×10⁻⁶. 17 cm -3 The anode conductor (14) is a Schottky contact metal, typically a common metal such as Al, Ti, Ni, or W, which forms a Schottky contact with the polycrystalline silicon withstand layer (9).

[0023] Furthermore, the first semiconductor material is silicon, SiC, Ga2O3, GaN, AlGaN, AlN, or diamond.

[0024] Furthermore, a floating P-type electric field shielding area (16) is provided at the bottom of the slot grid area within the N-type withstand layer (2).

[0025] Furthermore, N virtual gates (N≥1) are respectively provided on both sides of the trench gate; the virtual gate includes a trench wall dielectric layer (10), an N-type heavily doped polysilicon gate region (7) located in the trench, and a semiconductor implantation enhancement region (5), a P-type base region (6), and a P-type ohmic contact region (3) located on both sides of the trench; emitter metal (12) is provided on the N-type heavily doped polysilicon gate region (7) and the P-type ohmic contact region (3) of the virtual gate.

[0026] Furthermore, a floating P-type electric field shielding area (16) is provided at the bottom of the slot grid and the virtual grid.

[0027] The effective effects of this invention are as follows:

[0028] 1. The present invention provides a MOSFET device with a reverse bias diode integrated on the trench gate surface and an IGBT device with a reverse bias diode integrated on the trench gate surface. The cathode of the reverse bias diode is connected to the polysilicon gate (7) and the anode conductor is connected to the source metal (12). Through the electrothermal feedback gate voltage regulation mechanism, active protection against short circuit events is achieved, which significantly improves the short circuit tolerance of the device.

[0029] 2. When the gate voltage fast switching causes negative gate voltage oscillation, the reverse bias diode will conduct in the forward direction, thereby clamping the gate voltage to the diode's forward voltage drop, preventing excessively high negative gate voltage oscillation from causing long-term reliability issues with the gate dielectric. Attached Figure Description

[0030] Figure 1 This is a cell diagram of the MOSFET device with a reverse-biased diode integrated on the trench gate surface in Example 1.

[0031] Figure 2 This is a cell diagram of a MOSFET device with an integrated reverse-biased diode on the gate surface of the trench with an electric field shielding area at the bottom, as shown in Example 2.

[0032] Figure 3 This is a cell diagram of a MOSFET device with an integrated reverse-biased diode on the surface of the slot gate, which has an electric field shielding region on both sides of the slot gate in Example 3.

[0033] Figure 4 This is a cell diagram of a MOSFET device with an integrated reverse-biased diode on the surface of the slot gate, which has electric field shielding areas on both sides and the bottom of the slot gate in Example 4.

[0034] Figure 5 This is a cell diagram of a MOSFET device with a deep trench electric field shielding region on both sides of the trench gate integrated with a reverse bias diode in Example 5.

[0035] Figure 6This is a cell diagram of a MOSFET device with a deep trench electric field shielding region on both sides of the trench gate and an electric field shielding region at the bottom of the trench, as shown in Example 6.

[0036] Figure 7 This is a comparison of the short-circuit withstand curves of one design in Example 6 and a conventional structure.

[0037] Figure 8 The image shows a comparison of the transfer characteristic curves of a design in Example 6 with those of a conventional structure.

[0038] Figure 9 This is a cell diagram of a MOSFET device with a deep trench electric field shielding region on both sides of the trench gate integrated with a reverse bias diode in Example 7.

[0039] Figure 10 This is a cell diagram of a MOSFET device with a deep trench electric field shielding region on both sides of the trench gate and an electric field shielding region at the bottom of the trench, as shown in Example 8.

[0040] Figure 11 This is a cell diagram of the IGBT device with a reverse-biased diode integrated on the trench gate surface in Example 9.

[0041] Figure 12 This is a cell diagram of an IGBT device with an electric field shielding area at the bottom of the tank and an integrated reverse-biased diode on the grid surface in Example 10.

[0042] Figure 13 This is a cell diagram of the IGBT device with a dummy gate and an integrated reverse bias diode on the trench gate surface in Example 11.

[0043] Figure 14 This is a cell diagram of the IGBT device with a dummy gate and an integrated reverse bias diode on the trench gate surface in Example 12.

[0044] In the figure: 1 is the N-type heavily doped substrate or P-type collector region of the first semiconductor material; 2 is the N-type withstand voltage layer; 3 is the P-type heavily doped ohmic contact region; 4 is the N-type heavily doped ohmic contact region; 5 is the N-type current extension region or N-type injection enhancement region; 6 is the P-type base region; 7 is the N-type heavily doped polysilicon gate region; 8 is the N-type heavily doped polysilicon; 9 is the polysilicon withstand voltage layer; 10 is the trench wall dielectric layer; 11 is the dielectric passivation layer; 12 is the source ohmic contact metal or emitter ohmic contact metal; 13 is the drain ohmic contact metal or collector ohmic contact metal; 14 is the anode conductor; 15 is the P-type electric field shielding region extending into the semiconductor region; 16 is the trench bottom P-type electric field shielding region; 17 is the P-type heavily doped electric field shielding region; and 19 is the N-type buffer layer. Detailed Implementation

[0045] To make the objectives, technical solutions, and technical effects of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0046] Example 1

[0047] This embodiment provides a MOSFET device with a reverse-biased diode integrated on the trench gate surface, as shown in the schematic diagram. Figure 1 As shown, it includes:

[0048] The substrate (1) is an N-type heavily doped substrate (1) made of a first type of semiconductor, an N-type withstand voltage layer (2) made of a first type of semiconductor is disposed on the substrate (1), and a trench gate region is disposed at the middle position of the cell surface; an N-type current extension region (5) made of a first type of semiconductor is disposed on the N-type withstand voltage layer (2); a P-type base region (6) made of a first type of semiconductor is disposed on the N-type current extension region (5), a P-type heavily doped source ohmic contact region (3) made of a first type of semiconductor and an N-type heavily doped source ohmic contact region (4) made of a first type of semiconductor are disposed on the P-type base region (6), and a source ohmic contact metal (12) is disposed on the P-type heavily doped source ohmic contact region (3) and the N-type heavily doped source ohmic contact region (4), and a drain ohmic contact metal (13) is disposed at the bottom of the substrate (1); the trench gate region includes a trench wall dielectric layer (10) and an N-type heavily doped polysilicon gate region (7) located in the trench.

[0049] The feature is that a reverse bias diode with the cathode connected to the polysilicon gate (7) and the anode conductor connected to the source metal (12) is disposed between the polysilicon gate (7) and the source electrode (12); the reverse bias diode is composed of a cathode N-type heavily doped polysilicon (8), a polysilicon withstand voltage layer (9) and an anode conductor (14); the reverse bias diode is covered with a dielectric passivation layer (11).

[0050] The feature is that, when the reverse-biased diode is a PN junction diode, the polysilicon withstand voltage layer (9) can be composed of N-type or P-type lightly doped polysilicon, and its doping is generally 1×10⁻⁶. 17 cm -3 The anode conductor (14) is P-type heavily doped polycrystalline silicon.

[0051] Furthermore, when the reverse-biased diode is a Schottky diode, the polycrystalline silicon withstand voltage layer (9) is composed of N-type polycrystalline silicon, and its doping is generally 1×10⁻⁶. 17 cm -3 The anode conductor (14) is a Schottky contact metal, typically a common metal such as Al, Ti, Ni, or W, which forms a Schottky contact with the polycrystalline silicon withstand layer (9).

[0052] Furthermore, the first semiconductor material is silicon, SiC, Ga2O3, GaN, AlGaN, AlN, or diamond.

[0053] The working principle of the MOSFET power device in this embodiment is as follows:

[0054] At room temperature, the polysilicon diode with its gate on the trench surface is in a reverse-biased state, having almost no effect on the gate drive. During a short circuit, the high drain voltage causes a sharp increase in channel current, resulting in significant power loss within the device, especially near the channel, and a rapid rise in lattice temperature. Meanwhile, the reverse leakage current of the reverse-biased polysilicon PN diode or Schottky diode positioned above the channel increases by several orders of magnitude with increasing device temperature. This leakage current generates a large voltage drop across the external gate resistor, diverting most of the applied gate voltage across it, while the gate voltage itself drops sharply. This sharp drop in gate voltage significantly weakens the device's channel conduction capability, causing a rapid decrease in saturation current. This prevents the device temperature from rising further. This temperature-triggered electrothermal negative feedback mechanism directly limits peak power dissipation during a short circuit, effectively curbing the rise in junction temperature, thus significantly extending the short-circuit withstand time, and potentially even achieving unrestricted short-circuit withstand time. Furthermore, when the device is turned off rapidly, if a negative gate voltage occurs, and the negative gate voltage is lower than the forward turn-on voltage of the integrated polysilicon PN junction diode or Schottky diode, the originally reverse-biased diode will start to be forward-biased, so that the negative gate voltage is clamped near the turn-on voltage of the diode, thus avoiding the negative gate voltage oscillation that would reduce gate reliability.

[0055] Example 2

[0056] This embodiment provides a MOSFET device with a reverse-biased diode integrated on the gate surface of the trench, where the trench bottom has an electric field shielding region. A schematic diagram is shown below. Figure 2 As shown. In Example 2, a P-type electric field shielding region (16) is provided at the bottom of the slot grid region described in Example 1, located in the N-type current extension region (5). The P-type electric field shielding region (16) is in contact with the source ohmic contact metal (12) in the three-dimensional layout design, and the rest of the structure is the same as in Example 1.

[0057] Example 3

[0058] This embodiment provides a MOSFET device with an integrated reverse-biased diode on the surface of the trench gate, having electric field shielding regions on both sides of the trench gate. A schematic diagram is shown below. Figure 3 As shown. In this embodiment, a P-type electric field shielding region (15) that extends into the semiconductor region is provided below the P-type ohmic contact region (3) on both sides of the slot gate described in embodiment 1. The P-type electric field shielding region (15) is close to the bottom of the N-type current extension region (5); the rest of the configuration is the same as in embodiment 1.

[0059] Example 4

[0060] This embodiment provides a MOSFET device with an integrated reverse-biased diode on the trench gate surface, having electric field shielding regions on both sides and the bottom of the trench gate. A schematic diagram is shown below. Figure 4 As shown. In Example 4, a P-type electric field shielding region (16) is provided at the bottom of the slot grid region of Example 3 within the N-type current extension region (5). The P-type electric field shielding region (16) is in contact with the source ohmic contact metal (12) in the three-dimensional layout design, and the rest of the structure is the same as that of Example 3.

[0061] Example 5

[0062] This embodiment provides a MOSFET device with a reverse-biased diode integrated on the surface of the trench gate, having deep trench electric field shielding regions on both sides of the trench gate. A schematic diagram is shown below. Figure 5 As shown. In Example 5, two deep trenches extending into the semiconductor are provided on both sides of the trench gate described in Example 1. The sidewalls and bottom of the deep trenches are provided with P-type heavily doped electric field shielding regions (17) located inside the semiconductor. The P-type heavily doped electric field shielding regions (17) are in contact with the P-type heavily doped source ohmic contact region (3). A source metal (12) is provided in the deep trenches. The source metal (12) in the deep trenches is in direct contact with the P-type heavily doped electric field shielding regions (17). The rest of the configuration is the same as in Example 1.

[0063] Example 6

[0064] This embodiment provides a MOSFET device with a reverse-biased diode integrated on the gate surface, having deep trench electric field shielding regions on both sides of the trench gate and an electric field shielding region at the bottom of the trench. A schematic diagram is shown below. Figure 6 As shown. In Example 6, a P-type electric field shielding region (16) is provided at the bottom of the slot grid region of Example 5 within the N-type current extension region (5). The P-type electric field shielding region (16) is in contact with the source ohmic contact metal (12) in the three-dimensional layout design, and the rest of the structure is the same as that of Example 5.

[0065] One specific case in this embodiment: The substrate (1) is doped with 1×10 19 cm -3 The thickness of SiC is assumed to be 2 μm in the simulation (in reality it is hundreds of μm, and the series resistance can be considered separately); the N-type withstand layer (2) is doped with 1×10 16 cm -3 SiC with a thickness of 12 μm; P-type heavily doped source ohmic contact region (3) is doped with 3×10 19 cm -3 SiC with a thickness of 0.3 μm; N-type heavily doped source ohmic contact region (4) is doped with 3×10 19 cm-3 The SiC has a thickness of 0.3 μm; the N-type current extension region (5) is doped with 5×10⁻⁶ ppm. 16 cm -3 The SiC has a thickness of 1.4 μm; the P-type base region (6) is doped with 1.5 × 10⁻⁶ ppm. 17 cm -3 SiC with a thickness of 0.5 μm; the P-type electric field shielding region (16) is set to a peak concentration of 1×10 19 cm -3 Gaussian doping; the P-type heavily doped electric field shielding region (17) is set to a peak concentration of 1×10⁻⁶. 19 cm -3 Gaussian doping; dielectric layer (10) is 50 nm SiO2; trench gate depth is 1.3 μm and width is 1 μm; deep trenches on both sides of the trench gate have a depth of 1.3 μm and a width of 1 μm, and a cell width of 5.1 μm; polysilicon gate (7) and N-type heavily doped polysilicon (8) are doped with 1×10 20 cm -3 The N-type polycrystalline silicon withstand layer (9) is doped with 4 × 10⁻⁶. 16 cm -3 The width is 0.8 μm, and the doping of the P-type heavily doped polycrystalline silicon (14) is 1×10⁻⁶. 18 cm -3 The thickness is 0.2 μm; the source ohmic contact metal (12) and drain ohmic contact metal (13) are Ti / Au, which are directly set as electrodes in the simulation; the dielectric passivation layer (11) is SiO2 or SiN, which can be omitted in the simulation; the simulation simulates the external gate resistance R in actual applications. G Set to 2 Ω.

[0066] The conventional structure used for comparison does not have a reverse-biased diode on its slot gate surface, but all other structures and parameters are exactly the same as in Example 6. Figure 7 This is a comparison of the short-circuit withstand curves of one design in Example 6 and a conventional structure. The conventional structure has a short-circuit withstand time of only 4.5 μs and a maximum lattice temperature exceeding 1200 K. With this invention, it can be seen that when a short circuit occurs, the maximum temperature within the device increases rapidly, just like in the conventional structure. Simultaneously, the leakage current of the polysilicon diode increases sharply, causing the applied gate voltage to drop rapidly due to the external gate resistance R. G This leads to an increase in the gate voltage V. GS The voltage drops rapidly from 15V to around 5V, thus reducing the drain current density J. DS The temperature is drastically reduced, and the internal temperature of the device is stabilized at around 700K, so that the device can remain in a short-circuit state without burning out.

[0067] Figure 8The image shows a comparison of the transfer characteristic curves of a design in Example 6 with that of a conventional structure. The conventional structure has a threshold voltage of 3.61 V and a specific on-resistance of 1.48 mΩ·cm. 2 In this embodiment, the threshold voltage is 3.82 V and the specific on-resistance is 1.49 mΩ·cm. 2 As can be seen, this embodiment introduces a polycrystalline silicon diode to improve short-circuit performance while causing almost no change in forward conduction performance.

[0068] Example 7

[0069] This embodiment provides a MOSFET device with a reverse-biased diode integrated on the surface of the trench gate, having deep trench electric field shielding regions on both sides of the trench gate. A schematic diagram is shown below. Figure 9 As shown; In Example 7, deep trenches are respectively provided on both sides of the trench gate described in Example 1. The sidewalls and bottom of the deep trenches are provided with P-type heavily doped electric field shielding regions (17) located in the semiconductor. The P-type heavily doped electric field shielding regions (17) are in contact with the P-type heavily doped source ohmic contact regions (3). A dielectric layer (10) and an N-type heavily doped polysilicon gate region (7) are sequentially provided in the deep trenches. The N-type heavily doped polysilicon gate region (7) is connected to the source metal (12). The rest of the settings are the same as in Example 1.

[0070] Example 8

[0071] This embodiment provides a MOSFET device with a reverse-biased diode integrated on the gate surface, having deep trench electric field shielding regions on both sides of the trench gate and an electric field shielding region at the bottom of the trench. A schematic diagram is shown below. Figure 10 As shown. In Example 8, a P-type electric field shielding region (16) is provided at the bottom of the slot gate region of Example 7 within the N-type current extension region (5). The P-type electric field shielding region (16) is in contact with the source ohmic contact metal (12) in the three-dimensional layout design, and the rest of the structure is the same as in Example 7.

[0072] Example 9

[0073] This embodiment provides an IGBT device with an integrated reverse-biased diode on the trench gate surface, as shown in the schematic diagram below. Figure 11 As shown, it includes:

[0074] A P-type collector region (1) of the first semiconductor is disposed on the collector region (1), an N-type buffer layer (19) of the first semiconductor is disposed on the collector region (1), an N-type withstand voltage layer (2) of the first semiconductor is disposed on the buffer layer (19), and a trench gate region is disposed at the middle position of the cell surface; an N-type implantation enhancement region (5) of the first semiconductor is disposed on both sides of the trench gate above the N-type withstand voltage layer (2); a P-type base region (6) of the first semiconductor is disposed on the N-type implantation enhancement region (5), and a P-type base region (6) of the first semiconductor is disposed on the P-type base region (6). The device comprises a P-type heavily doped emitter ohmic contact region (3) made of a first type of semiconductor and an N-type heavily doped emitter ohmic contact region (4) made of the first type of semiconductor adjacent to the trench gate region. Emitter ohmic contact metal (12) is provided on the P-type heavily doped emitter ohmic contact region (3) and the N-type heavily doped emitter ohmic contact region (4). Collector ohmic contact metal (13) is provided at the bottom of the collector region (1). The trench gate region includes a trench wall dielectric layer (10) and an N-type heavily doped polysilicon gate region (7) located in the trench.

[0075] The feature is that a reverse bias diode with the cathode connected to the polysilicon gate (7) and the anode connected to the emitter metal (12) is disposed between the polysilicon gate (7) and the emitter metal (12); the reverse bias diode is composed of a cathode N-type heavily doped polysilicon (8), a polysilicon withstand voltage layer (9) and an anode conductor (14); the reverse bias diode is covered with a dielectric passivation layer (11).

[0076] Furthermore, when the reverse-biased diode is a PN junction diode, the polysilicon withstand voltage layer (9) can be composed of N-type or P-type lightly doped polysilicon, with a doping level typically between 1×10⁻⁶. 17 cm -3 The anode conductor (14) is P-type heavily doped polycrystalline silicon.

[0077] Furthermore, when the reverse-biased diode is a Schottky diode, the polycrystalline silicon withstand voltage layer (9) is composed of N-type polycrystalline silicon, and its doping is generally 1×10⁻⁶. 17 cm -3 The anode conductor (14) is a Schottky contact metal, typically a common metal such as Al, Ti, Ni, or W, which forms a Schottky contact with the polycrystalline silicon withstand layer (9).

[0078] Furthermore, the first semiconductor material is silicon, SiC, Ga2O3, GaN, AlGaN, AlN, or diamond.

[0079] Example 10

[0080] This embodiment provides an IGBT device with an IGBT gate surface integrated with a reverse-biased diode having an electric field shielding region at the bottom of the tank, as shown in the schematic diagram below. Figure 12As shown. In Example 10, a floating P-type electric field shielding area (16) is provided at the bottom of the slot grid region of Example 9 within the N-type withstand layer (2), and the rest of the structure is the same as that of Example 9.

[0081] Example 11

[0082] This embodiment provides an IGBT device with a dummy gate and a surface-integrated reverse-biased diode in a trench gate, as shown in the schematic diagram below. Figure 13 As shown, in Example 11, N virtual gates (N≥1) are respectively provided on both sides of the trench gate described in Example 9; the virtual gate includes a trench wall dielectric layer (10), an N-type heavily doped polysilicon gate region (7) located in the trench, and a semiconductor implantation enhancement region (5), a P-type base region (6), and a P-type ohmic contact region (3) located on both sides of the trench; an emitter metal (12) is provided on the N-type heavily doped polysilicon gate region (7) and the P-type ohmic contact region (3) of the virtual gate.

[0083] Example 12

[0084] This embodiment provides an IGBT device with a dummy gate and a surface-integrated reverse-biased diode in a trench gate, as shown in the schematic diagram below. Figure 14 As shown, in Embodiment 12, a floating electric field shielding area (16) is provided at the bottom of the slot grid and the virtual grid described in Embodiment 11, and the rest of the settings are the same as in Embodiment 11.

[0085] The above description is merely a specific embodiment of the present invention. Any feature disclosed in this specification, unless specifically stated otherwise, can be replaced by other equivalent or similarly purposed alternative features. All disclosed features, or steps in all methods or processes, except for mutually exclusive features and / or steps, can be combined in any way. For example, in the above embodiments, the anode and cathode of the integrated diode are arranged in a two-dimensional arrangement on both sides. In actual three-dimensional devices, arrangements in other directions can be made to further reduce the cell size.

Claims

1. A MOSFET device cell with a trench gate surface integrated reverse-biased diode to improve short-circuit withstand capability, comprising: The substrate (1) is an N-type heavily doped substrate (1) made of a first type of semiconductor, an N-type withstand voltage layer (2) made of a first type of semiconductor is disposed on the substrate (1), and a trench gate region is disposed at the middle position of the cell surface; an N-type current extension region (5) made of a first type of semiconductor is disposed on the N-type withstand voltage layer (2); a P-type base region (6) made of a first type of semiconductor is disposed on the N-type current extension region (5), a P-type heavily doped source ohmic contact region (3) made of a first type of semiconductor and an N-type heavily doped source ohmic contact region (4) made of a first type of semiconductor are disposed on the P-type base region (6), and a source ohmic contact metal (12) is disposed on the P-type heavily doped source ohmic contact region (3) and the N-type heavily doped source ohmic contact region (4), and a drain ohmic contact metal (13) is disposed at the bottom of the substrate (1); the trench gate region includes a trench wall dielectric layer (10) and an N-type heavily doped polysilicon gate region (7) located in the trench. The feature is that a reverse bias diode with the cathode connected to the polysilicon gate (7) and the anode conductor connected to the source metal (12) is disposed between the polysilicon gate (7) and the source electrode (12); the reverse bias diode is composed of a cathode N-type heavily doped polysilicon (8), a polysilicon withstand voltage layer (9) and an anode conductor (14); the reverse bias diode is covered with a dielectric passivation layer (11).

2. As described in claim 1, characterized in that When the reverse bias diode is a PN junction diode, the polysilicon withstand voltage layer (9) can be composed of N-type or P-type lightly doped polysilicon, and its doping is generally 1×10⁻⁶. 17 cm -3 The anode conductor (14) is P-type heavily doped polycrystalline silicon.

3. As described in claim 1, characterized in that When the reverse-biased diode is a Schottky diode, the polysilicon withstand layer (9) is composed of N-type polysilicon, and its doping is generally 1×10⁻⁶. 17 cm -3 The anode conductor (14) is a Schottky contact metal, typically a common metal such as Al, Ti, Ni, or W, which forms a Schottky contact with the polycrystalline silicon withstand layer (9).

4. As described in claims 1-3, characterized in that The first semiconductor material is silicon, SiC, Ga2O3, GaN, AlGaN, AlN, or diamond.

5. As described in claims 1-4, characterized in that... The bottom of the slot grid region is located in the N-type current extension region (5) and a P-type electric field shielding region (16) is provided. The P-type electric field shielding region (16) is in contact with the source ohmic contact metal (12) in the three-dimensional layout design.

6. As described in claims 1-4, characterized in that On both sides of the trench gate, below the P-type heavily doped source ohmic contact region (3), there are electric field shielding regions (15) that penetrate into the semiconductor region. The electric field shielding regions (15) penetrate into and are close to the bottom of the N-type current extension region (5).

7. As described in claims 1-4 and 6, characterized in that The bottom of the slot grid region is located in the N-type current extension region (5) and a P-type electric field shielding region (16) is provided. The P-type electric field shielding region (16) is in contact with the source ohmic contact metal (12) in the three-dimensional layout design.

8. As described in claims 1-4, characterized in that Deep trenches are provided on both sides of the trench gate. P-type heavily doped electric field shielding regions (17) are provided on the sidewalls and bottom of the deep trenches within the semiconductor. The P-type heavily doped electric field shielding regions (17) are in contact with the P-type heavily doped source ohmic contact regions (3). Source metal (12) is provided in the deep trenches. The source metal (12) in the deep trenches is in direct contact with the P-type heavily doped electric field shielding regions (17).

9. As described in claims 1-4 and 8, characterized in that The bottom of the slot grid region is located in the N-type current extension region (5) and a P-type electric field shielding region (16) is provided. The P-type electric field shielding region (16) is in contact with the source ohmic contact metal (12) in the three-dimensional layout design.

10. As described in claims 1-4, characterized in that Deep trenches are provided on both sides of the trench gate. P-type heavily doped electric field shielding region (17) is provided on the sidewall and bottom of the deep trench within the semiconductor. The P-type heavily doped electric field shielding region (17) is in contact with the P-type heavily doped source ohmic contact region (3). A dielectric layer (10) and an N-type heavily doped polysilicon gate region (7) are sequentially provided in the deep trench. The N-type heavily doped polysilicon gate region (7) is connected to the source metal (12).

11. As described in claims 1-4 and 10, characterized in that The bottom of the slot grid region is located in the N-type current extension region (5) and a P-type electric field shielding region (16) is provided. The P-type electric field shielding region (16) is in contact with the source ohmic contact metal (12) in the three-dimensional layout design.

12. An IGBT device cell with a trench gate surface integrated reverse-biased diode to improve short-circuit withstand capability, comprising: A P-type collector region (1) of the first semiconductor is disposed on the collector region (1), an N-type buffer layer (19) of the first semiconductor is disposed on the collector region (1), an N-type withstand voltage layer (2) of the first semiconductor is disposed on the buffer layer (19), and a trench gate region is disposed at the middle position of the cell surface; an N-type implantation enhancement region (5) of the first semiconductor is disposed on both sides of the trench gate above the N-type withstand voltage layer (2); a P-type base region (6) of the first semiconductor is disposed on the N-type implantation enhancement region (5), and a P-type base region (6) of the first semiconductor is disposed on the P-type base region (6). The device comprises a P-type heavily doped emitter ohmic contact region (3) made of a first type of semiconductor and an N-type heavily doped emitter ohmic contact region (4) made of the first type of semiconductor adjacent to the trench gate region. Emitter ohmic contact metal (12) is provided on the P-type heavily doped emitter ohmic contact region (3) and the N-type heavily doped emitter ohmic contact region (4). Collector ohmic contact metal (13) is provided at the bottom of the collector region (1). The trench gate region includes a trench wall dielectric layer (10) and an N-type heavily doped polysilicon gate region (7) located in the trench. The feature is that a reverse bias diode with the cathode connected to the polysilicon gate (7) and the anode connected to the emitter metal (12) is disposed between the polysilicon gate (7) and the emitter metal (12); the reverse bias diode is composed of a cathode N-type heavily doped polysilicon (8), a polysilicon withstand voltage layer (9) and an anode conductor (14); the reverse bias diode is covered with a dielectric passivation layer (11).

13. As described in claim 12, characterized in that When the reverse bias diode is a PN junction diode, the polysilicon withstand voltage layer (9) can be composed of N-type or P-type lightly doped polysilicon, and its doping is generally 1×10⁻⁶. 17 cm -3 The anode conductor (14) is P-type heavily doped polycrystalline silicon.

14. As described in claim 12, characterized in that When the reverse-biased diode is a Schottky diode, the polysilicon withstand layer (9) is composed of N-type polysilicon, and its doping is generally 1×10⁻⁶. 17 cm -3 The anode conductor (14) is a Schottky contact metal, typically a common metal such as Al, Ti, Ni, or W, which forms a Schottky contact with the polycrystalline silicon withstand layer (9).

15. As described in claims 12-14, characterized in that The first semiconductor material is silicon, SiC, Ga2O3, GaN, AlGaN, AlN, or diamond.

16. As described in claims 12-15, characterized in that The bottom of the slot grid area is located within the N-type withstand layer (2) and is provided with a floating P-type electric field shielding area (16).

17. As described in claims 12-15, characterized in that N virtual gates (N≥1) are respectively provided on both sides of the trench gate; the virtual gate includes a trench wall dielectric layer (10), an N-type heavily doped polysilicon gate region (7) located in the trench, a floating P-type electric field shielding region (16) located at the bottom of the trench, and a semiconductor implantation enhancement region (5), a P-type base region (6), and a P-type ohmic contact region (3) located on both sides of the trench; an emitter metal (12) is provided on the N-type heavily doped polysilicon gate region (7) and the P-type ohmic contact region (3) of the virtual gate.

18. As described in claims 12-15 and 17, characterized in that The bottom of the slot grid and the virtual grid is provided with a floating P-type electric field shielding area (16).

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