Semiconductor device and preparation method thereof
By forming a first groove with its bottom lower than the substrate surface and forming a protective sidewall on the sidewall of the gate stack structure during the semiconductor device fabrication process, the device reliability problem caused by the side-cutting of the trench isolation structure in the fabrication of embedded germanium-silicon epitaxial layers is solved, and the device reliability and breakdown voltage are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-28
- Publication Date
- 2026-03-13
Smart Images
Figure CN121665660A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology
[0002] Embedded silicon germanium (eSiGe) technology is a strained silicon technology used to improve the performance of PMOS transistors. It increases the channel stress of PMOS transistors and enhances their carrier mobility by selectively forming embedded silicon germanium epitaxial layers in the source and drain regions of PMOS transistors.
[0003] However, existing fabrication processes for embedded germanium-silicon epitaxial layers typically involve first forming a gate stack structure on a substrate, then forming a first sidewall on the sidewalls of the gate stack structure. A sacrificial layer is then formed conformally on the substrate, the first sidewall, and the gate stack structure. After opening the sacrificial layer in the active region, the active regions on both sides of the gate stack structure are etched to form trenches. Silicon-germanium is then epitaxially grown inside and outside the trenches before the sacrificial layer is removed. The gate stack structure is usually strip-shaped, with part of each strip landing on the active region and the other part landing on the trench isolation structure. Figure 1a This is a schematic diagram of the morphology of an existing trench isolation structure after the grooves are formed. Figure 1b This is a schematic diagram showing the topography of the portion of the existing first sidewall located in the active region after the sacrificial layer has been removed. Figure 1c This is a VBD (Voltage to Breakdown, Vbd) test pattern for an existing embedded germanium-silicon epitaxial layer. (Example:) Figure 1a , Figure 1b and Figure 1c As shown, because a wet cleaning process is performed on the substrate during etching of the active region and before epitaxial growth of silicon-germanium inside and outside the trench, the wet cleaning process causes the portion of the trench isolation structure protruding from the substrate surface to be side-cut (e.g. Figure 1a (as shown by the dashed circle); the top of the trench isolation structure is higher than the surface of the substrate, so there is a height difference between the area of the first sidewall on the trench isolation structure and the area on the active region. When sidewalling occurs, the first sidewall is exposed at the junction of the active region and the trench isolation structure, which allows the etchant during the removal of the sacrificial layer to contact the first sidewall and damage it (e.g., as shown by the dashed circle); and the top of the trench isolation structure is higher than the surface of the substrate, so the area of the first sidewall on the trench isolation structure has a height difference with the area on the active region. When sidewalling occurs, the first sidewall is exposed at the junction of the active region and the trench isolation structure, which allows the etchant during the removal of the sacrificial layer to contact the first sidewall and damage it (e.g., as shown by the dashed circle). Figure 1b (As shown by the dashed circle), especially the part of the first sidewall located in the active region, will damage the device, eventually leading to a decrease in the breakdown voltage, VBD failure, and reliability issues.
[0004] Although it is currently possible to control the amount of sidewall cut in the trench isolation structure before removing the sacrificial layer to mitigate damage to the first sidewall, this narrows other related process windows and leads to other problems such as failure of embedded germanium-silicon epitaxial layer growth or deterioration of film quality. Summary of the Invention
[0005] The purpose of this invention is to provide a semiconductor device and its fabrication method to solve the problems of low reliability in existing semiconductor devices.
[0006] To achieve the above objectives, the present invention provides a method for fabricating a semiconductor device, comprising:
[0007] A substrate is provided having a trench isolation structure that defines an active region, the top of the trench isolation structure being higher than the surface of the substrate;
[0008] A plurality of gate stack structures are formed on the substrate. The gate stack structures extend along a first direction and are spaced apart along a second direction. Each gate stack structure includes a first part and a second part. The first part is located on the active region and the second part is located on the trench isolation structure.
[0009] The trench isolation structures on both sides of the second portion are etched to form a first groove, the bottom of which is lower than the surface of the substrate;
[0010] A first sidewall is formed on the sidewall of the gate stack structure, and the first sidewall extends into the first groove, at least covering the sidewall of the first groove near the center of the trench isolation structure.
[0011] A sacrificial layer is formed on the substrate, the sacrificial layer at least conformally covering the substrate, the first sidewall, and the top of the gate stack structure;
[0012] Open the sacrificial layers on both sides of the first portion and etch the active region to form a second groove;
[0013] An embedded epitaxial layer is formed in the second groove; and,
[0014] Remove the sacrificial layer.
[0015] Optionally, the first sidewall fills the first groove, and the sacrificial layer is located on the substrate; or, the first sidewall covers the sidewall of the first groove near the center of the trench isolation structure, and at least a portion of the sacrificial layer extends into and fills the first groove.
[0016] Optionally, the trench isolation structures on both sides of the second portion are etched using an isotropic etching process, so that the sidewall of the first groove near the center of the trench isolation structure protrudes in a direction toward the center of the trench isolation structure.
[0017] Optionally, the depth of the first groove is 10nm to 25nm.
[0018] Optionally, the gate stack structure includes a gate oxide layer, a gate electrode layer, and a gate masking layer stacked sequentially, and the sacrificial layer includes a protective layer and a mask layer stacked sequentially. The step of removing the sacrificial layer includes:
[0019] Remove the mask layer and the gate masking layer simultaneously;
[0020] Remove the protective layer.
[0021] Optionally, the material of the gate oxide layer is different from the material of the trench isolation structure.
[0022] Optionally, the gate oxide layer is made of silicon oxynitride, and the trench isolation structure is made of silicon oxide.
[0023] Optionally, the step of etching the active region includes:
[0024] The active region is etched using a dry etching process to form a second groove with an initial shape; and,
[0025] The active region is further etched along the second groove using a wet etching process to form the second groove with the final shape.
[0026] Optionally, after etching the active region using the dry etching process and before continuing to etch the active region along the second groove using the wet etching process, a wet cleaning process is performed on the substrate; and,
[0027] After the active region is etched along the second groove using the wet etching process, and before the embedded epitaxial layer is formed in the second groove, the substrate is subjected to another wet cleaning process.
[0028] Optionally, after removing the sacrificial layer, a second sidewall is formed that covers the first sidewall.
[0029] Optionally, the first sidewall fills the first groove, and the second sidewall is located on the substrate; or, the first sidewall covers the sidewall of the first groove near the center of the trench isolation structure, and at least a portion of the second sidewall extends into the first groove to fill it.
[0030] The present invention also provides a semiconductor device, comprising:
[0031] A substrate having a trench isolation structure defining an active region, the top of the trench isolation structure being higher than the surface of the substrate;
[0032] A plurality of gate stack structures are located on the substrate. The gate stack structures extend along a first direction and are spaced apart along a second direction. Each gate stack structure includes a first part and a second part. The first part is located on the active region, and the second part is located on the trench isolation structure.
[0033] A first groove is located in the trench isolation structure on both sides of the second portion, and the bottom of the first groove is lower than the surface of the substrate;
[0034] A first sidewall, located on the sidewall of the gate stack structure, extends into the first groove, at least covering the sidewall of the first groove near the center of the trench isolation structure; and,
[0035] An embedded epitaxial layer is located in the active regions on both sides of the first portion.
[0036] Optionally, the sidewall of the first groove near the center of the trench isolation structure protrudes in a direction toward the center of the trench isolation structure.
[0037] Optional, also includes:
[0038] The second side wall covers the first side wall.
[0039] Optionally, the first sidewall fills the first groove, and the second sidewall is located on the substrate; or, the first sidewall covers the sidewall of the first groove near the center of the trench isolation structure, and the second sidewall extends into the first groove to fill it.
[0040] Optionally, the depth of the first groove is 10nm to 25nm.
[0041] Optionally, the gate stack structure includes a gate oxide layer and a gate electrode layer stacked sequentially, wherein the material of the gate oxide layer is different from the material of the trench isolation structure.
[0042] Optionally, the gate oxide layer is made of silicon oxynitride, and the trench isolation structure is made of silicon oxide.
[0043] In the semiconductor device fabrication method provided by the present invention, a plurality of gate stack structures are formed on a substrate. The gate stack structures extend along a first direction and are spaced apart along a second direction. Each gate stack structure includes a first part and a second part. The first part is located on an active region within the substrate, and the second part is located on a trench isolation structure within the substrate. The trench isolation structure on both sides of the second part is etched to form a first groove. The bottom of the first groove is lower than the surface of the substrate. A first sidewall is formed on the sidewall of the gate stack structure. The first sidewall extends into the corresponding first groove and at least covers the sidewall of the corresponding first groove near the center of the trench isolation structure. A sacrificial layer is formed on the substrate. The sacrificial layer at least conformally covers the substrate, the first sidewall, and the top of the gate stack structure. The sacrificial layer on both sides of the first part is opened and the active region is etched to form a second groove. An embedded epitaxial layer is formed in the second groove. The sacrificial layer is removed. In this invention, the bottom of the first groove is lower than the surface of the substrate, and therefore the bottom of the first sidewall is also lower than the surface of the substrate. During the wet cleaning process performed when etching the active region and before forming the embedded epitaxial layer, the first sidewall can better protect the trench isolation structure, preventing the trench isolation structure from being side-cut, thereby avoiding damage to the first sidewall when removing the sacrificial layer, and thus improving the reliability of the semiconductor device. Accordingly, this invention also provides a semiconductor device. Attached Figure Description
[0044] Figure 1a This is a schematic diagram of the morphology of an existing trench isolation structure after the grooves are formed;
[0045] Figure 1b This is a schematic diagram of the morphology of the portion of the existing gate stack structure located on the active region after the sacrificial layer has been removed.
[0046] Figure 1c VBD test pattern of an existing embedded germanium-silicon epitaxial layer;
[0047] Figure 2 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention;
[0048] Figure 3~ Figure 13 The diagram shows the corresponding structural steps of the semiconductor device fabrication method provided in the embodiments of the present invention. Figure 13 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;
[0049] Figure 14 This is a schematic diagram of the topography of the trench isolation structure of a semiconductor device provided in an embodiment of the present invention;
[0050] The attached figures are labeled as follows:
[0051] 100 - Substrate; 101 - First trench, STI - Trench isolation structure; 200 - Gate stack structure; 201 - Gate oxide layer; 202 - Gate electrode layer; 203 - Gate masking layer; 204 - First sub-sidewall; 214 - First sub-sidewall material layer; 205 - Second sub-sidewall; 215 - Second sub-sidewall material layer; 206 - Third sub-sidewall; 207 - Fourth sub-sidewall; 301 - Protective layer; 401 - Mask layer; 501 - Second trench; 511 - Embedded epitaxial layer; 600 - Cap layer. Detailed Implementation
[0052] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0053] Figure 13 This is a schematic diagram of the semiconductor device provided in this embodiment. Figure 13 As shown, the semiconductor device includes a substrate 100, which can be made of semiconductor substrates such as silicon, silicon-on-insulator, germanium, silicon-germanium, or germanium-on-insulator. A trench isolation structure STI is formed in the substrate 100, extending from the substrate 100 into the substrate 100, and is used to define active regions AA within the substrate 100. Two adjacent active regions AA are isolated by the trench isolation structure STI.
[0054] In this embodiment, the top of the trench isolation structure STI is higher than the surface of the substrate 100. The material of the trench isolation structure STI is silicon oxide, but it should not be limited to this. In other embodiments, the trench isolation structure STI can also be other dielectric materials, such as high-k dielectrics such as metal oxides.
[0055] Combination Figure 3aAs shown, the substrate 100 has a plurality of gate stack structures 200, each gate stack structure 200 being strip-shaped and extending along a first direction x and spaced apart along a second direction y. For each gate stack structure 200, in the first direction x, a portion of the gate stack structure 200 is located on the trench isolation structure STI, and another portion is located on the active region AA. For ease of distinction, the portion of the gate stack structure 200 located on the active region AA (i.e., the portion overlapping with the active region AA) is referred to as the first portion, and the portion of the gate stack structure 200 located on the trench isolation structure STI (i.e., the portion overlapping with the trench isolation structure STI) is referred to as the second portion. It can be understood that the first portion and the second portion of the same gate stack structure 200 are actually an integral structure, which are different regions of the same gate stack structure 200.
[0056] Please continue reading. Figure 13 The gate stack structure 200 includes a gate oxide layer 201 and a gate electrode layer 202. Both the gate oxide layer 201 and the gate electrode layer 202 are patterned film layers, and the gate oxide layer 201 and the gate electrode layer 202 are stacked sequentially from bottom to top.
[0057] In this embodiment, the material of the gate oxide layer 201 is different from the material of the trench isolation structure STI, thereby avoiding damage to the gate oxide layer 201 during the etching process of the trench isolation structure STI when fabricating the semiconductor device. Furthermore, by selecting a suitable material, the dielectric constant of the gate oxide layer 201 can be changed. For example, when the material of the trench isolation structure STI is silicon oxide, the material of the gate oxide layer 201 can be silicon oxynitride. The material of the gate electrode layer 202 is typically a conductive material such as polycrystalline silicon or a metal.
[0058] Furthermore, the trench isolation structure STI has a first groove 101 located on both sides of the second portion and extending from the surface of the trench isolation structure STI into the trench isolation structure STI. The bottom of the first groove 101 needs to be lower than the surface of the substrate 100 (i.e., lower than the surface of the active region AA). Figure 13 As can be seen, the groove isolation structure STI is roughly convex in shape, and the surface of the groove isolation structure STI has a protrusion. The protrusion is sandwiched between two first grooves 101, and the second part is located on the protrusion.
[0059] Optionally, the depth of the first groove can be 10nm to 25nm, but should not be limited to this.
[0060] The semiconductor device further includes a first sidewall that covers the sidewalls of the gate stack structure 200, meaning the first sidewall covers both the sidewalls of the first portion and the second portion. The first sidewall is typically a stacked structure made of dielectric materials such as silicon oxide or silicon nitride. For example, in this embodiment, the first sidewall includes a first sub-sidewall 204 and a second sub-sidewall 205. The first sub-sidewall 204 covers the sidewalls of the gate oxide layer 201 and the gate electrode layer 202 and extends to cover a portion of the surface of the substrate 100 (or the trench isolation structure STI). The second sub-sidewall 205 is located on the first sub-sidewall 204 and covers its surface. Furthermore, the material of the first sub-sidewall 204 is typically a dielectric material such as silicon oxide, while the second sub-sidewall 205 can be a dielectric material such as silicon nitride.
[0061] Please continue reading. Figure 13 Since the first part is located on the active region AA, the area of the first sidewall covering the sidewall of the first part is also located on the active region AA. The second part is located on the trench isolation structure STI, so the area of the first sidewall covering the sidewall of the second part extends into the first groove 101 and covers the sidewall of the first groove 101 near the center of the trench isolation structure STI. In this way, the first sidewall actually covers the sidewall of the protrusion, thereby ensuring that the trench isolation structure STI is not side-cut during the fabrication of the semiconductor device, which will be described in detail later.
[0062] Furthermore, from Figure 13 As can be seen, the bottom of the first sidewall has a height difference. Specifically, the bottom of the area of the first sidewall covering the first part of the sidewall is higher than the bottom of the area covering the second part of the sidewall. For the first sidewall covering any sidewall of the same gate stack structure 200, the bottom of the first sidewall has a step at the junction of the active region AA and the trench isolation structure STI.
[0063] Furthermore, the semiconductor device also includes a second sidewall that covers the first sidewall. In this embodiment, the second sidewall includes a third sub-sidewall 206 and a fourth sub-sidewall 207. The third sub-sidewall 206 covers the first sidewall (specifically, it covers the second sub-sidewall 205), and the fourth sub-sidewall 207 covers the third sub-sidewall 206. The material of the third sub-sidewall 206 is typically a dielectric material such as silicon oxide, while the fourth sub-sidewall 207 can be a dielectric material such as silicon nitride.
[0064] Furthermore, since the first sidewall in this embodiment covers the sidewall of the first groove 101 near the center of the trench isolation structure STI, but does not completely fill the first groove 101, the second sidewall also extends into the first groove 101 to fill it. Specifically, the third sub-sidewall 206 covers the second sub-sidewall 205 and extends into the corresponding first groove 101 to fill it, while the fourth sub-sidewall 207 is located on the substrate 100 and covers the portion of the sidewall of the third sub-sidewall 206 that extends beyond the first groove 101.
[0065] It should be noted that in some embodiments, if the width of the trench isolation structure STI is small, the width of the first groove 101 will also be small, and the first sidewall may directly fill the first groove 101. In this case, the second sidewall will not enter the first groove 101, but will only be located on the substrate 100. Correspondingly, in some embodiments, if the third sub-sidewall 206 cannot fill the first groove 101, at least a portion of the fourth sub-sidewall 207 will extend into the corresponding first groove 101 to fill it; or, in some embodiments, the third sub-sidewall 206 may also partially fill the first groove 101, with the other portion located on the substrate 100.
[0066] Furthermore, the semiconductor device also includes a lightly doped drain (LDD) and a doped pocket region. The lightly doped drain is located on both sides of the gate stack structure 200, primarily within the active region AA (and partially within the trench isolation structure STI). The doped pocket region surrounds the corresponding lightly doped drain near the channel. The lightly doped drain improves the short-channel effect of the transistor, and the shallow junction formed between the lightly doped drain and the channel helps reduce leakage current. The doped pocket region narrows the depletion region below the gate stack structure 200, mitigating the short-channel effect and further reducing leakage current.
[0067] The type of dopant ions in the lightly doped region is consistent with the type of transistor to be formed, while the type of dopant ions in the doped pocket region is opposite to the type of transistor to be formed. In this embodiment, the type of transistor to be formed is a PMOS transistor, the dopant ions in the lightly doped region are one or more P-type ions selected from B, Ga, or In, and the dopant ions in the doped pocket region are one or more N-type ions selected from P, As, or Sb.
[0068] The semiconductor device further includes an embedded epitaxial layer 511 located in the active regions AA on both sides of the gate stack structure 200 (specifically the first part) and extending through the lightly doped region into the substrate 100. The embedded epitaxial layer 511 on both sides of the gate stack structure 200 is doped for source and drain respectively, thus serving as the source and drain.
[0069] In this embodiment, the material of the embedded epitaxial layer 511 can be germanium silicon, and the shape of the embedded epitaxial layer 511 is diamond-shaped, that is, the “∑” shape recognized in the industry, but it should not be limited to this. In some embodiments, the material of the embedded epitaxial layer 511 can be other possible epitaxial materials, and the shape of the embedded epitaxial layer 511 can also be other shapes, such as rectangle, inverted trapezoid, U-shape, etc.
[0070] Each of the embedded epitaxial layers 511 also has a cap layer 600 covering the corresponding embedded epitaxial layer 511. The cap layer 600 can protect the embedded epitaxial layer 511 and can be converted into a metal silicide layer to serve as the contact metal of the embedded epitaxial layer 511.
[0071] In this embodiment, the capping layer 600 may be made of silicon and may be doped with boron to increase the carrier concentration.
[0072] Based on this, this embodiment also provides a method for fabricating the semiconductor device. Figure 2 This is a flowchart illustrating the fabrication method of the semiconductor device provided in this embodiment. Figure 2 As shown, the method for fabricating the semiconductor device includes:
[0073] Step S100: Provide a substrate having a trench isolation structure defining an active region, the top of the trench isolation structure being higher than the surface of the substrate;
[0074] Step S200: A plurality of gate stack structures are formed on the substrate. The gate stack structures extend along a first direction and are spaced apart along a second direction. Each gate stack structure includes a first part and a second part. The first part is located on the active region and the second part is located on the trench isolation structure.
[0075] Step S300: Etch the trench isolation structure on both sides of the second portion to form a first groove, the bottom of the first groove being lower than the surface of the substrate;
[0076] Step S400: A first sidewall is formed on the sidewall of the gate stack structure, the first sidewall extending into the corresponding first groove, at least covering the sidewall of the corresponding first groove near the center of the trench isolation structure;
[0077] Step S500: A sacrificial layer is formed on the substrate, the sacrificial layer at least conformally covering the substrate, the first sidewall, and the top of the gate stack structure;
[0078] Step S600: Open the sacrificial layer on both sides of the first portion and etch the active region to form a second groove;
[0079] Step S700: Form an embedded epitaxial layer in the second groove; and,
[0080] Step S800: Remove the sacrificial layer.
[0081] Figures 3a to 13 This is a schematic diagram of the structure corresponding to the steps of the semiconductor device fabrication method provided in this embodiment. Next, we will combine... Figures 3a to 13 The method for fabricating the semiconductor device provided in this embodiment will be described in detail.
[0082] like Figure 3a and Figure 3b As shown, where, Figure 3b yes Figure 3a A schematic cross-sectional view of the semiconductor structure along the BB direction is shown in step S100. The substrate 100 is provided, and a trench isolation structure STI is formed in the substrate 100. The trench isolation structure STI extends from the surface of the substrate 100 into the substrate 100 for isolating two adjacent active regions AA. The top of the trench isolation structure STI is higher than the surface of the substrate 100.
[0083] The method for forming the trench isolation structure STI can be, for example, forming a mask layer on the substrate 100. Figure 3a and Figure 3b (Not shown in the image), then the mask layer and a portion of the substrate 100 are etched to form an isolation trench. An isolation material is then filled into the isolation trench, and planarization is performed to remove the isolation material from the mask layer. The mask layer is then removed. The isolation material within the isolation trench constitutes the trench isolation structure (STI). After removing the mask layer, the top of the trench isolation structure STI will be higher than the surface of the substrate 100. The thickness of the trench isolation structure STI extending beyond the surface of the substrate 100 is the thickness of the mask layer.
[0084] In this embodiment, the isolation material is silicon oxide, therefore the material of the trench isolation structure STI is silicon oxide, but it should not be limited thereto. In other embodiments, the isolation material can also be other dielectric materials, such as high-k dielectrics like metal oxides.
[0085] Please continue reading. Figure 3a and Figure 3b Step S200 is executed, in which a plurality of gate stack structures 200 are formed on the substrate 100. Each gate stack structure 200 is strip-shaped and extends along a first direction x and is spaced apart along a second direction y. Each gate stack structure 200 includes a first part and a second part. The first part is located on the active region AA, and the second part is located on the trench isolation structure STI. That is, the first part is the portion of the gate stack structure 200 that overlaps with the active region AA, and the second part is the portion of the gate stack structure 200 that overlaps with the trench isolation structure STI.
[0086] In this step, each gate stack structure 200 includes a gate oxide layer 201, a gate electrode layer 202, and a gate shielding layer 203, which are stacked sequentially from bottom to top. In this embodiment, the material of the gate oxide layer 201 is different from the material of the trench isolation structure STI. Specifically, the material of the gate oxide layer 201 is silicon oxynitride, the material of the gate electrode layer 202 can be polysilicon or a metal or other conductive material, and the material of the gate shielding layer 203 can be silicon nitride or other dielectric material.
[0087] like Figure 4 As shown, in step S300, the trench isolation structure STI on both sides of the second portion is etched to form a first groove 101 in the trench isolation structure STI on both sides of the second portion. The bottom of the first groove 101 needs to be lower than the surface of the substrate 100. After etching, the trench isolation structure STI has a protrusion sandwiched between the two first grooves 101 in the trench isolation structure STI.
[0088] It is understood that, since the material of the trench isolation structure STI is different from the material of the gate oxide layer 201, by selecting the etchant for etching the trench isolation structure STI, it can be ensured that the gate oxide layer 201 is not damaged when etching the trench isolation structure STI.
[0089] In this embodiment, the etching amount of the trench isolation structure STI can be 10nm to 25nm, so the depth of the first groove 101 formed can also be 10nm to 25nm, but should not be limited thereto. The etching amount of the trench isolation structure STI can be determined according to the height difference between the top of the trench isolation structure STI and the surface of the substrate 100, and at least it needs to be ensured that the bottom of the first groove 101 is lower than the surface of the substrate 100.
[0090] In some embodiments, an isotropic etching process (either dry or wet etching) can be used to etch the trench isolation structure STI on both sides of the second portion. In this embodiment, a wet etching process is used, and the etchant for the wet etching process is a hydrogen fluoride solution. Due to the etching characteristics of the isotropic etching process, the sidewall of the first groove 101 formed near the center of the trench isolation structure STI will protrude towards the center of the trench isolation structure STI. As a result, the protruding part of the trench isolation structure STI will have a constricted shape that is wide at both ends and narrow in the middle.
[0091] like Figure 5 As shown, in step S400, a first sub-sidewall material layer 214 and a second sub-sidewall material layer 215 are sequentially formed on the substrate 100. The first sub-sidewall material layer 214 and the second sub-sidewall material layer 215 are stacked sequentially and cover the sidewalls and top of the substrate 100 and the gate stack structure 200 in a conformal manner, and also extend into the first groove 101 to fill the first groove 101 (or it may only cover the inner wall of the first groove 101).
[0092] like Figure 6 As shown, the second sub-sidewall material layer 215 and the first sub-sidewall material layer 214 are etched using a dry etching process, thereby removing the second sub-sidewall material layer 215 and the first sub-sidewall material layer 214 on the substrate 100 and the top of the gate stack structure 200, while retaining the second sub-sidewall material layer 215 and the first sub-sidewall material layer 214 on the sidewall of the gate stack structure 200. The second sub-sidewall material layer 215 and the first sub-sidewall material layer 214 on the sidewall of the gate stack structure 200 respectively constitute the second sub-sidewall 205 and the first sub-sidewall 204, and the second sub-sidewall 205 and the first sub-sidewall 204 ultimately constitute the first sidewall.
[0093] from Figure 6As can be seen, the first sidewall covers the sidewalls of the gate stack structure 200, that is, the sidewalls of the gate oxide layer 201, the gate electrode layer 202, and the gate shielding layer 203. The area covered by the first sidewall for the first portion is only located on the substrate 100, while the area covering the second portion extends into the corresponding first groove 101, covering the sidewall of the corresponding first groove 101 near the center of the trench isolation structure STI. In this way, the first sidewall can cover the sidewall of the protrusion of the trench isolation structure STI, thereby protecting the trench isolation structure STI.
[0094] It should be noted that when the sidewall of the first groove 101 near the center of the groove isolation structure STI protrudes towards the center of the groove isolation structure STI, the portion of the first sidewall located within the first groove 101 will also replicate the shape of the first groove 101. In this way, the first sidewall can better include the protruding part of the groove isolation structure STI and further ensure that the groove isolation structure STI will not be side-cut.
[0095] In this embodiment, the material of the first sub-sidewall material layer 214 is typically a dielectric material such as silicon oxide, while the material of the second sub-sidewall material layer 215 can be a dielectric material such as silicon nitride. Since the first sub-sidewall 204 and the second sub-sidewall 205 are obtained by etching the first sub-sidewall material layer 214 and the second sub-sidewall material layer 215, respectively, the material of the first sub-sidewall 204 can also be a dielectric material such as silicon oxide, and the material of the second sub-sidewall 205 can also be a dielectric material such as silicon nitride.
[0096] like Figure 7 As shown, ion implantation is performed on the substrate 100 on both sides of the gate stack structure 200 (mainly for the active region AA) to form the lightly doped region and the doped pocket region in the active region AA on both sides of the gate stack structure 200, the doped pocket region surrounding the corresponding lightly doped region on the side near the channel.
[0097] Please continue reading. Figure 7 In step S500, a protective layer 301 and a mask layer 401 are sequentially formed on the substrate 100. The protective layer 301 and the mask layer 401 are stacked sequentially and conformally cover the substrate 100, the first sidewall, and the top of the gate stack structure 200. Since the first sidewall in this embodiment does not completely fill the first groove 101, the protective layer 301 also extends into the first groove 101 to fill it. The protective layer 301 and the mask layer 401 together constitute a sacrificial layer.
[0098] In some embodiments, if the first sidewall completely fills the first groove 101, the protective layer 301 will not enter the first groove 101; or, if the protective layer 301 does not completely fill the first groove 101, at least a portion of the mask layer 401 will enter and fill the first groove 101; or, the protective layer 301 may partially fill the first groove 101, with another portion located on the substrate 100. In any case, as long as the sacrificial layer can conformally cover the substrate 100, the first sidewall, and the top of the gate stack structure 200, whether the sacrificial layer needs to extend into the first groove 101 depends on the width of the first groove 101 and the thickness of the sacrificial layer.
[0099] In this embodiment, the protective layer 301 and the mask layer 401 are formed using atomic layer deposition (ALD) technology. However, this should be limited to the present invention, and other deposition processes may also be used to form the protective layer 301 and the mask layer 401.
[0100] Furthermore, the protective layer 301 can be made of silicon oxide or silicon oxynitride, and the thickness of the protective layer 301 is preferably 3 nm to 5 nm. The mask layer 401 can be made of silicon nitride, and the thickness of the mask layer 401 is preferably 100 nm to 150 nm.
[0101] like Figure 8 As shown, in step S600, the mask layer 401 and the protective layer 301 are etched using a dry etching process, thereby removing the mask layer 401 and the protective layer 301 on both sides of the first part, opening the mask layer 401 and the protective layer 301 on both sides of the first part, and exposing the active regions AA on both sides of the first part.
[0102] Please continue reading. Figure 8 The active regions AA on both sides of the first portion are etched to form a second groove 501. The second groove 501 extends downward from the surface of the substrate 100, beyond the lightly doped region, and continues to extend downward into the interior of the substrate 100. In this embodiment, the shape of the second groove 501 is diamond-shaped, but it should not be limited thereto. In some embodiments, the shape of the second groove 501 can also be designed as a rectangle, an inverted trapezoid, a U-shape, etc., as needed.
[0103] The specific steps for forming the second groove 501 are as follows: First, a dry etching process is performed on the substrate 100 to form the second groove 501 with an initial shape, which is typically U-shaped. Then, a wet etching process is performed on the substrate 100, where the etchant flows into the second groove 501 to continue etching the substrate 100 within the second groove 501. Because the etchant in the wet etching process is selective for crystal orientation, the shape and size of the second groove 501 will change after etching, forming the second groove 501 with its final shape. In this embodiment, the etchant used in the wet etching process on the substrate 100 is tetramethylammonium hydroxide (TMAN). This etchant... <111> The etching rate of the crystal orientation is lower than that of other crystal orientations. After etching is completed, the final shape of the second groove 501 is diamond-shaped.
[0104] In some embodiments, the etchant used in the wet etching process of the substrate 100 may also be potassium hydroxide (KOH).
[0105] It should be noted that when the mask layer 401 and the protective layer 301 on both sides of the first portion are etched to open the active region AA, and when the substrate 100 is etched to form the second groove 501, the mask layer 401 and the protective layer 301 on top of the gate stack structure 200 are also removed. It is conceivable that the remaining mask layer 401 and the protective layer 301 may only be located on the sidewalls of the gate stack structure 200 and on the sidewall of the first groove 101 near the center of the trench isolation structure STI.
[0106] Furthermore, after etching the substrate 100 using a dry etching process, a wet cleaning process is performed to remove the polymer generated during etching and residual photoresist. After wet etching the substrate 100, another wet cleaning process is performed to clean the inner wall of the second groove 501 and remove the oxide material from the inner wall of the second groove 501. The cleaning agent in the wet cleaning process typically contains hydrofluoric acid, which easily corrodes the trench isolation structure STI. In this embodiment, the sidewalls of the protrusions of the trench isolation structure STI are covered by the first sidewall. During the wet cleaning process, the hydrofluoric acid will not contact the protrusions of the trench isolation structure STI, thus preventing the trench isolation structure STI from being side-cut.
[0107] like Figure 9As shown, in step S700, the embedded epitaxial layer 511 is formed in the second groove 501 using a selective epitaxy process, and the embedded epitaxial layer 511 can fill the second groove 501. The selective epitaxial growth process can be any one of low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), and molecular beam epitaxy (MBE).
[0108] like Figure 10 As shown, a capping layer 600 is formed on each of the embedded epitaxial layers 511, the capping layer 600 covering the corresponding embedded epitaxial layer 511, and can be subsequently converted into a metal silicide layer as the contact metal of the embedded epitaxial layer 511.
[0109] like Figure 11 As shown, in step S800, the mask layer 401 is stripped with phosphoric acid. In this embodiment, since the gate masking layer 203 is made of the same material as the mask layer 401, the gate masking layer 203 will also be removed synchronously, so that the gate stack structure 200 is left with only the gate oxide layer 201 and the gate electrode layer 202.
[0110] It should be noted that, in Figure 8 During the wet cleaning process, since the first sidewall protects the trench isolation structure STI (specifically, the protrusion of the trench isolation structure STI), the trench isolation structure STI is not side-exposed. When the mask layer 401 is removed, the first sidewall is not exposed, so phosphoric acid will not come into contact with the first sidewall, thereby avoiding damage to the first sidewall by phosphoric acid and improving the reliability of the semiconductor device.
[0111] like Figure 12 As shown, the protective layer 301 is removed using hydrofluoric acid.
[0112] like Figure 13 As shown, a second sidewall is formed on the sidewall of the gate stack structure 200, and the second sidewall covers the first sidewall. In this embodiment, the second sidewall includes a third sub-sidewall 206 and a fourth sub-sidewall 207. The third sub-sidewall 206 covers the first sidewall, and the fourth sub-sidewall 207 covers the third sub-sidewall 206. Furthermore, the material of the third sub-sidewall 206 is typically a dielectric material such as silicon oxide, while the fourth sub-sidewall 207 can be a dielectric material such as silicon nitride. The method for forming the second sidewall is similar to the method for forming the first sidewall, and will not be described again here.
[0113] Subsequently, source and drain electrodes can be formed by source and drain doping in the embedded epitaxial layer 511 on both sides of each gate stack structure 200.
[0114] Figure 14 This is a schematic diagram of the topography of the trench isolation structure (STI) of the semiconductor device provided in this embodiment. Figure 14 As can be seen, the first sidewall in this embodiment can effectively protect the trench isolation structure STI. The trench isolation structure STI is not side-cut during the fabrication of the semiconductor device, thus avoiding damage to the first sidewall when removing the sacrificial layer.
[0115] In summary, in the semiconductor device fabrication method provided in this embodiment of the invention, a plurality of gate stack structures are formed on a substrate. The gate stack structures extend along a first direction and are spaced apart along a second direction. Each gate stack structure includes a first portion and a second portion. The first portion is located on an active region within the substrate, and the second portion is located on a trench isolation structure within the substrate. The trench isolation structure on both sides of the second portion is etched to form a first groove, the bottom of which is lower than the surface of the substrate. A first sidewall is formed on the sidewall of the gate stack structure, the first sidewall extending into the corresponding first groove and at least covering the sidewall of the corresponding first groove near the center of the trench isolation structure. A sacrificial layer is formed on the substrate, the sacrificial layer at least conformally covering the substrate, the first sidewall, and the top of the gate stack structure. The sacrificial layer on both sides of the first portion is opened and the active region is etched to form a second groove. An embedded epitaxial layer is formed in the second groove. The sacrificial layer is then removed. In this invention, the bottom of the first groove is lower than the surface of the substrate. Therefore, the bottom of the first sidewall is also lower than the surface of the substrate. During the wet cleaning process performed when etching the active region and before forming the embedded epitaxial layer, the first sidewall can better protect the trench isolation structure, preventing the trench isolation structure from being side-cut, thereby avoiding damage to the first sidewall when removing the sacrificial layer, and thus improving the reliability of the semiconductor device. Accordingly, this invention also provides a semiconductor device.
[0116] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.
[0117] It should also be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.
[0118] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.
[0119] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and not to limit the scope of the invention. It must be noted that the singular forms “a” and “an” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive OR”, unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or devices in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.
Claims
1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided having a trench isolation structure that defines an active region, the top of the trench isolation structure being higher than the surface of the substrate; A plurality of gate stack structures are formed on the substrate. The gate stack structures extend along a first direction and are spaced apart along a second direction. Each gate stack structure includes a first part and a second part. The first part is located on the active region and the second part is located on the trench isolation structure. The trench isolation structures on both sides of the second portion are etched to form a first groove, the bottom of which is lower than the surface of the substrate; A first sidewall is formed on the sidewall of the gate stack structure, and the first sidewall extends into the first groove, at least covering the sidewall of the first groove near the center of the trench isolation structure. A sacrificial layer is formed on the substrate, the sacrificial layer at least conformally covering the substrate, the first sidewall, and the top of the gate stack structure; Open the sacrificial layers on both sides of the first portion and etch the active region to form a second groove; An embedded epitaxial layer is formed in the second groove; and, Remove the sacrificial layer.
2. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The first sidewall fills the first groove, and the sacrificial layer is located on the substrate; or, the first sidewall covers the sidewall of the first groove near the center of the trench isolation structure, and at least a portion of the sacrificial layer extends into and fills the first groove.
3. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The trench isolation structures on both sides of the second part are etched using an isotropic etching process, so that the sidewall of the first groove near the center of the trench isolation structure protrudes in a direction toward the center of the trench isolation structure.
4. The method for fabricating a semiconductor device as described in claim 1 or 3, characterized in that, The depth of the first groove is 10nm to 25nm.
5. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The gate stack structure includes a gate oxide layer, a gate electrode layer, and a gate masking layer stacked sequentially. The sacrificial layer includes a protective layer and a mask layer stacked sequentially. The step of removing the sacrificial layer includes: Remove the mask layer and the gate masking layer simultaneously; Remove the protective layer.
6. The method for fabricating a semiconductor device as described in claim 5, characterized in that, The material of the gate oxide layer is different from the material of the trench isolation structure.
7. The method for fabricating a semiconductor device as described in claim 6, characterized in that, The gate oxide layer is made of silicon oxynitride, and the trench isolation structure is made of silicon oxide.
8. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The step of etching the active region includes: The active region is etched using a dry etching process to form a second groove with an initial shape; and, The active region is further etched along the second groove using a wet etching process to form the second groove with the final shape.
9. The method for fabricating a semiconductor device as described in claim 8, characterized in that, After etching the active region using the dry etching process and before continuing to etch the active region along the second groove using the wet etching process, the substrate undergoes a wet cleaning process; and, After the active region is etched along the second groove using the wet etching process, and before the embedded epitaxial layer is formed in the second groove, the substrate is subjected to another wet cleaning process.
10. The method for fabricating a semiconductor device as described in claim 1 or 5, characterized in that, After the sacrificial layer is removed, a second sidewall is formed that covers the first sidewall.
11. The method for fabricating a semiconductor device as described in claim 10, characterized in that, The first sidewall fills the first groove, and the second sidewall is located on the substrate; or, the first sidewall covers the sidewall of the first groove near the center of the trench isolation structure, and at least a portion of the second sidewall extends into the first groove to fill it.
12. A semiconductor device, characterized in that, include: A substrate having a trench isolation structure defining an active region, the top of the trench isolation structure being higher than the surface of the substrate; A plurality of gate stack structures are located on the substrate. The gate stack structures extend along a first direction and are spaced apart along a second direction. Each gate stack structure includes a first part and a second part. The first part is located on the active region, and the second part is located on the trench isolation structure. A first groove is located in the trench isolation structure on both sides of the second portion, and the bottom of the first groove is lower than the surface of the substrate; A first sidewall, located on the sidewall of the gate stack structure, extends into the first groove, at least covering the sidewall of the first groove near the center of the trench isolation structure; and, An embedded epitaxial layer is located in the active regions on both sides of the first portion.
13. The semiconductor device as claimed in claim 12, characterized in that, The sidewall of the first groove near the center of the trench isolation structure protrudes in a direction toward the center of the trench isolation structure.
14. The semiconductor device as claimed in claim 12, characterized in that, Also includes: The second side wall covers the first side wall.
15. The method for fabricating a semiconductor device as described in claim 14, characterized in that, The first sidewall fills the first groove, and the second sidewall is located on the substrate; or, the first sidewall covers the sidewall of the first groove near the center of the trench isolation structure, and the second sidewall extends into the first groove to fill it.
16. The semiconductor device according to any one of claims 12 to 15, characterized in that, The depth of the first groove is 10nm to 25nm.
17. The semiconductor device according to any one of claims 12 to 15, characterized in that, The gate stack structure includes a gate oxide layer and a gate electrode layer stacked sequentially, and the material of the gate oxide layer is different from the material of the trench isolation structure.
18. The semiconductor device as claimed in claim 17, characterized in that, The gate oxide layer is made of silicon oxynitride, and the trench isolation structure is made of silicon oxide.