Semi-floating junction isolation

Abstract

The present disclosure relates generally to semi-floating junction isolation. In an example, a semiconductor device includes an epitaxial layer (106), a buried layer (108), a deep well (112), a drift well (122, 224), a contact well (120, 222), and a contact region (126). The buried layer (108), the deep well (112), the drift wells (122, 224), the contact wells (120, 222), and the contact region (126) each have a conductivity type opposite to a conductivity type of the epitaxial layer (106). The buried layer (108) is spaced apart from a top surface of the epitaxial layer (106). The deep well (112) extends in the epitaxial layer (106) and touches the buried layer (108). And the deep well (112) transversely surrounds the active region above the buried layer (108). The drift well (122, 224) extends to a depth in the epitaxial layer (106) and extends laterally from the deep well (112) toward the active region. The contact well (120, 222) extends to a greater depth in the epitaxial layer (106) and touches the drift well (122, 224). The contact region (126) extends in the contact well (120, 222).

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to semi-floating junction isolation. Background Technology

[0002] When devices are integrated into or on the same integrated circuit (IC) die, the challenge lies in substrate parasitic leakage and voltage. Various techniques have been developed to address this leakage and voltage. However, the challenge can persist, especially for certain applications such as high-voltage applications. Summary of the Invention

[0003] The present invention is provided to present a simplified selection of the disclosed concepts, which will be further described below in specific embodiments including the provided figures. Various disclosed apparatuses and methods can be advantageously applied to semiconductor substrates implementing junction isolation between devices. While such embodiments are expected to increase the operating voltage before junction breakdown occurs, a specific result is not required unless explicitly stated in the specific claims.

[0004] The examples described herein are semiconductor devices. A semiconductor device includes an epitaxial layer, a buried layer, a deep well, a drift well, a contact well, and a contact region. The epitaxial layer has a first conductivity type. The epitaxial layer is located above a semiconductor substrate. The buried layer has a second conductivity type opposite to the first conductivity type. The buried layer is spaced apart from the top surface of the epitaxial layer. The deep well has a second conductivity type. The deep well extends in the epitaxial layer and touches the buried layer. The deep well laterally surrounds an active region in the epitaxial layer above the buried layer. The drift well has a second conductivity type. The drift well extends in the epitaxial layer to a first depth. The drift well extends laterally from the deep well toward the active region. The contact well has a second conductivity type. The contact well extends in the epitaxial layer to a second greater depth and touches the drift well. The contact region has a second conductivity type. The contact region extends in the contact well.

[0005] Another example is an integrated circuit. An integrated circuit comprises transistors and field plates. The transistors are located in the active region within a semiconductor substrate. The transistors include a source region in the semiconductor substrate, a drain region in the semiconductor substrate, and a gate electrode above the semiconductor substrate. The semiconductor substrate includes a buried layer, a deep well, and a drift well. The source and drain regions are located above the buried layer. The deep well extends into the buried layer. The deep well laterally surrounds the active region. The drift well extends laterally from the deep well and into the drain region. The buried layer, deep well, drift well, and drain region are doped with corresponding dopants having the same conductivity type. The field plate is located above the semiconductor substrate and above the drift well. The field plate is laterally positioned between the deep well and the drain region.

[0006] Another example is a method for forming a semiconductor device. A buried layer is formed in a semiconductor substrate. The buried layer has a first conductivity type. An epitaxial layer is formed above the semiconductor substrate. The epitaxial layer has a second conductivity type opposite to the first conductivity type. The buried layer is spaced apart from the top surface of the epitaxial layer. A deep well is formed extending in the epitaxial layer and touching the buried layer. The deep well laterally surrounds an active region in the epitaxial layer above the buried layer. The deep well has a first conductivity type. A drift well is formed extending in the epitaxial layer. The drift well extends laterally from the deep well toward the active region. The drift well has a first conductivity type. A contact well is formed extending in the epitaxial layer and touching the drift well. The contact well has a first conductivity type. A contact region is formed extending in the epitaxial layer and in the contact well. The contact region has a first conductivity type.

[0007] The foregoing summary provides a fairly broad overview of various features of the examples disclosed herein in order to better understand the following detailed description. Additional features and advantages of such examples will be described below. The described examples can be readily used as a basis for modifying or designing other examples within the scope of the appended claims. Attached Figure Description

[0008] To understand the above features in detail, please refer to the following detailed description in conjunction with the accompanying drawings.

[0009] Figure 1 This is a cross-sectional view of a semiconductor device based on some examples.

[0010] Figure 2 This is a cross-sectional view of another semiconductor device based on some examples.

[0011] Figure 3 for Figure 1 and 2 A layout diagram of the various components of a semiconductor device.

[0012] Figure 4 This is a cross-sectional view of a semiconductor device based on some examples.

[0013] Figure 5 A graph illustrating the voltage curves of the contact trap and the junction isolation trench according to the example.

[0014] Figure 6 To illustrate bias based on some examples Figure 4 A diagram illustrating the effect of junction isolation field plates in semiconductor devices.

[0015] Figure 7 This is a cross-sectional view of a semiconductor device based on some examples.

[0016] Figure 8 , 9Figures 10 and 10 are corresponding circuit diagrams of integrated circuits (ICs) implementing semi-floating junction isolation trenches according to some examples.

[0017] Figure 11 , 12 Numbers 13, 14, 15, 16, 17, 18, and 19 represent the various manufacturing stages based on the example method. Figure 4 A cross-sectional view of a semiconductor device.

[0018] Figure 20 , 21 22, 23, 24, 25, and 26 are examples of manufacturing stages based on the example method. Figure 2 Semiconductor devices with junction isolation trench connection mechanisms (and) Figure 4 A cross-sectional view (similar to the one in the middle).

[0019] The drawings and accompanying detailed description are provided to help understand the features of various examples and do not limit the scope of the appended claims. Examples illustrated in the drawings and described in the accompanying detailed description can be readily used as the basis for modifications or designs of other examples within the scope of the appended claims. Where possible, the same reference numerals may be used to refer to the same elements common in the drawings. The drawings are drawn to clearly illustrate the relevant elements or features, and are not necessarily drawn to scale. Detailed Implementation

[0020] Various features are described below with reference to the accompanying diagrams. The illustrated examples may not possess all aspects or advantages shown. Aspects or advantages described in connection with a particular example are not necessarily limited to that example and can be practiced in any other example, even if not so stated or explicitly described. Furthermore, the methods described herein may be described with a specific order of operations, but other methods according to other examples may be implemented with more or fewer operations in various other orders (e.g., different serial or parallel executions involving various operations). In the following discussion, doping levels may be described using quantitative and / or qualitative terms, where less than 1 × 10⁻⁶. 16 cm -3 The doping level is lightly doped, at 1×10⁻⁶. 16 cm -3 With 1×10 18 cm 3 The doping level is moderate, between 1×10 18 cm -3 With 1×10 20 cm 3 The doping levels between them are heavily doped and higher than 1×10. 20 cm -3 The doping level is extremely heavy doping. The doping level at the boundaries of these ranges can be qualitatively referred to by either terminology indicating a higher or lower range.

[0021] This disclosure generally, but not exclusively, relates to semi-floating junction isolation in a semiconductor substrate. In some embodiments, a buried layer and a deep well form a junction isolation trench in the semiconductor substrate. The deep well surrounds an active region in the semiconductor substrate located above the buried layer. Devices such as transistors or diodes may be formed in the active region. A drift well extends from the deep well and touches a contact well. A contact region is located in the contact well. In some embodiments, the contact region may be the cathode terminal of a diode or the drain terminal of a transistor. In operation, in a first embodiment, the junction isolation trench is electrically connected to the contact region via the drift well, which allows the voltage of the junction isolation trench to follow the voltage of the contact region. In another embodiment, a pinch-off occurs in the drift well, allowing the junction isolation trench to be electrically floated from the contact region. This operation allows for an increase in the voltage of the contact region before breakdown of the junction formed by the junction isolation trench and the semiconductor substrate inside the junction isolation trench. Other benefits and advantages can be achieved.

[0022] Figure 1 and 2 The following are corresponding cross-sectional views of semiconductor devices 100 and 200 according to some examples. Figure 3 Typically displayed Figure 1 and 2 Layout diagram of various components of semiconductor devices 100 and 200. Figure 3 The display corresponds to Figure 1 and 2 The cross-sectional location is shown in the cross-sectional diagram described in the figure. For example... Figure 3 As explained in the text, semiconductor device 100 and semiconductor device 200 can be arranged in a colloquial horizontal "runway" configuration.

[0023] Figure 1 and 2 Semiconductor devices 100 and 200 typically implement a junction isolation mechanism that includes a junction isolation trench (e.g., including a buried layer 108 and a deep well 112) in a semiconductor substrate. The junction isolation trench typically contains a portion of the semiconductor substrate in which a device (e.g., a diode, transistor, etc.) is disposed. The junction isolation trench and the portion of the semiconductor substrate in which the device is disposed form a pn junction, which allows the device to be isolated from other portions of the semiconductor substrate.

[0024] exist Figure 1 and 2In this configuration, the corresponding junction isolation trench is configured to be semi-floating during operation of the device within a portion of the semiconductor substrate surrounded by the junction isolation trench. The junction isolation trench is not ohmically electrically connected to another node or active component. As detailed later, in a first embodiment, the junction isolation trench may be electrically connected to another doped region of the device via a drift well (e.g., which may be a drift well portion). A junction isolation field plate is located above the drift well, which may form a type of junction field-effect transistor (JFET) connection via the drift well. In other embodiments (e.g., the second and third embodiments described later), the junction isolation trench is not electrically connected to other doped regions of the device. This type of connection and disconnection allows for an increase in the voltage of the junction isolation trench, which in turn allows for an increase in the breakdown voltage of the pn junction between the semiconductor substrate and the junction isolation trench.

[0025] Figure 1 and 2 A semiconductor substrate 102 is shown. In the illustrated example, the semiconductor substrate 102 includes a semiconductor support (or disposal) substrate 104 (or disposal wafer) and an epitaxial layer 106. The semiconductor support substrate 104 may be a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or any other suitable substrate. The epitaxial layer 106 is epitaxially grown on or above the semiconductor support substrate 104. The epitaxial layer 106 may be or contain silicon (Si), silicon germanium (SiGe), gallium arsenide (GaAs), gallium nitride (GaN), the like, or combinations thereof. In some examples, the semiconductor support substrate 104 is or contains a silicon substrate (which may be diced from bulk silicon at the end of semiconductor processing), and the epitaxial layer 106 is or contains a silicon layer. In some examples, the epitaxial layer 106 may be omitted, and the semiconductor material of the semiconductor substrate 102 (e.g., in which or on which devices are formed) may be or contain silicon (Si), silicon germanium (SiGe), gallium arsenide (GaAs), the like, or combinations thereof. Semiconductor substrate 102 has a top main surface, on which devices (e.g., diodes, transistors, etc.) are typically disposed and formed.

[0026] Various doped buried layers, wells, and doped regions are located in the semiconductor substrate 102. Generally, reference... Figure 1 A buried layer 108 (e.g., a doped buried layer), a deep well 112, a drift well 122, a contact well 120, and contact regions 124, 126 (e.g., doped regions) are located in a semiconductor substrate 102. An epitaxial layer 106 (or more generally, the semiconductor substrate 102) is doped with a dopant of a first conductivity type (e.g., a p-type dopant). The buried layer 108, deep well 112, drift well 122, contact well 120, and contact regions 124, 126 are doped with corresponding dopants of the same second conductivity type (e.g., an n-type dopant), the second conductivity type being opposite or reversed to the first conductivity type. Generally, reference... Figure 2The buried layer 108, deep well 112, well 220 (which includes drift well portion 224 and well portion 222), buried layer 230 (e.g., a doped buried layer), and contact regions 124, 126 are located in the semiconductor substrate 102. The epitaxial layer 106 (or more generally, the semiconductor substrate 102) and the buried layer 230 are doped with a corresponding dopant of a first conductivity type (e.g., a p-type dopant). The buried layer 108, deep well 112, well 220, and contact regions 124, 126 are doped with a corresponding dopant of the same second conductivity type (e.g., an n-type dopant), the second conductivity type being opposite or reversed to the first conductivity type.

[0027] exist Figure 1 and 2 In both cases, the corresponding junction isolation trench includes a buried layer 108 and a deep well 112. As illustrated, the junction isolation trench may also include a contact region 124, and in other instances, the contact region 124 may be omitted. The junction isolation trench (e.g., buried layer 108 and deep well 112) and the epitaxial layer 106 (e.g., or more generally, semiconductor substrate 102) are doped in opposite or opposite directions between the junction isolation trench and the epitaxial layer 106 within the junction isolation trench to form a pn junction.

[0028] A buried layer 108 is disposed in a semiconductor substrate 102 (e.g., a semiconductor support substrate 104). The buried layer 108 extends from the interface between the semiconductor support substrate 104 and the epitaxial layer 106 to a certain depth within the semiconductor support substrate 104. Although Figure 3 It is not specified in the text, but the deep buried layer 108 is in Figure 3 Extending laterally throughout the layout shown herein. As used herein, a buried layer is a layer located in a semiconductor substrate (e.g., semiconductor substrate 102) and having characteristics such as conductivity type or dopant concentration, spaced apart from the top surface of the semiconductor substrate (e.g., the top main surface of epitaxial layer 106) by spacer layers or materials having significantly different characteristics (e.g., different conductivity types or different dopant concentrations). For example, a buried layer may be an n-doped diffusion layer spaced apart from the top surface of the semiconductor substrate by an n-type or p-type in-situ doped epitaxial layer.

[0029] A deep well 112 is disposed in a semiconductor substrate 102 (e.g., in an epitaxial layer 106, as illustrated). The deep well 112 extends from near the top main surface of the semiconductor substrate 102 to and contacts a buried layer 108. The deep well 112 extends along... Figure 3 The outer perimeter of the layout described.

[0030] Contact region 124 is disposed in semiconductor substrate 102 (e.g., in epitaxial layer 106 as illustrated). Contact region 124 is located in deep well 112 and extends from the top main surface of semiconductor substrate 102 into semiconductor substrate 102. In other embodiments, contact region 124 may be omitted.

[0031] The deep well 112 extends to and contacts the deep buried layer 108, and the deep buried layer 108 is in Figure 3 When extending laterally throughout the overall layout, the deep well 112 and the buried layer 108 form a "bathtub" (e.g., a junction isolation trench) in which devices may be formed. The deep well 112 and the buried layer 108 typically contain and permit the isolation of portions of the semiconductor substrate 102 in which devices are formed.

[0032] Dielectric isolation structures 116 and 118 are disposed at the top main surface of semiconductor substrate 102 and extend into semiconductor substrate 102 (e.g., into epitaxial layer 106, as illustrated). Dielectric isolation structures 116 and 118 may be or contain any suitable dielectric or isolation material. In some instances, dielectric isolation structures 116 and 118 are shallow trench isolation (STI), and in some instances, dielectric isolation structures 116 and 118 may be other dielectric isolation structures, such as field oxide structures, localized oxidation of silicon (LOCOS) structures, stepped gate dielectric structures, etc. Dielectric isolation structure 116 is at least partially laterally disposed within deep well 112 and extends laterally away from the interior of junction isolation trench 112. Dielectric isolation structure 116 extends laterally from contact region 124.

[0033] refer to Figure 1 and 3 A contact well 120 is disposed in the semiconductor substrate 102 (e.g., in the epitaxial layer 106, as illustrated). The contact well 120 extends from near the top main surface of the semiconductor substrate 102 to a certain depth in the epitaxial layer 106. The depth to which the contact well 120 extends is less than the depth of the top of the buried layer 108, and therefore, the contact well 120 does not extend as deep as the buried well 112. A portion of the epitaxial layer 106, oppositely doped to the contact well 120 and the buried layer 108, lies vertically between the contact well 120 and the buried layer 108. The contact well 120 is generally laterally positioned between the dielectric isolation structure 116 and the dielectric isolation structure 118.

[0034] Contact region 126 is disposed in semiconductor substrate 102 (e.g., in epitaxial layer 106 as illustrated). Contact region 126 is located in contact well 120 and extends from the top main surface of semiconductor substrate 102 into semiconductor substrate 102. Dielectric isolation structure 116 extends laterally from contact region 124 to contact region 126. Contact region 126 is laterally located between dielectric isolation structures 116 and 118.

[0035] Drift well 122 is disposed in semiconductor substrate 102 (e.g., in epitaxial layer 106, as illustrated). Drift well 122 is located below dielectric isolation structure 116. Drift well 122 extends laterally from deep well 112 to contact well 120. Drift well 122 extends to a depth in epitaxial layer 106, said depth being shallower than the depth to which contact well 120 extends. Drift well 122 can be considered as a shallow well. Figure 3 As shown, the deep well 112 laterally surrounds the drift well 122, which in turn laterally surrounds the contact well 120.

[0036] The dopant concentrations in the buried layer 108, deep well 112, drift well 122, and contact well 120 are greater than the dopant concentration in the epitaxial layer 106. The dopant concentration in the contact region 124 is greater than the dopant concentration in the deep well 112, and the dopant concentration in the contact region 126 is greater than the dopant concentration in the contact well 120.

[0037] In some instances, the epitaxial layer 106 can be used at a concentration of approximately 1 × 10⁶. 14 cm -3 Up to approximately 5×10 15 cm -3 In-situ p-doping with a p-type dopant (e.g., boron) within the specified range, for example, light doping. In some instances, the buried layer 108 may be p-doped with a concentration of approximately 1 × 10⁸. 17 cm -3 Up to approximately 8×10 18 cm -3 An n-type layer doped (e.g., moderately to heavily doped) with an n-type dopant (e.g., phosphorus and / or arsenic) within the range of [specific parameters]. In some instances, the deep well 112 may be an n-type layer doped (e.g., moderately to heavily doped) with a concentration of approximately 1 × 10 [specific parameters]. 17 cm -3 Up to approximately 2×10 20 cm -3 n-wells doped with n-type dopant within a range of approximately 1 × 10⁻⁶. In some instances, the contact well 120 may be an n-well doped with an concentration of approximately 1 × 10⁻⁶. 17 cm -3 Up to approximately 2×10 20 cm -3 An n-well doped with an n-type dopant within a range of approximately 1 × 10⁻⁶. In some instances, the drift well 122 may be an n-well doped with an n-type dopant concentration of approximately 1 × 10⁻⁶. 17 cm -3 Up to approximately 2×10 20 cm -3 n-wells doped with n-type dopant (e.g., moderately to heavily doped) within a range. In some examples, contact regions 124, 126 can be used with concentrations of approximately 1 × 10⁻⁶. 20 cm -3 Up to approximately 3×1021 cm -3 n-type dopant within the range of n-type dopant, for example, extremely heavy doping.

[0038] refer to Figure 2 and 3 Well 220 is disposed in semiconductor substrate 102 (e.g., in epitaxial layer 106 as illustrated). Well 220 extends from near the top main surface of semiconductor substrate 102 to a certain depth in epitaxial layer 106. The depth to which well 220 extends is less than the depth of the top of buried layer 108, and therefore well 220 does not extend as deep as deep well 112. Well 220 is partially located below dielectric isolation structure 116. Well 220 extends laterally from deep well 112 to dielectric isolation structure 118.

[0039] A buried layer 230 is disposed in the semiconductor substrate 102 (e.g., in the epitaxial layer 106, as illustrated). The buried layer 230 is located beneath the dielectric isolation structure 116. The buried layer 230 overlaps with and dominates the lower portion of the well 220 underlying the dielectric isolation structure 116. The dopant concentration of the buried layer 230 is greater than that of the well 220.

[0040] The overlap of the buried layer 230 and the well 220 creates a well portion 222 and a drift well portion 224 of the well 220. The drift well portion 224 extends laterally from the deep well 112 to the well portion 222 (similar to...). Figure 1 A drift trap 122 extends laterally from the deep trap 112 to the contact trap 120. The drift trap portion 224 is located above the buried layer 230. The drift trap portion 224 and the buried layer 230 extend laterally from the deep trap 112 and laterally surround the trap portion 222. Figure 3 As shown, the deep well 112 laterally surrounds the drift well portion 224, which in turn laterally surrounds the well portion 222. The deep well 112 also laterally surrounds the buried layer 230.

[0041] Contact region 126 is located in well portion 222. A portion of epitaxial layer 106, which is oppositely doped to well 220 and buried layer 108, is vertically located between well portion 222 and buried layer 108.

[0042] The dopant concentrations in the buried layer 108, deep well 112, and well 220 (including drift well portion 224 and well portion 222) are greater than the dopant concentration in the epitaxial layer 106. The dopant concentration in the contact region 124 is greater than the dopant concentration in the deep well 112, and the dopant concentration in the contact region 126 is greater than the dopant concentration in the well 220 (e.g., well portion 222). The dopant concentration in the buried layer 230 is greater than the dopant concentration in the epitaxial layer 106.

[0043] In some instances, the epitaxial layer 106 can be used at a concentration of approximately 1 × 10⁶. 14 cm-3 Up to approximately 5×10 15 cm -3 In-situ p-doping with a p-type dopant (e.g., boron) within the specified range, for example, light doping. In some instances, the buried layer 108 may be p-doped with a concentration of approximately 1 × 10⁸. 17 cm -3 Up to approximately 8×10 18 cm -3 An n-type layer doped (e.g., moderately to heavily doped) with an n-type dopant (e.g., phosphorus and / or arsenic) within the range of [specific parameters]. In some instances, the deep well 112 may be an n-type layer doped (e.g., moderately to heavily doped) with a concentration of approximately 1 × 10 [specific parameters]. 17 cm -3 Up to approximately 2×10 20 cm -3 n-wells doped with n-type dopant within a range of approximately 1 × 10⁻⁶. In some instances, well 220 (e.g., comprising drift well portion 224 and well portion 222) may be an n-well doped with an n-type dopant concentration of approximately 1 × 10⁻⁶. 17 cm -3 Up to approximately 2×10 20 cm -3 n-wells doped with n-type dopant within a range of (e.g., moderately to heavily doped). In some instances, the buried layer 230 can be used with a concentration of approximately 5 × 10⁻⁶. 17 cm -3 Up to approximately 7×10 20 cm -3 The range of n-type dopant p-doping, for example, from moderate to very heavy doping. In some instances, contact regions 124 and 126 can be used with concentrations of approximately 1 × 10⁻⁶. 20 cm -3 Up to approximately 3×10 21 cm -3 n-type dopant within the range of n-type dopant, for example, extremely heavy doping.

[0044] refer to Figure 1 and 2 As mentioned, in some instances, the epitaxial layer 106 may be omitted. In such instances, a buried layer 108 may be implanted at a certain depth in the semiconductor substrate 102, and a well may be implanted in the semiconductor substrate 102 extending from the top main surface of the semiconductor substrate 102 to a depth at or above the buried layer 108. The well may be reverse-doped with the buried layer 108, similar to what has been described with respect to the epitaxial layer 106.

[0045] The junction isolation plate 130 is located above and on the dielectric isolation structure 116, and the drift trap 122 ( Figure 1 (middle) or drift trap section 224 ( Figure 2Above the (middle) junction isolation field plate 130. The junction isolation field plate 130 is or contains a conductive material. In some examples, the junction isolation field plate 130 is or contains doped polysilicon (polysilicon). In some examples, the junction isolation field plate 130 may be or contains a metal. As illustrated, the junction isolation field plate 130 may be at the gate level and may be formed by a process used to form the gate electrode of another device. The junction isolation field plate 130 may also be considered as a gate electrode. In other examples, the field plate may be located in a metal layer above the semiconductor substrate 102 (e.g., in or above one or more dielectric layers). Dielectric spacers 132 are located on the respective sidewalls of the junction isolation field plate 130 and may be any suitable dielectric material, such as silicon nitride, silicon oxynitride, silicon carbonitride, the like, or combinations thereof.

[0046] A dielectric layer 140 is disposed on or over a semiconductor substrate 102. This dielectric layer is sometimes referred to as a pre-metal dielectric layer. More specifically, the dielectric layer 140 is disposed on or over dielectric isolation structures 116, 118, junction isolation field plate 130, and dielectric spacer 132. The dielectric layer 140 may comprise multiple dielectric layers. For example, the dielectric layer 140 may include an etch-stop layer (e.g., silicon nitride (SiN) or the like) conformally disposed along the surfaces of, for example, the dielectric isolation structures 116, 118, junction isolation field plate 130, and dielectric spacer 132, and may include an interlayer dielectric (e.g., oxide or the like) disposed on the etch-stop layer.

[0047] Metal contacts 144, 146, and 148 are disposed through dielectric layer 140 and respectively contact contact region 124, contact region 126, and junction isolation field plate 130. Each of the metal contacts 144, 146, and 148 may include one or more barrier layers and / or adhesive layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), the like, or combinations thereof) conformally located in a respective opening through dielectric layer 140, and may include conductive filler material (e.g., metal, such as tungsten (W), copper (Cu), combinations thereof, etc.) located on and / or above one or more barrier layers and / or adhesive layers.

[0048] Metal wires 154, 156, and 158 are disposed on and above the dielectric layer 140 and the corresponding metal contacts 144, 146, and 148. Each of the metal wires 154, 156, and 158 may include one or more barrier layers and / or adhesive layers, as well as conductive filler material located on and / or above the one or more barrier layers and / or adhesive layers, similar to the metal contacts 144, 146, and 148.

[0049] Device area 170 is usually in Figure 1 , 2As shown in Figure 3. Device region 170 is a region in which a device may be formed. Device region 170 may define an active region of semiconductor substrate 102 in which a device may be formed, as illustrated in subsequent examples. Other structures of the device may be formed in device region 170 above semiconductor substrate 102, such as field plates, gate electrodes, etc. Device region 170 is generally laterally located inside contact well 120 or well portion 222. Device region 170 may include contact well 120 or well portion 222 and may include contact region 126. Contact well 120 or well portion 222 generally laterally surrounds device region 170. Dielectric isolation structure 118 extends laterally from contact region 126 into device region 170 of semiconductor substrate 102. As described laterally, contact region 126 and contact well 120 or well portion 222 may be formed as part of a device formed in device region 170, such as the cathode region of a diode, the drain region of a transistor, etc. Any device formed in the device region 170 on the semiconductor substrate 102 (e.g., epitaxial layer 106) is housed within a junction isolation trench (e.g., buried layer 108 and deep well 112).

[0050] Figure 1 and 2 This demonstrates different junction isolation trench connection mechanisms. Semiconductor devices can implement this. Figure 1 and 2 Any one of the isolation groove connection mechanisms and any other similar connection mechanisms. Figure 1 The junction isolation groove connection mechanism includes a drift trap 122, a contact trap 120, and a junction isolation field plate 130. Figure 2 The junction isolation trench connection mechanism includes a drift trap portion 224, a trap portion 222, and a junction isolation field plate 130. These junction isolation trench connection mechanisms can provide electrical connection to the junction isolation trench under certain operating conditions (e.g., one operating mode) and can electrically disconnect the junction isolation trench in other operating modes. Figure 1 The junction isolation groove connection mechanism can be more easily integrated with the process to form some devices, while Figure 2 The junction isolation groove connection mechanism can be more easily integrated with the process to form other devices. Additionally, in some instances, Figure 2 The buried layer 230 in the middle allows for improved tuning of the breakdown voltage.

[0051] Junction isolation channels (e.g., deep well 112 and buried layer 108) may be configured to semi-float during operation of the device formed in device region 170. The junction isolation channels may be ohmically floating. In this context, "ohmically floating" means that the junction isolation channel is not directly electrically connected to a potential node via an ohmic connection, which can hold the junction isolation channel at the voltage of the potential node. For example, metal contacts 144 and metal wires 154 may not be ohmically connected to another node or active component. In some instances, metal contacts 144 and metal wires 154 are omitted, and there are no metal contacts to contact region 124. In other instances (e.g., non-floating embodiments), the junction isolation channel may be ohmically connected to another node, such as in circuitry controlling the voltage of the junction isolation channel.

[0052] During operation, the junction isolation groove connection mechanism can operate in three schemes. In the first scheme, refer to... Figure 1 The junction isolation groove is electrically connected to the contact well 120 and the contact area 126 via the drift well 122, and references... Figure 2 The junction isolating field 130 is electrically connected to the well portion 222 and the contact region 126 via the drift well portion 224. In the first embodiment, the voltage difference between the junction isolation field plate 130 and the contact region 126 is low, such that the region below the junction isolation field plate 130 in the drift well 122 or the drift well portion 224 is not depleted and remains conductive. Therefore, in the first embodiment, the voltage of the junction isolation trench is generally equal to the voltage of the contact region 126. In the second embodiment, the junction isolation trench becomes electrically disconnected from the contact region 126 and the contact well 120 or the well portion 222. In the second embodiment, the voltage difference between the junction isolation field plate 130 and the contact region 126 is sufficiently high, such that the region below the junction isolation field plate 130 in the drift well 122 or the drift well portion 224 becomes depleted and pinched off. In this second embodiment, the voltage of the junction isolation trench can remain substantially constant, while the voltage of the contact region 126 can vary. In the third embodiment, the junction isolation trench remains electrically disconnected from contact region 126 and contact well 120 or well portion 222, and (i) the voltage difference between the junction isolation trench and (ii) contact region 124 and contact well 120 or well portion 222 becomes sufficiently large to cause leakage from contact well 120 or well portion 222 to the buried layer 108 (e.g., through the epitaxial layer 106). The leakage can cause the voltage of the junction isolation trench to substantially follow the voltage of contact region 126 and contact well 120 or well portion 222. At a sufficiently large voltage in contact region 126, breakdown may occur.

[0053] In the first embodiment, the electrical connection via drift trap 122 or drift trap portion 224 allows the voltage of the junction isolation trench to increase with the voltage of contact region 126. Furthermore, in the third embodiment, the voltage of the junction isolation trench can be attributed to leakage and thus increases. These voltage increases in the junction isolation trench reduce the voltage drop across the pn junction formed between the epitaxial layer 106 and the junction isolation trench. Therefore, with a lower voltage drop across this pn junction, pn junction breakdown can occur at higher operating voltages (e.g., higher voltages in contact region 126).

[0054] A tunable junction isolation plate 130 is used to adjust the voltage difference that causes the drift well 122 or drift well portion 224 to become depleted. The lateral position of the junction isolation plate 130 between (i) the deep well 112 and (ii) the contact well 120 or well portion 222 can affect the electric field experienced by the drift well 122 or drift well portion 224, which can lead to depletion. Furthermore, Figure 3 The instructions in the document (and Figure 1 and 2 The lateral dimensions (e.g., length) of the junction isolation plate 130 in the cross-section (as described in the diagram) may affect the electric field. Furthermore, the voltage or potential applied to the junction isolation plate 130 may also affect the electric field. Any or more of these characteristics can be modified or tuned to control the transition from the first scheme to the second scheme.

[0055] Furthermore, any one or more devices formed in device region 170 can operate at much negative voltages than otherwise achievable. The semi-floating junction isolation trench extends the circuit's ability to operate at more negative voltages while maintaining isolation from the semiconductor substrate outside the junction isolation trench.

[0056] Figure 4 This is a cross-sectional view of a semiconductor device 400 according to some examples. The semiconductor device 400 includes a diode formed in device region 170. Figure 4 The isolation groove connection mechanism described above is the one mentioned above. Figure 1 The described and illustrated junction isolation groove connection mechanism can be implemented in other instances. Figure 2 The junction isolation groove connection mechanism. Similar components described above are indicated by the same reference numerals, and descriptions of such components are omitted here to avoid repetition.

[0057] remove Figure 1 (or in other implementations,) Figure 2 Apart from the doped layer, well, and region, the anode well 402, anode terminal 404 (e.g., a doped region), and buried layer 406 (e.g., a doped layer) are located in the semiconductor substrate 102. The anode well 402, anode terminal 404, buried layer 406, and epitaxial layer 106 (or more generally, semiconductor substrate 102) are doped with corresponding dopants of the same first conductivity type (e.g., p-type dopant). Figure 1 (or in other implementations,) Figure 2 Other doped layers, wells, and regions are as described above.

[0058] An anode well 402, an anode terminal 404, and a buried layer 406 are located within a semiconductor substrate 102 (e.g., within an epitaxial layer 106, as illustrated). The anode well 402 extends from near the top main surface of the semiconductor substrate 102 to a depth within the epitaxial layer 106. The anode well 402 is typically laterally surrounded by a dielectric isolation structure 118. The anode terminal 404 is located within the anode well 402 and extends from the top main surface of the semiconductor substrate 102 into the semiconductor substrate 102. The dielectric isolation structure 118 laterally surrounds the anode terminal 404. The dielectric isolation structure 118 laterally extends from a contact region 126 to the anode terminal 404. The buried layer 406 is located below the anode well 402, and more specifically, between the anode well 402 and the buried layer 108. In the illustrated example, the buried layer 406 extends laterally beyond the anode well 402, and in other examples, the buried layer 406 does not extend laterally beyond the anode well 402.

[0059] The dopant concentrations in the anode well 402 and buried layer 406 are greater than the dopant concentration in the epitaxial layer 106. The dopant concentration in the anode terminal 404 is greater than the dopant concentration in the anode well 402.

[0060] In some instances, the anode trap 402 may be used with a concentration of approximately 1 × 10⁻⁶. 17 cm -3 Up to approximately 2×10 20 cm -3 P-wells doped with p-type dopant within a range of (e.g., moderately to heavily doped). In some instances, the anode terminal 404 can be used with a concentration of approximately 1 × 10⁻⁶. 20 cm -3 Up to approximately 3×10 21 cm -3 p-type dopant within the range of p-type dopant, for example, extremely heavy doping. In some instances, buried 406 can be used with concentrations of approximately 5 × 10⁻⁶. 17 cm -3 Up to approximately 7×10 20 cm -3 p-doping of n-type dopants within the range of moderate to heavy doping.

[0061] exist Figure 4 In the semiconductor device 400, the contact well 120 is a cathode well, and the contact area 126 is a cathode terminal. As shown, the drift well 122 can extend laterally from the contact well 120 toward the anode well 402 lying beneath the dielectric isolation structure 118.

[0062] Semiconductor device 400 includes an anode field plate 412 and a cathode field plate 414. The anode field plate 412 is located above and on a dielectric isolation structure 118 near an anode well 402 and an anode terminal 404. The cathode field plate 414 is located above and on the dielectric isolation structure 118 near a contact well 120 and a contact region 126. The anode field plate 412 and the cathode field plate 414 are laterally located between the anode terminal 404 and the contact region 126 (e.g., a cathode terminal). Field plates 412 and 414 are or comprise conductive material. In some examples, field plates 412 and 414 are or comprise doped polysilicon (polysilicon). In some examples, field plates 412 and 414 may be or comprise metal. As illustrated, field plates 412 and 414 may be at the gate level and may be formed by a process used to form the gate electrode of another device. Field plates 412 and 414 may also be considered as gate electrodes. In other examples, the field plates may be located in a metal layer above the semiconductor substrate 102 (e.g., in or above one or more dielectric layers). Field plates 412, 414 may resemble the junction isolation field plate 130. Dielectric spacers 416 are located on the respective sidewalls of field plates 412, 414 and may be any suitable dielectric material, such as silicon nitride, silicon oxynitride, silicon carbonitride, the like, or combinations thereof. Examples may include multiple individual anode field plates, each with an independent applied voltage. Furthermore, examples may include multiple individual cathode field plates, each with an independent applied voltage. Any number of field plates can be used to control electrostatic behavior in the active device region, thereby producing higher breakdown voltage, lower on-resistance, and / or lower parasitic capacitance.

[0063] Metal contacts 424, 426, and 428 are positioned to pass through dielectric layer 140 and contact anode terminal 404, anode field plate 412, and cathode field plate 414, respectively. Metal wires 434, 436, and 438 are disposed on and above dielectric layer 140 and the corresponding metal contacts 424, 426, and 428. Metal contacts 424, 426, and 428 may be similar to metal contacts 144, 146, and 148 described above. Metal wires 434, 436, and 438 may be similar to metal wires 154, 156, and 158 described above.

[0064] In some instances, the anode terminal 404 and the anode field plate 412 are ohmically connected together (e.g., via metal contacts 424, 426, metal lines 434, 436, and other metal lines and / or metal vias above the dielectric layer 140), and the contact area 126 (e.g., the cathode terminal) and the cathode field plate 414 are ohmically connected together (e.g., via metal contacts 146, 428, metal lines 156, 438, and other metal lines and / or metal vias above the dielectric layer 140). In some instances, the anode terminal 404 and the anode field plate 412 are ohmically connected to a ground node. The field plates 412, 414 can control the electric field in the diode. The field plates 412, 414 can allow for a greater potential distribution in the semiconductor substrate 102, which can improve the breakdown voltage. Field plates 412 and 414 allow for relatively deep impact ionization peaks in the semiconductor substrate 102, which are located away from any interface between the semiconductor material and the dielectric material (e.g., in the dielectric isolation structure 118) of the semiconductor substrate 102. Relatively deep impact ionization peaks can introduce low-channel hot carrier risk into the diode. In other embodiments, field plates 412 and 414 may be omitted.

[0065] Junction isolation field plate 130 can be ohmically connected to various nodes to control the electric field in drift trap 122 or drift trap portion 224, thereby controlling when depletion and pinch-off occur. In some instances, junction isolation field plate 130, anode terminal 404, and anode field plate 412 are ohmically connected together (e.g., via metal contacts 148, 424, 426, metal lines 158, 434, 436, and other metal lines and / or metal vias above dielectric layer 140). In other instances, junction isolation field plate 130, anode terminal 404, and anode field plate 412 are ohmically connected to a ground node. In other instances, junction isolation field plate 130 can be ohmically connected to another node that controls the voltage applied to junction isolation field plate 130, which can be independent of other voltages of semiconductor device 400. As previously described, the junction isolation trenches (e.g., deep trap 112 and buried layer 108) are semi-floating.

[0066] Figure 5 A graph illustrating voltage profile 502 for contact area 126 (e.g., cathode terminal) and voltage profile 504 for junction isolation trench (e.g., deep well 112 and buried layer 108) according to an example. In implementation Figure 4 In this example of the semiconductor device 400, the junction isolation field plate 130, the anode terminal 404 and the anode field plate 412 are ohmically connected to the ground node, and the contact area 126 and the cathode field plate 414 are ohmically connected together.

[0067] The voltage curve 502 of contact region 126 (e.g., cathode terminal) increases linearly from time t0 to time t3. The first embodiment 512 increases from time t0 to time t1. In the first embodiment 512, the junction isolation trench is electrically connected to the contact well 120 and the contact region 126 via the drift well 122. The voltage difference between the junction isolation field plate 130 and the contact region 126 is low, ensuring that the region below the junction isolation field plate 130 in the drift well 122 is not depleted and remains conductive. Therefore, in the first embodiment 512, the voltage curve 504 of the junction isolation trench is generally equal to the voltage curve 502 of the contact region 126.

[0068] The second scheme 514 is from time t1 to time t2. In the second scheme 514, the junction isolation trench becomes electrically disconnected from the contact region 126 and the contact well 120. The voltage difference between the junction isolation field plate 130 and the contact region 126 is high enough that the region below the junction isolation field plate 130 in the drift well 122 becomes depleted and pinched off. The voltage curve 504 of the junction isolation trench remains substantially constant, while the voltage curve 502 of the contact region 126 continues to increase linearly.

[0069] The third scheme 516 is from time t2 to time t3. In the third scheme 516, the junction isolation trench remains electrically disconnected from the contact region 126 and the contact well 120, and (i) the voltage difference between the junction isolation trench and (ii) the contact region 126 and the contact well 120 becomes large enough to cause leakage from the contact well 120 to the buried layer 108. The leakage causes the voltage curve 504 of the junction isolation trench to generally follow the voltage curve 502 of the contact region 126. At time t3, a sufficiently large voltage in the contact region 126 causes breakdown.

[0070] Figure 6 To illustrate bias based on some examples Figure 4 A diagram illustrating the effect of the junction isolation field plate 130 in the semiconductor device 400. In this example, the anode terminal 404 and the anode field plate 412 are ohmically connected to the ground node, and the contact area 126 and the cathode field plate 414 are ohmically connected together. The voltage of the junction isolation field plate 130 is independently controlled. Figure 6 The voltage profiles of the junction isolation trench under different voltages (Vfp) of the junction isolation field plate 130 are shown as a function of the voltage of the contact region 126 (e.g., the cathode region). As illustrated, a more negative voltage (Vfp) of the junction isolation field plate 130 causes depletion in the drift well 122 at lower voltages of the junction isolation trench and the contact region 126, while a more positive voltage (Vfp) of the junction isolation field plate 130 causes depletion in the drift well 122 at higher voltages of the junction isolation trench and the contact region 126. Therefore, the voltage of the junction isolation trench can be controlled by the voltage of the junction isolation field plate 130. Furthermore, the breakdown voltage of the pn junction between the epitaxial layer 106 and the junction isolation trench is independent of the voltage of the junction isolation field plate 130.

[0071] Figure 7 This is a cross-sectional view of a semiconductor device 700 according to some examples. The semiconductor device 700 includes a drain-extended metal-oxide-semiconductor (DeMOS) transistor (e.g., a drain-extended n-type metal-oxide-semiconductor (DeNMOS) transistor) formed in device region 170. In some other examples, various doped regions and / or wells may be added or modified to implement a laterally diffused metal-oxide-semiconductor (LDMOS) transistor in device region 170. Figure 7 The isolation groove connection mechanism described above is the one mentioned above. Figure 1 The described and illustrated junction isolation groove connection mechanism can be implemented in other instances. Figure 2 The junction isolation groove connection mechanism. Similar components described above are indicated by the same reference numerals, and descriptions of such components are omitted here to avoid repetition.

[0072] Figure 7 In this context, DeMOS refers to a multifinite device containing multiple source and drain regions. Generally speaking, Figure 7 The image shows one half of the DeMOS. The other half can be mirrored around the midline of the DeMOS, as described later.

[0073] remove Figure 1 (or in other implementations,) Figure 2 Apart from the doped layers, wells, and regions of the epitaxial layer 106, reverse source wells 712, 714, source wells 716, 718, source contact regions 720, 722, drain well 726, drain terminal 728, and drift well 730 are located in the semiconductor substrate 102. The reverse source wells 712, 714, and epitaxial layer 106 (or more generally, semiconductor substrate 102) are doped with corresponding dopants of the same first conductivity type (e.g., p-type dopants). The source wells 716, 718, source contact regions 720, 722, drain well 726, drain terminal 728, and drift well 730 are doped with corresponding dopants of the same second conductivity type (e.g., n-type dopants), the second conductivity type being opposite or reversed to the first conductivity type. Figure 1 (or in other implementations,) Figure 2 Other doped layers, wells, and regions are as described above.

[0074] Dielectric isolation structures 702 and 704 are disposed on the top main surface of semiconductor substrate 102 and extend into semiconductor substrate 102 (e.g., in epitaxial layer 106, as illustrated). Dielectric isolation structures 702 and 704 are similar to dielectric isolation structures 116 and 118. Gate dielectric layers 703 and 705 are disposed on the top main surface of semiconductor substrate 102 and extend laterally from dielectric isolation structures 702 and 704, respectively. Similarly, gate dielectric layer 707 is disposed on the top main surface of semiconductor substrate 102 and extends laterally from dielectric isolation structure 118. Gate dielectric layers 703, 705, and 707 may be or comprise any dielectric layer, such as silicon oxide, silicon nitride, etc.

[0075] Reverse source wells 712, 714, source wells 716, 718, and source contact regions 720, 722 are located in the semiconductor substrate 102 (e.g., in the epitaxial layer 106, as illustrated). Reverse source wells 712, 714 extend from near the top main surface of the semiconductor substrate 102 to a certain depth in the epitaxial layer 106. Reverse source well 712 is typically laterally surrounded by and partially extends below the gate dielectric layer 703, and reverse source well 714 is typically laterally located between the gate dielectric layers 705, 707 and partially extends below the gate dielectric layer.

[0076] Source wells 716 and 718 extend from near the top main surface of semiconductor substrate 102 into epitaxial layer 106 to a depth less than that of the corresponding reverse source wells 712 and 714. Source well 716 is located in reverse source well 712 and is typically laterally surrounded by gate dielectric layer 703. Source well 718 is located in reverse source well 714 and is typically laterally located between gate dielectric layers 705 and 707.

[0077] Source contact region 720 is located in source well 716 and extends from the top main surface of semiconductor substrate 102 into semiconductor substrate 102. Gate dielectric layer 703 laterally surrounds source contact region 720. Source contact region 722 is located in source well 718 and extends from the top main surface of semiconductor substrate 102 into semiconductor substrate 102. Source contact region 722 is laterally located between gate dielectric layers 705 and 707. Dielectric isolation structure 118 extends laterally from contact region 126 to gate dielectric layer 707, which in turn extends laterally to source contact region 722.

[0078] The dopant concentrations in the reverse source wells 712 and 714 are greater than the dopant concentration in the epitaxial layer 106. The dopant concentrations in the source wells 716 and 718 are greater than the dopant concentrations in the reverse source wells 712 and 714. The dopant concentrations in the source contact regions 720 and 722 are greater than the dopant concentrations in the source wells 716 and 718.

[0079] Drain well 726, drain terminal 728, and drift well 730 are located in semiconductor substrate 102 (e.g., in epitaxial layer 106 as illustrated). In this example, contact well 120 and contact region 126 are the drain well and drain terminal, respectively. Drain well 726 extends from near the top main surface of semiconductor substrate 102 to a certain depth in epitaxial layer 106. Drain well 726 is typically laterally located between dielectric isolation structures 702 and 704.

[0080] Drain terminal 728 is located in drain well 726 and extends from the top main surface of semiconductor substrate 102 into semiconductor substrate 102. Drain terminal 728 is laterally located between dielectric isolation structures 702 and 704. Dielectric isolation structure 704 extends laterally from drain terminal 728 to gate dielectric layer 705, which extends laterally to source contact region 722. Dielectric isolation structure 702 extends laterally from drain terminal 728 to gate dielectric layer 703, which extends laterally to source contact region 720.

[0081] Drift well 730 extends laterally from drain well 726 below dielectric isolation structures 702, 704 (e.g., laterally from drain well 726 toward reverse source well 712 and laterally from drain well 726 toward reverse source well 714). Drift well 730 extends to a depth in epitaxial layer 106 that is shallower than the depth to which drain well 726 extends. Drift well 122 extends laterally from contact well 120 below dielectric isolation structure 118 (e.g., laterally from contact well 120 toward reverse source well 714).

[0082] The dopant concentration of the drain well 726 is greater than that of the epitaxial layer 106, and may be equal to that of the contact well 120. The dopant concentration of the drain terminal 728 is greater than that of the drain well 726, and may be equal to that of the contact region 126.

[0083] In some instances, the reverse source traps 712 and 714 can be constructed using a concentration of approximately 1 × 10⁻⁶. 17 cm -3 Up to approximately 2×10 20 cm -3 P-wells doped with p-type dopant within a range of approximately 5 × 10⁻⁶ (e.g., moderately to heavily doped). In some examples, source wells 716, 718, and drain well 726 may be p-wells doped with p-type dopant at concentrations of approximately 5 × 10⁻⁶. 17 cm -3 Up to approximately 7×10 20 cm -3 n-wells doped with n-type dopant within a range of (e.g., moderately to heavily doped). In some examples, the source contacts 720, 722 and the drain terminal 728 can be used at concentrations of approximately 1 × 10⁻⁶. 20cm -3 Up to approximately 3×10 21 cm -3 The n-type dopant is within the range of n-type dopant, for example, extremely heavy doping. In some instances, the contact well 120 may be doped with an concentration of about 1 × 10⁻⁶. 17 cm -3 Up to approximately 2×10 20 cm -3 n-wells doped with n-type dopants (e.g., moderately to heavily doped) within the range of n-type dopants.

[0084] The DeMOS includes gate electrodes 740, 742, and 744, and drain field plates 746, 748, and 750. Gate electrode 740 and drain field plate 746 are laterally located between source well 716 and drain well 726. Gate electrode 740 is located above and on gate dielectric layer 703, and may further be located above and on dielectric isolation structure 702. Gate electrode 740 is located near source contact region 720 and source well 716, and vertically overlaps a portion of reverse source well 712. Drain field plate 746 is located above and on dielectric isolation structure 702, but in some instances, drain field plate 746 is located on gate dielectric layer or other dielectric structures. Drain field plate 746 is located near drain terminal 728 and drain well 726, and is located above drift well 730 extending from drain well 726 and lying beneath dielectric isolation structure 702.

[0085] Gate electrode 742 and drain field plate 748 are laterally located between source well 718 and drain well 726. Gate electrode 742 is located above and on gate dielectric layer 703, and may further be located above and on dielectric isolation structure 704. Gate electrode 742 is located near source contact region 722 and source well 718, and vertically overlaps a portion of reverse source well 714. Drain field plate 748 is located above and on dielectric isolation structure 704, but in some instances, drain field plate 748 is located on gate dielectric layer or other dielectric structures. Drain field plate 748 is located near drain terminal 728 and drain well 726, and is located above drift well 730 extending from drain well 726 and lying beneath dielectric isolation structure 704.

[0086] Gate electrode 744 and drain field plate 750 are laterally located between source well 718 and contact well 120. Gate electrode 744 is located above and on gate dielectric layer 707, and may further be located above and on dielectric isolation structure 118. Gate electrode 744 is located near source contact region 722 and source well 718, and vertically overlaps a portion of reverse source well 714. Drain field plate 750 is located above and on dielectric isolation structure 118, but in some instances, drain field plate 748 is located on gate dielectric layer or other dielectric structures. Drain field plate 750 is located near contact region 126 (e.g., drain terminal) and contact well 120, and is located above drift well 122 extending from contact well 120 and lying beneath dielectric isolation structure 118.

[0087] Gate electrodes 740, 742, 744 and drain field plates 746, 748, 750 are or comprise conductive materials. In some embodiments, gate electrodes 740, 742, 744 and drain field plates 746, 748, 750 are or comprise doped polysilicon. In some embodiments, gate electrodes 740, 742, 744 and drain field plates 746, 748, 750 may be or comprise metal. In other embodiments, the drain field plates may be located in a metal layer above the semiconductor substrate 102 (e.g., in or above one or more dielectric layers). Drain field plates 746, 748, 750 may increase the breakdown voltage. In some embodiments, drain field plates 746, 748, 750 may be omitted. Dielectric spacers (not numbered) are located on the respective sidewalls of gate electrodes 740, 742, 744 and drain field plates 746, 748, 750, and may resemble dielectric spacer 132. Examples may include multiple individual drain field plates (e.g., one drain field plate is illustrated here), each of which may have an independent applied voltage. Any number of field plates can be used to control electrostatic behavior in the active device region, thereby producing higher breakdown voltage, lower on-resistance, and / or lower parasitic capacitance.

[0088] The dielectric layer 140 is further disposed on or above the dielectric isolation structures 702, 704, gate electrodes 740, 742, 744, drain field plates 746, 748, 750, and dielectric spacers. Metal contacts 752, 754, 756, 758, 760, 762, 764, 766, 768 are disposed through the dielectric layer 140. Metal contact 752 contacts the source contact region 720. Metal contact 754 contacts the gate electrode 740. Metal contact 756 contacts the drain field plate 746. Metal contact 758 contacts the drain terminal 728. Metal contact 760 contacts the drain field plate 748. Metal contact 762 contacts the gate electrode 742. Metal contact 764 contacts the source contact region 722. Metal contact 766 contacts the gate electrode 744. Metal contact 768 contacts the drain field plate 750. Metal contacts 752 to 768 are similar to metal contacts 144, 146, and 148. Metal wires 770, 772, 774, 776, 778, 780, 782, 784, and 786 are disposed on and above dielectric layer 140 and the corresponding metal contacts 752, 754, 756, 758, 760, 762, 764, 766, and 768. Metal wires 770 to 786 are similar to metal wires 154, 156, and 158.

[0089] In some instances, source contact regions 720 and 722 are electrically connected together (e.g., through metal contacts 752 and 764, metal lines 770 and 782, and other metal lines and / or metal vias above dielectric layer 140). Drain terminal 728 and contact region 126 (e.g., drain terminal) are electrically connected together (e.g., through metal contacts 758 and 146, metal lines 776 and 156, and other metal lines and / or metal vias above dielectric layer 140). Gate electrodes 740, 742, and 744 are electrically connected together (e.g., through metal contacts 754, 762, and 766, metal lines 772, 780, and 784, and other metal lines and / or metal vias above dielectric layer 140). Drain field plates 746, 748, and 750 are ohmically connected together (e.g., via metal contacts 756, 760, 768, metal lines 774, 778, 786, and other metal lines and / or metal vias above dielectric layer 140). Junction isolation field plate 130 may be ohmically connected to source contacts 720, 722 (e.g., via metal contacts 148, 752, 764, metal lines 158, 770, 782, and other metal lines and / or metal vias above dielectric layer 140), or may be ohmically connected to another node, which may have a voltage independent of any node in the DeMOS. As previously described, the junction isolation trenches (e.g., contact 124, deep well 112, and buried layer 108) are semi-floating.

[0090] Half-pitch 788 extends from the center or midline of source contact regions 720, 722 to the adjacent drain terminal 728 or contact region 126. A first device half 790 is shown and includes three half-pitches 788. Any odd number of half-pitches 788 may be included in the first device half 790. A second device half 792 includes components of the first device half 790 in a mirror configuration (e.g., mirrored around the midline of the source contact region 720), but is not specifically described to avoid confusion. Figure 7 Features. The components of the second device half 792 are generally depicted by the second device half region 794.

[0091] Figure 8 This is a circuit diagram 800 of an integrated circuit (IC) implementing a semi-floating junction isolation trench according to some examples. The IC of circuit diagram 800 may be located on an IC die. Circuit diagram 800 includes high-side circuitry 802 and low-side transistor 804. High-side circuitry 802 may be or contain any circuitry or component thereof (e.g., one or more transistors). For example, high-side circuitry 802 may be part of a power stage (such as in a buck converter), high-voltage switching circuitry, etc. Transistor 804 may be any transistor in junction isolation trench 810, such as... Figure 7 The DeMOS and LDMOS described above. The junction isolation trench 810 and the junction isolation trench connection mechanism can be similar to those described above. Figure 1 or Figure 2 As described.

[0092] The node of high-side circuit 802 is ohmically connected to the drain node of transistor 804. The substrate (or body) node and the source node of transistor 804 are ohmically connected to the ground node. The gate node of transistor 804 is ohmically connected to the output node of drive circuit 806. The junction isolation trench 810 is ohmically floating and semi-floating (e.g., electrically connected to the drain node of transistor 804 via a drift trap in a first embodiment), as described above.

[0093] The high-side circuit 802 can operate within a voltage range from 0V to the breakdown voltage of the transistor 804. Therefore, the voltage at the node where the ohmic connection of the high-side circuit 802 is made to the drain node can be in the range from 0V to the breakdown voltage.

[0094] Furthermore, when both the substrate (or body) node and the source node are ohmically connected to the ground node, and the junction isolation trench 810 is electrically connected to the drain node in the first embodiment, the voltage of the junction isolation trench 810 can be equal to or greater than the voltage of the substrate (or body) node. This prevents unfavorable parasitic junctions between the drain node, the semiconductor substrate, and the junction isolation trench (e.g., a parasitic NPN structure) from conducting.

[0095] Figure 9This is a circuit diagram 900 of an IC implementing a semi-floating junction isolation trench according to some examples. The IC of circuit diagram 900 may be located on an IC die. Circuit diagram 900 includes high-side circuitry 902 and cascaded low-side transistors 904, 914. High-side circuitry 902 may be or contain any circuitry or component thereof (e.g., one or more transistors). For example, high-side circuitry 902 may be part of a power stage (such as in a buck converter), high-voltage switching circuitry, etc. Transistor 904 may be any transistor in junction isolation trench 910, such as... Figure 7 The DeMOS and LDMOS described above. The junction isolation trench 910 and the junction isolation trench connection mechanism can be similar to those described above. Figure 1 or Figure 2 As described. Similarly, transistor 914 can be any transistor in another junction isolation trench 920, such as Figure 7 The DeMOS and LDMOS described above. The junction isolation trench 920 can be similar to the one described above. Figure 1 or Figure 2 As described.

[0096] The node of high-side circuit 902 is ohmically connected to the drain node of transistor 904. The substrate (or body) node of transistor 904 is ohmically connected to the ground node. The gate node of transistor 904 is ohmically connected to the output node of drive circuit 906. The source node of transistor 904 is ohmically connected to the drain node of transistor 914 and the input node of diode 930. The substrate (or body) node and the source node of transistor 914 are ohmically connected to the ground node. The gate node of transistor 914 is ohmically connected to the output node of drive circuit 916. Junction isolation trench 910 is ohmically floating and semi-floating (e.g., electrically connected to the drain node of transistor 904 via a drift trap in a first embodiment), as described above. Junction isolation trench 920 is ohmically connected to the ground node. Junction isolation trenches 910 and 920 may be separate trenches in a semiconductor substrate.

[0097] The high-side circuit 902 can operate within a voltage range from 0V to the breakdown voltage of the transistor 904. Therefore, the voltage at the node where the ohmic connection of the high-side circuit 902 is made to the drain node can be from 0V to the breakdown voltage.

[0098] Diode 930 typically describes a clamping mechanism that maintains the voltage at or below the pinch-off voltage of the drift well extending from the junction isolation trench 910 at the source node of transistor 904 and the drain node of transistor 914. With the substrate (or body) node of transistor 904 ohmically connected to ground, the voltage of the junction isolation trench 910 will be equal to or greater than the voltage of the substrate (or body) node of transistor 904. When the voltage at the source node of transistor 904 is clamped at or below the pinch-off voltage, the unfavorable parasitic junction between the drain node of transistor 904, the semiconductor substrate, and the junction isolation trench 910 (e.g., a parasitic NPN structure) is typically non-conductive. The pinch-off voltage can be tuned by modifying the position of the junction isolation field plate 130 above the drift well connected to the junction isolation trench 910, modifying the lateral dimensions (e.g., length) of the junction isolation field plate 130, and / or modifying the bias voltage applied to the junction isolation field plate 130.

[0099] Figure 10 This is a circuit diagram 1000 of an IC implementing a semi-floating junction isolation trench according to some examples. The IC of circuit diagram 1000 may be located on an IC die. Circuit diagram 1000 includes low-side circuitry 1002 and high-side transistor 1004. Low-side circuitry 1002 may be or contain any circuitry or component thereof (e.g., one or more transistors). For example, low-side circuitry 1002 may be part of a power stage (such as in a buck converter), low-voltage switching circuitry, etc. Transistor 1004 may be any transistor in junction isolation trench 1010, such as... Figure 7 The DeMOS and LDMOS described above. The junction isolation trench 1010 and the junction isolation trench connection mechanism can be similar to those described above. Figure 1 or Figure 2 As described.

[0100] The voltage input (VIN) node is ohmically connected to the drain node of transistor 1004. The substrate (or body) node and the source node of transistor 1004 are ohmically connected together and ohmically connected to the node of low-side circuit 1002. The gate node of transistor 1004 is ohmically connected to the output node of drive circuit 1006. The junction isolation trench 1010 is ohmically floating and semi-floating (e.g., in a first embodiment, electrically connected to the drain node of transistor 1004 via a drift trap), as described above.

[0101] The low-side circuit 1002 can operate within a voltage range from 0V to the breakdown voltage of the transistor 1004. Therefore, the voltage at the node where the low-side circuit 1002 is electrically connected to the source node can be in the range from 0V to the breakdown voltage. In some instances, the breakdown voltage can be increased, which allows the circuit to interface with higher voltages than otherwise achievable.

[0102] exist Figure 8 , 9 In the circuit diagrams 800, 900, and 1000 of 10, transistors 804, 904, 914, and 1004 are described as having a drain node, a source node, a substrate (or body) node, and a gate node. The drain node may include or correspond to a drain well and / or drain terminal in a corresponding junction isolation trench in, for example, the semiconductor substrate 102 (e.g., epitaxial layer 106), similar to... Figure 7 As described herein. A source node may include or correspond to a source well and / or source contact region in a corresponding junction isolation trench in, for example, the semiconductor substrate 102 (e.g., epitaxial layer 106). A substrate (or body) node may include or correspond to a substrate well and / or substrate contact region in a corresponding junction isolation trench in, for example, the semiconductor substrate 102 (e.g., epitaxial layer 106), which is doped with the same conductivity type as the semiconductor substrate 102. A gate node may include or correspond to a gate electrode, for example, on or above the semiconductor substrate 102.

[0103] Figures 11 to 19 Explain the process at each manufacturing stage based on the example method. Figure 4 A cross-sectional view of the semiconductor device 400. To avoid unnecessary repetition, doped buried layers, wells, and doped regions are formed by implanting dopants into the semiconductor substrate 102. To form doped buried layers, wells, or doped regions by implantation, a photoresist may be deposited (e.g., by spin coating) on ​​or above the semiconductor substrate 102, and photolithographic patterning is used to expose regions corresponding to the locations where doped buried layers, wells, or doped regions are to be formed. Using the patterned photoresist as a mask, implantation is performed to implant dopants into the semiconductor substrate 102, thereby forming doped buried layers, wells, or doped regions. After implantation, the photoresist may be removed, such as by wet stripping or ashing. Figures 11 to 19 Examples of the various dopant types and concentrations of doped buried layers, wells, and doped regions described above are provided.

[0104] refer to Figure 11 The buried layer 108 is formed in the semiconductor support substrate 104. The buried layer 108 can be formed by implanting dopants into the semiconductor support substrate 104. (Reference) Figure 12An epitaxial layer 106 is formed on or above a semiconductor support substrate 104. The epitaxial layer 106 can be formed using epitaxial growth via a suitable epitaxial growth process, such as low-pressure chemical vapor deposition (LPCVD). For example, the epitaxial layer 106 may be in-situ doped during epitaxial growth. The type and concentration of dopants in the epitaxial layer 106 are as described above. In the illustrated example, the semiconductor support substrate 104 and the epitaxial layer 106 form a semiconductor substrate 102. In other examples, another semiconductor substrate may be used. For instance, the semiconductor substrate 102 may be a bulk silicon wafer (e.g., without the epitaxial layer 106) in which a buried layer 108 is embedded at a depth within the semiconductor substrate 102.

[0105] refer to Figure 13 The deep well 112 is formed in the semiconductor substrate 102. The deep well 112 can be formed by implanting dopant into the epitaxial layer 106. (Reference) Figure 14 Drift well 122 is formed in semiconductor substrate 102. Drift well 122 can be formed by implanting dopant into epitaxial layer 106. (Reference) Figure 15 The buried layer 406 is formed in the semiconductor substrate 102. The buried layer 406 can be formed by implanting dopants into the epitaxial layer 106.

[0106] refer to Figure 16 Dielectric isolation structures 116 and 118 are formed in the semiconductor substrate 102. In the illustrated example, dielectric isolation structures 116 and 118 are STI (Surface Mount Technology), and in other examples, dielectric isolation structures 116 and 118 may be or include other dielectric isolation structures, such as field oxide structures, LOCOS structures, stepped gate dielectric structures, etc. To form the illustrated dielectric isolation structures 116 and 118, a hard mask may be deposited on or above the semiconductor substrate 102 and patterned using appropriate photolithography and etching processes. Using the patterned hard mask, trenches are etched into the semiconductor substrate 102. Dielectric material is deposited in the trenches. For example, the dielectric material may be or include nitrides, oxides, the like, or combinations thereof, and may be formed or deposited using in-situ vapor generation (ISSG) oxidation, atomic layer deposition (ALD), high aspect ratio chemical vapor deposition (HAR-CVD), flowable chemical vapor deposition (FCVD), the like, or combinations thereof. Excess dielectric material and hard masks can be removed, for example, by using chemical mechanical polishing (CMP).

[0107] refer to Figure 17 Contact well 120 (e.g., cathode well) and anode well 402 are formed in semiconductor substrate 102. Contact well 120 can be formed by implanting a dopant into epitaxial layer 106 in an implantation process, and anode well 402 can be formed by implanting a dopant into epitaxial layer 106 in another implantation process. Reference Figure 18Contact regions 124 and 126 (e.g., cathode terminals) and anode terminal 404 are formed in semiconductor substrate 102. Contact regions 124 and 126 can be formed by implanting dopants into epitaxial layer 106 in an implantation process, and anode terminal 404 can be formed by implanting dopants into epitaxial layer 106 in another implantation process.

[0108] refer to Figure 19 A junction isolation field plate 130, an anode field plate 412, and a cathode field plate 414 are formed above a semiconductor substrate 102. Material for the field plates 130, 412, and 414 is deposited on or above the semiconductor substrate 102. The material for the field plates 130, 412, and 414 can be deposited using any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. In some instances, such as when the field plates 130, 412, and 414 are or contain doped polysilicon, the polysilicon can be doped in situ and / or by implantation. The material for the field plates 130, 412, and 414 is then patterned into the field plates 130, 412, and 414 using suitable photolithography and etching processes. In instances where the device includes one or more gate electrodes, one or more gate electrodes can be formed using the junction isolation field plate 130.

[0109] Dielectric spacers 132 and 416 are formed on the sidewalls of field plates 130, 412, and 414. Conformal dielectric layers are conformally formed on or above the sidewalls and upper surfaces of field plates 130, 412, and 414, such as using a suitable deposition process similar to CVD or ALD. The conformal dielectric layers are anisotropically etched, for example, by reactive ion etching (RIE), thereby producing the dielectric spacers 132 and 416.

[0110] refer to Figure 4A dielectric layer 140 is formed over the semiconductor substrate 102. The dielectric layer 140 may comprise one or more dielectric layers formed of any suitable dielectric material and deposited by any suitable deposition process (such as CVD, PVD, etc.). Metal contacts 144, 146, 148, 424, 426, 428 are formed through the dielectric layer 140, and metal lines 154, 156, 158, 434, 436, 438 are formed above and over the metal contacts 144, 146, 148, 424, 426, 428, and respectively, and are formed above and over the dielectric layer 140. To form the metal contacts, photolithography and etching processes are used to form openings through the dielectric layer 140. The corresponding openings expose the corresponding contact areas 124, 126, the anode terminal 404, and the field plates 130, 412, 414. A barrier layer and / or adhesive layer may be conformally deposited in the opening and above the dielectric layer 140, such as by CVD, ALD, etc., and filler metal may be deposited on the barrier layer and / or adhesive layer, such as by CVD, ALD, etc. The barrier layer and / or adhesive layer and filler metal in the opening form metal contacts 144, 146, 148, 424, 426, 428. The barrier layer and / or adhesive layer and filler metal above the dielectric layer 140 may be patterned into metal lines 154, 156, 158, 434, 436, 438, such as by appropriate photolithography and etching processes.

[0111] Figures 20 to 26 Explain the process at each manufacturing stage based on the example method. Figure 2 Includes diodes (and) Figure 4 A cross-sectional view of a semiconductor device with a junction isolation trench connection mechanism (similar to the one in the middle). Figures 20 to 26 Examples of the various dopant types and concentrations of doped buried layers, wells, and doped regions described above are provided.

[0112] As mentioned above Figures 11 to 13 The described process will be carried out. (See reference.) Figure 20 The well 220 is formed in the semiconductor substrate 102. The well 220 can be formed by implanting a dopant into the epitaxial layer 106. (Reference) Figure 21 A buried layer 230 is formed in the semiconductor substrate 102. The buried layer 230 can be formed by implanting dopants into the epitaxial layer 106. As previously described, a portion of the buried layer 230 overlaps with a portion of the well 220. Because the dopant concentration in the buried layer 230 is greater than that in the well 220, the buried layer 230 dominates in the overlapping portion. This forms a drift well portion 224 of the well 220 located above the buried layer 230 and a well portion 222 of the well 220 laterally adjacent to the buried layer 230.

[0113] refer to Figure 22 The buried layer 406 is formed in the semiconductor substrate 102, similar to the above description. Figure 15As described. Reference Figure 23 Dielectric isolation structures 116 and 118 are formed in the semiconductor substrate 102, similar to those described above. Figure 16 As described. Reference Figure 24 The anode well 402 is formed in the semiconductor substrate 102, similar to the above description. Figure 17 As described. Reference Figure 25 Contact regions 124, 126 and anode terminal 404 are formed in semiconductor substrate 102, similar to the above description. Figure 18 As described. Reference Figure 26 The isolation field plate 130, the anode field plate 412, and the cathode field plate 414 are formed above the semiconductor substrate 102, similar to the above description. Figure 19 As described above. Next, a dielectric layer 140 is formed over the semiconductor substrate 102, similar to the above description. Figure 4 As described above. Metal contacts 144, 146, 148, 424, 426, and 428 are formed through the dielectric layer 140, and metal lines 154, 156, 158, 434, 436, and 438 are formed above and on the metal contacts 144, 146, 148, 424, 426, and 428, respectively, and are formed above and on the dielectric layer 140, similar to the description above.

[0114] Given the methods described above, various other devices can be formed in the junction isolation trench. Different and / or additional doped buried layers, wells, and / or contact regions can be formed in the semiconductor substrate through implantation similar to that described above. Different and / or additional field plates and / or gate electrodes can be formed on and over the semiconductor substrate using processes similar to those described above to form field plates 130, 412, 414. Thus, devices such as Figure 7 A device of DeMOS, LDMOS, or another transistor.

[0115] Although various examples have been described in detail, it should be understood that various changes, substitutions and alterations may be made therein without departing from the scope defined by the appended claims.

Claims

1. A semiconductor device comprising: An epitaxial layer having a first conductivity type is located above a semiconductor substrate; A buried layer having a second conductivity type opposite to the first conductivity type, the buried layer being spaced apart from the top surface of the epitaxial layer; A deep well having the second conductivity type, the deep well extending in the epitaxial layer and touching the buried layer, the deep well laterally surrounding an active region in the epitaxial layer above the buried layer; A drift trap having the second conductivity type, the drift trap extending to a first depth in the epitaxial layer, the drift trap extending laterally from the deep trap toward the active region; A contact well having the second conductivity type, the contact well extending in the epitaxial layer to a second greater depth and touching the drift well; and A contact area having the second conductivity type, the contact area extending in the contact well.

2. The semiconductor device of claim 1, wherein the contact well is at least a portion of the device surrounded by the contact region, and the at least portion of the device is located in the active region.

3. The semiconductor device of claim 2, wherein the buried layer and the deep well are configured to ohmically float during operation of the device.

4. The semiconductor device of claim 1, further comprising a diode located in the active region, the diode including an anode well extending in the epitaxial layer, wherein the contact well is a cathode well of the diode.

5. The semiconductor device of claim 1, further comprising a transistor located in the active region, the transistor including a source well in the epitaxial layer, wherein the contact well is a drain well of the transistor.

6. The semiconductor device of claim 5, wherein the transistor is a laterally diffused metal-oxide-semiconductor (LDMOS) transistor.

7. The semiconductor device of claim 5, wherein the transistor is a drain diffuse metal-oxide-semiconductor (DeMOS) transistor.

8. The semiconductor device of claim 1, further comprising a field plate located above the drift trap.

9. The semiconductor device of claim 8, wherein the field plate is ohmically connected to the anode contact terminal of the diode in the active region.

10. The semiconductor device of claim 8, wherein the field plate is ohmically electrically connected to the source contact terminal of the transistor in the active region.

11. The semiconductor device of claim 1, wherein the first conductivity type is p-type and the second conductivity type is n-type.

12. An integrated circuit, comprising: A first transistor is located in a first active region in a semiconductor substrate, wherein: The first transistor includes: The first source region is located in the semiconductor substrate; A first drain region is located in the semiconductor substrate; and A first gate electrode is located above the semiconductor substrate; and The semiconductor substrate comprises: The first buried layer, wherein the first source region and the first drain region are located above the first buried layer; A first deep well, extending into the first buried layer, laterally surrounding the first active region; and A first drift well extends laterally from the first deep well and into the first drain region, wherein the first buried layer, the first deep well, the first drift well, and the first drain region are doped with corresponding dopants having the same conductivity type; and A field plate is located above the semiconductor substrate and above the first drift well, and the field plate is laterally positioned between the first deep well and the first drain region.

13. The integrated circuit of claim 12, wherein the field plate is ohmically electrically connected to the first source region.

14. The integrated circuit of claim 12, wherein the first buried layer and the first deep well are configured to float ohmically during operation of the first transistor.

15. The integrated circuit of claim 12, further comprising a second transistor located in a second active region in the semiconductor substrate, wherein: The second transistor includes: The second source region is located in the semiconductor substrate; A second drain region is located in the semiconductor substrate, and the second drain region is ohmically connected to the first source region; and A second gate electrode is located above the semiconductor substrate; and The semiconductor substrate further comprises: The second buried layer, the second source region and the second drain region are located above the second buried layer; and A second deep well extends into the second buried layer and laterally surrounds the second active region, wherein the second buried layer, the second deep well, and the second drain region are doped with corresponding dopants having the same conductivity type as the first buried layer.

16. The integrated circuit of claim 15, wherein the second source region is ohmically connected to the second buried layer and the second deep well.

17. A method of forming a semiconductor device, the method comprising: A buried layer is formed in a semiconductor substrate, the buried layer having a first conductivity type; An epitaxial layer is formed over the semiconductor substrate, the epitaxial layer having a second conductivity type opposite to the first conductivity type, and the buried layer is spaced apart from the top surface of the epitaxial layer; A deep well is formed in the epitaxial layer that extends and touches the buried layer, the deep well laterally surrounding the active region in the epitaxial layer above the buried layer, the deep well having the first conductivity type; A drift well is formed extending in the epitaxial layer, the drift well extending laterally from the deep well toward the active region, the drift well having the first conductivity type; as well as A contact well is formed in the epitaxial layer that extends and touches the drift well, the contact well having the first conductivity type; as well as A contact region is formed extending in the epitaxial layer and the contact well, the contact region having the first conductivity type.

18. The method of claim 17, further comprising forming a means surrounded by the contact area in the active region, wherein the contact trap is part of the means.

19. The method of claim 18, wherein the buried layer and the deep well are configured to ohmically float during operation of the device.

20. The method of claim 17, further comprising forming a field plate above the drift trap.

21. The method of claim 20, wherein the field plate is ohmically connected to the anode terminal of the diode in the active region.

22. The method of claim 20, wherein the field plate is ohmically electrically connected to the source terminal of the transistor in the active region.

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