Semiconductor device, preparation method and electronic equipment
By using the selectivity difference of the etch protection layer in three-dimensional stacked semiconductor devices, the contact hole fabrication process is simplified, solving the problems of long process cycle and high cost, and improving device performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-17
- Publication Date
- 2026-03-13
AI Technical Summary
The fabrication process of contact holes in three-dimensional stacked semiconductor devices is complex, resulting in long process cycles and high costs.
By employing a material selectivity ratio lower than that of the dielectric layer but higher than that of the source and drain structures, the etching protective layer is used as a difference in etching selectivity to achieve simultaneous etching of vias in a single operation, simplifying the fabrication process.
While ensuring reliability, the fabrication process of through holes is simplified, the process cycle and cost are reduced, and the uniformity of through holes and device performance are improved.
Smart Images
Figure CN121665682A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device, a fabrication method, and an electronic device. Background Technology
[0002] As integrated circuits develop, the feature size of transistors continues to shrink, slowing down the development of traditional two-dimensional planar structures. Therefore, the industry is currently focusing on three-dimensional integration to further increase integration density and improve device performance through three-dimensional stacking.
[0003] However, for three-dimensional stacked semiconductor devices (also known as 3D stacked devices), the contact hole depths of each transistor vary due to their different heights. Furthermore, since the contact holes need to be etched to contact the source and drain of the corresponding transistors without damaging them, the fabrication process for the contact holes in 3D stacked devices is typically complex, resulting in long processing times and high costs. Therefore, simplifying the fabrication process for contact holes in 3D stacked devices has become a key issue for those skilled in the art. Summary of the Invention
[0004] In view of the above, this application provides a semiconductor device, a fabrication method, and an electronic device, as follows:
[0005] A semiconductor device, comprising:
[0006] Substrate;
[0007] A plurality of transistor structures are stacked sequentially from bottom to top on one side of the substrate, and an etch protection layer is provided on the side of the source structure and drain structure of the transistor structure away from the substrate. The etch protection layer covers the side of the source structure and the drain structure away from the substrate, respectively. The source structure and the drain structure are located on opposite sides of the gate structure of the transistor structure along a first direction, which is parallel to the plane of the substrate.
[0008] A dielectric layer is located on one side of the substrate, and the transistor structure is located in the dielectric layer and is mutually insulated and isolated through the dielectric layer;
[0009] The vias correspond to the source structure and the drain structure, respectively. The vias include a first via and a second via. The first via extends from the side of the dielectric layer away from the substrate to the etch protection layer. The second via penetrates the etch protection layer and extends to the source structure and the drain structure. The first via and the second via are connected. Metal interconnects are formed in the vias to bring out the source structure and the drain structure.
[0010] When etching to form the via, the etching protection layer is used to achieve an etching selectivity lower than that of the dielectric layer, but higher than that of the source structure and the drain structure.
[0011] Optionally, the material of the etched protective layer is an insulating material, and the dielectric constant of the material of the etched protective layer is less than a preset value.
[0012] Optionally, the material of the etched protective layer is SiOC.
[0013] Optionally, along the second direction, the thickness of the etched protective layer ranges from 2 nm to 100 nm, including the endpoint values;
[0014] The second direction is perpendicular to the plane in which the substrate is located.
[0015] Optionally, the thickness of the etched protective layer is equal along the second direction.
[0016] Optionally, the plurality of transistor structures include at least one of fin field-effect transistors and nanosheet ring-gate field-effect transistors.
[0017] A method for fabricating a semiconductor device, used to fabricate the semiconductor device described in any of the above embodiments, comprising:
[0018] Provide a substrate;
[0019] Multiple transistor structures are formed in a stacked manner from bottom to top on one side of the substrate. During the formation of each transistor structure, an etch protection layer is formed on the side of the source structure and the drain structure away from the substrate. The etch protection layer covers the side of the source structure and the drain structure away from the substrate. The source structure and the drain structure are located on opposite sides of the gate structure of the transistor structure along a first direction, which is parallel to the plane of the substrate.
[0020] In the process of forming each of the transistor structures, a dielectric layer is also formed on one side of the substrate, the transistor structures are located in the dielectric layer and are mutually insulated and isolated through the dielectric layer;
[0021] After forming the transistor structure and the dielectric layer, vias are formed corresponding to the source structure and the drain structure, respectively; wherein forming the vias includes:
[0022] The first via is formed, and the first via extends from the side of the dielectric layer away from the substrate to the etch protection layer;
[0023] A second via is formed, which penetrates the etched protective layer and extends to the source structure and the drain structure, and the first via is connected to the second via;
[0024] Metal interconnects are formed in the via to bring out the source structure and the drain structure.
[0025] When etching to form the via, the etching protection layer is used to achieve an etching selectivity lower than that of the dielectric layer, but higher than that of the source structure and the drain structure.
[0026] Optionally, forming the through hole includes:
[0027] After the transistor structure and the dielectric layer are formed, and before the first via is formed, a photoresist layer is formed on the side of the dielectric layer away from the substrate;
[0028] After the photoresist layer is exposed and developed, the dielectric layer is etched to form the first via.
[0029] After forming the first via, the photoresist layer is removed, and the portion of the etch protection layer exposed in the first via is etched to form the second via.
[0030] Optionally, the plurality of transistor structures includes a first transistor structure and a second transistor structure, and forming a plurality of transistor structures stacked sequentially from bottom to top on one side of the substrate includes:
[0031] The first transistor structure is formed on one side of the substrate, and the etching protection layer is formed thereon;
[0032] A first dielectric layer is formed, which covers the first transistor structure and the etch protection layer on the side away from the substrate;
[0033] The second transistor structure is formed on the side of the first dielectric layer away from the substrate, and the etching protection layer is formed thereon;
[0034] A second dielectric layer is formed, which covers the second transistor structure and the etch protection layer on the side away from the substrate, and the second dielectric layer is in contact with the first dielectric layer;
[0035] The first via corresponding to the first transistor structure extends sequentially through the second dielectric layer and the first dielectric layer to the etch protection layer of the first transistor structure, and the first via corresponding to the second transistor structure extends through the second dielectric layer to the etch protection layer of the second transistor structure.
[0036] An electronic device includes the semiconductor device described in any of the above embodiments. Compared with related technologies, the beneficial effects of the technical solution of this application are as follows:
[0037] The semiconductor device includes a substrate, multiple transistor structures stacked on one side of the substrate and within a dielectric layer, and an etch-protected layer covering the source and drain structures of the transistor structures. It also includes vias corresponding to the source and drain structures, respectively. The vias include a first via and a second via. The first via extends from the side of the dielectric layer away from the substrate to the etch-protected layer, and the second via penetrates the etch-protected layer, extending to the source and drain structures. The first and second vias are connected. Metal interconnects are formed within the vias to guide the source and drain structures. Therefore, the first vias and second vias of each transistor structure are all located within the same film layer structure. Furthermore, since the etch-protected layer can achieve a lower etch selectivity than the dielectric layer when etching the first via, the etching process will stop when the etch reaches the etch-protected layer due to the reduced etching rate. Therefore, the etch protection layer can serve as an etch barrier layer for the first via, preventing damage to the source and drain structures when forming vias of different depths. The first via can be etched simultaneously in one operation. Similarly, when etching to form the second via, the etch selectivity of the etch protection layer is higher than that of the source and drain structures. Therefore, during the etching of the second via, the etching rate will decrease and stop when the source and drain structures are reached, preventing damage to them. The second via can also be etched simultaneously in one operation. Thus, semiconductor devices can simplify the via fabrication process while ensuring reliability, effectively solving the problems of long process cycles and high costs caused by via fabrication in semiconductor devices. Attached Figure Description
[0038] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0039] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size should still fall within the scope of the technical content disclosed in this application, provided that they do not affect the effects and purposes that this application can produce.
[0040] Figure 1 This application provides a schematic diagram of the structure of a semiconductor device;
[0041] Figure 2 A schematic diagram of the structure of another semiconductor device provided in this application;
[0042] Figure 3 A flowchart of a preparation method provided in this application;
[0043] Figure 4 This is a schematic diagram of the structure formed by each step in the preparation method provided in this application. Detailed Implementation
[0044] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0045] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0046] As described in the background section, simplifying the fabrication process of contact holes in 3D stacked devices has become a key issue for those skilled in the art.
[0047] Based on the above, this application provides a semiconductor device, such as... Figure 1 As shown, Figure 1 This application provides a schematic diagram of a semiconductor device, which includes: a substrate 100, a plurality of transistor structures 200 located on one side of the substrate 100, and an etched protective layer 300 located on the side of the source structure 202 and drain structure 204 of the transistor structures 200 away from the substrate 100. The source structure 202 and drain structure 204 are respectively located on opposite sides of the gate structure 206 of the transistor structure 200 along a first direction, which is parallel to the plane of the substrate 100. The substrate 100 can be a bulk silicon or SOI substrate, on which a semiconductor layer 208 of the transistor structures 200 (e.g., the first transistor structure 1 described later) is formed, but this application does not limit this, and the specific method depends on the circumstances. It should be noted that the source structure 202 and drain structure 204 are the source and drain doped regions in the transistor structure 200, respectively.
[0048] Multiple transistor structures 200 located on one side of the substrate 100 are stacked sequentially from bottom to top, and etch protection layers 300 respectively cover the sides of the source structure 202 and the drain structure 204 away from the substrate 100. Specifically, each of the multiple transistor structures 200 is provided with a corresponding etch protection layer 300, and the source structure 202 and drain structure 204 of each transistor structure 200 are covered with etch protection layer 300, that is, except for the gate structure 206, the source structure 202 and drain structure 204 of each transistor structure 200 are covered with etch protection layer 300.
[0049] Continue as Figure 1 As shown, the semiconductor device also includes a dielectric layer 400 located on one side of the substrate 100, and vias 500 corresponding to the source structure 202 and the drain structure 204, respectively. Transistor structures 200 are located within the dielectric layer 400, and the transistor structures 200 are mutually insulated from each other through the dielectric layer 400. That is, multiple transistor structures 200 and the dielectric layer 400 are disposed on the same side of the substrate 100, and the multiple transistor structures 200 are covered by the dielectric layer 400 and mutually insulated from each other through the dielectric layer 400.
[0050] The aforementioned via 500 includes a first via 502 and a second via 504. The first via 502 extends from the side of the dielectric layer 400 away from the substrate 100 to the etch protection layer 300. The second via 504 penetrates the etch protection layer 300 and extends to the source structure 202 and the drain structure 204. The first via 502 and the second via 504 are connected. Metal interconnects 506 are formed in the via 500 to guide the source structure 202 and the drain structure 204. That is, the source structure 202 and the drain structure 204 are electrically connected to external metal electrodes through the metal interconnects 506 in their corresponding vias 500. It should be noted that the vias 500 corresponding to the source structure 202 and the drain structure 204 mentioned above refer to the vias 500 respectively provided above the source structure 202 and the drain structure 204 in each transistor structure 200, so as to bring out the source structure 202 and the drain structure 204 of each transistor structure 200 through the vias 500.
[0051] Specifically, when etching to form the via 500, the etching protection layer 300 achieves an etching selectivity higher than that of the dielectric layer 400, but lower than that of the source structure 202 and the drain structure 204. In other words, when etching to form the first via 502, the etching selectivity of the etching protection layer 300 is lower than that of the dielectric layer 400; when etching to form the second via 504, the etching selectivity of the etching protection layer 300 is higher than that of the source structure 202 and the drain structure 204. It should be noted that etching selectivity is generally defined as the ratio of the etching rates of two different materials under the same etching conditions during the etching process.
[0052] As described above, the vias 500 of the source structure 202 and drain structure 204 of each transistor structure 200 in this semiconductor device all include interconnected first vias 502 and second vias 504. The first via 502 is formed in the dielectric layer 400, and the second via 504 is formed in the etch protection layer 300. Therefore, the first vias 502 and the second vias 504 of each transistor structure 200 are all located in the same film layer structure. Thus, the first vias 502 and the second vias 504 of each transistor structure 200 can be etched synchronously in the same etching process. Furthermore, since the etching selectivity of the etch protection layer 300 is lower than that of the dielectric layer 400 when etching the first via 502, the etching will stop when the etching rate decreases upon reaching the etch protection layer 300, thus achieving self-stopping etching. Therefore, the etch protection layer 300 can serve as an etch barrier layer for the first via 502. When forming first vias 502 of different depths, the etch protection layer 300 prevents damage to the source structure 202 and drain structure 204, allowing first vias 502 of different depths corresponding to different transistor structures 200 to be etched synchronously in one operation. Furthermore, when forming the second via 504, the etch selectivity of the etch protection layer 300 is higher than that of the source structure 202 and drain structure 204. That is, the etch selectivity of the source structure 202 and drain structure 204 is lower than that of the etch protection layer 300. Therefore, during the etching of the second via 504, when etching reaches the source structure 202 and drain structure 204, the etching will stop due to the reduced etching rate, preventing damage to the source structure 202 and drain structure 204.
[0053] In summary, the semiconductor device provided in this application simplifies the fabrication process of the via 500 while ensuring reliability. Both the first and second vias are etched in a single operation, effectively solving the problems of long process cycles and high costs associated with the fabrication of the via 500 in this semiconductor device. Furthermore, the single-operation etching of the first and second vias ensures that the vias are as consistent as possible, improving the uniformity of the vias in the semiconductor device and guaranteeing device performance.
[0054] In one embodiment of this application, the etching protective layer 300 is made of an insulating material, and the dielectric constant of the etching barrier layer is less than a preset value, i.e., the etching protective layer 300 is a low-k material. This allows the etching protective layer 300 to achieve insulation of the source structure 202 and drain structure 204 it covers, except for the via 500, and can also suppress parasitic capacitance, thus not affecting the operation of the semiconductor device. It should be noted that low-k material refers to an insulating material with a dielectric constant (k value) lower than that of traditional silicon dioxide (SiO2, k≈3.9~4.3). Generally, materials with k≤3.9 are defined as low-k materials, but for a more stringent standard, k≤2.8 is used as the boundary. This application does not limit this, and it depends on the specific circumstances.
[0055] In one embodiment of this application, the material of the etched protective layer 300 is SiOC, also known as carbon composite silicon suboxide. However, this application does not limit this and the specific material may be chosen depending on the circumstances.
[0056] In one embodiment of this application, along a second direction perpendicular to the plane of the substrate 100, the thickness of the etched protective layer 300 ranges from 2 nm to 100 nm, including the endpoint values. However, this application does not limit this value and the specific thickness depends on the circumstances.
[0057] In one embodiment of this application, the thickness of the etch protective layer 300 is equal along the second direction, meaning that the thickness of the etch protective layer 300 is equal for each of the plurality of transistor structures 200. Therefore, in this semiconductor device, the thickness of the etch protective layer 300 is uniform, meaning the depth of the second via 504 can be the same. Thus, when simultaneously forming the second vias 504 of each transistor structure 200, the etching parameters of the second vias 504 of each transistor structure 200 can also be the same, simplifying the etching process of the second via 504 and further simplifying the fabrication process of the via 500.
[0058] In one embodiment of this application, the plurality of transistor structures 200 may include at least one of fin field-effect transistors and nanosheet gate-around field-effect transistors. However, this application is not limited thereto and the specific implementation depends on the circumstances.
[0059] Based on the foregoing, in a specific embodiment of this application, such as Figure 2 As shown, for example, the semiconductor device includes a first transistor structure 1 and a second transistor structure 2 stacked sequentially from bottom to top. Along the second direction, the thickness H1 of the etch barrier layer can be 70 nm, the depth H2 of the via 500 of the first transistor structure 1 can be 1300 nm, the depth H3 of the via 500 of the second transistor structure 2 can be 600 nm, and the thickness H4 of the source structure 202 and drain structure 204 of each transistor structure 200 can be 30 nm. It should be noted that during the formation of the semiconductor device described in this embodiment, the thickness loss of the etch protection layer 300 below the first via 502 is approximately 10 nm. Based on this, the etching selectivity ratio of the dielectric layer 400 to the etch protection layer 300 can be greater than 120:1. The etch protection layer 300 can effectively serve as an etch barrier layer during the etching process of the first via 502, so that the first via 502 of each transistor structure 200 can be etched in one step, simplifying the fabrication process of the via 500.
[0060] This application also provides a method for fabricating a semiconductor device, which is used to fabricate the semiconductor device described in any of the above embodiments. For example... Figure 3 The diagram shown is a flowchart of a method for fabricating a semiconductor device according to this application. The method includes:
[0061] S1: A substrate 100 is provided. The substrate 100 may be a bulk silicon or SOI substrate 100, but this application does not limit it and it depends on the specific circumstances.
[0062] S2: A plurality of transistor structures 200 are formed in a bottom-to-top stacked manner on one side of the substrate 100. During the formation of each transistor structure 200, an etch protection layer 300 is formed on the side of the source structure 202 and drain structure 204 of each transistor structure 200 away from the substrate 100. The etch protection layer 300 covers the side of the source structure 202 and drain structure 204 away from the substrate 100. The source structure 202 and drain structure 204 are located on opposite sides of the gate structure 206 of the transistor structure 200 along a first direction, which is parallel to the plane of the substrate 100.
[0063] S3: During the formation of each transistor structure 200, a dielectric layer 400 is also formed on one side of the substrate 100. The transistor structures 200 are located in the dielectric layer 400 and are mutually insulated and isolated through the dielectric layer 400.
[0064] S4: After forming the transistor structure 200 and the dielectric layer 400, vias 500 are formed, corresponding to the source structure 202 and the drain structure 204, respectively. Forming the vias 500 includes:
[0065] A first via 502 is formed, which extends from the side of the dielectric layer 400 away from the substrate 100 to the etch protection layer 300.
[0066] A second via 504 is formed, which penetrates the etched protective layer 300 and extends to the source structure 202 and the drain structure 204, and the first via 502 is connected to the second via 504.
[0067] S5: After forming the via 500, a metal connection line 506 is formed in the via 500 to bring out the source structure 202 and the drain structure 204.
[0068] Specifically, when etching to form the via 500, the etching protection layer 300 is used to achieve an etching selectivity lower than that of the dielectric layer 400, but higher than that of the source structure 202 and the drain structure 204. In other words, when etching to form the first via 502, the etching selectivity of the etching protection layer 300 is lower than that of the dielectric layer 400; when etching to form the second via 504, the etching selectivity of the etching protection layer 300 is higher than that of the source structure 202 and the drain structure 204.
[0069] As described above, the fabrication method includes covering each transistor structure 200 with an etch protection layer 300 above the source structure 202 and drain structure 204, respectively. This ensures that when etching to form the first via 502, the etch selectivity of the etch protection layer 300 is lower than that of the dielectric layer 400; and when etching to form the second via 504, the etch selectivity of the etch protection layer 300 is higher than that of the source structure 202 and drain structure 204. Furthermore, since the first via 502 is formed in the dielectric layer 400 and the second via 504 is formed in the etch protection layer 300, meaning that the first via 502 and the second via 504 of each transistor structure 200 are located in the same film layer structure, the first via 502 and the second via 504 of each transistor structure 200 can be etched synchronously in the same etching process, and the second via 504 can also be etched synchronously in the same etching process.
[0070] It should be noted that, because the etching selectivity of the etch protector layer 300 is lower than that of the dielectric layer 400 when etching to form the first via 502, the etching process will stop when the etching reaches the etch protector layer 300 due to the reduced etching rate. Therefore, the etch protector layer 300 can act as an etching barrier layer for the first via 502, so that when forming first vias 502 of different depths, the source structure 202 and drain structure 204 will not be damaged due to the barrier effect of the etch protector layer 300, allowing the first vias 502 of different depths corresponding to different transistor structures 200 to be etched simultaneously in one go. In addition, when forming the second via 504, the etching selectivity of the etch protection layer 300 is higher than that of the source structure 202 and the drain structure 204. That is, the etching selectivity of the source structure 202 and the drain structure 204 is lower than that of the etch protection layer 300. Therefore, during the etching of the second via 504, when etching reaches the source structure 202 and the drain structure 204, the etching will stop due to the decrease in etching rate, and the source structure 202 and the drain structure 204 will not be damaged.
[0071] In summary, this fabrication method simplifies the fabrication process of via 500 while ensuring reliability, effectively solving the problems of long process cycle and high cost caused by the fabrication of via 500 in this semiconductor device.
[0072] In one embodiment of this application, forming a via 500 includes: after forming a transistor structure 200 and a dielectric layer 400, and before forming a first via 502, forming a photoresist layer 600 on the side of the dielectric layer 400 away from the substrate 100; after exposing and developing the photoresist layer 600, etching the dielectric layer 400 to form the first via 502; after forming the first via 502, removing the photoresist layer 600, and etching the portion of the etching protection layer 300 exposed in the first via 502 to form a second via 504. It should be noted that removing the photoresist layer 600 before etching to form the second via 504 can effectively prevent the byproducts of the photoresist layer 600 from affecting the etching environment, thereby ensuring etching reliability.
[0073] In one embodiment of this application, taking a plurality of transistor structures 200 including a first transistor structure 1 and a second transistor structure 2 as an example, forming a plurality of transistor structures 200 arranged in a sequentially stacked manner from bottom to top on one side of a substrate 100 includes: forming a first transistor structure 1 on one side of the substrate 100 and forming an etch protection layer 300; forming a first dielectric layer 402, the first dielectric layer 402 covering the first transistor structure 1 and the side of the etch protection layer 300 away from the substrate 100, that is, the first dielectric layer 402 covering the source structure 202 of the first transistor structure 1 and the... An etch protection layer and a gate metal layer are formed above the drain structure 204; a second transistor structure 2 is formed on the side of the first dielectric layer 402 away from the substrate 100, and an etch protection layer 300 is formed; a second dielectric layer 404 is formed, which covers the second transistor structure 2 and the side of the etch protection layer 300 away from the substrate 100, and the second dielectric layer 404 is connected to the first dielectric layer 402, that is, the second dielectric layer 404 covers the etch protection layer 300 and the gate metal layer above the source structure 202 and the drain structure 204 of the second transistor structure 2.
[0074] In this configuration, the first via 502 corresponding to the first transistor structure 1 extends sequentially through the second dielectric layer 404 and the first dielectric layer 402 to the etch protection layer 300 of the first transistor structure 1. Similarly, the first via 502 corresponding to the second transistor structure 2 extends through the second dielectric layer 404 to the etch protection layer 300 of the second transistor structure 2. This ensures that the first via 502 of each transistor structure 200 is located in the dielectric layer 400, and the second via 504 is located in the etch protection layer 300. Consequently, the first via 502 can be etched in one step, and the second via 504 can be etched in one step.
[0075] To gain a clearer understanding of the semiconductor device and its fabrication method provided in this application, the following describes the specific fabrication process using the semiconductor device, which includes a first transistor structure 1 and a second transistor structure 2 stacked from bottom to top.
[0076] like Figure 4 As shown in ab, a substrate 100 is first provided, on which a well region is formed and a semiconductor layer 1-208 having a first transistor structure 1 is formed. An oxide layer (typically SiO2) is formed on the surface of the semiconductor layer 1-208. Figure 4 As shown in Figure cd, a hard mask is formed on the oxide layer surface, and a dummy gate is formed by photolithography. As shown in Figure ef, sidewalls are formed, and ion implantation is performed to form the source region (the aforementioned source structure 202) and the drain region (the aforementioned drain structure 204). Figure 4 As shown in gh, an etching barrier layer is deposited, and a planarization layer is formed above the etching protection layer 300. For example... Figure 4As shown in Figure ij, planarization is performed, and dummy gates are removed. After dummy gate removal, a metal layer is deposited. Figure 4 As shown in kl, the metal layer is etched to form the gate metal layer (the aforementioned gate structure 206), and an oxide layer is formed covering the gate metal layer and the etch protection layer 300. As... Figure 4 As shown in Figure mn, the semiconductor layer 2-208 of the second transistor structure 2 is formed above the first dielectric layer 402 using oxide bonding. It should be noted that oxide-silicon bonding can also be used to form the semiconductor layer 2-208 above the first dielectric layer 402. If oxide bonding is used, the first dielectric layer 402 includes both the oxide layer covering the gate metal layer and the etch protection layer 300, and the subsequently bonded oxide layer; if oxide-silicon bonding is used, the first dielectric layer 402 only includes the oxide layer covering the gate metal layer and the etch protection layer 300.
[0077] like Figure 4 As shown in OV, the fabrication process of the first transistor structure 1 is then repeated, and a second transistor structure 2 is formed above the first dielectric layer 402. The difference is that the second transistor structure 2 exposes the area used to set the via 500 of the first transistor structure 1 (e.g., Figure 4 (as shown in t). Figure 4 As shown in wz, a photoresist layer 600 is formed above the second dielectric layer 404, and a first via 502 is formed by etching in one step. The photoresist layer 600 is then removed, and a second via 504 is formed by etching in one step. Finally, a metal interconnect 506 is formed in the via 500, forming a structure as shown in wz. Figure 1 The semiconductor device shown.
[0078] It should be noted that, in order to ensure complete etching in each etching process, a certain amount of over-etching can be set when etching to form the first via 502 and the second via 504. Although a certain amount of over-etching is set, since the etching selectivity of the etch protection layer 300 is less than that of the dielectric layer 400, but greater than that of the source structure 202 and the drain structure 204, the loss of the structure below the first via 502 and the second via 504 is very small.
[0079] This application also provides an electronic device that includes the semiconductor device described in any of the above embodiments.
[0080] In summary, this application provides a semiconductor device, a fabrication method, and an electronic device. The semiconductor device includes a substrate, multiple transistor structures stacked on one side of the substrate within a dielectric layer, and an etch-protective layer covering the source and drain structures of the transistor structures. It also includes vias corresponding to the source and drain structures, respectively. The vias include a first via and a second via. The first via extends from the side of the dielectric layer away from the substrate to the etch-protective layer, and the second via penetrates the etch-protective layer, extending to the source and drain structures. The first and second vias are connected. Metal interconnects are formed within the vias to guide the source and drain structures. Thus, the first vias of each transistor structure are all located within the same film layer structure, and the second vias are all located within the same film layer structure. Furthermore, since the etching selectivity of the etch-protective layer is lower than that of the dielectric layer when etching to form the first via, the etching process stops when the etching rate decreases upon reaching the etch-protective layer. Therefore, the etch protection layer can act as an etch barrier layer for the first via, preventing damage to the source and drain structures when forming vias of different depths. The first via can be etched simultaneously in one go. Similarly, when etching to form the second via, the etch selectivity of the etch protection layer is higher than that of the source and drain structures. Therefore, during the etching of the second via, the etching rate will stop when reaching the source and drain structures, preventing damage to the source and drain structures. The second via can also be etched simultaneously in one go.
[0081] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on its differences from other embodiments, and similar or identical parts between embodiments can be referred to interchangeably. For the apparatuses disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.
[0082] It should be noted that, in the description of this application, the terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component centrally located at the same time.
[0083] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.
[0084] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A semiconductor device, characterized in that, include: Substrate; A plurality of transistor structures are stacked sequentially from bottom to top on one side of the substrate, and an etch protection layer is provided on the side of the source structure and drain structure of the transistor structure away from the substrate. The etch protection layer covers the side of the source structure and the drain structure away from the substrate, respectively. The source structure and the drain structure are located on opposite sides of the gate structure of the transistor structure along a first direction, which is parallel to the plane of the substrate. A dielectric layer is located on one side of the substrate, and the transistor structure is located in the dielectric layer and is mutually insulated and isolated through the dielectric layer; The vias correspond to the source structure and the drain structure, respectively. The vias include a first via and a second via. The first via extends from the side of the dielectric layer away from the substrate to the etch protection layer. The second via penetrates the etch protection layer and extends to the source structure and the drain structure. The first via and the second via are connected. Metal interconnects are formed in the vias to bring out the source structure and the drain structure. When etching to form the via, the etching protection layer is used to achieve an etching selectivity lower than that of the dielectric layer, but higher than that of the source structure and the drain structure.
2. The semiconductor device according to claim 1, characterized in that, The material of the etched protective layer is an insulating material, and the dielectric constant of the material of the etched protective layer is less than a preset value.
3. The semiconductor device according to claim 2, characterized in that, The material of the etched protective layer is SiOC.
4. The semiconductor device according to claim 1, characterized in that, Along the second direction, the thickness of the etched protective layer ranges from 2nm to 100nm, including the endpoint values; The second direction is perpendicular to the plane in which the substrate is located.
5. The semiconductor device according to claim 1 or 4, characterized in that, Along the second direction, the thickness of the etched protective layer is equal.
6. The semiconductor device according to claim 1, characterized in that, The plurality of transistor structures include at least one of fin field-effect transistors and nanosheet ring gate field-effect transistors.
7. A method for fabricating a semiconductor device, characterized in that, For preparing the semiconductor device according to any one of claims 1-6, comprising: Provide a substrate; Multiple transistor structures are formed in a stacked manner from bottom to top on one side of the substrate. During the formation of each transistor structure, an etch protection layer is formed on the side of the source and drain structures of the transistor structure away from the substrate. The etch protection layer covers the side of the source and drain structures away from the substrate, respectively. The source and drain structures are located on opposite sides of the gate structure of the transistor structure along a first direction, which is parallel to the plane of the substrate. In the process of forming each of the transistor structures, a dielectric layer is also formed on one side of the substrate, the transistor structures are located in the dielectric layer and are mutually insulated and isolated by the dielectric layer; After forming the transistor structure and the dielectric layer, vias are formed corresponding to the source structure and the drain structure, respectively; wherein forming the vias includes: A first via is formed, the first via extending from the side of the dielectric layer away from the substrate to the etch protection layer; A second via is formed, which penetrates the etched protective layer and extends to the source structure and the drain structure, and the first via is connected to the second via; Metal interconnects are formed in the via to bring out the source structure and the drain structure. When etching to form the via, the etching protection layer is used to achieve an etching selectivity lower than that of the dielectric layer, but higher than that of the source structure and the drain structure.
8. The method for fabricating a semiconductor device according to claim 7, characterized in that, Forming the through hole includes: After the transistor structure and the dielectric layer are formed, and before the first via is formed, a photoresist layer is formed on the side of the dielectric layer away from the substrate; After the photoresist layer is exposed and developed, the dielectric layer is etched to form the first via. After forming the first via, the photoresist layer is removed, and the portion of the etch protection layer exposed in the first via is etched to form the second via.
9. The method for fabricating a semiconductor device according to claim 7, characterized in that, The plurality of transistor structures include a first transistor structure and a second transistor structure, and the plurality of transistor structures formed on one side of the substrate in a sequentially stacked manner from bottom to top include: The first transistor structure is formed on one side of the substrate, and the etching protection layer is formed thereon; A first dielectric layer is formed, which covers the first transistor structure and the etch protection layer on the side away from the substrate; The second transistor structure is formed on the side of the first dielectric layer away from the substrate, and the etching protection layer is formed thereon; A second dielectric layer is formed, which covers the second transistor structure and the etch protection layer on the side away from the substrate, and the second dielectric layer is in contact with the first dielectric layer; The first via corresponding to the first transistor structure extends sequentially through the second dielectric layer and the first dielectric layer to the etch protection layer of the first transistor structure, and the first via corresponding to the second transistor structure extends through the second dielectric layer to the etch protection layer of the second transistor structure.
10. An electronic device, characterized in that, Includes the semiconductor device according to any one of claims 1-6.