Semiconductor device

Abstract

A semiconductor device includes an active pattern including a channel region. The channel region is arranged between the first source / drain pattern and the second source / drain pattern spaced apart from each other in a first direction and between the second source / drain pattern spaced apart from each other in the first direction. The channel region is configured to connect the first source / drain patterns to each other and to connect the second source / drain patterns to each other. A gate electrode is disposed on a bottom surface of the active pattern and between the first source / drain patterns and between the second source / drain patterns. An upper interconnect line is disposed on a top surface of the active pattern opposite a bottom surface of the active pattern, and is connected to the first source / drain pattern.

Description

[0001] This application is a divisional application of the invention application filed on May 21, 2020, with application number 202010436421.4 and title "Semiconductor Device". Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0059390, filed on May 21, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including a field-effect transistor and a method for manufacturing the same. Background Technology

[0004] The demand for highly reliable, high-performance, and / or multifunctional semiconductor devices is increasing. The structural complexity and / or integration density of semiconductor devices have increased to meet these technical requirements. Summary of the Invention

[0005] An exemplary embodiment of the present invention provides a semiconductor device with high integration density and improved reliability.

[0006] According to an exemplary embodiment of the present invention, a semiconductor device includes an active pattern comprising a channel region. The channel region is disposed between a first source / drain pattern and a second source / drain pattern spaced apart from each other in a first direction. The channel region is configured to connect the first source / drain pattern and the second source / drain pattern to each other. A gate electrode is disposed on the bottom surface of the active pattern and is disposed between the first source / drain pattern and between the second source / drain pattern. An upper interconnect is disposed on the top surface of the active pattern opposite to the bottom surface of the active pattern and is connected to the first source / drain pattern.

[0007] According to an exemplary embodiment of the present invention, a semiconductor device includes a first source / drain pattern and a second source / drain pattern spaced apart from each other in a first direction. An active pattern is disposed between opposing sidewalls of the first and second source / drain patterns. A gate electrode is disposed on the bottom surface of the active pattern. An insulating layer is disposed on the top surface of the active pattern. An upper interconnect is disposed on the insulating layer and electrically connected to the first source / drain pattern. The first source / drain pattern includes a first portion adjacent to a side surface of the active pattern and a second portion extending from the first portion into the insulating layer. The maximum width of the first portion in the first direction is smaller than the maximum width of the second portion in the first direction.

[0008] According to an exemplary embodiment of the present invention, a semiconductor device includes a substrate comprising a PMOS region and an NMOS region. A plurality of first active regions are disposed on the PMOS region. The plurality of first active regions extend in a first direction. A plurality of second active regions are disposed on the NMOS region. The plurality of second active regions extend in the first direction. A gate electrode intersects the plurality of first active regions and the plurality of second active regions and extends in a second direction intersecting the first direction. A portion of the gate electrode is located between a bottom surface of the first active region and a top surface of the substrate. First source / drain patterns are spaced apart from each other in the first direction, and the gate electrode is located between them. The first source / drain patterns are connected to the plurality of first active regions. An upper interconnect is disposed on the top surface of the first active region opposite the bottom surface of the first active region. The upper interconnect is connected to at least a portion of the first source / drain patterns. Attached Figure Description

[0009] Exemplary embodiments will become clearer from the following brief description, taken in conjunction with the accompanying drawings. The drawings illustrate non-limiting exemplary embodiments as described herein.

[0010] Figure 1 This is a top plan view illustrating an exemplary embodiment of a semiconductor device according to a concept conceived in the present invention; Figures 2A to 2C These are exemplary embodiments of the present invention, respectively along Figure 1 Cross-sectional views taken from lines A-A', B-B', and C-C'; Figure 3 This illustrates an exemplary semiconductor device according to the concept of the present invention. Figure 1 A cross-sectional view taken by line A-A'; Figure 4A and Figure 4B This illustrates an exemplary semiconductor device according to the concept of the present invention. Figure 1 A cross-sectional view taken by line A-A'; Figure 5 This illustrates an exemplary semiconductor device according to the concept of the present invention. Figure 1 A cross-sectional view taken by line A-A'; Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 and Figure 16 This is a top plan view illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the concept of the present invention; Figure 7A , Figure 9A , Figure 11A , Figure 13A , Figure 15A and Figure 17A These are exemplary embodiments of the present invention, respectively along Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 and Figure 16 A cross-sectional view taken by line A-A'; Figure 7B , Figure 9B , Figure 11B , Figure 13B , Figure 15B and Figure 17B These are exemplary embodiments of the present invention, respectively along Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 and Figure 16 The cross-sectional view taken by line B-B'.

[0011] It should be noted that these figures are intended to illustrate the general characteristics of the methods, structures, and / or materials utilized in particular exemplary embodiments, and to supplement the written description provided below. However, these figures are not necessarily to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments, and should not be construed as limiting or restricting the range of values ​​or characteristics included through the exemplary embodiments. For example, for clarity, the relative thickness and positioning of molecules, layers, regions, and / or structural elements may be reduced or exaggerated. The use of similar or identical reference numerals in the various figures is intended to indicate the presence of similar or identical elements or features. Detailed Implementation

[0012] Exemplary embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments are illustrated.

[0013] Figure 1 This is a top plan view illustrating an exemplary embodiment of a semiconductor device according to a concept conceived in the present invention. Figures 2A to 2C These are exemplary embodiments of the present invention, respectively along Figure 1 The cross-sectional views taken from lines A-A', B-B', and C-C'.

[0014] Reference Figure 1 and Figures 2A to 2C The lower substrate 102 may include a p-channel metal-oxide-semiconductor field-effect transistor ("PMOSFET") region PR and an n-channel metal-oxide-semiconductor field-effect transistor ("NMOSFET") region NR. The lower substrate 102 may be a semiconductor substrate formed of or comprising silicon, germanium, or silicon-germanium, or a compound semiconductor substrate. For example, the lower substrate 102 may be a silicon wafer. However, exemplary embodiments of the inventive concept are not limited thereto.

[0015] In an exemplary embodiment, the PMOSFET region PR and the NMOSFET region NR may be logic cell regions on which logic transistors constituting logic circuits of a semiconductor device are formed. For example, logic transistors constituting a processor core or I / O terminals may be arranged on the logic cell regions of the lower substrate 102. The PMOSFET region PR and the NMOSFET region NR may include a number of logic transistors. The PMOSFET region PR and the NMOSFET region NR may be spaced apart from each other in a first direction D1. Each of the PMOSFET region PR and the NMOSFET region NR may extend in a second direction D2 perpendicular to the first direction D1.

[0016] Multiple active patterns AP1 and AP2 extending in the second direction D2 can be disposed on the PMOSFET region PR and the NMOSFET region NR. For example, as Figure 1 In the exemplary embodiment shown, active patterns AP1 and AP2 may include a first active pattern AP1 on a PMOSFET region PR and a second active pattern AP2 on an NMOSFET region NR. The first active pattern AP1 and the second active pattern AP2 may be disposed on the top surface of the lower substrate 102 (e.g., on a third direction D3) and may have fin-shaped structures protruding on a third direction D3 perpendicular to the top surface of the lower substrate 102. Each of the first active pattern AP1 and the second active pattern AP2 may include a bottom surface APb facing the top surface of the lower substrate 102 and a top surface APa (e.g., on a third direction D3) opposite the bottom surface APb.

[0017] In this specification, for ease of description, spatial relative terms such as "below," "under," "lower," "bottom," "top," "above," and "above" are used to describe the relationship between one element or feature shown in the accompanying drawings and another element or feature. It should be understood that spatial relative terms are intended to cover different orientations of the device other than those shown in the figures during use or operation. For example, as... Figures 6 to 11B As shown, if the device in the figure is inverted, elements described as "below other elements" or "below other elements" will therefore be oriented "above other elements or features." Thus, the exemplary term "below" can encompass both orientations of "above" and "below." Similarly, a semiconductor extending in a first direction D1 can be rotated to change its orientation to a second direction D2, a third direction D3, etc. Semiconductor devices according to exemplary embodiments of the present invention can be oriented in other directions, and the spatial relative descriptive terms used herein are interpreted accordingly.

[0018] Gate electrodes GE may intersect with the first active pattern AP1 and the second active pattern AP2 and extend in the first direction D1. Gate electrodes GE may be spaced apart from each other in the second direction D2. When viewed in plan view, gate electrodes GE may overlap with channel regions CH1. Each of the gate electrodes GE may be arranged to face the bottom surface of each of the channel regions CH and the two side surfaces of each of the channel regions, which are opposite each other and extend in the third direction D3 and are spaced apart in the first direction D1 (see...). Figure 2C For example, the gate electrode GE may be formed of or include at least one of a conductive metal nitride (e.g., titanium nitride or tantalum nitride) or a metallic material (e.g., titanium, tantalum, tungsten, copper, or aluminum). However, exemplary embodiments of the inventive concept are not limited thereto. A portion of the gate electrode GE may be located between the bottom surface APb of the first active pattern AP1 and the second active pattern AP2 and the top surface of the lower substrate 102 (e.g., spaced apart in a third direction D3 between them), as... Figure 2A As shown. Furthermore, the uppermost surface of the gate electrode GE can be located at a horizontal height not higher than the top surface APa of the first active pattern AP1 and the second active pattern AP2. For example, the distance between the top surface of the lower substrate 102 and the uppermost surface of the gate electrode (e.g., on the third direction D3) can be less than or equal to the distance between the top surface of the lower substrate 102 and the top surface APa of the first active pattern AP1 and the second active pattern AP2 (e.g., on the third direction D3).

[0019] A pair of gate spacers GS may be disposed on two opposing sidewalls of each of the gate electrodes GE. The gate spacers GS may extend along the gate electrode GE in a first direction D1. The bottom surface of the gate spacers GS may be located at a horizontal height below the bottom surface of the gate electrode GE. For example, the distance between the top surface of the lower substrate 102 and the bottom surface of the gate spacers GS (e.g., in a third direction D3) may be less than the distance between the top surface of the lower substrate 102 and the bottom surface of the gate electrode GE (e.g., in a third direction D3). The bottom surface of the gate spacers GS may be coplanar with the bottom surface of the first lower insulating layer 112, which will be described below. The gate spacers GS may be formed of or include at least one of SiCN, SiCON, and SiN. In an exemplary embodiment, the gate spacers GS may have a multilayer structure comprising at least two layers, each layer being made of SiCN, SiCON, or SiN. However, exemplary embodiments of the inventive concept are not limited thereto.

[0020] A gate dielectric pattern GI may be located between a gate electrode GE and a first active pattern AP1 and a second active pattern AP2. Each of the gate dielectric patterns GI may extend along the top surface of a corresponding gate electrode GE (e.g., in a third direction D3). Each of the gate dielectric patterns GI may (e.g., in a third direction D3) cover the bottom surface and two side surfaces of each of the channel regions CH1, which extend in the third direction D3 and are spaced apart in a first direction D1. The gate dielectric pattern GI may be formed of or comprise at least one high-k dielectric material. Examples of high-k dielectric materials may include at least one selected from the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. However, exemplary embodiments of the inventive concept are not limited thereto.

[0021] A gate cap pattern GP may be disposed (e.g., on a third direction D3) on the bottom surface of each of the gate electrodes GE. The gate cap pattern GP may extend along the gate electrode GE in a first direction D1. The gate cap pattern GP may comprise a material having etch selectivity relative to the first lower insulating layer 112 and the second lower insulating layer 114, which will be described below. For example, the gate cap pattern GP may be formed of or include at least one of SiON, SiCN, SiCON, and SiN. However, exemplary embodiments of the inventive concept are not limited thereto.

[0022] A first source / drain pattern SD1 may be disposed on a side surface of a first active pattern AP1. The first source / drain pattern SD1 may include impurities of a first conductivity type (e.g., p-type). A first channel region CH1 may be located between a pair of first source / drain patterns SD1. A second source / drain pattern SD2 may be disposed on a side surface of a second active pattern AP2. The second source / drain pattern SD2 may include impurities of a second conductivity type (e.g., n-type). A second channel region CH2 may be located between a pair of second source / drain patterns SD2.

[0023] The first source / drain pattern SD1 and the second source / drain pattern SD2 can be epitaxial patterns formed by a selective epitaxial growth process. The bottom surfaces of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be disposed at a horizontal height lower than the bottom surfaces of the first channel region CH1 and the second channel region CH2. For example, the distance between the top surface of the lower substrate 102 and the bottom surfaces of the first source / drain pattern SD1 and the second source / drain pattern SD2 (e.g., on the third direction D3) can be less than the distance between the top surface of the lower substrate 102 and the bottom surfaces of the first channel region CH1 and the second channel region CH2 (e.g., on the third direction D3). The first source / drain pattern SD1 and the second source / drain pattern SD2 can have a top surface disposed at a higher horizontal height than the top surfaces of the first channel region CH1 and the second channel region CH2. For example, the distance between the top surface of the lower substrate 102 and the top surfaces of the first source / drain pattern SD1 and the second source / drain pattern SD2 (e.g., on the third direction D3) may be greater than the distance between the top surface of the lower substrate 102 and the top surfaces of the first channel region CH1 and the second channel region CH2 (e.g., on the third direction D3). The first source / drain pattern SD1 may comprise a semiconductor material (e.g., SiGe) with a lattice constant greater than that of the lower substrate 102. In this exemplary embodiment, the first source / drain pattern SD1 may apply compressive stress to the first channel region CH1. In an exemplary embodiment, the second source / drain pattern SD2 may comprise the same semiconductor material as the material of the lower substrate 102 (e.g., Si).

[0024] The first source / drain pattern SD1 may penetrate the first upper insulating layer 120, which will be described below, and may extend to cover a portion of the top surface of the first upper insulating layer 120. Each of the first source / drain patterns SD1 may include a first portion SDB and a second portion SDE extending from the first portion SDB (e.g., in the third direction D3). The first portion SDB of the first source / drain pattern SD1 may be disposed between opposing sidewalls of the first active pattern AP1 (e.g., in the second direction D2). The second portion SDE of the first source / drain pattern SD1 may be located at a vertical horizontal height higher than the top surface APa of the first active pattern AP1. For example, the distance between the top surface of the lower substrate 102 and the second portion SDE of the first source / drain pattern SD1 (e.g., in the third direction D3) may be greater than the distance between the top surface of the lower substrate 102 and the top surface APa of the first active pattern AP1 (e.g., in the third direction D3). Figure 2AAs shown, the maximum width W2 of the second portion SDE of the first source / drain pattern SD1 (e.g., its length in the second direction D2) can be greater than the maximum width W1 of the first portion SDB of the first source / drain pattern SD1 (e.g., its length in the second direction D2). For example, the first source / drain pattern SD1 can have a maximum width at a horizontal height higher than the top surface APa of the first active pattern AP1 (e.g., in the third direction D3).

[0025] The first upper insulating layer 120, the second upper insulating layer 122, and the third upper insulating layer 124 may be stacked sequentially on the top surface APa of the first active pattern AP1. For example, as Figure 2A As shown, the second upper insulating layer 122 (e.g., on the third direction D3) can be directly disposed on the top surface of the first upper insulating layer 120. The third upper insulating layer 124 (e.g., on the third direction D3) can be directly disposed on the top surface of the second upper insulating layer 122.

[0026] Each of the first to third upper insulating layers 120, 122, and 124 may include a silicon oxide layer or a silicon oxynitride layer. However, exemplary embodiments of the present invention are not limited thereto.

[0027] The upper contact UAC can pass through the second upper insulating layer 122 and can be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2. The upper contact UAC may have a strip pattern extending in the first direction D1. For example, as Figure 2A In the exemplary embodiment shown, the upper contact UAC (e.g., on the third direction D3) may be directly disposed on the top surface of the second portion SDE of the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0028] The first upper interconnect POR1, the second upper interconnect POR2, and the upper via UV can be disposed in the third upper insulating layer 124. For example, as Figure 2AAs shown, the bottom surface of the upper via UV (e.g., on third-direction D3) can directly contact the top surface of the upper contact UAC (e.g., on third-direction D3). The bottom surface of the first upper interconnect POR1 can contact the top surface of the upper via UV. The upper via UV can connect the first upper interconnect POR1 and the second upper interconnect POR2 to the upper contact UAC. The first upper interconnect POR1 and the second upper interconnect POR2 can be power rails, such as embedded power rails. For example, the first upper interconnect POR1 and the second upper interconnect POR2 can be supplied with a power supply voltage or a ground voltage. The first upper interconnect POR1 can be connected to at least one of the first source / drain patterns SD1 via the upper via UV. The second upper interconnect POR2 can be connected to at least one of the second source / drain patterns SD2 via the upper via UV. The first upper interconnect POR1 can be used to apply a power supply voltage to the first source / drain pattern SD1, and the second upper interconnect POR2 can be used to apply a ground voltage to the second source / drain pattern SD2.

[0029] First upper interconnect POR1 and second upper interconnect POR2 may extend in the second direction D2. The width of the first upper interconnect POR1 (e.g., its length in the first direction D1) may be greater than the width of the first active pattern AP1 (e.g., its length in the first direction D1). When viewed in a plan view, the first upper interconnect POR1 (e.g., in the third direction D3) may at least partially overlap with each of the first source / drain patterns SD1 disposed thereunder. Similarly, the width of the second upper interconnect POR2 (e.g., its length in the first direction D1) may be greater than the width of the second active pattern AP2 (e.g., its length in the first direction D1). When viewed in a plan view, the second upper interconnect POR2 (e.g., in the third direction D3) may at least partially overlap with each of the second source / drain patterns SD2 disposed thereunder.

[0030] The first lower insulating layer 112, the second lower insulating layer 114, and the third lower insulating layer 116 can be arranged between the first active pattern AP1 and the second active pattern AP2 and the lower substrate 102.

[0031] A first lower insulating layer 112 may be disposed on the bottom surface APb of the first active pattern AP1 and the second active pattern AP2. For example, the top surface of the first lower insulating layer 112 (e.g., on the third direction D3) may be directly disposed on the bottom surface APb of the first active pattern AP1 and the second active pattern AP2. The first lower insulating layer 112 may cover the gate spacer GS and the first source / drain pattern SD1 and the second source / drain pattern SD2. The bottom surface of the first lower insulating layer 112 (e.g., on the third direction D3) may be substantially coplanar with the bottom surface of the gate cap pattern GP and the bottom surface of the gate spacer GS. A second lower insulating layer 114 may be formed on the bottom surface of the first lower insulating layer 112 and may cover the gate cap pattern GP. For example, the top surface of the second lower insulating layer 114 (e.g., on the third direction D3) may be directly disposed on the bottom surface of the first lower insulating layer 112. For example, the first lower insulating layer 112 and the second lower insulating layer 114 may include silicon oxide layers. However, exemplary embodiments of the inventive concept are not limited thereto.

[0032] The lower contact LAC may be arranged to pass through the first lower insulating layer 112 and the second lower insulating layer 114, and may be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2. For example, a contact hole may be formed in the first lower insulating layer 112 and the second lower insulating layer 114 to pass through the first lower insulating layer 112 and the second lower insulating layer 114 and expose the first source / drain pattern SD1 or the second source / drain pattern SD2. The lower contact LAC may be disposed in the contact hole. The lower contact LAC may be arranged between a pair of gate electrodes GE. The lower contact LAC may extend from a first portion SDB of the first source / drain pattern SD1 (e.g., on a third direction D3) to the bottom surface of the second lower insulating layer 114.

[0033] The lower interconnect LML and lower via LV can be disposed in the third lower insulating layer 116. For example, as Figure 2A In the exemplary embodiment shown, the bottom surface of the lower contact LAC (e.g., on the third direction D3) may be disposed on the top surface of the third lower insulating layer 116 and may directly contact the top surface of the third lower insulating layer 116. However, the exemplary embodiments of the inventive concept are not limited thereto. A lower via LV can connect the lower contact LAC to the lower interconnect LML. For example, as Figure 2A As shown, the top surface of the lower via LV (e.g., on third-party D3) may contact the bottom surface of the lower contact LAC (e.g., on third-party D3). The top surface of the lower interconnect LML (e.g., on third-party D3) may contact the bottom surface of the lower via LV (e.g., on third-party D3).

[0034] like Figure 2CAs shown, the gate contact GC may be configured to pass through the second lower insulating layer 114 and the gate cap pattern GP, ​​and may be electrically connected to the gate electrode GE. In an exemplary embodiment, when viewed in a plan view, the gate contact GC may be arranged between the PMOSFET region PR and the NMOSET region NR. For example, the gate contact GC may be spaced apart from the PMOSFET region PR and the NMOSET region NR in a first direction D1. The gate contact GC may pass through the gate cap pattern GP and may contact the bottom surface of the gate electrode GE. The bottom surface of the gate contact GC (e.g., in a third direction D3) may be coplanar with the bottom surface of the second lower insulating layer 114 (e.g., in a third direction D3). Opposite to the direction in which the upper contacts UAC extend upward to the first upper interconnect POR1 and the second upper interconnect POR2, the gate contact GC extends downward to the lower interconnect LML.

[0035] Figure 3 It is along the exemplary embodiment of the concept of the present invention. Figure 1 A cross-sectional view taken from line A-A'.

[0036] Reference Figure 3 ,and Figure 2A The exemplary embodiments shown are different. Figure 3 An exemplary embodiment includes a first active pattern AP1, the top surface of which is located at a horizontal height above the interface between a first portion SDB and a second portion SDE of the first source / drain pattern SD1. For example, the distance between the top surface of the lower substrate 102 (e.g., on a third-direction D3) and the top surface of the first active pattern AP1 (e.g., on a third-direction D3) is greater than the distance between the top surface of the lower substrate and the interface between the first portion SDB and the second portion SDE of the first source / drain pattern SD1.

[0037] Figure 4A and Figure 4B This illustrates an exemplary semiconductor device according to the concept of the present invention. Figure 1 A cross-sectional view taken from line A-A'.

[0038] Reference Figure 4AThe second portion SDE of the first source / drain pattern SD1 may include a first member SDE-1 and a second member SDE-2 spaced apart from each other in the first direction D1. Each of the first member SDE-1 and the second member SDE-2 may pass through the first upper insulating layer 120 and may be connected to the first portion SDB of the first source / drain pattern SD1. Some portions of the first member SDE-1 and the second member SDE-2 passing through the second portion SDE of the first upper insulating layer 120 may have a narrower width (e.g., a shorter length in the first direction D1) than the portions of the first member SDE-1 and the second member SDE-2 disposed above the first upper insulating layer 120.

[0039] Reference Figure 4B In the exemplary embodiment shown, the second portion SDE of the first source / drain pattern SD1 can be connected to the first portion SDB of the first source / drain pattern SD1 through an opening formed in the first upper insulating layer 120. Therefore, the first portion SDB and the second portion SDE of the first source / drain pattern SD1 can be seamlessly connected to each other without the first upper insulating layer 120 or the first lower insulating layer 112 between them.

[0040] Figure 5 This illustrates an exemplary semiconductor device according to the concept of the present invention. Figure 1 A cross-sectional view taken from line A-A'.

[0041] Reference Figure 5 A semiconductor device according to an exemplary embodiment of the present invention may have a gate-all-around structure. For example, a first active pattern AP1 may include a plurality of channel regions CHP between adjacent first source-drain patterns SD1. The channel regions CHP may be stacked and vertically spaced apart from each other. An insulating pattern ILL may be located between the first source-drain pattern SD1 and the gate electrode GE. The insulating pattern ILL may be located between the channel regions CHP. The insulating pattern ILL may electrically isolate the gate electrode GE from the first source-drain pattern SD1.

[0042] Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 and Figure 16 This is a top plan view illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. Figure 7A , Figure 9A , Figure 11A , Figure 13A , Figure 15A and Figure 17A They are along Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 and Figure 16 A cross-sectional view taken from line A-A'. Figure 7B , Figure 9B , Figure 11B , Figure 13B , Figure 15B and Figure 17B They are along Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 and Figure 16 The cross-sectional view taken by line B-B'.

[0043] To facilitate the explanation of the method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention, Figures 6 to 11B The diagram shows a capsized shape of a semiconductor device. However, exemplary embodiments of the inventive concept are not limited thereto.

[0044] Reference Figure 6 , Figure 7A and Figure 7B A substrate 100 may be formed, comprising a first active pattern AP1 and a second active pattern AP2. The substrate 100 may include an etch stop layer ESL.

[0045] In an exemplary embodiment, an ion implantation process and / or an epitaxial growth process may be performed on the semiconductor layer to form an etch stop layer (ESL). A substrate 100 including the etch stop layer (ESL) can then be formed by growing a semiconductor layer on the ESL. In an exemplary embodiment, the substrate 100 may be formed of or include silicon and silicon germanium. However, exemplary embodiments of the present invention are not limited thereto.

[0046] The substrate 100, including the etch stop layer ESL, can be patterned to form a first active pattern AP1 and a second active pattern AP2. The etch stop layer ESL may be located below the first active pattern AP1 and the second active pattern AP2.

[0047] A device isolation layer ST may be formed on the substrate 100 to fill the gap region between the first active pattern AP1 and the second active pattern AP2. The device isolation layer ST may be formed of or comprise an insulating material such as silicon oxide. However, exemplary embodiments of the inventive concept are not limited thereto.

[0048] Reference Figure 8 , Figure 9A and Figure 9B The first source / drain pattern SD1, the second source / drain pattern SD2, and the gate structure GST can be formed on the first active pattern AP1.

[0049] For example, the first portion SDB of the first source / drain pattern SD1 can be formed on the first active pattern AP1. Figure 9A In the exemplary embodiment shown, the first portion SDB of the first source / drain pattern SD1 can be directly formed on the first active pattern AP1. The first portion SDB of the second source / drain pattern SD2 can be formed on the second active pattern AP2. For example, the first portion SDB of the second source / drain pattern SD2 can be directly formed on the second active pattern AP2. The first portion SDB of the first source / drain pattern SD1 can be doped with a p-type impurity, and the first portion SDB of the second source / drain pattern SD2 can be doped with an n-type impurity. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in other exemplary embodiments, the first portion SDB of the first source / drain pattern SD1 can be doped with an n-type impurity, and the first portion SDB of the second source / drain pattern SD2 can be doped with a p-type impurity.

[0050] The first portion SDB of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be an epitaxial pattern formed by a selective epitaxial growth process. For example, the first active pattern AP1 and the second active pattern AP2 can be partially recessed. Subsequently, an epitaxial growth process can be performed on the recessed portions of the first active pattern AP1 and the second active pattern AP2. The first lower insulating layer 112 can be formed to cover the first portion SDB of the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0051] Then, the gate electrode GE can be formed to intersect with the first active pattern AP1 and the second active pattern AP2, and extend in the first direction D1. A gate dielectric pattern GI can be formed between the gate electrode GE and the first active pattern AP1 and the second active pattern AP2, respectively. A gate spacer GS can be formed on both side surfaces of each of the gate electrodes GE. A gate capping pattern GP can be formed on the gate electrode GE, respectively.

[0052] Reference Figure 10 , Figure 11A and Figure 11B A lower interconnect LML can be formed to electrically connect to a first portion SDB of the first source / drain pattern SD1 and the second source / drain pattern SD2. For example, a second lower insulating layer 114 can be formed on the first lower insulating layer 112. A lower contact LAC can be formed through the first lower insulating layer 112 and the second lower insulating layer 114 and can be coupled to the first portion SDB of the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0053] A third lower insulating layer 116 may be formed on the second lower insulating layer 114. For example, the bottom surface of the third lower insulating layer 116 may be formed directly on the top surface of the second lower insulating layer 114. The lower interconnect LML and the lower via LV connecting the lower interconnect LML to the lower contact LAC may be formed in the third lower insulating layer 116.

[0054] Reference Figure 12 , Figure 13A and Figure 13B A lower substrate 102 can be formed. A wafer bonding process can be performed such that the bottom surface of the third lower insulating layer 116 (e.g., on the third-direction D3) faces the top surface of the lower substrate 102. The lower substrate 102 can be a carrier substrate or an interconnect substrate. In an exemplary embodiment in which the lower substrate 102 is an interconnect substrate, interconnects in the lower substrate 102 can be electrically connected to lower interconnects LML.

[0055] Reference Figure 14 , Figure 15A and Figure 15B A portion of the substrate 100 can be removed to expose a first portion of the first source / drain pattern SD1 and the second source / drain pattern SD2, namely the first portion SDB.

[0056] For example, partial removal of substrate 100 may include: performing an etching process to expose an etch stop layer ESL; and performing a CMP process to expose the top surface of a first portion of the first source / drain pattern SD1 and the second source / drain pattern SD2, namely the top surface of the first portion of the first source / drain pattern SD1.

[0057] In an exemplary embodiment, as a result of partially removing the substrate 100, the first active pattern AP1 can be divided into a plurality of patterns arranged in the second direction D2. For example, as Figure 15A As shown, a first active pattern AP1, including a channel region CH1, can be arranged between the opposite sidewalls of the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0058] Reference Figure 16 , Figure 17A and Figure 17BThe second portion SDE of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be formed on the first portion SDB of the first source / drain pattern SD1 and the second source / drain pattern SD2. For example, the bottom surface (e.g., on a third-direction D3) of the second portion SDE of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be directly formed on the top surface (e.g., on a third-direction D3) of the first source / drain pattern SD1 and the second source / drain pattern SD2. The second portion SDE of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be an epitaxial pattern grown from the first portion SDB of the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0059] For example, a first upper insulating layer 120 may be formed on a first active pattern AP1 and a second active pattern AP2, as well as a first source / drain pattern SD1 and a second source / drain pattern SD2. A patterning process may then be performed on the first upper insulating layer 120 to form openings exposing the top surfaces of a first portion SDB of the first source / drain pattern SD1 and the second source / drain pattern SD2. Next, an epitaxial growth process may be performed to form a second portion SDE of the first source / drain pattern SD1 and the second source / drain pattern SD2. An epitaxial growth process may be performed such that the width W2 of the second portion SDE of the first source / drain pattern SD1 and the second source / drain pattern SD2 is greater than the width W1 of the first portion SDB of the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0060] Return to reference Figure 1 , Figure 2A and Figure 2B A second upper insulating layer 122 may be formed on the first upper insulating layer 120. For example, the bottom surface of the second upper insulating layer 122 (e.g., on a third direction D3) may be disposed directly on the top surface of the first upper insulating layer 120. An upper contact UAC may be formed through the second upper insulating layer 122. The upper contact UAC may be coupled to a second portion SDE of the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively.

[0061] A third upper insulating layer 124 may be formed on the second upper insulating layer 122 to cover the upper contact UAC. A first upper interconnect POR1 and a second upper interconnect POR2, as well as an upper via UV, may be formed in the third upper insulating layer 124. The upper via UV may be configured to electrically connect the first upper interconnect POR1 and the second upper interconnect POR2 to at least one upper contact UAC.

[0062] In a semiconductor device according to an exemplary embodiment of the present invention, a power transmission network is stably formed on a second surface of a semiconductor substrate. As a result, the reliability and integration density of the semiconductor device can be increased.

[0063] While exemplary embodiments of the inventive concept have been specifically shown and described, one of those skilled in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: Electric rails; An insulating layer is disposed on the power rail; The first trench area is disposed on the insulating layer; The second channel area is located on top of the first channel area; A gate electrode is disposed on the first channel region and the second channel region; Source / drain, which is adjacent to the gate electrode; as well as A first via is disposed between the power rail and the source / drain, and electrically connects the source / drain and the power rail. A portion of the gate electrode is disposed between the first channel region and the second channel region.

2. The semiconductor device according to claim 1, wherein, The insulating layer extends between the first trench region and the power rail.

3. The semiconductor device according to claim 1, wherein, The source / drain extends through the insulating layer.

4. The semiconductor device according to claim 1, wherein, The first via directly contacts the power rail.

5. The semiconductor device according to claim 1, wherein, The insulating layer comprises silicon oxide or silicon oxynitride.

6. The semiconductor device according to claim 1, further comprising: Interconnects are disposed on the gate electrode; as well as A second via is disposed between the interconnect and the source / drain, and electrically connects the interconnect and the source / drain.

7. The semiconductor device according to claim 1, wherein, The semiconductor device has a gate-all-around structure.

8. A semiconductor device, comprising: Electric rails; The first trench area is located above the power rail; The second channel area is located above the first channel area; An insulating layer extends between the first trench region and the power rail; A gate electrode is located above the first channel region, the second channel region, and the insulating layer; The source / drain electrode is adjacent to the gate electrode and extends through the insulating layer; as well as The first via directly contacts the power rail and electrically connects the power rail to the source / drain. A portion of the gate electrode is disposed between the first channel region and the second channel region.

9. The semiconductor device according to claim 8, further comprising: The first contact is electrically connected to the source / drain and the first via.

10. The semiconductor device of claim 8, further comprising: Interconnects are disposed on the gate electrode; as well as A second via is disposed between the interconnect and the source / drain, and electrically connects the interconnect and the source / drain.

11. The semiconductor device according to claim 8, wherein, The semiconductor device has a gate-all-around structure.

12. A semiconductor device, comprising: Substrate; An active pattern is disposed on the substrate and includes a first channel region and a second channel region disposed on the first channel region; The first gate electrode intersects with the active pattern; The second gate electrode intersects with the active pattern; The source / drain is disposed between the first gate electrode and the second gate electrode; An insulating layer is disposed on the first gate electrode and the second gate electrode; Electric rails, which are mounted on the insulating layer; as well as A first via is disposed between the power rail and the source / drain, and electrically connects the source / drain and the power rail. A portion of the first gate electrode is disposed between the first channel region and the second channel region.

13. The semiconductor device of claim 12, further comprising: Interconnects disposed on the substrate; as well as A second via is disposed between the interconnect and the source / drain, and electrically connects the interconnect and the source / drain.

14. The semiconductor device of claim 13, further comprising: Upper contact element, which is coupled to the source / drain and the first via; as well as The lower contact is coupled to the source / drain and the second via.

15. The semiconductor device according to claim 12, wherein, The semiconductor device has a gate-all-around structure.

Images