Photoelectric synapse device based on LLTO ion gate and preparation method thereof

Abstract

The invention belongs to the technical field of semiconductors, and relates to a photoelectric synapse device based on an LLTO ion gate, which comprises a substrate, a bottom electrode, a gate medium, a channel, a source electrode and a drain electrode, the gate medium is made of lithium lanthanum titanate, and the channel is made of a two-dimensional semiconductor film. The photoelectric synapse device has the characteristic that volatile synapse and non-volatile synapse are adjustable, has a large storage window, a high switch ratio, anticlockwise transfer curve hysteresis, quick response and excellent stability, has synapse response to electricity and optics, can perform low-power-consumption operation, and has a wide application prospect. The method is one of ideal candidate device systems for advanced electronic devices and neuromorphic calculation in the future.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a photoelectric synapse device based on an LLTO ion gate and its fabrication method. Background Technology

[0002] With the advent of the machine learning era, unstructured data is exploding, and traditional computing systems based on the von Neumann architecture have reached their limits in processing such massive amounts of data. Especially when dealing with complex problems requiring extensive information exchange, these traditional computing systems suffer from low efficiency and high energy consumption. Therefore, artificial neural networks, modeled after the brain's neural integration and signal processing, have attracted considerable interest. Artificial neural networks consist of a large number of artificial neurons and synapses, and synaptic devices that mimic the function of biological synapses are the most basic building blocks of artificial neural networks. Therefore, constructing efficient and multifunctional synaptic devices is crucial for the development of artificial neural networks.

[0003] Currently, the mainstream artificial synaptic devices are three-terminal synaptic devices, which include a gate electrode, a dielectric layer, a channel material, a source electrode, and a drain electrode. The selection of the channel material and dielectric layer is closely related to their performance. In previous studies, the selection of channel materials mainly included oxide materials and organic materials. For oxide materials, resistance control mainly occurs on the channel surface. To achieve effective resistance control, the channel material thickness needs to be relatively thin, which places high demands on the material growth process. Organic channel materials have defects such as physical and chemical instability, thus limiting their application. In addition, dielectric layers that can form an electrical double layer include solid electrolytes, ionic liquids, and ion gels. Solid electrolytes have been widely studied because they are compatible with flexible substrates, can be printed, and are compatible with monolithic integrated circuits. However, solid electrolytes have the disadvantage of low ion mobility, and there is still much room for improvement in the synaptic characteristics of synaptic devices made from them. Therefore, due to the limitations of dielectric layers and channel materials, three-terminal devices with excellent overall performance are very scarce. That is, it is difficult to ensure good performance in terms of on / off ratio and hysteresis while meeting low power consumption requirements.

[0004] Furthermore, current synaptic devices typically focus on a single signal output and a single timescale; for example, most can only achieve a single non-volatile synaptic function in response to electrical signals (i.e., long-term synaptic plasticity). This singularity makes synaptic devices unable to meet the diverse functional requirements of biological synapses, hindering the integration and optimization of neuromorphic chips. Integrating multimodal synaptic plasticity, including electronic, ionic, and photosensitive modes, is a feasible approach to improve the memory storage efficiency and processing capabilities of neuromorphic synaptic devices. For instance, the introduction of optical signals enables the visualization of stimulus responses in neuroscience, providing more dimensions of information for research.

[0005] Therefore, how to integrate multimodal synaptic plasticity and improve the overall performance of synaptic devices has become a technical problem that urgently needs to be solved in the process of simulating brain-like signal processing through artificial intelligence learning. Summary of the Invention

[0006] Based on this, the purpose of the present invention is to overcome the defects or deficiencies of the prior art and provide a photoelectric synapse device based on an LLTO ion gate and its fabrication method.

[0007] The present invention is achieved through the following technical solution: a photoelectric synaptic device based on an LLTO ion gate, comprising: a substrate, a bottom electrode, a gate dielectric, and a channel stacked sequentially, and a source electrode and a drain electrode spaced apart above the channel; the gate dielectric is made of lithium lanthanum titanate, and the channel is made of a two-dimensional semiconductor thin film.

[0008] Compared with existing technologies, the optoelectronic synaptic device described in this invention has the characteristics of adjustable volatile and non-volatile synapses, a large storage window, high on / off ratio, counterclockwise transfer curve hysteresis, fast response, excellent stability, and synaptic response to both electrical and optical aspects. It can also perform low-power operation, making it one of the ideal candidate device systems for future advanced electronic devices and neuromorphic computing.

[0009] In one embodiment, the thickness of the gate dielectric is 40-60 nm.

[0010] In one embodiment, the two-dimensional semiconductor thin film is WS2, MoTe2, MoS2 or ReS2.

[0011] In one embodiment, the bottom electrode includes a Cr electrode disposed on a substrate and an Au electrode disposed on the Cr electrode.

[0012] In one embodiment, the thickness of the Cr electrode is 3-7 nm, and the thickness of the Au electrode is 7-13 nm.

[0013] In one embodiment, the source electrode and the drain electrode are independently made of one or any combination of Cu, Al, Au, Ag, Mo, W, Ni, Fe, Zn and Pt, and the thickness of both the source electrode and the drain electrode is 30-70 nm.

[0014] In one embodiment, the bottom electrode is located directly below the portion of the channel not covered by the source electrode and the drain electrode.

[0015] The present invention also provides a method for fabricating the photoelectric synaptic device, comprising the following steps: S1, fabricating a bottom electrode on a substrate; S2, fabricating a gate dielectric on the bottom electrode; S3, fabricating a channel on the gate dielectric; S4, fabricating a source electrode and a drain electrode on the channel to obtain the photoelectric synaptic device.

[0016] In one embodiment, step S2 includes: forming a gate dielectric by magnetron sputtering lithium lanthanum titanate onto the bottom electrode.

[0017] In one embodiment, step S3 includes: preparing a two-dimensional semiconductor material using chemical vapor deposition and transferring it onto a gate dielectric using a dry or wet method.

[0018] To better understand and implement this invention, the following detailed description is provided in conjunction with the accompanying drawings. Attached Figure Description

[0019] Figure 1 This is a three-dimensional structural diagram of the photoelectric synaptic device based on the LLTO ion gate of the present invention.

[0020] Figure 2 for Figure 1 A schematic diagram of the structure of a photoelectric synapse device.

[0021] Figure 3 for Figure 1 XPS images of LLTO grid media.

[0022] Figure 4 for Figure 1 Raman characterization image of the MoS2 channel.

[0023] Figure 5 This is a schematic diagram of the ion modulation mechanism of the photoelectric synaptic device of the present invention, wherein, Figure 5 (A) represents the initial state without applied gate voltage. Figure 5 (B) represents the state where a positive voltage is applied to the bottom electrode. Figure 5 (C) represents the state in which a negative voltage is applied to the bottom electrode.

[0024] Figure 6(A) shows the electrical transport performance of the photoelectric synaptic device of the present invention, specifically the output characteristic curve.

[0025] Figure 6(B) shows the electrical transport performance of the photoelectric synaptic device of the present invention, specifically the transfer characteristic curve.

[0026] Figure 7 This invention relates to the synaptic function of the photoelectric synaptic device under different gate voltages.

[0027] Figure 8 The EPSC of the volatile synapse of the photoelectric synapse device of the present invention under stimulation of different pulse widths.

[0028] Figure 9(A) shows the volatile synaptic PPF characteristics of the photoelectric synaptic device of the present invention, specifically the change of EPSC with different pulse intervals under two consecutive identical excitations.

[0029] Figure 9(B) shows the volatile synaptic PPF characteristics of the photoelectric synaptic device of the present invention, specifically the relationship between the PPF index and the pulse interval time.

[0030] Figure 10(A) shows the long-term plasticity of the volatile synapse of the photoelectric synapse device of the present invention, specifically the effect of the number of pulses on the EPSC value.

[0031] Figure 10(B) shows the long-term plasticity of the volatile synapse of the photoelectric synapse device of the present invention, specifically the effect of continuous pulses on the EPSC value.

[0032] Figure 11(A) shows the EPSC variation under different electrical pulse widths in the non-volatile synapse of the photoelectric synapse device of the present invention.

[0033] Figure 11(B) shows the EPSC variation under different electrical pulse amplitude stimulations in the non-volatile synapse of the photoelectric synapse device of the present invention.

[0034] Figure 11(C) shows the EPSC change under a single enhanced pulse stimulation in the non-volatile synapse of the photoelectric synapse device of the present invention.

[0035] Figure 11(D) shows the EPSC change under a single inhibitory pulse stimulation in the non-volatile synapse of the photoelectric synapse device of the present invention.

[0036] Figure 12(A) shows the long-term plasticity of the non-volatile synapse of the photoelectric synapse device of the present invention, specifically the effect of the number of pulses on the EPSC value.

[0037] Figure 12(B) shows the long-term plasticity of the non-volatile synapse of the photoelectric synapse device of the present invention, specifically the effect of continuous pulses on the EPSC value.

[0038] Figure 13(A) shows the optical synaptic function of the photoelectric synaptic device of the present invention, specifically the effect of different light intensity stimulation duration on EPSC.

[0039] Figure 13(B) shows the optical synaptic function of the photoelectric synaptic device of the present invention, specifically the effect of different pulse intensities on EPSC.

[0040] Figure 13(C) shows the optical synaptic function of the photoelectric synaptic device of the present invention, specifically the effect of different numbers of light pulses on EPSC.

[0041] Figure 13(D) shows the optical synaptic function of the photoelectric synaptic device of the present invention, specifically the effect of continuous pulses on EPSC.

[0042] Figure 13(E) shows the optical synaptic function of the photoelectric synaptic device of the present invention, specifically the change in EPSC under a single enhanced pulse stimulation.

[0043] Figure 13(F) shows the optical synaptic function of the photoelectric synaptic device of the present invention, specifically the change in EPSC under a single inhibitory pulse stimulus. Detailed Implementation

[0044] This invention further explores the reasons for the limited synaptic plasticity and overall performance of existing three-terminal synaptic devices: Currently, typical three-terminal synaptic devices, such as electrolyte-gated transistors (EGTs, also known as electric double-layer transistors (EDLTS), mainly rely on pure electrostatic effects for operation. When a gate voltage is applied, cations or anions in the electrolyte accumulate on the surface of the charged electrode due to electrostatic attraction, thus forming an electric double layer (EDL) at the gate electrode-electrolyte interface, while simultaneously inducing another EDL at the electrolyte-channel material interface. To address the low ion mobility of solid electrolytes, existing technologies improve ion mobility by doping the solid electrolyte with salt. However, since this transistor relies solely on electrostatic effects, protons or ions quickly return to their equilibrium positions after the gate voltage is removed, resulting in a short relaxation time and making it difficult to effectively simulate non-volatile synapses. Moreover, devices relying solely on ion migration or interfacial charge accumulation mechanisms are susceptible to thermodynamic relaxation effects, leading to the decay of weighted information.

[0045] In terms of transistor performance, the pure electrostatic effect limits the penetration depth of the electric field formed by ion aggregation at the channel interface. In the on-state, carriers are confined to the surface, limiting the maximum conduction current; the off-state current mainly depends on the intrinsic carrier concentration of the channel material, and is difficult to further reduce due to factors such as material quality and fabrication process. Therefore, the on / off ratio of an EGT (typically 10-1) is limited. 3 ~10 6 Performance such as these is difficult to improve further.

[0046] Furthermore, this transistor typically employs a top-gate structure. In a top-gate structure, the channel is directly passivated by the dielectric layer, preventing contact with external air and thus offering better stability. Additionally, the low contact resistance between the channel layer and the source / drain electrodes is beneficial for improving the performance of the synaptic device. However, the top-gate electrode obscures the bottom gate material and the channel material, affecting the optical response characteristics of the channel material. Therefore, this places higher demands on the structure, material composition, and fabrication methods of both the top-gate electrode and the channel material. This not only increases cost but also limits the integration of multimode synapses due to the complex structure and cumbersome fabrication methods, ultimately impacting the overall performance improvement of the synaptic device.

[0047] Given the limitations of the pure electrostatic effect in improving the performance of EGT (Electrostatic Transistor), this invention proposes to enhance the performance of three-terminal synaptic devices through electrochemical doping modification via reduction-oxidation reactions. When a gate voltage is applied, ions are attracted to the surface of the channel or gate material, modulating the channel conductivity through electrostatic effects. Simultaneously, ions absorb or release electrons through redox reactions, altering the carrier concentration and distribution in the channel. Since the rate of redox reactions is typically slower than pure ion migration, the conductivity state of the channel material does not immediately disappear after the gate voltage is removed. This means the transistor can control the retention time and quantity of channel carriers by controlling the absorption and release of different numbers of electrons by ions on the channel and gate material surfaces, thereby controlling the device to achieve both volatile synapses (i.e., short-term synaptic plasticity, STP) and non-volatile synapses (i.e., long-term synaptic plasticity, LTP). Meanwhile, in order to improve the photoresponse and reduce the fabrication difficulty and cost, this invention considers screening materials for bottom-gate structure synaptic devices based on reduction-oxidation reactions, and further improving the overall performance of bottom-gate structure synaptic devices by optimizing the materials, thickness and fabrication process of each layer.

[0048] Based on the above concept, this invention screened solid electrolytes and found that lithium-ion solid electrolytes have good ionic conductivity, can provide channels for ions in the channel, have a lower on-state voltage drop than other gate dielectrics, and are stable with a long shelf life. Devices made from them have good operating performance and a lower operating voltage. Among lithium-ion solid electrolytes, lithium lanthanum carbonate (Li... 0.33 La 0.56 Lithium and titanium ions in TiO3 (LLTO) can be attracted to the surface of the channel or gate material under the influence of the gate voltage. During this process, titanium ions can undergo redox reactions, absorbing or releasing electrons (e.g., TiO3 in LLTO). 3+ Become Ti 4+ During the process, electrons can be released into the surrounding environment. Compared with other solid electrolytes, LLTO, as a perovskite-type lithium-ion solid electrolyte, has high room temperature ionic conductivity, excellent structure, insulation and thermal stability. As an ion gate, it helps to improve the overall performance of synaptic devices.

[0049] Furthermore, this invention discovers that two-dimensional semiconductor materials, such as BP (Black phosphorus) and TMD (Transition-metal dichalcogenides), possess tunable band gaps ranging from ~1 eV to ~2 eV, exhibiting the potential to generate photoresponse and making them ideal candidates for channel materials. Compared to oxide materials, organic materials, graphene, and other materials, two-dimensional semiconductor materials (MoTe2, WSe2, MoS2, or ReS2, etc.) demonstrate better chemical stability and environmental robustness at the interface with the electrolyte, making them suitable for long-term applications.

[0050] The ionic conductivity, capacitance, interfacial stability, mechanical flexibility, and environmental stability of electrolytes affect the physiological and chemical properties of the interface between two-dimensional semiconductor materials and electrolytes, thus influencing the performance of synaptic devices. Therefore, this invention screens two-dimensional semiconductor materials based on LLTO ion gates and finds that the N-type semiconductor material MoS2, used as a channel, can better control the electrons released by titanium ions. Regarding material thickness, different thicknesses of MoS2 affect the degree of interfacial coupling between it and the LLTO ion gate. A suitable thickness allows for smoother ion migration and reactions at the interface, thereby optimizing the performance of the synaptic device. Simultaneously, the thickness of the LLTO ion gate also affects its ion transport capability. Too thin a gate may result in insufficient ion transport channels, while too thick a gate may increase resistance to ion migration. A suitable thickness ensures efficient ion transport and good interaction with the MoS2 channel material. Furthermore, the thickness of MoS2 also affects its light absorption and response characteristics. Thinner MoS2 may have lower light absorption efficiency, while excessively thick MoS2 may increase light scattering within the material, reducing the sensitivity of the photoresponse. Besides affecting ion transport, the thickness of the LLTO ion gate also influences the overall mechanical properties and stability of the device. Excessive thickness may make the device more prone to cracking or delamination when bent or under stress. By optimizing the materials and thickness of the gate dielectric and channel, the synaptic device fabricated in this invention exhibits both electrical and optical synaptic responses.

[0051] However, in practical use, this invention found that the synaptic device is not sensitive enough to changes in gate voltage, making it difficult to accurately control the number of electrons absorbed and released by lithium ions, thus limiting the application of the synaptic device.

[0052] To improve the sensitivity of synaptic devices to voltage changes at the bottom gate electrode, this invention uses an Au electrode instead of the commonly used pure silicon electrode. The Au electrode has extremely high conductivity, effectively transmitting the gate voltage signal to the gate dielectric layer, thereby enabling the control of channel carriers. However, in bottom-gate structures, the adhesion between the Au electrode and the substrate is weak, making stable attachment of the bottom electrode difficult. Therefore, this invention adds a Cr electrode layer between the Au electrode and the substrate to form a Cr / Au composite electrode. The adhesion of the Cr electrode ensures a tight bond between the electrode and the substrate, providing a stable foundation for the Au electrode; the high conductivity of the Au electrode ensures efficient charge transport. The synergistic effect of these two elements allows the bottom electrode to effectively transmit the gate voltage signal to subsequent layers while maintaining stable attachment, providing a reliable electrical basis for the normal operation of the device.

[0053] To make the synaptic device more sensitive to voltage changes at the bottom electrode, this invention positions the source and drain electrodes at opposite ends of the channel above the channel, and positions the composite electrode directly below the portion of the channel not covered by the source and drain electrodes. In other words, the projections of the source, drain, and bottom electrodes in the horizontal plane do not overlap. This arrangement reduces mutual interference between electrodes, resulting in a more uniform electric field distribution and improved device sensitivity to voltage changes. Simultaneously, this arrangement also affects the device's heat dissipation performance; a well-designed layout helps dissipate heat effectively, preventing localized overheating from negatively impacting device performance.

[0054] The stability and performance of bottom-gate synaptic devices are generally lower than those of top-gate structures. To improve the performance of synaptic devices, this invention optimizes the fabrication process. First, this invention uses magnetron sputtering with radio frequency sputtering to fabricate LLTO ion gates, and by optimizing the fabrication conditions and the thickness of LLTO, the LLTO achieves a higher ionic conductivity (up to 6.06 × 10⁻⁶). -4 The large window and high on / off ratio transfer curve with counterclockwise hysteresis (S / cm) were achieved in the synaptic device, demonstrating that the device modulates carriers through ions. The large window and high on / off ratio provide the conditions for simulating synaptic function. The specific conditions for magnetron sputtering were: sputtering power of 80W, sputtering pressure of 0.5Pa, sputtering gas ratio of Ar:O2 = 70:30, and sputtering time of 2h. Among these, sputtering power affects the energy and number of sputtered particles. If the sputtering power is too low, it is difficult to form a dense film, resulting in more voids and defects in the film, which hinders ion migration. On the other hand, if the sputtering power is too high, it will damage the LLTO surface. The sputtering pressure determines the density of gas molecules during sputtering. Too low or too high pressure can easily lead to difficulty in forming a dense film and reduce ion migration ability. In the sputtering gas, an appropriate amount of oxygen can ensure the oxygen content in LLTO, maintain the stability of its crystal structure, optimize the oxygen vacancy concentration, and thus improve the ionic conductivity of LLTO.

[0055] Based on this, the present invention discovered that when the bottom electrode thickness is too thick, an excessive height difference will occur between the bottom electrode and the substrate, affecting the quality of the LLTO thin film sputtered by magnetron sputtering, and consequently impacting the performance of the entire synaptic device. However, if the bottom electrode is too thin, it may lead to excessive resistance, affecting charge transport efficiency. Furthermore, an excessively thin bottom electrode is easily damaged by high-power ion bombardment during magnetron sputtering, affecting its integrity and stability. In addition, the thickness of the Cr electrode affects its bonding strength with the substrate; too thin may result in weak bonding, while too thick may increase the overall resistance of the electrode, affecting charge transport efficiency. The thickness of the Au electrode not only affects conductivity but also the mechanical properties and corrosion resistance of the electrode. Too thin may lead to easy wear or corrosion during use, while too thick may increase costs without significantly improving device performance. Therefore, the present invention optimized the thickness of the Cr and Au electrodes, ultimately selecting a Cr thickness of 5 nm and an Au thickness of 10 nm.

[0056] Furthermore, current methods for preparing the channel material MoS2 in opto-synaptic devices typically involve mechanical exfoliation, followed by the use of optical microscopy to select target materials of uniform thickness and appropriate size to achieve better electron mobility. However, this preparation method is complex and difficult to scale up for mass production. Surprisingly, this invention reveals that after adjusting the structure, materials, and thickness as described above, the synaptic plasticity and performance of the opto-synaptic device are significantly improved. Even when using MoS2 grown by chemical vapor deposition (CVD) instead of mechanically exfoliated MoS2, the performance of the resulting opto-synaptic device still surpasses that of the traditional EGT, thus achieving a reduction in fabrication difficulty while improving the performance of the opto-synaptic device.

[0057] In summary, the opto-synaptic device of the present invention, based on its ability to be fabricated on a large scale and in batches, possesses the characteristics of adjustable volatile and non-volatile synapses, a large storage window, high on / off ratio, counterclockwise transfer curve hysteresis, fast response, excellent stability, and synaptic response to both electrical and optical aspects. It can also perform low-power operation, making it one of the ideal candidate device systems for future advanced electronic devices and neuromorphic computing.

[0058] The following describes the photoelectric synaptic device based on an LLTO ion gate and its fabrication method provided by the present invention, with reference to specific embodiments and accompanying drawings.

[0059] See Figure 1 and Figure 2 This embodiment provides a photoelectric synapse device based on an LLTO ion gate, including a substrate 1, a bottom electrode 2, a gate dielectric 3, a channel 4, and a source electrode 5 and a drain electrode 6 disposed at intervals on the side surface of the channel 4 away from the gate dielectric 3.

[0060] The substrate 1 includes a silicon layer 11 and a SiO2 oxide layer 12 disposed above the silicon layer 11, wherein the thickness of the SiO2 oxide layer 12 is 280-320 nm, preferably 285 nm-298 nm.

[0061] The bottom electrode 2 is a composite electrode, comprising a first electrode layer 21 disposed above the SiO2 oxide layer 12, and a second electrode layer 22 disposed above the first electrode layer 21. In this embodiment, the first electrode layer 21 is a Cr electrode with a thickness of 3-7 nm, preferably 5 nm, and the second electrode layer 22 is an Au electrode with a thickness of 7-13 nm, preferably 10 nm. Preferably, the bottom electrode 2 is disposed directly below the portion of the channel 4 not covered by the source electrode 5 and the drain electrode 6, i.e., the projections of the source electrode 5, the drain electrode 6, and the bottom electrode 2 on the horizontal plane do not overlap, and the source electrode 5 and the drain electrode 6 are respectively located at both ends of the bottom electrode 2.

[0062] The gate dielectric 3 is made of LLTO (Li 0.33 La 0.56 The TiO3 thin film, preferably, has a gate dielectric 3 thickness of 40-60 nm, more preferably 54 nm.

[0063] The channel 4 is made of a two-dimensional semiconductor thin film, which is WS2, MoTe2, MoS2 or ReS2, preferably a MoS2 thin film. The channel 4 is completely isolated from the bottom electrode 2 by the gate dielectric 3. The thickness of the channel 4 is preferably 1-10 nm, and the length is preferably 4-12 µm.

[0064] The source electrode 5 and drain electrode 6 are independently made of one or any composite metal selected from Cu, Al, Au, Ag, Mo, W, Ni, Fe, Zn, and Pt, with a thickness of 30-70 nm. In this embodiment, the source electrode 5 and drain electrode 6 are made of Au, with a thickness of 50 nm.

[0065] This embodiment also provides a method for fabricating the above-mentioned photoelectric synaptic device, including the following steps.

[0066] S0. Pretreatment of substrate 1: Substrate 1 was sequentially immersed in an appropriate amount of acetone, isopropanol, and water for ultrasonic cleaning for 10 minutes, then removed and dried. It was then treated with nitrogen-oxygen plasma for 10 minutes to improve the hydrophilicity of substrate 1. The thickness of the SiO2 oxide layer 12 on substrate 1 is 285 nm.

[0067] S1. Fabrication of the bottom electrode 2 on substrate 1: Cr electrode 21 and Au electrode 22 are fabricated on substrate 1 using processes such as ultraviolet lithography, development, vacuum metal evaporation, and lift-off. Specifically, the pattern of the bottom electrode 2 is defined on substrate 1 using photolithography. Subsequently, a Cr / Au composite electrode is deposited on the substrate using a vacuum evaporation deposition apparatus. The Cr electrode 21 is in contact with SiO2 below the Au electrode 22. Finally, the patterned bottom electrode 1 is obtained through a lift-off process. The thickness of the Cr electrode 21 is 5 nm, and the thickness of the Au electrode 22 is 10 nm.

[0068] S2. Preparing the gate dielectric 3 on the bottom electrode 2: An electrolyte target composed of Li2O, La2O3, and TiO2 is sputtered onto the bottom electrode 2 using magnetron sputtering radio frequency sputtering. The sputtering power is 80W, the sputtering pressure is 0.5Pa, the sputtering gas ratio is Ar:O2 = 70:30, and the sputtering time is 2h. The thickness is 54nm, and the elemental ratio of Li2O, La2O3, and TiO2 is 2~3%:50~60%:35~45%, preferably 2.54%:56.28%:41.18%. Figure 3 XPS images confirmed that the sputtered film in this embodiment was LLTO, and the ionic conductivity of the film was measured to be 6.06 × 10⁻⁶. -4 S / cm.

[0069] S3. A channel 4 is prepared on the gate dielectric 3, which includes step S31, preparation of a two-dimensional material thin film and step S32, transfer of the two-dimensional material thin film.

[0070] S31. Preparation of two-dimensional material thin films: MoS2 continuous thin films were grown on sapphire substrates using chemical vapor deposition (CVD). Figure 4 The Raman spectroscopy confirmed that the material obtained in this embodiment was MoS2.

[0071] S32. Transfer of Two-Dimensional Material Thin Films: A PMMA anisole solution was spin-coated onto a continuous MoS2 thin film and placed in high-purity water until the MoS2 / PMMA film was suspended on the surface of the pure water. The MoS2 was then transferred onto the gate dielectric 3, corresponding to the bottom electrode 2 of the target substrate 1. Next, the PMMA was cleaned with acetone solution, and a MoS2 channel mask pattern was fabricated using photolithography. Helium plasma was used to remove areas not protected by the photoresist. Finally, the sample was immersed in a PG propylene glycol solution to remove the photoresist, resulting in a patterned MoS2 conductive channel 4.

[0072] S4. Fabrication of source electrode 5 and drain electrode 6 above channel 4: Source electrode 5 and drain electrode 6 are fabricated on channel 4 using processes such as ultraviolet lithography, development, vacuum metal evaporation, and lift-off. Source electrode 5 covers the left edge above channel 4, is made of Au, and has a thickness of 50 nm. Drain electrode 6 covers the right edge above channel 4, is made of Au, and has a thickness of 50 nm. Specifically, the patterns of source electrode 5 and drain electrode 6 are fabricated above channel 4 using photolithography, Au electrodes are deposited on the substrate using a vacuum evaporation deposition apparatus, and then source electrode 5 and drain electrode 6 are obtained through a lift-off process.

[0073] The photoelectric synapse device is obtained through the above steps S1-S5. The device is a three-terminal transistor with the three ports being the source electrode 5, the drain electrode 6, and the bottom electrode 2 (i.e., the bottom gate electrode).

[0074] The working mechanism of the photoelectric synaptic device prepared in this embodiment is mainly to control the ion arrangement by applying different voltages. At the same time, during the voltage conversion process, the ions undergo redox reactions to change their valence state, thereby releasing more electrons and exhibiting synaptic behavior.

[0075] Firstly, in the initial state without applied gate voltage, the ion arrangement inside LLTO is disordered, such as... Figure 5 As shown in (A); when a positive voltage is applied to the bottom electrode, the cations inside LLTO near the bottom electrode are repelled and accumulate at the surface where MoS2 and LLTO meet. They can absorb the electrons migrating from MoS2, thus keeping the source-drain current in an off-state, as shown in (A). Figure 5 As shown in (B); when a negative voltage is applied to the bottom electrode, the cations near MoS2 inside LLTO are attracted and return to the surface where the bottom electrode contacts LLTO, while Ti... 3+ It undergoes an oxidation reaction to become Ti 4+ This releases a large number of electrons, increasing the current within MoS2, thereby enabling synaptic behavior, such as... Figure 5 As shown in (C); applying a positive voltage to the bottom electrode can make Ti 4+ It undergoes a reduction reaction to become Ti 3+ The device was restored to Figure 5 (B) State; After a period of time after the voltage is stopped from being applied to the bottom electrode, the device returns to its original state. Figure 5 (A) is the initial state.

[0076] The photoelectric synaptic device in this embodiment is a typical three-terminal transistor architecture, which relies on the absorption and release of electrons by ions to modulate the conductivity of the channel.

[0077] First, while maintaining the gate voltage V GS Within the range of -3V to 3V (in 1V increments), the source-drain voltage V DSBy gradually scanning from -1V to 1V (step size 0.01V), the output characteristic curves under different gate voltage regulation were obtained, as shown in Figure 6(A). The curves show that the channel contact resistance of the fabricated device is very small, close to that of an ohmic contact.

[0078] Then, while maintaining the source-drain voltage V DS Within the range of -0.5V to 0.5V (in 0.2V increments), the gate voltage V GS The transfer characteristic curve of the photoelectric synapse device was obtained by cyclic scanning from -5V to 5V (in 0.05V steps), as shown in Figure 6(B). The experimental results show that the hysteresis window of the device's transfer characteristic curve is large, indicating that it possesses the prerequisites for realizing non-volatile electronic synapse function. Simultaneously, its maximum switching current ratio reaches 10. 8 The level indicates that the LLTO has a good gate voltage regulation effect, and the off-state current reaches 10. -13 A, thereby achieving low power consumption.

[0079] If both volatile and non-volatile synaptic behaviors can be achieved simultaneously in a single device, the size and power consumption of artificial neural networks can be significantly reduced. Furthermore, the photoelectric synaptic device fabricated in this invention operates at a relatively low gate voltage (V0). GS With a gate voltage of <5V, volatile synaptic behavior can be achieved, and under higher gate voltage control (V GS With a voltage greater than 6V, non-volatile synaptic behavior can be achieved, such as... Figure 7 As shown in the diagram. The following sections will introduce volatile synapses and non-volatile synapses separately.

[0080] Firstly, for volatile synaptic function, electrical pulses of varying widths (50ms to 500ms) were applied to the bottom gate (amplitude -3V) to simulate EPSC under different pulse stimulation durations, such as... Figure 8 As shown, the EPSC value of this device increases with the increase of the pulse width, and then weakens with a large decreasing slope, which is consistent with the characteristics of STP.

[0081] Subsequently, two continuous electrical pulses with a width of 50 ms and an amplitude of -4 V were used as stimulation inputs to trigger the PPF behavior of the device. Figure 9(A) shows the variation of EPSC with different pulse intervals under two consecutive identical excitations. When the pulse interval is 100 ms, the amplitude of the second peak current is significantly greater than that of the first peak current. However, as the pulse interval increases, the difference in amplitude between the two peak currents gradually decreases, which is similar to the PPF behavior of biological synapses. The PPF exponent can be obtained according to the following formula:

[0082] A2 and A1 represent the amplitudes of the first and second EPSCs, respectively.

[0083] To better observe the attenuation changes of the device, a graph showing the relationship between the PPF exponent and the pulse interval time was plotted, as shown in Figure 9(B), and then fitted using a double exponential attenuation function:

[0084] Two time constants can be obtained, namely As shown by the red curve in Figure 9(B), the curve basically matches the distribution of the test scatter points, which indicates that the photoelectric synaptic device based on LLTO has similar characteristics to biological synapses in terms of PPF behavior.

[0085] Finally, to demonstrate that the volatile synaptic function achieved by the device fabricated in this invention can simulate the long-term synaptic plasticity similar to biological synapses, different numbers of negative voltage pulse sequences (pulse amplitude -4V, pulse width 50ms, pulse interval 50ms) were first applied to the device gate. The experimental results are shown in Figure 10(A). As the number of pulses increases, the EPSC value of the device also increases, and the memory retention time of the device also becomes longer. Based on this, this invention simultaneously introduces LTP and LTD, applying 20 consecutive pulses to LTP and LTD respectively, with a pulse amplitude of ±4V. The results are shown in Figure 10(B). This indicates that the device meets the conditions for the STP to LTP transition, and this enhancement / inhibition characteristic contributes to the high-precision recognition function of artificial neural networks.

[0086] To demonstrate non-volatile synaptic behavior, electrical pulses of varying widths (50 ms to 500 ms) were first applied to the bottom gate (pulse amplitude -6 V) to simulate EPSC under different pulse stimulation durations. Then, electrical pulses of varying amplitudes (-6 V to -10 V) were applied to the bottom gate (pulse width 50 ms) to simulate EPSC under different pulse intensities, as shown in Figures 11(A) and 11(B). As the pulse width or pulse amplitude increased, the EPSC value of the device also increased, but subsequently decreased with a small decreasing slope and stabilized after a period of time, consistent with the characteristics of LTP. To further demonstrate the existence of LTP, the single-pulse retention of the device was verified, as shown in Figures 11(C) and 11(D). Pulses with a pulse width of 500 ms and pulse amplitudes of +13 V and -13 V were applied to the device, respectively, and current monitoring was performed continuously for one hour. It was found that the EPSC exhibited good stability in both enhanced and suppressed states.

[0087] Similar to volatile synaptic behavior, non-volatile synaptic behavior also requires multiple consecutive pulses to demonstrate long-term plasticity. First, different numbers of negative voltage pulse sequences (pulse amplitude -6V, pulse width 50ms, pulse interval 50ms) were applied to the device gate. The results are shown in Figure 12(A). As the number of pulses increases, the EPSC value of the device also increases, and the memory retention state of the device also varies. This is similar to the effect expressed by biological neurons forming different levels of memory strength through multiple stimulations. Based on this, we simultaneously introduced LTP and LTD, applying 20 consecutive pulses to LTP and LTD respectively, with pulse amplitudes of -6V and +7V. The results are shown in Figure 12(B). As can be seen from the image, the device maintains good stability from the stimulation pulse to the memory erasure pulse, consistent with the characteristics of biological synapses learning and forgetting through stimulation.

[0088] Similar to electricity, if a device can generate photogenerated carriers through illumination and then modulate and respond to them, then it can be proven that the device can also be used as a photoresponsive device. To verify whether LLTO-based ion-controlled transistors can respond to illumination, a series of experiments were conducted.

[0089] First, the illumination wavelength was set to 532nm, and the device surface was illuminated with light intensities of varying pulse widths (100ms to 600ms) (illuminance of 15.5W / cm²). 2 ), to simulate EPSC under different light intensity stimulation durations, and then with different light intensities (13.8 W / cm²). 2 Up to 18.1 W / cm 2 An electrical pulse (with a pulse width of 100 ms) was applied to the bottom gate to simulate EPSC under stimulation of different pulse intensities. The results are shown in Figures 13(A) and 13(B). As can be seen from the images, the device fabricated in this embodiment is responsive to illumination and can achieve non-volatile synaptic behavior.

[0090] Similarly, as shown in Figures 13(C) and 13(D), different numbers of light pulses (pulse width 100ms, light intensity 15.5W / cm²) were applied to the device. 2 This demonstrates that the device can achieve different memory retention states by varying the number of light exposures, thus enabling its application in multi-level memory storage. Based on this, we simultaneously introduced 20 light pulses and 20 electrical pulses for modulation (pulse width 100ms, light intensity 15.5W / cm²). 2 (The voltage amplitude is 7V). The images demonstrate that the device fabricated in this embodiment still exhibits good stability for optical synapses.

[0091] Finally, as shown in Figures 13(E) and 13(F), pulses with a width of 500 ms and an intensity of 19.8 W / cm² were applied to the device. 2 Using a 15V voltage pulse and continuous current monitoring for one hour, it was found that the EPSC exhibited good stability in both enhanced and suppressed states. Further evidence demonstrates that the device can also achieve relatively stable non-volatile synaptic behavior under illumination.

[0092] In summary, the photoelectric synapse device provided by this invention has the following advantages: (1) Photosynaptic devices have a large storage window (intact hysteresis from start voltage to end voltage) and a high switching ratio (10). 8 It has advantages such as counterclockwise transfer curve hysteresis, fast response, excellent stability, and high durability.

[0093] (2) Photoelectric synaptic devices have the characteristics of tunable volatile and non-volatile synapses, that is, by applying different gate voltages, ions inside LLTO can absorb and release different numbers of electrons.

[0094] (3) Photoelectric synaptic devices have synaptic responses to both electrical and optical signals.

[0095] (4) The photoelectric synaptic device can perform low-power operation, with its off-state current reaching 10 -13 ~10 -12 A. A gate voltage of 2V is sufficient to regulate the channel carriers.

[0096] (5) The gate dielectric of the opto-synaptic device is manufactured by magnetron sputtering, and the channel material is grown by CVD. While meeting the requirements of high-performance artificial neural network devices, it can achieve large-area, batch fabrication, making it suitable for industrial-scale production. This solves the complexity of fabricating two-dimensional material device arrays and the compatibility issues of arraying processes. The fabrication scheme of this opto-synaptic device does not require knowledge beyond basic microelectronics expertise and micro / nano fabrication technology, and the fabrication process has low requirements for experimental equipment, enabling large-scale fabrication in the laboratory, which is conducive to promoting the research and development of artificial neural network devices.

[0097] The embodiments described above are merely examples of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

Claims

1. A photoelectric synaptic device based on an LLTO ion gate, characterized in that, It includes a substrate, a bottom electrode, a gate dielectric, and a channel stacked sequentially, as well as a source electrode and a drain electrode spaced apart above the channel; the gate dielectric is made of lithium lanthanum titanate, and the channel is made of a two-dimensional semiconductor thin film.

2. The photoelectric synapse device according to claim 1, characterized in that, The thickness of the gate dielectric is 40-60 nm.

3. The photoelectric synapse device according to claim 1, characterized in that, The two-dimensional semiconductor thin film is WS2, MoTe2, MoS2 or ReS2.

4. The photoelectric synapse device according to claim 1, characterized in that, The bottom electrode includes a Cr electrode disposed on the substrate and an Au electrode disposed on the Cr electrode.

5. The photoelectric synapse device according to claim 4, characterized in that, The thickness of the Cr electrode is 3-7 nm, and the thickness of the Au electrode is 7-13 nm.

6. The photoelectric synapse device according to claim 1, characterized in that, The source electrode and drain electrode are independently made of one or any combination of Cu, Al, Au, Ag, Mo, W, Ni, Fe, Zn and Pt, and the thickness of both the source electrode and drain electrode is 30-70 nm.

7. The photoelectric synapse device according to claim 1, characterized in that, The bottom electrode is located directly below the portion of the channel that is not covered by the source electrode or the drain electrode.

8. The method for fabricating the photoelectric synaptic device according to any one of claims 1-7, characterized in that, Includes the following steps: S1. Fabricate a bottom electrode on a substrate; S2. Fabricate a gate dielectric on the bottom electrode; S3. Fabricate a channel on the gate dielectric; S4. Prepare the source electrode and drain electrode on the channel to obtain the photoelectric synapse device.

9. The preparation method according to claim 8, characterized in that, Step S2 includes: forming a gate dielectric by magnetron sputtering lithium lanthanum titanate onto the bottom electrode.

10. The preparation method according to claim 9, characterized in that, Step S3 includes: preparing a two-dimensional semiconductor material using chemical vapor deposition and transferring it onto a gate dielectric using a dry or wet method.

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