Method for improving edge electric leakage of TOPCon battery

Abstract

The invention belongs to the technical field of solar cell production, and particularly relates to a method for improving edge electric leakage of a TOPCon cell. According to the invention, an N-type silicon wafer is adopted for processing, after the silicon wafer is annealed, laser mask opening treatment is added to the four edges of the back surface of the silicon wafer, and then normal chain type front HF cleaning and RCA etching reaction are carried out, so that an n + Poly layer at the mold opening position of the back surface edge can be removed, and isolation strips from the side edges and the front surface are formed; the full isolation state of the front P region and the back n + Poly is realized, the n + Poly layer and the tunneling oxide layer on the edge of the cell structure prepared by the method are removed, the problem of cell electric leakage caused by frequent unclean removal of the mask on the side edge of the silicon wafer is solved, and the production efficiency and yield of the cell are improved.

Description

Technical Field

[0001] This invention relates to the field of solar cell manufacturing technology, and in particular to a method for improving edge leakage current in TOPCon cells. Background Technology

[0002] N-type silicon tunneling oxide passivated contact (TOPCon) solar cell technology utilizes a stacked structure of ultra-thin silicon oxide and doped polycrystalline silicon (Poly-Si) for passivation on the back surface. This tunneling oxide passivation contact structure allows majority carriers to penetrate the oxide layer while blocking minority carriers, effectively achieving selective carrier passage and significantly reducing the recombination rate of minority carriers. This not only achieves excellent surface passivation but also ensures compatibility with high-temperature processes and avoids the high recombination problem at electrode contacts. The fabrication of N-type TOPCon monocrystalline bifacial solar cells requires two doping processes: boron diffusion doping on the front side and phosphorus doping on the back side. One of the biggest challenges in the process is achieving isolation between the front P-region and the back N-region on the silicon wafer side. Currently, in the production process of TOPCon cells, the boron doped layer on the back and sides is removed by wet chain removal of BSG and alkaline polishing in a tank. The polycrystalline silicon layer and doped phosphorus layer on the front are removed by wet chain removal of PSG and alkaline polishing in a tank. Improper cleaning can easily lead to over-polishing of the doped areas or incomplete removal of the plating, resulting in edge leakage, affecting the passivation effect, hindering light absorption and reducing the fill factor, ultimately leading to a decrease in efficiency.

[0003] Patent publication number CN112349584B discloses a method for removing edge plating and a method for fabricating TOPCon batteries. This application improves the removal effect of edge plating by improving the chain-type water film and tank-type circulating bubbling system, which is a commonly used method in mass production. However, the tunneling oxide layer and phosphorus-doped polycrystalline silicon layer on the back of the TOPCon are currently prepared by PECVD. A silicon oxide mask is also prepared outside the doped polycrystalline silicon. This mask protects the back contact passivation structure from being damaged in the RCA alkaline solution during the subsequent wet chain-type PSG removal and tank-type RCA plating removal process. This mask is generated by the reaction of SiH4 and N2O under PECVD. The mask contains nitrogen, which is difficult to remove with HF. When removing the front edge plating mask during the chain-type PSG removal process, it is affected by the solubility fluctuation and liquid level fluctuation of the HF solution at different life stages. The mask on the side of the silicon wafer is often not completely removed, resulting in battery leakage and affecting battery efficiency and yield stability. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a method for improving edge leakage in TOPCon batteries. This method can solve the problem of edge leakage even when wet cleaning of the battery side plating is incomplete, thereby improving battery efficiency and yield.

[0005] To achieve the above technical objectives, the specific technical solution of the present invention is as follows: The present invention proposes a method for improving edge leakage current of a TOPCon battery, comprising the following steps:

[0006] S1. Texturing: The silicon wafer is placed in a mixture of alkali and polishing additives to react, remove the damaged layer on the surface of the silicon wafer, reduce the recombination rate of photogenerated carriers, and form a uniform pyramidal textured surface structure.

[0007] S2, Boron diffusion and oxidation: The silicon wafer obtained in step S1 is inserted into a quartz boat and subjected to single-sided boron diffusion in a high-temperature furnace tube. A boron source is introduced for deposition. Oxygen is introduced for push-junction oxidation to form a BSG layer.

[0008] S3, BSG removal and alkaline polishing: A chain machine is used to remove the BSG layer on the back and four sides of the silicon wafer; a tank machine is used to perform alkaline polishing on the back of the silicon wafer to remove the PN junctions wrapped around the back and sides.

[0009] S4. Tunneling / n+Poly layer preparation and crystallization: On the polished back surface of the silicon wafer, a tunneling oxide layer and a doped amorphous silicon layer are deposited sequentially using PECVD technology, and a silicon oxide mask is prepared; after annealing, the doped amorphous silicon is crystallized into a doped polycrystalline silicon film n+Poly layer.

[0010] S5. Laser film opening: A green picosecond laser is used to open the film on the four edges of the back of the silicon wafer. The laser ablates the silicon oxide mask on the four sides of the back of the silicon wafer.

[0011] S6. Mask Removal and RCA Etching: A chain machine is used to remove the silicon oxide mask on the front and four sides of the silicon wafer; then a tank machine is used to perform RCA etching on the Poly layer coated on the front and sides of the silicon wafer using an alkaline reaction.

[0012] S7. Acid washing of BSG and mask: The silicon wafer obtained in step S6 is cleaned in the acid bath of the RCA machine to remove the BSG on the front side and the mask on the back side of the silicon wafer.

[0013] S8. Passivation film preparation: AlOx is deposited on both sides of the silicon wafer using an ALD machine to form an AlOx passivation layer on the surface.

[0014] S9, Anti-reflective coating: SixNy layer is deposited on the front and back sides of the silicon wafer;

[0015] S10. Electrode fabrication: Electrodes are prepared by screen printing silver paste on both the front and back sides.

[0016] Furthermore, in step S1, the silicon wafer is reacted in a mixture of alkali and polishing additive at a temperature of 80–85°C for a time of 400–500 seconds.

[0017] Furthermore, in step S2, the boron source is BCl3, the deposition temperature is 800–850°C, the push-bond oxidation temperature is 900–1050°C, the doping sheet resistance is 300–400 Ω / sq, and the thickness of the oxidized BSG layer is 80–120 nm.

[0018] Furthermore, in step S3, the silicon wafer is removed from the front side and four sides using a chain machine under water film protection and an HF solution with a volume concentration of 28% to 35% by means of rollers carrying the liquid.

[0019] Furthermore, in step S4, the thickness of the tunneling oxide layer is 1–2 nm, the thickness of the phosphorus-doped amorphous silicon layer is 80–150 nm, the thickness of the silicon oxide mask is 10–25 nm, the sheet resistance of the doped layer is 50–150 Ω / sq, and the annealing temperature is 650–850 °C.

[0020] Furthermore, in step 5, the green picosecond laser creates a film width of 200–400 μm on the four edges of the back side of the silicon wafer, and the laser power is 80–150 W.

[0021] Furthermore, in step S6, the silicon wafer is removed from the front and four sides of the silicon wafer using a chain machine under the protection of a water film and by using an HF solution with a volume concentration of 28% to 35% in a roller-driven liquid-carrying manner.

[0022] Furthermore, in step S7, the silicon wafer is cleaned using HF with a volume concentration of 15% to 25%.

[0023] Furthermore, in step S9, the SixNy layer film formed on the front side of the silicon wafer has a thickness of 60-80 nm and a refractive index of 2.0-2.05; the SixNy layer film formed on the back side of the silicon wafer has a thickness of 70-90 nm and a refractive index of 2.10-2.15.

[0024] The beneficial effects of this invention are as follows: After crystallization by annealing, this invention adds laser masking treatment to the edges of the four sides of the back side of the silicon wafer, and then performs normal chain-type front HF cleaning and RCA etching reaction, so that the n+Poly layer at the back edge can be removed, forming an isolation band with the sides and the front side, realizing a complete isolation state between the front P area and the back n+Poly, and solving the problem of leakage at the edge of the battery. Attached Figure Description

[0025] Figure 1This is a process flow diagram of the method for improving edge leakage current of TOPCon batteries according to the present invention.

[0026] Figure 2 This is a diagram of a conventional TOPCon battery structure.

[0027] Figure 3 This is a structural diagram of the TOPCon battery after improving edge leakage according to the present invention.

[0028] The corresponding names of the labels in the figure are as follows: 1. Electrode; 2. SixNy layer; 3. P emitter; 4. AlOx passivation layer; 5. n+Poly layer; 6. Tunneling oxide layer. Detailed Implementation

[0029] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0030] like Figure 1 As shown, this application provides a method for improving edge leakage current in TOPCon batteries. An N-type silicon wafer with a resistivity of 0.4–2.1 Ω·cm and a thickness of 100–130 μm is selected, and the wafer is processed using the following steps:

[0031] S1. Texturing: The silicon wafer is placed in a mixture of alkali and polishing additives at a temperature of 80-85℃ for 400-500 seconds to remove the damaged layer on the surface of the silicon wafer and reduce the recombination rate of photogenerated carriers; a uniform pyramidal textured surface structure is formed, which is beneficial to light absorption on the front side of the silicon wafer.

[0032] S2, Boron Diffusion and Oxidation: The silicon wafer obtained in step S1 is inserted into a quartz boat and subjected to single-sided boron diffusion in a high-temperature furnace tube. A boron source is introduced for doping deposition, wherein the boron source is BCl3, the sheet resistance of the doping is 300-400 Ω / sq, and the deposition temperature is 800-850℃. Oxygen is introduced for push-bonding oxidation at a temperature of 900-1050℃. In the entire process, the high-temperature furnace can be heated to 800-850℃ first for boron deposition, and then heated to 900-1050℃ for push-bonding oxidation. The final oxidized BSG layer (borosilicate glass layer) has a thickness of 80-120 nm. The borosilicate glass layer is a byproduct of boron diffusion and can be removed with HF solution.

[0033] S3. BSG Removal and Alkaline Polishing: The silicon wafer obtained in step S2 is cleaned using a chain machine with a water film protection and a 28%–35% HF solution on rollers to remove the BSG layer on the front and four sides of the silicon wafer. After removing the BSG layer on the back and four sides of the silicon wafer, an alkaline polishing process is performed on the back of the silicon wafer using a tank machine. Since the back and four sides of the silicon wafer are not protected by the BSG layer, they are polished in the alkaline solution, thereby removing the PN junctions that have spread around the back and sides. However, the PN junctions on the front of the silicon wafer are not affected by the alkaline polishing because they are protected by the BSG layer and remain intact.

[0034] S4. Tunneling / n+Poly Layer Preparation and Crystallization: On the polished back surface of the silicon wafer, a tunneling oxide layer 6 and a phosphorus-doped amorphous silicon layer are sequentially deposited using PECVD technology, and a silicon oxide mask is prepared. The thickness of the tunneling oxide layer 6 is 1-2 nm, the thickness of the phosphorus-doped amorphous silicon layer is 80-150 nm, and the sheet resistance is 50-150 Ω / sq. The final silicon oxide mask has a thickness of 10-25 nm. The ultrathin tunneling oxide layer is used to achieve efficient electron transport and solve the leakage problem in battery manufacturing. Then, after annealing, the doped amorphous silicon is crystallized into a doped polycrystalline silicon film n+Poly layer 5. During the annealing process, the temperature is controlled at 650-850℃ and the annealing time is 60-120 min.

[0035] The n+Poly layer 5, together with the silicon oxide mask, forms a passivation contact structure, which has the following functions: reducing recombination: reducing carrier recombination losses at the silicon-metal interface; improving contact: providing low-resistance ohmic contacts and improving carrier collection efficiency; and optical optimization: reducing parasitic light absorption through thinning processes (such as 30nm).

[0036] S5. Laser Delamination: A green picosecond laser is used to delaminate the four edges of the back side of the silicon wafer obtained in step S4. The delamination width is 200-400 μm. The mask in this area is removed. During the test, the effect of improving battery leakage can be tested by different delamination widths and comparative analysis can be performed. During the delamination process, a green picosecond laser with a laser power of 80-150W is used to ablate the silicon oxide mask on the four sides of the back side of the silicon wafer, so that the n+Poly layer at the delamination edge of the back side of the silicon wafer can be removed.

[0037] S6. Mask Removal and RCA Etching: The silicon wafer obtained in step S5 is subjected to RCA etching using a chain-type machine with a water film protection and a 28%–35% HF solution on rollers to remove the silicon oxide mask on the front and four sides of the wafer. After the silicon oxide mask on the front and four sides of the wafer is removed, an alkaline reaction is used to perform RCA etching on the n+Poly layer 5 deposited on the front and sides of the wafer. During the etching process, the n+Poly layer 5 on the front and sides of the wafer will be etched away in the alkaline solution because it is not protected by the silicon oxide mask. At the same time, the n+Poly layer 5 in the laser-opened areas on the four edges of the back of the wafer will also be etched away, etching down to the silicon substrate.

[0038] Unlike existing technologies, in steps S5 and S6 of this application, the four edges of the back side of the silicon wafer are first opened by laser, and then the normal chain-type front HF cleaning and RCA etching reaction are performed. The n+Poly layer 5 at the edge of the back side of the silicon wafer is removed, forming an isolation band with the side and the front side, thereby achieving a complete isolation state between the front P area and the back n+Poly, eliminating the risk of edge leakage.

[0039] S7. Acid washing of BSG and mask: The silicon wafer obtained in step S6 is cleaned in the acid bath of the RCA machine. In this application, an HF solution with a volume concentration of 15% to 25% is used for cleaning, which can remove the BSG on the front side of the silicon wafer and the silicon oxide mask on the back side.

[0040] S8. Passivation film preparation: AlOx (aluminum oxide) deposition passivation is performed on both sides of the silicon wafer using an ALD machine, and finally an AlOx passivation layer 4 with a thickness of 5-10 nm is formed on the surface of the silicon wafer;

[0041] S9. Anti-reflection coating: SixNy layer 2 (silicon nitride layer) is deposited on the front and back sides of the silicon wafer using PECVD. The thickness of the SixNy layer 2 film formed on the front side of the silicon wafer is 60-80 nm, and the refractive index is 2.0-2.05. The thickness of the SixNy layer 2 film formed on the back side of the silicon wafer is 70-90 nm, and the refractive index is 2.10-2.15.

[0042] S10. Electrode fabrication: Electrodes are prepared by screen printing silver paste on both the front and back sides.

[0043] This application proposes a method to improve edge leakage of TOPCon cells. Unlike existing technologies, this method involves laser-etching the back of the silicon wafer after annealing and crystallization of the doped amorphous silicon. This process removes the masking on the four sides of the back of the wafer, and then uses RCA alkaline etching to completely remove the n+Poly layer 5 at the four edges, forming an isolation band between the front and back sides. This achieves complete isolation between the front P-region and the back n+Poly layer 5, directly eliminating edge leakage caused by wet process instability. This significantly improves cell yield and reduces hot spots caused by localized cell leakage, thus enhancing module reliability and lifespan. Furthermore, AlOx passivation is added to the back of the silicon wafer, improving passivation effectiveness and significantly increasing cell efficiency. The process is simple and easy to implement; simply adding a laser-etching step to existing processes achieves significant advantages in cell efficiency, yield, and module reliability.

[0044] like Figures 2-3 As shown, the existing conventional battery structure is as follows: Figure 2 As shown, the structure includes electrode 1, SixNy layer 2, P emitter 3, AlOx passivation layer 4, n+Poly layer 5, and tunneling oxide layer 6. The n+Poly layer 5 and tunneling oxide layer 6 at the cell edge are retained. The front P-region of the silicon wafer and the back n+Poly layer 5 are not completely isolated, thus posing a risk of leakage. The TOPCon cell structure fabricated using the method described above for improving edge leakage in this application is as follows: Figure 3 As shown, now for such Figure 2 In the conventional battery structure shown, the edge n+Poly layer 5 and tunneling oxide layer 6 of the TOPCon battery structure prepared in this application are both removed, achieving complete isolation between the front P region and the back n+Poly layer 5, directly eliminating the edge leakage problem caused by wet process instability.

[0045] Example 1:

[0046] An N-type silicon wafer with a resistivity of 1.5 Ω·cm and a thickness of 110 μm was selected, and the wafer was processed using the following steps:

[0047] S1. Texturing: The silicon wafer is placed in a mixture of alkali and polishing additives at 85°C and reacted for 500 seconds to remove the damaged layer on the surface of the silicon wafer and form a uniform pyramidal textured surface.

[0048] S2, Boron diffusion and oxidation: The silicon wafer obtained in step S1 is inserted into a quartz boat and subjected to single-sided boron diffusion in a high-temperature furnace tube. BCl3 is introduced for doping deposition for 5 minutes at a deposition temperature of 800℃. Then, oxygen is introduced for push-bonding oxidation for 10 minutes at a push-bonding oxidation temperature of 1000℃. Finally, a BSG layer (borosilicate glass layer) with a thickness of 100nm is formed.

[0049] S3. BSG Removal and Alkaline Polishing: The silicon wafer obtained in step S2 is treated with a chain machine under the protection of a water film. The BSG layer on the front and four sides of the silicon wafer is removed by using a 30% HF solution on rollers. Then, the back of the silicon wafer is treated with alkaline polishing using a tank machine. Since the back and four sides of the silicon wafer are not protected by the BSG layer, they are polished in the alkaline solution, thereby removing the PN junctions that have spread around the back and sides. The PN junctions on the front of the silicon wafer are not affected by alkaline polishing because they are protected by the BSG layer and are retained.

[0050] S4. Tunneling / n+Poly layer preparation and crystallization: On the polished back surface of the silicon wafer, a tunneling oxide layer 6 and a phosphorus-doped amorphous silicon layer are sequentially deposited using PECVD technology, and a silicon oxide mask is prepared. The final silicon oxide mask has a thickness of 15nm. Then, after annealing at 800℃ for 100min, the doped amorphous silicon is crystallized into a doped polycrystalline silicon film n+Poly layer 5.

[0051] S5, Laser Deformation: A green picosecond laser with a power of 150W is used to deform the four edges of the back side of the silicon wafer obtained in step S4. The width of the deformation is 200μm. The silicon oxide mask on the four sides of the back side of the silicon wafer is melted away by the laser.

[0052] S6. Mask Removal and RCA Etching: The silicon wafer obtained in step S5 is used with a chain machine under the protection of a water film. The silicon oxide mask on the front and four sides of the silicon wafer is removed by using a 30% HF solution on rollers. Then, the n+Poly layer 5 deposited on the front and sides of the silicon wafer is RCA etched using an alkaline reaction with a tank machine.

[0053] S7. Pickling BSG and mask: The silicon wafer obtained in step S6 is cleaned in the acid bath of the RCA machine using an HF solution with a volume concentration of 15% to 25% to remove the BSG on the front side and the silicon oxide mask on the back side of the silicon wafer.

[0054] S8. Passivation film preparation: AlOx (aluminum oxide) deposition passivation is performed on both sides of the silicon wafer using an ALD machine to form an 8nm thick AlOx passivation layer on the silicon wafer surface;

[0055] S9. Anti-reflection coating: SixNy layer 2 (silicon nitride layer) is deposited on the front and back sides of the silicon wafer using PECVD. The front side of the silicon wafer has an 80nm thick SixNy layer 2, and the back side of the silicon wafer has a 90nm thick SixNy layer.

[0056] S10. Electrode fabrication: Electrodes are prepared by screen printing silver paste on both the front and back sides.

[0057] Example 2: TOPCon cells are fabricated using the same method as in Example 1. The difference from Example 1 is that the laser film opening width in step S5 of this example is 250nm, while other parameters and methods are the same as in Example 1.

[0058] Example 3: TOPCon cells are fabricated using the same method as in Example 1. The difference from Example 1 is that the laser film opening width in step S5 of this example is 300nm, while other parameters and methods are the same as in Example 1.

[0059] Example 4: TOPCon cells are fabricated using the same method as in Example 1. The difference from Example 1 is that the laser film opening width in step S5 of this example is 350nm, while other parameters and methods are the same as in Example 1.

[0060] Example 5: TOPCon cells are fabricated using the same method as in Example 1. The difference from Example 1 is that the laser film opening width in step S5 of this example is 400nm, while other parameters and methods are the same as in Example 1.

[0061] Comparative Example: TOPCon batteries were fabricated using the same method as in Example 1. The difference from the example is that the S5 laser film-opening step was omitted in this comparative example. Other parameters and methods are the same as in Example 1.

[0062] TOPCon Battery Performance Testing: The batteries prepared in Examples 1, 2, 3, 4, 5 and the comparative example were subjected to performance testing. The test data are shown in Table 1 below. Wherein, ETa is the battery conversion efficiency, Uoc is the open circuit voltage, Isc is the short circuit current, Rs is the series resistance, Rsh is the parallel resistance, and IRev2 is the reverse current.

[0063] Table 1

[0064] Group Number of tests Film opening width (µm) ETa (%) Uoc(V) Isc(A) Rs(Ω) Rsh(Ω) FF(%) IRev2 Example 1 1398 200 25.29 0.7312 13.94 0.00068 1651 85.22 0.011 Example 2 1278 250 25.21 0.7311 13.94 0.00069 1638 85.21 0.012 Example 3 1314 300 25.24 0.7312 13.95 0.00068 1643 85.23 0.013 Example 4 1426 350 25.28 0.7313 13.95 0.00067 1652 85.45 0.013 Example 5 1325 400 25.30 0.7312 13.95 0.00069 1668 85.50 0.012 Comparative Example 1184 0 24.91 0.7310 13.92 0.00069 1185 84.13 0.16

[0065] As shown in Table 1, the conventional TOPCon battery prepared in the comparative example, without laser film opening treatment, had an IRev2 value of 0.16. However, the TOPCon batteries prepared in Examples 1 to 5 of this application with improved leakage current, all underwent laser film opening treatment during preparation, and the measured IRev2 values ​​were 0.011, 0.012, 0.013, 0.013, and 0.012, respectively. The IRev2 values ​​of the batteries prepared in Examples 1 to 5 were all significantly lower than the IRev2 values ​​of the conventional TOPCon battery in the comparative example. This demonstrates that the method for improving edge leakage current of TOPCon batteries disclosed in this application can effectively reduce the risk of battery leakage current, solve the problem of edge leakage current of batteries, and improve battery yield.

[0066] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for improving edge leakage current in TOPCon batteries, characterized in that, Includes the following steps: S1. Texturing: The silicon wafer is placed in a mixture of alkali and polishing additives to react, remove the damaged layer on the surface of the silicon wafer, reduce the recombination rate of photogenerated carriers, and form a uniform pyramidal textured surface structure. S2, Boron diffusion and oxidation: The silicon wafer obtained in step S1 is inserted into a quartz boat and subjected to single-sided boron diffusion in a high-temperature furnace tube. A boron source is introduced for deposition. Oxygen is introduced for push-junction oxidation to form a BSG layer. S3, BSG removal and alkaline polishing: A chain machine is used to remove the BSG layer on the back and four sides of the silicon wafer; a tank machine is used to perform alkaline polishing on the back of the silicon wafer to remove the PN junctions wrapped around the back and sides. S4. Tunneling / n+Poly layer preparation and crystallization: On the polished back surface of the silicon wafer, a tunneling oxide layer and a doped amorphous silicon layer are deposited sequentially using PECVD technology, and a silicon oxide mask is prepared; after annealing, the doped amorphous silicon is crystallized into a doped polycrystalline silicon film n+Poly layer. S5. Laser film opening: A green picosecond laser is used to open the film on the four edges of the back of the silicon wafer. The laser ablates the silicon oxide mask on the four sides of the back of the silicon wafer. S6. Mask Removal and RCA Etching: A chain machine is used to remove the silicon oxide mask on the front and four sides of the silicon wafer; then a tank machine is used to perform RCA etching on the Poly layer coated on the front and sides of the silicon wafer using an alkaline reaction. S7. Acid washing of BSG and mask: The silicon wafer obtained in step S6 is cleaned in the acid bath of the RCA machine to remove the BSG on the front side and the mask on the back side of the silicon wafer. S8. Passivation film preparation: AlOx is deposited on both sides of the silicon wafer using an ALD machine to form an AlOx passivation layer on the surface. S9, Anti-reflective coating: SixNy layer is deposited on the front and back sides of the silicon wafer; S10. Electrode fabrication: Electrodes are prepared by screen printing silver paste on both the front and back sides.

2. The method for improving edge leakage current of a TOPCon battery according to claim 1, characterized in that, In step S1, the silicon wafer is reacted in a mixture of alkali and polishing additive at a temperature of 80-85°C for a time of 400-500 seconds.

3. The method for improving edge leakage current of a TOPCon battery according to claim 1, characterized in that, In step S2, the boron source is BCl3, the deposition temperature is 800-850℃, the push-bond oxidation temperature is 900-1050℃, the doping sheet resistance is 300-400Ω / sq, and the thickness of the oxidized BSG layer is 80-120nm.

4. The method for improving edge leakage current of a TOPCon battery according to claim 1, characterized in that, In step S3, the silicon wafer is removed from the front and four sides using a chain machine under water film protection and an HF solution with a volume concentration of 28% to 35% by means of rollers.

5. The method for improving edge leakage current of a TOPCon battery according to claim 1, characterized in that, In step S4, the thickness of the tunneling oxide layer is 1-2 nm, the thickness of the phosphorus-doped amorphous silicon layer is 80-150 nm, the thickness of the silicon oxide mask is 10-25 nm, the sheet resistance of the doped layer is 50-150 Ω / sq, and the annealing temperature is 650-850 °C.

6. The method for improving edge leakage current of a TOPCon battery according to claim 1, characterized in that, In step 5, the green picosecond laser creates a film with a width of 200–400 μm on the four edges of the back side of the silicon wafer, and the laser power is 80–150 W.

7. The method for improving edge leakage current of a TOPCon battery according to claim 1, characterized in that, In step S6, the silicon wafer is removed from the front and four sides of the silicon wafer using a chain machine under the protection of a water film and an HF solution with a volume concentration of 28% to 35% by means of rollers carrying the liquid.

8. The method for improving edge leakage current of a TOPCon battery according to claim 1, characterized in that, In step S7, the silicon wafer is cleaned using HF with a volume concentration of 15% to 25%.

9. A method for improving edge leakage current of a TOPCon battery according to any one of claims 1-8, characterized in that, In step S9, the SixNy layer film formed on the front side of the silicon wafer has a thickness of 60-80 nm and a refractive index of 2.0-2.05; the SixNy layer film formed on the back side of the silicon wafer has a thickness of 70-90 nm and a refractive index of 2.10-2.15.

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