Display device and electronic device

Abstract

The invention provides a display device and an electronic device. The display device includes: a substrate; a first transistor positioned on the substrate and including a first semiconductor layer and a first gate electrode; a second transistor positioned on the first transistor and including a second semiconductor layer and a second gate electrode; and a light emitting element positioned on the second transistor and electrically connected to the first transistor, in which the first gate electrode of the first transistor and the second semiconductor layer of the second transistor are electrically connected to each other through the contact hole.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0124787, filed on September 12, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] One or more embodiments relate to display devices and electronic devices. Background Technology

[0004] To overcome the many drawbacks of cathode ray tubes, such as their heavy weight and large size, various flat panel display devices have been developed. These devices can include liquid crystal displays (LCDs), field emission displays (FEDs), plasma display panels (PDPs), organic light-emitting diode (OLED) displays, and more.

[0005] Among these flat panel display devices, organic light-emitting diode (OLED) displays use organic light-emitting diodes that emit light through the recombination of electrons and holes to output images. These OLED displays are attracting attention as the next generation of displays due to their fast response speed and low power consumption. Summary of the Invention

[0006] One or more embodiments provide a display device with improved integration density and an electronic device including the display device.

[0007] However, the exemplary embodiments of this disclosure are not limited to those set forth herein. Other exemplary embodiments of this disclosure will become more apparent to those skilled in the art from the following detailed description of the disclosure.

[0008] Additional aspects will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practicing the embodiments presented in this disclosure.

[0009] According to one or more embodiments, a display device includes: a substrate; a first transistor positioned on the substrate, the first transistor including a first semiconductor layer and a first gate electrode; a second transistor positioned on the first transistor, the second transistor including a second semiconductor layer and a second gate electrode; and a light-emitting element positioned on the second transistor and electrically connected to the first transistor, wherein the first gate electrode of the first transistor and the second semiconductor layer of the second transistor are electrically connected to each other through a contact hole.

[0010] In an embodiment, the display device may further include: a conductive layer positioned on an insulating layer covering a second semiconductor layer, wherein the conductive layer is electrically connected to a first gate electrode and a second semiconductor layer through a contact hole, and at least a portion of the conductive layer may vertically overlap with the first gate electrode and the second semiconductor layer.

[0011] In one embodiment, the contact hole can expose the side surface of the source region of the second transistor.

[0012] In an embodiment, the display device may further include a third transistor located on the same layer as the second transistor, and the third transistor may include a second semiconductor layer and a third gate electrode.

[0013] In an embodiment, the display device may further include: a first scan line and a second scan line, positioned on the same layer between the first transistor and the second transistor, wherein the first scan line may form a double gate of the second transistor together with the second gate electrode, and the second scan line may form a double gate of the third transistor together with the third gate electrode.

[0014] In an embodiment, the first scan line and the second scan line can be arranged parallel to each other.

[0015] In an embodiment, the display device may further include a first voltage line and an initialization voltage line, positioned on the same layer between the second gate electrode and the light-emitting element.

[0016] In an embodiment, the first voltage line and the initialization voltage line may be arranged parallel to the first scan line.

[0017] In one embodiment, two sub-pixels arranged adjacent to each other in a direction perpendicular to the first voltage line can share the first voltage.

[0018] In an embodiment, the first semiconductor layer may include polysilicon, and the second semiconductor layer may include oxide semiconductor.

[0019] According to one or more embodiments, a display device includes: a substrate including a display area and a peripheral area positioned outside the display area; a plurality of sub-pixels positioned in the display area; and a plurality of first voltage lines extending in a first direction and configured to apply a first voltage to the plurality of sub-pixels, wherein two sub-pixels among the plurality of sub-pixels share the first voltage line of the plurality of first voltage lines, and the two sub-pixels are arranged adjacent to each other in a second direction perpendicular to the first direction relative to the first voltage line.

[0020] In one embodiment, the two sub-pixels can be symmetrical with respect to the first voltage line.

[0021] In an embodiment, each of the two sub-pixels may include a first scan line, a second scan line, and an initialization voltage line parallel to the first direction.

[0022] In an embodiment, each of the plurality of sub-pixels may include: a first transistor positioned on a substrate, the first transistor including a first semiconductor layer and a first gate electrode; a second transistor positioned on the first transistor, the second transistor including a second semiconductor layer and a second gate electrode; and a light-emitting element positioned on the second transistor and electrically connected to the first transistor, wherein the first gate electrode of the first transistor and the second semiconductor layer of the second transistor may be electrically connected to each other through a contact hole.

[0023] In an embodiment, the display device may further include: a conductive layer positioned on an insulating layer covering a second semiconductor layer, wherein the conductive layer is electrically connected to a first gate electrode and a second semiconductor layer through a contact hole, and at least a portion of the conductive layer may vertically overlap with the first gate electrode and the second semiconductor layer.

[0024] In one embodiment, the contact hole can expose the side surface of the source region of the second transistor.

[0025] In an embodiment, the display device may further include a third transistor located on the same layer as the second transistor, and the third transistor may include a second semiconductor layer and a third gate electrode.

[0026] In an embodiment, the display device may further include: a first scan line and a second scan line, positioned on the same layer between the first transistor and the second transistor, wherein the first scan line may form a double gate of the second transistor together with the second gate electrode, and the second scan line may form a double gate of the third transistor together with the third gate electrode.

[0027] In an embodiment, the area of ​​the first gate electrode may be larger than the area of ​​the channel region of the first transistor in a plan view.

[0028] In an embodiment, the first semiconductor layer may include polysilicon, and the second semiconductor layer may include oxide semiconductor.

[0029] According to one or more embodiments, an electronic device including a display device is provided, wherein the display device includes: a substrate; a first transistor positioned on the substrate, the first transistor including a first semiconductor layer and a first gate electrode; a second transistor positioned on the first transistor, the second transistor including a second semiconductor layer and a second gate electrode; and a light-emitting element positioned on the second transistor and electrically connected to the first transistor, wherein the first gate electrode of the first transistor and the second semiconductor layer of the second transistor are electrically connected to each other through a contact hole. Attached Figure Description

[0030] The above and other aspects, features, and advantages of specific embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0031] The following accompanying drawings illustrate preferred embodiments of the present disclosure and, together with the detailed description of the present disclosure below, serve to further understand the technical concept of the present disclosure; therefore, the present disclosure should not be construed as limited to the matters described in these drawings:

[0032] Figure 1 This is a schematic plan view of an example of a display device according to one embodiment;

[0033] Figure 2 yes Figure 1 A schematic block diagram of the structure of a display device;

[0034] Figure 3 yes Figure 1 The equivalent circuit diagram of a sub-pixel of the display device;

[0035] Figure 4 It is shown that the arrangement is in Figure 1 A schematic layout diagram of the positions of thin-film transistors, capacitors, etc. in sub-pixels included in a display device;

[0036] Figure 5 It is shown Figure 1 A schematic plan view of an example of two adjacent sub-pixels of a display device;

[0037] Figure 6 It is shown Figure 1 A schematic cross-sectional view of a portion of the display device;

[0038] Figure 7 It is shown Figure 6 An enlarged schematic cross-sectional view of an example of part A shown; and

[0039] Figure 8 This is a schematic diagram illustrating an example in which an electronic device including a display device according to an embodiment is implemented as a head-mounted display. Detailed Implementation

[0040] Referring now to embodiments in detail, examples of which are shown in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this regard, embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, embodiments are described below only by reference to the accompanying drawings to illustrate various aspects. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of…” modify the entire list of elements before / after the list of elements, rather than modifying individual elements in the list.

[0041] Because this disclosure allows for various modifications and numerous embodiments, specific embodiments will be shown in the accompanying drawings and described in detail in the written description. The effects and features of this disclosure, as well as the methods for achieving these effects and features, will become apparent from the embodiments and drawings described below in detail. However, this disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein.

[0042] In the following embodiments, the terms "first," "second," etc., are not used in a limiting sense, but are used to distinguish one element from another.

[0043] Unless the context clearly indicates otherwise, the singular form as used herein is intended to include the plural form as well.

[0044] It will also be understood that the terms “comprising” and / or “including” as used herein indicate the presence of the stated features or elements, but do not preclude the presence or addition of one or more other features or elements.

[0045] In the following embodiments, it will be understood that when a portion such as a membrane, region, or element is referred to as being “on” another portion, this can include not only the case where the portion is directly on the other portion, but also the case where an intervening membrane, intervening region, or intervening element may be present therein.

[0046] For ease of illustration, the dimensions of the elements in the accompanying drawings may be exaggerated or reduced. For example, because the dimensions and / or thicknesses of the elements in the drawings are arbitrarily shown for ease of illustration, this disclosure is not limited thereto.

[0047] In the following description, embodiments will be described in detail with reference to the accompanying drawings. When describing embodiments with reference to the accompanying drawings, the same or corresponding elements are indicated by the same reference numerals, and redundant descriptions are omitted.

[0048] Figure 1 This is a schematic plan view of an example of a display device according to one embodiment. Figure 2 yes Figure 1 A schematic block diagram of the structure of the display device. Figure 3 yes Figure 1 The equivalent circuit diagram of a sub-pixel of the display device. Figure 4 It is shown that the arrangement is in Figure 1 A schematic layout diagram showing the positions of thin-film transistors, capacitors, etc., in sub-pixels of a display device, and Figure 5 It is shown Figure 1 A schematic plan view of an example of two adjacent sub-pixels of a display device.

[0049] First, refer to Figure 1 and Figure 2 According to one embodiment, the display device 10 may include a substrate 100 having a display area DA for displaying an image and a peripheral area PA located outside the display area DA.

[0050] Multiple scan lines SL1, ..., SLn extend along a first direction X, multiple data lines DL1, ..., DLm extend along a second direction Y perpendicular to the first direction X, and multiple sub-pixels PX can be located in the display area DA. Here, m and n are each natural numbers greater than 0. In an embodiment, the vertical direction Z can be substantially perpendicular to the plane defined by the first direction X and the second direction Y.

[0051] The wiring along which electrical signals can be applied to multiple sub-pixels PX can include multiple scan lines SL1, ..., SLn and multiple data lines DL1, ..., DLm. For example, the multiple scan lines SL1, ..., SLn can be arranged in multiple rows extending in a first direction X to transmit scan signals to the sub-pixels PX. For example, the multiple data lines DL1, ..., DLm can be arranged in multiple columns extending in a second direction Y to transmit data signals to the sub-pixels PX. The multiple sub-pixels PX can be positioned at the intersection of the multiple scan lines SL1, ..., SLn and the multiple data lines DL1, ..., DLm.

[0052] Each sub-pixel PX may include a light-emitting element that emits red, green, blue, or white light. For example, each sub-pixel PX may include an organic light-emitting diode (OLED) as a light-emitting element.

[0053] In the peripheral area PA, a data driver 130 for applying data signals to the display area DA, a scan driver 150 for applying scan signals to the display area DA, a voltage controller 170 for controlling the voltage supplied to the display area DA, and a controller 190 for controlling the data driver 130, the scan driver 150 and the voltage controller 170 can be arranged.

[0054] The voltage controller 170 can generate and control the first voltage ELVDD, the second voltage ELVSS, and the initialization voltage VINT applied to the display area DA.

[0055] The first voltage ELVDD, the second voltage ELVSS, and the initialization voltage VINT can be applied to multiple sub-pixels PX. For example, the first voltage ELVDD can be a positive voltage, and the second voltage ELVSS can be a negative voltage or a ground voltage. That is, the second voltage ELVSS can have a lower level than the first voltage ELVDD.

[0056] Controller 190 can receive image signals RGB and control signals CS from an external source (e.g., a system board). Controller 190 can generate image data DATA by converting the data format of the image signals RGB into a format suitable for the interface between data driver 130 and controller 190. Controller 190 can then apply the image data DATA with the converted data format to data driver 130.

[0057] The controller 190 can generate and output a first control signal CS1 and a second control signal CS2 in response to a control signal CS applied from an external source. The first control signal CS1 can be defined as a scan control signal, and the second control signal CS2 can be defined as a data control signal. The first control signal CS1 can be applied to the scan driver 150. The second control signal CS2 can be applied to the data driver 130.

[0058] The scan driver 150 can generate multiple scan signals in response to the first control signal CS1. The multiple scan signals can be applied to multiple sub-pixels PX through multiple scan lines SL1, ..., SLn.

[0059] The data driver 130 can generate multiple data voltages corresponding to the image data DATA in response to the second control signal CS2. Multiple data voltages can be applied to multiple sub-pixels PX via multiple data lines DL1, ..., DLm. The data driver 130 can simultaneously apply data voltages generated in sub-pixel rows to multiple sub-pixels PX via multiple data lines DL1, ..., DLm.

[0060] Multiple sub-pixels (PXs) can receive multiple data voltages in response to multiple scan signals. Multiple sub-pixels (PXs) can display an image by emitting light with brightness corresponding to the multiple data voltages. Multiple sub-pixels (PXs) can display an image by emitting light sequentially or simultaneously.

[0061] Reference Figures 1 to 3 Each of the multiple sub-pixels PX may include a first transistor T1, a second transistor T2, a third transistor T3, and a light-emitting element OLED electrically connected to the first transistor T1.

[0062] Among multiple sub-pixels PX, the sub-pixel PX connected to the i-th scan line 155 among multiple scan lines SL1, ..., SLn and the j-th data line 131 among multiple data lines DL1, ..., DLm can be defined as the first sub-pixel PX. n Here, i is a natural number greater than 0 and less than or equal to n, and j is a natural number greater than 0 and less than or equal to m.

[0063] The i-th scan line 155 may include a first scan line 151 and a second scan line 152. The first scan line 151 and the second scan line 152 can respectively transmit scan signals GWi and GC to the first sub-pixel PX. n .

[0064] Data line j 131 can transmit the data voltage VDATA to the first sub-pixel PX. n The data voltage VDATA can have a voltage level corresponding to the image signal RGB input to the display device 10.

[0065] The first voltage line 173 can transmit the first voltage ELVDD to the first sub-pixel PX. n The second voltage line 177 can transmit the second voltage ELVSS to the first sub-pixel PX. n Furthermore, initialization voltage line 174 can transmit the initialization voltage VINT to the first sub-pixel PX. n .

[0066] Meanwhile, the first transistor T1 can be a P-type transistor with a low-temperature polycrystalline silicon (LTPS) semiconductor layer. However, this is merely illustrative, and the first transistor T1 can also be an N-type transistor.

[0067] The second transistor T2 and the third transistor T3 can each be an N-type transistor with an oxide semiconductor layer. However, this is merely illustrative, and the second transistor T2 and / or the third transistor T3 can be P-type transistors.

[0068] The first transistor T1 may include a first gate electrode, a first driving electrode, and a second driving electrode. The first gate electrode of the first transistor T1 may be connected to a first node N1, the first driving electrode may be connected to a first voltage line 173, and the second driving electrode may be connected to a second node N2. The first transistor T1 may be referred to as a driving transistor.

[0069] The second transistor T2 may include a second gate electrode, a first switching electrode, and a second switching electrode. The second gate electrode of the second transistor T2 may be connected to a first scan line 151, the first switching electrode may be connected to a first node N1, and the second switching electrode may be connected to a third node N3. The second transistor T2 may be referred to as a switching transistor or a scanning transistor.

[0070] The third transistor T3 may include a third gate electrode, a first initialization electrode, and a second initialization electrode. The third gate electrode of the third transistor T3 may be connected to the second scan line 152, the first initialization electrode may be connected to the third node N3, and the second initialization electrode may be connected to the second node N2. The third transistor T3 may be referred to as an initialization transistor.

[0071] In addition, each of the multiple sub-pixels PX may also include a first capacitor Cst and a second capacitor Cpr.

[0072] The first electrode of the first capacitor Cst can be connected to the first node N1, and the second electrode of the first capacitor Cst can be connected to the initialization voltage line 174. The first capacitor Cst can be referred to as a storage capacitor.

[0073] The first capacitor Cst can store the voltage between the first node N1 and the initialization voltage line 174. The amount of drive current flowing through the first transistor T1 can be determined based on the voltage stored in the first capacitor Cst. The light-emitting element OLED can emit light based on the drive current.

[0074] The first electrode of the second capacitor Cpr can be connected to the third node N3, and the second electrode of the second capacitor Cpr can be connected to the j-th data line 131.

[0075] The second capacitor Cpr can store the voltage between the third node N3 and the j-th data line 131. The second capacitor Cpr can also initialize the first voltage ELVDD through the second node N2 and the third transistor T3. For example, the second capacitor Cpr can stabilize and initialize the voltage of the second node N2 by coupling its stored charge. As a result, the voltage of the second node N2 can be synchronized with the first voltage ELVDD.

[0076] The OLED light-emitting element may include a first electrode connected to the second node N2 and a second electrode connected to the second voltage line 177. The first electrode of the OLED light-emitting element may be referred to as the anode electrode or pixel electrode, and the second electrode of the OLED light-emitting element may be referred to as the cathode electrode or common electrode.

[0077] Reference Figure 4 and Figure 5 Also refer to Figure 2Two sub-pixels PX (i.e., the first sub-pixel PX) are arranged adjacent to each other in a second direction Y perpendicular to the first direction X, relative to the first voltage line 173. n Second sub-pixel PX n+1 They can share the first voltage ELVDD. In some embodiments, the first sub-pixel PX n Second sub-pixel PX n+1 It can be symmetrical with respect to the first voltage line 173.

[0078] First sub-pixel PX n Second sub-pixel PX n+1 Each of them may include a first scan line 151, 151a, a second scan line 152, 152a and an initialization voltage line 174 parallel to the first direction X.

[0079] In some embodiments, the first sub-pixel PX n The second gate electrode or second sub-gate electrode of the second transistor T2 can be connected to the first scan line 151 of the i-th scan line 155, and the first sub-pixel PX. n The third gate electrode or third sub-gate electrode of the third transistor T3 can be connected to the second scan line 152 of the i-th scan line 155, and the first sub-pixel PX n The first driving electrode of the first transistor T1 can be connected to the second sub-pixel PX n+1 Shared first voltage line 173.

[0080] First sub-pixel PX n The second electrode of the first capacitor Cst can be connected to the initialization voltage line 174 to which the initialization voltage VINT is applied, and the first sub-pixel PX n The second electrode of the second capacitor Cpr can be connected to the j-th data line 131 to which the data voltage VDATA is applied.

[0081] Second sub-pixel PX n+1 The second gate electrode or second sub-gate electrode of the second transistor T2 can be connected to the first scan line 151a of the i+1th scan line 155a, and the second sub-pixel PX n+1 The third gate electrode or third sub-gate electrode of the third transistor T3 can be connected to the second scan line 152a of the (i+1)th scan line 155a, and the second sub-pixel PX n+1 The first driving electrode of the first transistor T1 can be connected to the first sub-pixel PX n Shared first voltage line 173.

[0082] Second sub-pixel PX n+1The second electrode of the first capacitor Cst can be connected to the initialization voltage line 174 to which the initialization voltage VINT is applied, and the second sub-pixel PX n+1 The second electrode of the second capacitor Cpr can be connected to the j-th data line 131 to which the data voltage VDATA is applied.

[0083] Simultaneously, the signal is transmitted to the first sub-pixel PX via the first scan line 151. n The i-th scan signal GWi is transmitted to the second sub-pixel PX via the first scan line 151a. n+1 The i+1th scan signal GWi+1 can be generated sequentially in the scan driver 150.

[0084] Furthermore, data is transmitted to the first sub-pixel PX via the second scan line 152. n The i-th scan signal GC is transmitted to the second sub-pixel PX via the second scan line 152a. n+1 The i+1 scan signal GC can be a global gate signal used to synchronize multiple sub-pixels PX.

[0085] At the same time, it can be connected to the first sub-pixel PX n The longitudinal direction of each of the first scan line 151, the second scan line 152, the first voltage line 173, and the initialization voltage line 174 of the i-th scan line 155 can be parallel to the first direction X.

[0086] It can be connected to the second sub-pixel PX n+1 The longitudinal direction of each of the first scan line 151a of the (i+1)th scan line 155a, the second scan line 152a of the (i+1)th scan line 155a, the first voltage line 173, and the initialization voltage line 174 may also be parallel to the first direction X.

[0087] In other words, due to the first sub-pixel PX n Second sub-pixel PX n+1 Since the first voltage line 173 is shared, the longitudinal direction of each of the first scan line 151, the second scan line 152, the first voltage line 173, the initialization voltage line 174, the first scan line 151a and the second scan line 152a of the (i+1)th scan line 155a can be parallel to the first direction X.

[0088] In addition, the data voltage VDATA is applied to the first sub-pixel PX through it. n Second sub-pixel PX n+1 The j-th data line 131 can be arranged in the second direction Y, which is perpendicular to the first direction X.

[0089] Therefore, because the first sub-pixel PX n Second sub-pixel PX n+1 By sharing the first voltage line 173 and not having a separate first voltage line, the display device 10 according to one embodiment can have improved integration density.

[0090] Figure 6 It is shown Figure 1 A schematic cross-sectional view of a portion of the display device, and Figure 7 It is shown Figure 6 An enlarged schematic cross-sectional view of an example of part A shown. For example, Figure 6 It can be shown in Figures 1 to 5 An example of a subpixel PX is shown in the image.

[0091] Reference Figure 6 and Figure 7 as well as Figures 2 to 5 According to one embodiment, a sub-pixel PX may include, on its substrate 100, a first transistor T1, a second transistor T2 and a third transistor T3 positioned on the first transistor T1, a light-emitting element 400 positioned on the second transistor T2 and the third transistor T3 and electrically connected to the first transistor T1, a first capacitor Cst, and a second capacitor Cpr. The second transistor T2 and the third transistor T3 may be located on the same layer.

[0092] In some embodiments, the substrate 100 may be made of a transparent glass material primarily comprising SiO2. However, it is not limited thereto, and the substrate 100 may also be made of a transparent plastic material. The plastic material may be one selected from the group consisting of: polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide, polycarbonate (PC), cellulose triacetate (TAC), and cellulose acetate propionate (CAP).

[0093] The first semiconductor layer 510 may be formed on the substrate 100. The first semiconductor layer 510 may include a first source region 511, a first drain region 513, and a first channel region 512 located between the first source region 511 and the first drain region 513.

[0094] In some embodiments, the first semiconductor layer 510 may include a first source region 511 and a first drain region 513 doped with impurities on corresponding opposite sides of the first channel region 512. Here, the impurities may vary depending on the type of the first transistor T1 and may include N-type impurities or P-type impurities. That is, the first channel region 512, the first source region 511 located on one side of the first channel region 512, and the first drain region 513 located on the other side of the first channel region 512 may be referred to as the first semiconductor layer 510.

[0095] The first source region 511 or the first drain region 513 formed by doping can also be interpreted in some cases as the source electrode (or the first driving electrode) or the drain electrode (or the second driving electrode) of the first transistor T1. In some embodiments, the positions of the first source region 511 and the first drain region 513 can be switched with each other depending on the impurities doped into the first semiconductor layer 510.

[0096] The first semiconductor layer 510 may include polycrystalline silicon. For example, the first semiconductor layer 510 may be a layer comprising low-temperature polycrystalline silicon (LTPS), but is not limited thereto, and may also be a layer comprising oxide semiconductor.

[0097] As an alternative embodiment, a buffer layer may also be formed between the substrate 100 and the first semiconductor layer 510. The buffer layer can improve the properties of polysilicon by shielding impurities during the crystallization process used to form polysilicon, and a flat surface can be provided on the buffer layer.

[0098] A first insulating layer l1 may be formed on the first semiconductor layer 510 to cover the first semiconductor layer 510. A first conductive layer including a first gate electrode 520 may be formed on the first insulating layer l1. In a plan view, the first gate electrode 520 may have an area wider than the area of ​​the first channel region 512 of the first transistor T1.

[0099] The first gate electrode 520 can be formed together with the first semiconductor layer 510 to form a first transistor T1. The first transistor T1 can receive a first voltage ELVDD from the first source region 511 and supply driving current to the light-emitting element 400.

[0100] The first gate electrode 520 can also be used as the first electrode 520 of the first capacitor Cst. Therefore, the integration density of the display device 10 can be increased, and thus the area of ​​the first capacitor Cst and the first transistor T1 can be increased, thereby providing a high-quality image. However, this disclosure is not limited thereto. As another embodiment, the first electrode 520 of the first capacitor Cst can be a separate component from the first gate electrode 520 of the first transistor T1.

[0101] A second insulating layer l2 may be formed on the first conductive layer to cover the first conductive layer. A second conductive layer, including a second electrode 530 of the first capacitor Cst, may be formed on the second insulating layer l2. The second electrode 530 of the first capacitor Cst may be formed together with the first electrode 520 of the first capacitor Cst to form the first capacitor Cst.

[0102] A third insulating layer l3 may be formed on the second conductive layer to cover the second conductive layer. A third conductive layer, including the first scan line 151 and the second scan line 152 to which scan signals GWi and GC are respectively applied, may be formed on the third insulating layer l3.

[0103] A fourth insulating layer 14 may be formed on the third conductive layer to cover the third conductive layer. A second semiconductor layer 550 may be formed on the fourth insulating layer 14. The second semiconductor layer 550 may include a second source region 551, a second channel region 552, a second drain region 553, a third source region 553, a third channel region 554, and a third drain region 555.

[0104] The second channel region 552 may be located between the second source region 551 and the second drain region 553, and the third channel region 554 may be located between the third source region 553 and the third drain region 555. In some embodiments, the second drain region 553 and the third source region 553 may refer to the same region.

[0105] The positions of the second source region 551 and the second drain region 553 can be switched according to the impurities doped into the second semiconductor layer 550, and the positions of the third source region 553 and the third drain region 555 can be switched according to the impurities doped into the second semiconductor layer 550.

[0106] The second semiconductor layer 550 may be a layer including an oxide semiconductor, but is not limited thereto, and may optionally be a layer including polycrystalline silicon (e.g., low-temperature polycrystalline silicon (LTPS)).

[0107] A fifth insulating layer 15 may be formed on the second semiconductor layer 550 to cover the second semiconductor layer 550. A fourth conductive layer 560, which electrically connects the first gate electrode 520 and the second source region 551 of the second semiconductor layer 550 through contact holes, may be formed on the fifth insulating layer 15. At least a portion of the fourth conductive layer 560 may overlap with the first gate electrode 520 and the second semiconductor layer 550 in the vertical direction Z.

[0108] In some embodiments, the contact hole connected to the fourth conductive layer 560 can expose the side surface of the second source region 551 of the second semiconductor layer 550, and can also expose at least a portion of the upper surface of the first gate electrode 520. Therefore, the fourth conductive layer 560, the second source region 551, and the first gate electrode 520 can be electrically connected. For example, the fourth conductive layer 560 may be... Figure 3 The first node N1 is shown in the diagram.

[0109] In other words, the first transistor T1 and the second transistor T2 can be arranged on different layers, and the first gate electrode 520 of the first transistor T1 and the second source region 551 of the second transistor T2 can be connected through a single contact hole, thereby providing improved integration density for the display device 10.

[0110] A sixth insulating layer 16 may be formed on the fourth conductive layer 560 to cover the fourth conductive layer 560. A fifth conductive layer including multiple contacts CNT1, CNT2 and CNT3, a second gate electrode 571 and a third gate electrode 572 may be formed on the sixth insulating layer 16.

[0111] The second gate electrode 571 and the third gate electrode 572 may overlap with the second channel region 552 and the third channel region 554, respectively. The second gate electrode 571 may form a second transistor T2 together with the second source region 551, the second channel region 552 and the second drain region 553. In some embodiments, the third gate electrode 572 may form a third transistor T3 on the same layer as the second transistor T2 together with the third source region 553, the third channel region 554 and the third drain region 555.

[0112] Meanwhile, the first scan line 151 and the second scan line 152, located on the third insulating layer 13 and on the same layer between the first transistor T1 and the second transistor T2, can be referred to as the second sub-gate electrode 151 and the third sub-gate electrode 152, respectively. Therefore, the second sub-gate electrode 151 and the third sub-gate electrode 152 can form the dual gate of the second transistor T2 and the dual gate of the third transistor T3 together with the second gate electrode 571 and the third gate electrode 572, respectively.

[0113] The second sub-gate electrode 151 may be formed to overlap with the second gate electrode 571. In a plan view, the area of ​​the second sub-gate electrode 151 may be larger than the area of ​​the second gate electrode 571. The third sub-gate electrode 152 may also be formed to overlap with the third gate electrode 572. In a plan view, the area of ​​the third sub-gate electrode 152 may be larger than the area of ​​the third gate electrode 572.

[0114] When the second transistor T2 and the third transistor T3 have dual gates, the current flowing along the second transistor T2 and the third transistor T3 can be controlled more precisely. The interaction between the dual gates can improve the switching speed of the second transistor T2 and the third transistor T3, and the second transistor T2 and the third transistor T3 can be driven with low power.

[0115] A seventh insulating layer l7 may be formed on the fifth conductive layer to cover the fifth conductive layer. A sixth conductive layer, including the fourth contact portion CNT4 and the first electrode 581 of the second capacitor Cpr, may be formed on the seventh insulating layer l7.

[0116] The first electrode 581 of the second capacitor Cpr can be electrically connected between the second channel region 552 and the third channel region 554 of the second semiconductor layer 550 through a contact hole. The contact hole can expose at least a portion of the region between the second channel region 552 and the third channel region 554.

[0117] In other words, the first electrode 581 of the second capacitor Cpr can be electrically connected to the second transistor T2 and the third transistor T3 through a single contact hole instead of two different contact holes, thereby improving the integration density of the display device 10.

[0118] An eighth insulating layer 18 may be formed on the sixth conductive layer to cover the sixth conductive layer. A seventh conductive layer, including the second electrode 590 of the second capacitor Cpr, may be formed on the eighth insulating layer 18.

[0119] The second electrode 590 of the second capacitor Cpr can be arranged to overlap with the first electrode 581 of the second capacitor Cpr. Alternatively, the second electrode 590 of the second capacitor Cpr can be formed together with the first electrode 581 of the second capacitor Cpr to form the second capacitor Cpr.

[0120] In some embodiments, the second electrode 590 of the second capacitor Cpr may include the j-th data line 131 to which the data voltage VDATA is applied.

[0121] A ninth insulating layer 19 may be formed on the seventh conductive layer to cover the seventh conductive layer. An eighth conductive layer may be formed on the ninth insulating layer 19. The eighth conductive layer may include a first voltage line 173 to which the first voltage ELVDD is applied, an initialization voltage line 174 to which the initialization voltage VINT is applied, and a seventh contact portion CNT7.

[0122] The first voltage line 173 can be connected to the first source region 511 of the first transistor T1 via the first contact CNT1 formed on the sixth insulating layer l6. This allows the first voltage ELVDD to be applied to the first source region 511 of the first transistor T1.

[0123] The initialization voltage line 174 can be connected to the second electrode 530 of the first capacitor Cst via the second contact CNT2 formed on the sixth insulating layer l6. This allows the initialization voltage VINT to be stored in the first capacitor Cst.

[0124] The first insulating layer l1, the second insulating layer l2, the third insulating layer l3, the fourth insulating layer l4, the fifth insulating layer l5, the sixth insulating layer l6, the seventh insulating layer l7, the eighth insulating layer l8, and the ninth insulating layer l9 may each be formed of silicon nitride and / or silicon oxide.

[0125] The tenth insulating layer l10 can be formed on the eighth conductive layer to cover the eighth conductive layer. The ninth conductive layer, including the eighth contact portion CNT8, can be formed on the tenth insulating layer l10.

[0126] The eighth contact CNT8 can be electrically connected to the third drain region 555 of the third transistor T3 and the first drain region 513 of the first transistor T1 via the seventh contact CNT7 located on the ninth insulating layer l9 and the fourth contact CNT4 located on the seventh insulating layer l7. The eighth contact CNT8 can also be electrically connected to the pixel electrode 410 of the light-emitting element 400. That is, the pixel electrode 410 of the light-emitting element 400 can be electrically connected to the first drain region 513 of the first transistor T1 and the third drain region 555 of the third transistor T3 via the eighth contact CNT8.

[0127] The eleventh insulating layer l11 can be formed on the ninth conductive layer to cover the ninth conductive layer. The light-emitting element 400 can be positioned on the eleventh insulating layer l11 and can include a pixel electrode 410, a common electrode 430, and an intermediate layer 420 between the pixel electrode 410 and the common electrode 430 and including an emission layer. The light-emitting element 400 can be, for example, an organic light-emitting diode (OLED).

[0128] In one embodiment, pixel electrode 410 may be the anode of an organic light-emitting diode (OLED), and common electrode 430 may be the cathode of an organic light-emitting diode (OLED). However, this disclosure is not limited thereto, and depending on the driving method of the display device 10, pixel electrode 410 may be the cathode of an organic light-emitting diode (OLED), and common electrode 430 may be the anode of an OLED. When holes and electrons are injected into the intermediate layer 420 from pixel electrode 410 and common electrode 430, respectively, excitons are generated through recombination of the injected holes and electrons. Excitons can transition from an excited state to a ground state, thereby emitting light.

[0129] The tenth insulating layer l10 and the eleventh insulating layer l11 can each be formed from organic materials or from a film stack comprising organic and inorganic materials. Examples of organic materials may include imide polymers, general polymers (such as polymethyl methacrylate (PMMA) or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and mixtures thereof.

[0130] The first to ninth conductive layers may include at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0131] Meanwhile, the pixel electrode 410 can be a semi-transparent electrode or a reflective electrode. When the pixel electrode 410 is a semi-transparent electrode, it can include, for example, ITO, IZO, ZnO, In2O3, IGO, or AZO. When the pixel electrode 410 is a reflective electrode, it can have a reflective film including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and their compounds, and a layer formed of ITO, IZO, ZnO, In2O3, IGO, or AZO. Of course, this disclosure is not limited thereto, and the pixel electrode 410 can include various materials and can be modified in various ways (such as having a single-layer or multi-layer structure).

[0132] A pixel defining layer 350 covering the edge of the pixel electrode 410 can be disposed on the eleventh insulating layer 111. The pixel defining layer 350 can function or define sub-pixels PX by having openings corresponding to each sub-pixel PX (i.e., openings exposing at least the central portion of the pixel electrode 410). The pixel defining layer 350 can also increase the distance between the edge of the pixel electrode 410 and the common electrode 430, thereby suppressing the occurrence of arcing therebetween. The pixel defining layer 350 can be formed of an organic material such as polyimide or hexamethyldisiloxane (HMDSO).

[0133] Intermediate layer 420 can be formed on pixel electrode 410 exposed through openings in pixel defining layer 350. Intermediate layer 420 can include low molecular weight or high molecular weight materials. When intermediate layer 420 includes low molecular weight materials, intermediate layer 420 can have a single-layer or multi-layer structure including hole injection layer (HIL), hole transport layer (HTL), emitter layer (EML), electron transport layer (ETL), or electron injection layer (EIL), and can include various organic materials including copper phthalocyanine (CuPc), N,N'-di(naphthyl-1-yl)-N,N'-diphenylbenzidine (NPB), and tri-8-hydroxyquinoline aluminum (Alq3). These layers can be formed by vacuum deposition.

[0134] When the intermediate layer 420 comprises a high molecular weight material, it can typically have a structure including a hole transport layer (HTL) and an emitter layer (EML). In this case, the hole transport layer may comprise poly(3,4-ethylenedioxythiophene) (PEDOT), and the emitter layer may comprise a high molecular weight material (such as polyphenylene acetylene (PPV) or polyfluorene). The structure of the intermediate layer 420 is not limited to the structures described above and can have various structures. For example, the intermediate layer 420 may comprise a layer that is integrally formed throughout the plurality of pixel electrodes 410, or a layer patterned to correspond to each of the plurality of pixel electrodes 410.

[0135] The common electrode 430 can be arranged to cover the display area. Figure 1 The common electrode 430 can be integrally formed to cover multiple light-emitting elements 400 (the display area DA in the image). That is, the common electrode 430 can be formed as a single unit to cover multiple light-emitting elements 400. The common electrode 430 can be a semi-transparent electrode or a reflective electrode. When the common electrode 430 is a semi-transparent electrode, it can include a layer formed of a metal with a low work function (such as Li, Ca, Al, Ag, Mg) and any of its compounds (such as LiF) or a material having a multilayer structure such as LiF / Ca or LiF / Al, and a semi-transparent conductive layer such as ITO, IZO, ZnO, or In2O3. When the common electrode 430 is a reflective electrode, it can include a layer formed of a metal (such as Li, Ca, Al, Ag, Mg) and any of its compounds (such as LiF) or a material having a multilayer structure such as LiF / Ca or LiF / Al. However, the configuration and materials of the common electrode 430 are not limited thereto, and various modifications can be made to the common electrode 430.

[0136] Figure 8 This is a schematic diagram illustrating an example in which an electronic device including a display device according to an embodiment is implemented as a head-mounted display.

[0137] Reference Figure 8The electronic device, including the display device, can be implemented as a head-mounted display (HMD) 800. The HMD 800 may include a display unit 810, a main unit 820, and a wearing unit 830.

[0138] For example, the display unit 810 may include according to Figures 1 to 7 The display device 10 of the embodiment implements a screen. The main unit 820 may include a controller, a touch sensor, or an acoustic sensor that applies scanning signals and data signals to the display unit 810. A user may wear the HMD 800 using the wearing unit 830.

[0139] However, this is merely illustrative, and the electronic device is not limited to the HMD 800. For example, the electronic device can be any electronic device including display devices (such as virtual reality (VR) devices, mobile phones, smartphones, digital televisions (TVs), 3D televisions, personal computers (PCs) (such as tablet computers or laptop computers), home appliances, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigators, etc.).

[0140] According to one or more embodiments, two sub-pixels that are perpendicularly adjacent to each other can share a first voltage line, and a first transistor and a second transistor can be positioned on different layers such that the gate electrode of the first transistor and the source or drain region of the second transistor are electrically connected through a contact hole, thereby providing a display device with improved integration density.

[0141] However, the effects that can be obtained through this disclosure are not limited to those described above, and those skilled in the art will clearly understand other technical effects not mentioned in the above description of this disclosure.

[0142] While this disclosure has been described herein with reference to a limited number of embodiments and accompanying drawings, it is not limited thereto, and it will be apparent to those skilled in the art that various modifications and alterations may be made to this disclosure within the technical aspects of the disclosure and within the equivalent scope of the appended claims.

Claims

1. A display device, wherein, The display device includes: Base; A first transistor is positioned on the substrate, and the first transistor includes a first semiconductor layer and a first gate electrode; A second transistor is positioned on top of the first transistor, and the second transistor includes a second semiconductor layer and a second gate electrode; and A light-emitting element is positioned on the second transistor and electrically connected to the first transistor. The first gate electrode of the first transistor and the second semiconductor layer of the second transistor are electrically connected to each other through a contact hole.

2. The display device according to claim 1, wherein, The display device further includes: A conductive layer is positioned on an insulating layer covering the second semiconductor layer, and the conductive layer is electrically connected to the first gate electrode and the second semiconductor layer through contact holes. At least a portion of the conductive layer overlaps perpendicularly with the first gate electrode and the second semiconductor layer.

3. The display device according to claim 1, wherein, The contact hole exposes the side surface of the source region of the second transistor.

4. The display device according to claim 1, wherein, The display device further includes: The third transistor is located on the same layer as the second transistor. The third transistor includes the second semiconductor layer and the third gate electrode.

5. The display device according to claim 4, wherein, The display device further includes: The first scan line and the second scan line are positioned on the same layer between the first transistor and the second transistor. Wherein, the first scan line and the second gate electrode together form the dual gate of the second transistor, and The second scan line, together with the third gate electrode, forms the dual gate of the third transistor.

6. The display device according to claim 5, wherein, The first scan line and the second scan line are arranged parallel to each other.

7. The display device according to claim 5, wherein, The display device further includes: The first voltage line and the initialization voltage line are located on the same layer between the second gate electrode and the light-emitting element.

8. The display device according to claim 7, wherein, The first voltage line and the initialization voltage line are arranged parallel to the first scan line.

9. The display device according to claim 7, wherein, Two sub-pixels share a first voltage, and the two sub-pixels are arranged adjacent to each other in a direction perpendicular to the longitudinal direction of the first voltage line.

10. The display device according to claim 1, wherein, The first semiconductor layer comprises polycrystalline silicon, and the second semiconductor layer comprises an oxide semiconductor.

11. A display device, wherein, The display device includes: The substrate includes a display area and a peripheral area located outside the display area; Multiple sub-pixels are positioned in the display area; and Multiple first voltage lines extend in a first direction and are configured to apply a first voltage to the multiple sub-pixels. Wherein, two sub-pixels among the plurality of sub-pixels share a first voltage line among the plurality of first voltage lines, and the two sub-pixels are arranged adjacent to each other in a second direction perpendicular to the first direction relative to the first voltage line.

12. The display device according to claim 11, wherein, The two sub-pixels are symmetrical with respect to the first voltage line.

13. The display device according to claim 11, wherein, Each of the two sub-pixels includes a first scan line, a second scan line, and an initialization voltage line parallel to the first direction.

14. The display device according to claim 11, wherein, Each of the plurality of sub-pixels includes: A first transistor is positioned on the substrate, and the first transistor includes a first semiconductor layer and a first gate electrode; A second transistor is positioned on top of the first transistor, and the second transistor includes a second semiconductor layer and a second gate electrode; and A light-emitting element is positioned on the second transistor and electrically connected to the first transistor, and The first gate electrode of the first transistor and the second semiconductor layer of the second transistor are electrically connected to each other through a contact hole.

15. The display device according to claim 14, wherein, The display device further includes: A conductive layer is positioned on an insulating layer covering the second semiconductor layer, and the conductive layer is electrically connected to the first gate electrode and the second semiconductor layer through contact holes. At least a portion of the conductive layer overlaps perpendicularly with the first gate electrode and the second semiconductor layer.

16. The display device according to claim 14, wherein, The contact hole exposes the side surface of the source region of the second transistor.

17. The display device according to claim 14, wherein, The display device further includes: The third transistor is located on the same layer as the second transistor. The third transistor includes the second semiconductor layer and the third gate electrode.

18. The display device according to claim 17, wherein, The display device further includes: The first scan line and the second scan line are positioned on the same layer between the first transistor and the second transistor. Wherein, the first scan line and the second gate electrode together form the dual gate of the second transistor, and The second scan line, together with the third gate electrode, forms the dual gate of the third transistor.

19. The display device according to claim 14, wherein, In a plan view, the area of ​​the first gate electrode is larger than the area of ​​the channel region of the first transistor.

20. The display device according to claim 14, wherein, The first semiconductor layer comprises polycrystalline silicon, and the second semiconductor layer comprises an oxide semiconductor.

21. An electronic device, wherein, The electronic device includes: A display device, wherein the display device includes: Base; A first transistor is positioned on the substrate, and the first transistor includes a first semiconductor layer and a first gate electrode; A second transistor is positioned on top of the first transistor, and the second transistor includes a second semiconductor layer and a second gate electrode; and A light-emitting element is positioned on the second transistor and electrically connected to the first transistor. The first gate electrode of the first transistor and the second semiconductor layer of the second transistor are electrically connected to each other through a contact hole.

Images