Display panel and display device

Abstract

The invention provides a display panel and a display device, and relates to the technical field of display, and a first connecting metal layer is located between an array layer and a first flat layer; the first connecting metal layer comprises a first connecting metal part; the first flat layer comprises a first opening, and the first opening exposes the first connecting metal part; the first insulating layer is located on the side, away from the array layer, of the flat layer and comprises a first insulating part and a second insulating part which are connected with each other, the first insulating part is located outside the first opening, the second insulating part is located in the first opening, and the second insulating part comprises a second opening exposing the first connecting metal part. The anode layer comprises a first anode part and a second anode part which are connected with each other, the first anode part is located on the surface of the side, away from the array layer, of the first insulation part, and the second anode part is located on the surface of the side, away from the array layer, of the second insulation part and electrically connected with the first connecting metal part through the second opening. Introduction of the first insulating layer facilitates improvement of anode flatness and the display effect.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the continuous development of science and technology, more and more display products, such as mobile phones, tablets, laptops and smart wearable devices, are being widely used in people's daily lives and work, bringing great convenience to people's daily lives and work, and becoming an indispensable tool for people today.

[0003] For OLED (Organic Light Emitting Diode) display panels, the flatness of the anode directly affects the morphology of the sequentially deposited organic light-emitting layer and cathode, thus directly impacting the display uniformity of the light-emitting elements. Therefore, improving the flatness of the anode to enhance display uniformity is one of the most pressing technical challenges in OLED panel manufacturing. Summary of the Invention

[0004] To address the aforementioned technical problems, this disclosure provides a display panel and display device, which aim to improve anode flatness and enhance the display uniformity of display products.

[0005] In a first aspect, this disclosure provides a display panel, including an array layer, a first connecting metal layer, a first planarization layer, a first insulating layer, and an anode layer. The first connecting metal layer is located between the array layer and the first planarization layer. The first connecting metal layer includes a first connecting metal portion. The first planarization layer includes a first opening that penetrates the first planarization layer along the thickness direction of the display panel and exposes the first connecting metal portion. The first insulating layer is located on the side of the planarization layer opposite to the array layer. The first insulating layer includes a first insulating portion and a second insulating portion that are interconnected. The first insulating portion is located outside the first opening, and the second insulating portion is located within the first opening. The second insulating portion includes a second opening that exposes the first connecting metal portion. The anode layer is located on the side of the first insulating layer opposite to the array layer. The anode layer includes a first anode portion and a second anode portion that are interconnected. The first anode portion is located on the surface of the first insulating portion opposite to the array layer, and the second anode portion is located on the surface of the second insulating portion opposite to the array layer and is electrically connected to the first connecting metal portion through a second opening.

[0006] In a second aspect, this disclosure provides a display device, including the display panel provided in the first aspect of this disclosure.

[0007] The technical solution provided in this disclosure has the following advantages compared with the prior art: In the display panel provided in this embodiment, a first insulating layer is introduced between the first planarization layer and the anode layer. Outside the first opening, the first insulating portion, as a film layer of a certain thickness, is deposited on the side of the first planarization layer facing away from the array layer, thereby providing a more rigid and stable support platform for the first anode portion in the anode layer. This first insulating portion can cover and smooth any minor defects and roughness that may remain in the first planarization layer, providing a higher quality and more uniform interface for the deposition of the upper first anode portion. This also ensures that the first anode portion has high flatness, thereby guaranteeing uniform deposition of the organic light-emitting layer on it, avoiding the impact of a rough interface on the efficiency of the OLED device, and improving the final display uniformity and luminous efficiency.

[0008] Furthermore, in this embodiment, the first insulating layer is divided into a flat first insulating portion and a second insulating portion located in the first opening, and the anode layer is divided into a flat first anode portion and a second anode portion located in the first opening. The second opening on the first insulating layer is disposed inside the first opening on the first flat layer, and the second opening directly exposes the first connecting metal portion. When etching the second insulating portion in the first insulating layer to form the second opening, the etched second insulating portion is the part that directly contacts the first connecting metal portion, rather than the part that contacts the first flat layer. Because the selectivity of the etching of the first insulating layer for the first connecting metal portion is relatively high, the problem of over-etching the first flat layer is avoided. Furthermore, since the etched portion of the second insulating part is in direct contact with the first connecting metal part, the edge of the second insulating part can more easily form a positive cone angle during the etching process to form the second opening, rather than the chamfered angle formed when etching the first planar layer. This is beneficial to improving the inner wall morphology of the second opening and avoiding the formation of a gap when the second anode part crosses the boundary of the second insulating part (inner wall of the second opening) in the second opening. Thus, when the second anode part is electrically connected to the first connecting metal part through the second opening, the problem of broken lines or missing pixels in the second anode is fundamentally avoided, effectively improving the reliability of the anode layer. Attached Figure Description

[0009] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0010] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 The figure shown is a planar structural diagram of a display panel provided in an embodiment of this disclosure; Figure 2 The diagram shown is a schematic diagram of a film layer of a display panel provided in an embodiment of this disclosure; Figure 3 A schematic diagram of another film layer of the display panel shown; Figure 4 The diagram shows the mechanism of anode layer breakage during the etching of the first insulating layer. Figure 5 The diagram shown illustrates the relative positional relationship between pixel openings, the first opening, and the second opening in a display panel provided in this embodiment of the present disclosure. Figure 6 The figure shown is a plan view of a first insulating part, a second insulating part, a first anode part, and a second anode part in a display panel provided in an embodiment of this disclosure; Figure 7 The diagram shown is a planar structural diagram of the cathode layer in a display panel provided in an embodiment of this disclosure; Figure 8 As shown Figure 7 An enlarged schematic diagram of region Q in the middle; Figure 9 The diagram shown is a schematic of a film layer at the pixel opening and touch opening in a display panel provided in an embodiment of this disclosure; Figure 10 The diagram shown is a schematic diagram of another film layer at the pixel opening and touch opening in the display panel provided in the embodiment of this disclosure; Figure 11 The diagram shown is an enlarged schematic of an undercut space; Figure 12 The diagram shown is a schematic diagram of another film layer at the pixel opening and touch opening in the display panel provided in the embodiment of this disclosure; Figure 13 The diagram shown is a schematic diagram of another film layer at the pixel opening and touch opening in the display panel provided in this embodiment of the present disclosure; Figure 14 The diagram shows one possible arrangement of the touch electrodes and display cathode in a display panel. Figure 15 The diagram shows another arrangement of the touch electrodes and display cathode in the display panel; Figure 16 The diagram shown is a schematic diagram of another film layer at the pixel opening and touch opening in the display panel provided in the embodiment of this disclosure; Figure 17 The diagram shows another arrangement of the touch electrodes and display cathode in the display panel; Figure 18 The diagram shown is a structural schematic of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0012] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0013] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0014] Figure 1 The diagram shown is a planar structural diagram of a display panel provided in an embodiment of this disclosure. The display panel 100 includes a plurality of light-emitting elements D0, which are driven by a driving circuit P0 to achieve the light-emitting function. It should be noted that... Figure 1 The arrangement of the light-emitting element D0 and the driving circuit P0 is merely illustrative and is not intended to limit the scope of this disclosure. For example, the display panel 100 provided in this disclosure may be an OLED display panel.

[0015] Figure 2 The diagram illustrates a film layer of a display panel according to an embodiment of this disclosure, showing the film layer structure corresponding to a light-emitting element in the display panel. In the display panel, an array layer 40 is disposed on one side of a substrate 00. The basic structure of the light-emitting element D0 includes an anode layer 31, a light-emitting functional layer 32, and a cathode layer 30. Along a direction perpendicular to the substrate 00, the anode layer 31 and the cathode layer 30 are located on opposite sides of the light-emitting functional layer 32, with the anode layer 31 located on the side of the cathode layer 30 facing the substrate 00. The anode layer 31 is electrically connected to the array layer 40, which contains a pixel driving circuit. The pixel driving circuit P0 includes at least one transistor T, which is electrically connected to the anode layer 31 and provides a driving voltage to the light-emitting element D0, driving the light-emitting element D0 to emit light. The light-emitting functional layer 32 includes an organic light-emitting material. When an appropriate voltage is supplied, holes generated in the anode layer 31 and electrons generated in the cathode layer 30 combine in the light-emitting functional layer 32, producing light.

[0016] Optionally, an encapsulation layer 50 is provided on the side of the cathode layer 30 of the light-emitting element D away from the anode layer 31. Optionally, the encapsulation layer 50 includes an organic encapsulation layer 51 and two inorganic encapsulation layers 52 stacked together. The organic encapsulation layer 51 is located between the two inorganic encapsulation layers 52 and is used to isolate the light-emitting element from the external environment to avoid the influence of external moisture and oxygen on the light-emitting element.

[0017] Please continue to refer to this. Figure 1 and Figure 2The display panel 100 provided in this embodiment includes an array layer 40, a first connecting metal layer 10, a first planarization layer 80, a first insulating layer 20, and an anode layer 31. The first connecting metal layer 10 is located between the array layer 40 and the first planarization layer 80. The first connecting metal layer 10 includes a first connecting metal portion 11. The first planarization layer 80 includes a first opening K1. Along the thickness direction of the display panel, the first opening K1 penetrates the first planarization layer 80 and exposes the first connecting metal portion 11.

[0018] The first insulating layer 20 is located on the side of the planarization layer opposite to the array layer 40. The first insulating layer 20 includes a first insulating portion 21 and a second insulating portion 22 that are connected to each other. The first insulating portion 21 is located outside the first opening K1, and the second insulating portion 22 is located in the first opening K1. The second insulating portion 22 includes a second opening K2 that exposes the first connecting metal portion 11.

[0019] The anode layer 31 is located on the side of the first insulating layer 20 away from the array layer 40. The anode layer 31 includes a first anode portion 311 and a second anode portion 312 connected to each other. The first anode portion 311 is located on the side surface of the first insulating portion 21 away from the array layer 40, and the second anode portion 312 is located on the side surface of the second insulating portion 22 away from the array layer 40 and is electrically connected to the first connecting metal portion 11 through the second opening K2.

[0020] Considering that the array layer 40 of an OLED display panel typically contains complex driving circuits and metal wiring, these structures can create significant undulations and unevenness. Introducing a first planarization layer 80 into the display panel can improve these undulations and unevenness. However, the first planarization layer 80 (typically an organic layer) itself may still have certain defects or deformations under high temperature or stress, resulting in unevenness on the surface of the first planarization layer 80 away from the array layer 40. Therefore, in the display panel provided in this embodiment, a first insulating layer 20 is introduced between the first planarization layer 80 and the anode layer 31. In this disclosure, the first planarization layer 80 includes a first opening K1 exposing a first connecting metal portion 11, a first insulating portion 21 in the first insulating layer 20 is disposed in a flat area outside the first opening K1, a second insulating portion 22 is disposed in the first opening K1, and the second insulating portion 22 in the first opening K1 also has a second opening K2 exposing the first connecting metal portion 11. The first anode portion 311 in the anode layer 31 is located above the flat first insulating portion 21, the second anode portion 312 is located in the first opening K1 and on the surface of the second insulating portion 22, and part of the second anode portion 312 is located in the second opening K2 and is electrically connected to the first connecting metal portion 11 in the second opening K2.

[0021] As can be seen, outside the first opening K1, the first insulating portion 21, as a film layer of a certain thickness, is deposited on the side of the first planarization layer 80 opposite to the array layer 40, thereby providing a more rigid and stable support platform for the first anode portion 311 in the anode layer 31. This first insulating portion 21 can cover and smooth any minor defects and roughness that may remain in the first planarization layer 80, providing a higher quality and more uniform interface for the deposition of the upper first anode portion 311. Optionally, the first insulating layer 20 is an inorganic layer.

[0022] The luminous efficiency and lifetime of OLED devices are highly sensitive to the morphology of the anode surface. If the anode surface is rough or has sharp steps, it can lead to uneven deposition of the subsequent organic light-emitting layer, affecting luminous efficiency. It can also cause uneven electric field distribution, potentially resulting in excessively high local current density, forming dark spots, or accelerating device aging. In this disclosure, the area above the first anode portion 311 of the anode layer 31 can be used to deposit the subsequent organic light-emitting layer. Since the first insulating portion 21 has already planarized any minor defects and roughness that may exist in the first planarization layer 80, the first anode portion 311 also has high flatness, thus ensuring uniform deposition of the organic light-emitting layer on it. This avoids the impact of a rough interface on the OLED device efficiency, improving the final display uniformity and luminous efficiency.

[0023] Figure 3 The diagram shows another type of film layer in the display panel, which is similar to... Figure 2 The difference lies in the etching process. Openings are formed by etching the first insulating layer 20 and the first planarization layer 80, respectively. The anode layer 31 is electrically connected to the lower first connecting metal portion 11 through these openings. In this structure, when etching the first insulating layer 20, the etched portion is in direct contact with the first planarization layer 80. If the etching process of the first insulating layer 20 has a low selectivity for the lower first planarization layer 80, the lower first planarization layer 80 will also be etched simultaneously when the first insulating layer 20 is etched to form an opening, resulting in over-etching of the lower first planarization layer 80. Furthermore, etching the first insulating layer 20 is prone to side etching, for example, please refer to [reference needed]. Figure 4 Especially at the lateral edges of the first insulating layer 20, a chamfer exists after etching. When the anode layer 31 crosses the lateral boundary of the first insulating layer 20, the chamfer caused by etching and over-etching of the first planarization layer 80 can lead to poor morphology of the anode layer 31 at this point, and may even result in broken lines, such as gaps forming between the side of the first insulating layer 20 and the anode layer 31. During subsequent wet etching of the anode layer 31, the etching solution can seep into the structure from the gaps on the side of the first insulating layer 20, potentially leading to the loss of the entire pixel. Figure 4The diagram shows the mechanism by which the anode layer 31 is broken during the etching process of the first insulating layer 20.

[0024] To solve the above problems, please refer to... Figure 2 In this embodiment, the first insulating layer 20 is divided into a flat first insulating portion 21 and a second insulating portion 22 located in the first opening K1, and the anode layer 31 is divided into a flat first anode portion 311 and a second anode portion 312 located in the first opening K1. The second opening K2 on the first insulating layer 20 is disposed inside the first opening K1 on the first planarization layer 80, and the second opening K2 directly exposes the first connecting metal portion 11. Thus, when the second insulating portion 22 in the first insulating layer 20 is etched to form the second opening K2, the etched second insulating portion 22 is the portion that directly contacts the first connecting metal portion 11, rather than the portion that contacts the first planarization layer 80. Because the selectivity of the etching of the first insulating layer 20 for the first connecting metal portion 11 is relatively high, the problem of over-etching the first planarization layer 80 is avoided. Furthermore, since the etched portion of the second insulating portion 22 is in direct contact with the first connecting metal portion 11, during the etching process of the second insulating portion 22 to form the second opening K2, the edge of the second insulating portion 22 can more easily form a positive cone angle, rather than the chamfer angle formed when etching to the first planarization layer 80. This is beneficial to improving the inner wall morphology of the second opening K2 and preventing the second anode portion 312 from forming a gap when crossing the boundary of the second insulating portion 22 (inner wall of the second opening K2) in the second opening K2. Thus, when the second anode portion 312 is electrically connected to the first connecting metal portion 11 through the second opening K2, the problem of broken lines or missing pixels in the second anode is fundamentally avoided, effectively improving the reliability of the anode layer 31.

[0025] Figure 5 The diagram shown illustrates the relative positions of pixel opening K3, first opening K1, and second opening K2 in a display panel provided in this embodiment. Please refer to the diagram. Figure 2 and Figure 5 In one optional embodiment of this disclosure, the display panel further includes a pixel definition layer 60, which is located on the side of the anode layer 31 away from the array layer 40. The pixel definition layer 60 includes a plurality of pixel openings K3. Along the thickness direction of the display panel, the pixel openings K3 penetrate the pixel definition layer 60 and expose the first anode portion 311, and the pixel definition layer 60 covers the second anode portion 312.

[0026] Organic light-emitting material is filled in the pixel opening K3. In this disclosure, the pixel opening K3 in the pixel defining layer 60 precisely defines the deposition area of ​​the organic light-emitting material, thereby defining the actual light-emitting area of ​​each pixel. The second anode portion 312 is the portion of the anode layer 31 located above the second opening K2 of the first insulating layer 20, and electrically connected to the first connecting metal portion 11 through the second opening K2. The pixel defining layer 60 covers the second anode portion 312, that is, it covers the electrical connection area between the anode and the first connecting metal portion 11. This effectively isolates the connection area from the subsequently deposited cathode layer, preventing short circuits between the cathode and anode near the connection point. The pixel opening K3 of the pixel defining layer 60 exposes the first anode portion 311, which is the portion of the anode layer 31 located above the flat first insulating portion 21 of the first insulating layer 20. This is typically the main light-emitting area of ​​the pixel. The pixel opening K3 precisely defines the area where the organic light-emitting layer will be deposited, ensuring that the light-emitting process only occurs above the flat area provided by the first insulating part 21, thereby maximizing the display uniformity by utilizing the flatness provided by the first insulating part 21.

[0027] Please continue to refer to this. Figure 5 In one optional embodiment of this disclosure, a first gap exists between pixel opening K3 and first opening K1 along a direction parallel to the plane of the display panel. The width of the first gap is S, where S ≥ 6 μm. First opening K1 is located on the first planarization layer 80 and is a relatively large via for exposing the first connecting metal portion 11. Second opening K2 on the second insulating portion 22 is located within the first opening K1.

[0028] The aforementioned first interval refers to the minimum distance between the boundary of the first opening K1 corresponding to the first planarization layer 80 and the boundary of the pixel opening K3. That is, the minimum distance between the boundary of the pixel opening K3 near the first opening K1 and the boundary of the first opening K1 near the pixel opening K3.

[0029] In OLED manufacturing, organic materials such as organic light-emitting material layers and electron transport layers are typically deposited via vapor deposition. The stepped structure of the pixel defining layer 60 is used to pattern the organic layer. If the pixel opening K3 (the organic light-emitting material deposition area) is too close to the first opening K1 of the first planarization layer 80 (e.g., less than 6 μm), during the vapor deposition process, some organic light-emitting material may indirectly deposit onto the inner wall of the first opening K1 or even the edge of the connection area of ​​the first connecting metal portion 11 through vapor diffusion or oblique deposition. Therefore, setting a first gap of S≥6 μm provides sufficient lateral safety distance. This ensures that the vapor-deposited organic light-emitting material does not contaminate or come into contact with the area below the first planarization layer 80 used to connect the first connecting metal portion 11, thereby maintaining the electrical insulation of the connection area.

[0030] Furthermore, sufficient spacing ensures a clear boundary between the light-emitting area (first anode portion 311) and the electrical connection area (second anode portion 312) of the anode layer 31. This avoids interference caused by the light-emitting current path and the connection path being too close in space, while further ensuring that the pixel definition layer 60 can effectively cover the connection area (second anode portion 312), preventing short circuits at the connection point between the cathode and the first connection metal portion 11.

[0031] Please continue to refer to this. Figure 2 and Figure 5 In one optional embodiment of this disclosure, the first anode portion 311 and the second anode portion 312 are not in contact with the first planarization layer 80. If the anode layer 31 is directly deposited on the first planarization layer 80, the chemical solutions used in the subsequent etching and cleaning processes of the anode layer 31 may penetrate or corrode the organic film corresponding to the underlying first planarization layer 80, affecting the insulation and planarity of the first planarization layer 80. Since both the first anode portion 311 and the second anode portion 312 in the anode layer 31 are not in contact with the first planarization layer 80, it indicates that the anode layer 31 is completely isolated and supported by the upper first insulating layer 20. The first insulating layer 20 is an important insulating medium located between the first connecting metal portion 11 and the anode layer 31. The fact that the anode layer 31 is not in contact with the first planarization layer 80 (i.e., is completely isolated by the first insulating layer 20) maximizes the integrity of the first planarization layer 80 as an insulating layer.

[0032] In this design, the opening (second opening K2) on the first insulating layer 20 is designed inside the opening (first opening K1) on the first planarization layer 80, so that the edge of the first insulating layer 20 is etched onto the metal layer where the first connecting metal portion 11 is located. The etching of the first insulating layer 20 has a high selectivity for the first connecting metal portion 11, so the etching process of the first insulating layer 20 will not cause over-etching of the first connecting metal portion 11, thereby fundamentally avoiding the problems of low selectivity etching and over-etching of the organic film of the first planarization layer 80.

[0033] Please continue to refer to this. Figure 5 In one optional embodiment of this disclosure, the minimum width of the second opening K2 along a direction parallel to the plane of the display panel is C, where C ≥ 2 μm. Here, the minimum width can be understood as the minimum diameter. The second opening K2 is an opening located on the second insulating portion 22 in the first insulating layer 20, penetrating the second insulating portion 22 to expose the underlying first connecting metal portion 11.

[0034] In an OLED display panel, the first connecting metal portion 11, connected to the anode layer 31, performs the function of transmitting electrical signals to the anode. The size of the second opening K2 directly determines the contact area between the second anode portion 312 in the anode layer 31 and the first connecting metal portion 11. If the size of the second opening K2 is too small (e.g., C < 2 μm), the contact area between the second anode portion 312 and the first connecting metal portion 11 will decrease, thereby increasing the contact resistance between them. Therefore, in this embodiment, C ≥ 2 μm is set to ensure sufficient contact area between the second anode portion 312 and the first connecting metal portion 11, effectively reducing the contact resistance. For the first connecting metal portion 11, which carries a large current, this can significantly reduce IR drop (voltage drop), ensuring the reliability of signal transmission and the uniformity of current.

[0035] Considering that the second anode portion 312 needs to be completely deposited and cover the inner wall and bottom of the second opening K2 to ensure the reliability of the connection between the second anode portion 312 and the first connecting metal portion 11, if the width of the second opening K2 is too small, the second anode portion 312 will not completely cover the inner wall of the second opening K2. A relatively large width (aperture) helps to reduce the aspect ratio of the second opening K2, ensuring that the subsequently deposited anode layer 31 can more easily and completely cover the aperture wall and overlap well with the first connecting metal portion 11, preventing voids or weak points in the connection area, and further ensuring the reliability of the electrical connection.

[0036] In semiconductor and flat panel display manufacturing, lithography and etching errors increase dramatically when feature sizes approach the resolution limits of lithography equipment and materials. Smaller apertures place extremely high demands on lithographic alignment and etching uniformity. Setting the minimum width of the second aperture K2 to 2μm or more ensures a sufficiently large process window. This makes the lithography and etching processes more tolerant of parameters such as exposure energy, development time, and etching time, reducing defect rates caused by manufacturing fluctuations (e.g., incomplete aperture opening, aperture collapse), thereby improving product yield and production stability.

[0037] Please continue to refer to this. Figure 5 In one optional embodiment of this disclosure, the thickness of the second anode portion 312 that overlaps with the second opening K2 along the thickness direction of the display panel is greater than the thickness of the other second anode portions 312 that contact the second insulating portion 22.

[0038] The second insulating portion 22 refers to the portion of the first insulating layer 20 located inside the first opening K1. This second insulating portion 22 includes a sidewall portion that contacts the sidewall of the first opening K1 and a bottom portion that contacts the bottom of the first opening K1. The second anode portion 312 refers to the anode layer 31 located above the second insulating portion 22. The first anode portion 311 includes a sidewall anode that contacts the sidewall portion of the second insulating portion 22, a bottom anode that contacts the bottom portion of the second insulating portion 22, and a second anode portion 312 (which can be understood as a contact anode that actually performs the electrical connection function) that overlaps with the second opening K2 along the thickness direction of the display panel. The second anode portion 312 located on one side surface of the second insulating portion 22 refers to the aforementioned sidewall anode. It should be noted that the aforementioned sidewall anode, bottom anode, and contact anode are electrically connected and form an electrical connection with the first anode portion 311 outside the first opening K1, thereby enabling the electrical signal received through the contact anode to be stably transmitted to the first anode portion 311 outside the first opening K1, achieving control over the light emission of the corresponding light-emitting element.

[0039] The anode layer 31 has the greatest thickness in the second opening K2, ensuring that the anode layer 31 has the lowest internal resistance in this critical overlapping area. At the same time, this ensures high quality of the contact interface and the lowest contact resistance between the second anode portion 312 and the first connecting metal portion 11, effectively preventing heat generation and IR drop at the connection point.

[0040] Please continue to refer to this. Figure 5 In one optional embodiment of this disclosure, the second insulating portion 22 is disposed around the second opening K2, and at least a portion of the second insulating portion 22 is in direct contact with the first connecting metal portion 11; the width of the second insulating portion 22 in direct contact with the first connecting metal portion 11 is B, where B ≥ 0.9 μm.

[0041] For example, please refer to the relevant technologies. Figure 3 and Figure 4 The etched edge of the first insulating layer 20 falls on the first planarization layer 80, forcing the anode layer 31 to cross the step of the first planarization layer 80, which easily leads to wire breakage. This solution addresses this by ensuring that the second insulating portion 22 at least partially contacts the first connecting metal portion 11, and setting the width B of the second insulating portion 22 directly in contact with the first connecting metal portion 11 to be ≥0.9μm. This ensures that the boundary of the second opening K2 completely falls on the first connecting metal portion 11. This guarantees that when the anode layer 31 crosses the boundary of the second insulating portion 22, the underlying support it crosses is the first connecting metal portion 11, not the first planarization layer 80, thus fundamentally avoiding the problem of the anode layer 31 crossing the step of the first planarization layer 80 and eliminating the risk of wire breakage.

[0042] Since the boundary of the second opening K2 falls entirely on the first connecting metal portion 11, the lower contact material etched by the second insulating portion 22 changes from the first planarization layer 80, which has a low selectivity to the first insulating layer 20, to a metal layer (first connecting metal portion 11), which has a high selectivity to the first insulating layer 20. This facilitates the formation of a positive cone angle at the edge of the first opening K1 during the etching process, avoiding the chamfered angle caused by etching the first planarization layer 80 in conventional solutions. The positive cone angle of the first opening K1 sidewall helps improve the morphology of the anode layer 31, preventing gaps from forming between the edge of the first insulating layer 20 and the anode layer 31. This prevents the wet etching solution from seeping into the anode layer 31 through these gaps, thus avoiding pixel loss.

[0043] The aforementioned width B actually refers to the distance between the boundary of the second insulating portion 22 and the edge of the first planarization layer 80, which is actually the difference between the radius of the first opening K1 and the radius of the second opening K2. B ≥ 0.9 μm provides sufficient safety margin to ensure that, in actual production, even with photolithography and overlay errors, the boundary of the second insulating portion 22 can still stably fall on the first connecting metal portion 11 and stay away from the edge of the first planarization layer 80, thereby achieving structural design stability.

[0044] Please continue to refer to this. Figure 5 In one optional embodiment of this disclosure, in the first opening K1, the sidewall of the second insulating part 22 that is in direct contact with the first connecting metal part 11 is the first sidewall B1. The first sidewall B1 constitutes the inner wall of the second opening K2. Along the direction from the first anode part 311 to the first connecting metal part 11, the width of the second opening K2 tends to decrease. The acute angle in the angle between the first sidewall B1 and the first connecting metal part 11 is α, where 0 < α ≤ 60°.

[0045] Considering that if the first sidewall B1 of the second insulating portion 22 is perpendicular or nearly perpendicular to the first connecting metal portion 11, for example, α > 60°, the subsequently deposited anode layer 31 will become extremely thin at the bottom corner of the first sidewall B1 and the second opening K2 due to geometric shading effects, and may even break. Therefore, setting α ≤ 60° provides sufficient smoothness to the first sidewall B1, allowing the deposition material of the anode layer 31 to cover the sidewall more uniformly, avoiding excessive thinning and discontinuity of the film.

[0046] Because the anode layer 31 maintains sufficient thickness and continuity on the first sidewall B1, the conductive path of the anode layer 31 from the top of the second opening K2 corresponding to the second insulating part 22 to the bottom overlapping area of ​​the first connecting metal part 11 is ensured to be intact. This ensures that the anode layer 31 can reliably overlap with the first connecting metal part 11 in a high-quality, low-resistance manner, which helps to reduce the contact resistance at the connection point.

[0047] 60° is a critical engineering limit in semiconductor and flat panel display manufacturing for ensuring good step coverage in processes such as physical vapor deposition. Therefore, setting 0 < α ≤ 60° establishes a clear and controllable process window for the etching process of the first insulating layer 20. This helps to stabilize mass production and avoid yield losses caused by fluctuations in sidewall angles.

[0048] Please continue to refer to this. Figure 5 In one optional embodiment of this disclosure, the width of the first opening K1 decreases along the direction from the first anode portion 311 to the first connecting metal portion 11; in the first opening K1, the second sidewall B2 of the first flat layer 80 constitutes the inner wall of the first opening K1, and the acute angle between the second sidewall B2 and the first connecting metal portion 11 is θ, where 50°≤θ≤80°.

[0049] If the second sidewall B2 corresponding to the first opening K1 of the first flattening layer 80 is too steep (e.g., θ > 80° or even close to 90°), the subsequent deposition of the first insulating layer 20 will result in poor step coverage when crossing the first opening K1, easily leading to stress concentration or discontinuity at the bottom of the hole, thus affecting its flatness and support. If θ < 50°, it is difficult to achieve the effect of α ≤ 60° mentioned in the aforementioned embodiment.

[0050] Therefore, in this embodiment, 50°≤θ≤80° is set to ensure that the second sidewall B2 of the first flat layer 80 has a gentle and controllable ramp angle. This allows the first insulating layer 20 deposited thereon to form a smoother, less stressful transition structure, ensuring both the effective size of the connection area and providing a good support morphology for the first insulating layer 20.

[0051] Furthermore, an appropriate sidewall angle for the first opening K1 helps control the sidewall morphology of the deposited first insulating layer 20, thereby affecting the perpendicularity and positional accuracy of the subsequent etching of the first insulating layer 20. This helps ensure that the sidewall of the second opening K2 can stably fall on the first connecting metal portion 11, thus achieving the technical objectives of avoiding over-etching of the first planarization layer 80 and optimizing the boundary morphology of the first insulating layer 20 in the aforementioned scheme.

[0052] Furthermore, 50°≤θ≤80° is a range of tilt angles that organic materials can easily achieve and control in photolithography and wet / dry etching. This limitation ensures that the fabrication of the first opening K1 is reliable and mass-producible, avoiding photolithography or etching difficulties caused by excessively steep angles (such as θ>80°), and also avoiding excessive occupation of effective display area due to excessively gentle angles (such as θ<50°).

[0053] Please continue to refer to this. Figure 5In one optional embodiment of this disclosure, the minimum width of the first opening K1 along the direction parallel to the plane of the display panel is D, where D≤5μm. This minimum width can be regarded as the bottom width of the first opening K1, i.e., the minimum inner diameter.

[0054] In this disclosure, the first opening K1 is located on the first planarization layer 80 and serves as a channel connecting the first connecting metal part 11 and the upper first insulating layer 20 / anode layer 31. It does not emit light itself and belongs to the non-light-emitting area. Setting the minimum width of the first opening K1 to 5μm or less directly reduces the projected area of ​​the connecting structure on the display plane. This means that a larger area is left for the adjacent pixel opening K3 area (i.e., the actual light-emitting area). In panels with high pixel density, the area occupied by any non-light-emitting structure (such as transistors, connecting holes, wiring, etc.) directly encroaches on the light-emitting area of ​​the pixel. By setting D≤5μm, the occupation of the effective display area by the first opening K1 is minimized. While maintaining the same brightness, this helps to reduce the driving current (extending device lifespan); or while maintaining the same driving current, it improves the overall brightness of the panel.

[0055] It should be noted that the minimum width of the first opening K1 is greater than the width of the second opening K2. The minimum width D of the first opening K1 must have sufficient margin (B≥9μm) to accommodate the sidewall of the first insulating layer 20 and ensure that it falls above the first connecting metal part 11.

[0056] Figure 6 The diagram shown is a plan view of the first insulating portion 21, the second insulating portion 22, the first anode portion 311, and the second anode portion 312 in a display panel provided in an embodiment of this disclosure. Please refer to the diagram. Figure 5 and Figure 6 In one optional embodiment of this disclosure, along the thickness direction of the display panel, the outer contour of the orthographic projection of the first anode portion 311 and the second anode portion 312 is a first outer contour L1, and the outer contour of the orthographic projection of the first insulating portion 21 and the second insulating portion 22 is a second outer contour L2, with the first outer contour L1 located within the second outer contour L2. This ensures that the edge of the anode layer 31 does not exceed the range defined by the first insulating portion 21 and the second insulating portion 22 in the first insulating layer 20.

[0057] Considering that without the aforementioned constraints or in the event of photolithographic misalignment, the pattern of the anode layer 31 might extend beyond the boundary of the underlying first insulating layer 20, during subsequent wet etching of the anode layer 31 (typically used for patterning the anode layer 31), the etching solution could seep into the structure through tiny gaps at the exposed edges of the anode layer 31 or the edge of the first insulating layer 20. This would result in the erosion of a large area of ​​the anode layer 31 pixel pattern, leading to pixel loss or open circuits and extremely low yield. This disclosure requires that the outer contour of the anode layer 31 must be within the outer contour of the first insulating layer 20. This ensures that the anode layer 31 is always completely covered and protected by the inorganic support layer of the underlying first insulating layer 20. During the wet etching of the anode layer 31, the edge of the first insulating layer 20 effectively blocks the lateral penetration of the etching solution, completely eliminating the risk of pixel loss caused by bottom etching.

[0058] The pattern of the anode layer 31 is formed by photolithography and etching after the first insulating layer 20 has been formed. Overlapping errors are unavoidable during photolithography. By ensuring that the first insulating layer 20 is one size larger than the anode layer 31 (the anode layer 31 is located inside the first insulating layer 20), this structure provides a safety margin for the pattern of the anode layer 31 in the lateral direction. Even if a certain degree of overlapping deviation occurs during photolithography, the pattern of the anode layer 31 will not exceed the protection range of the first insulating layer 20, thus ensuring the process's tolerance to overlapping errors and improving production stability. The anode layer 31 is completely supported and carried by the first insulating layer 20, preventing the anode layer 31 from being suspended or contacting the unstable edge of the underlying organic film, ensuring the flatness and structural stability of the anode layer 31.

[0059] Please continue to refer to this. Figure 5 and Figure 6 In one optional embodiment of this disclosure, the distance between the first outer contour L1 and the second outer contour L2 is A, where A ≥ 0.5 μm.

[0060] The aforementioned embodiments stipulated that the anode layer 31 must be located inside the first insulating layer 20 to prevent the wet etching solution from penetrating and etching the anode layer 31. However, in actual production, alignment deviations (overlapping errors) may occur during the photolithography process. If the value of A is too small, a normal overlapping error may cause the boundary of the anode layer 31 to extend beyond the boundary of the first insulating layer 20. Setting A ≥ 0.5 μm provides a minimum safety margin. This margin ensures that even within the normal photolithography overlapping error range, the pattern boundary of the anode layer 31 remains within the boundary of the first insulating layer 20. This fundamentally guarantees the complete protection of the edge of the anode layer 31 by the first insulating layer 20, thereby reliably preventing lateral penetration of the wet etching solution and greatly improving product yield and reliability.

[0061] Furthermore, setting A ≥ 0.5 μm improves the tolerance for photolithographic alignment deviations. During anodizing, engineers have a wider process window, reducing scrap rates due to alignment errors and facilitating stable and efficient mass production.

[0062] While theoretically a larger A value results in greater safety, the size of A encroaches on the area of ​​the wiring and support structure beneath the first insulating layer 20. In practical applications, A can be set to 0.5 μm, which provides sufficient safety distance to handle overlay errors (i.e., ensures reliability) while avoiding excessive space occupation by the first insulating layer 20, thus maintaining a compact structure. Of course, in some other embodiments of this disclosure, A can also be selected from other values ​​greater than 0.5 μm, such as 0.55 μm, 0.6 μm, etc., and this disclosure does not specifically limit this.

[0063] When integrating touch functionality into a display panel, the touch sensing layer and the display panel can typically be integrated in three ways: on-chip, semi-in-cell, and in-cell. In an on-chip structure, the touch panel and display panel are manufactured independently and then assembled together via bonding, resulting in a thicker and heavier display product. A semi-in-cell structure integrates the touch sensing layer on top of the display panel, making the display product thinner and lighter than an on-chip structure. An in-cell structure embeds the touch functionality layer inside the display panel, resulting in the thinnest and lightest module.

[0064] The following description will use a fully embedded touch display panel as an example of the display panel provided in the embodiments of this disclosure.

[0065] Figure 7 The diagram shown is a planar structural diagram of the cathode layer in a display panel provided in an embodiment of this disclosure. Figure 8 As shown Figure 7 This is an enlarged schematic diagram of the central region Q. It should be noted that, in order to clearly show the display cathode 33 and touch electrode 39 in the cathode layer 30, Figure 8 Different patterns were applied to the display cathode 33 and the touch electrode 39, although both are actually located in the cathode layer 30. Figure 9 The diagram shown is a schematic of a film layer at the pixel opening K3 and touch opening K4 in a display panel provided in this embodiment of the present disclosure. It should be noted that... Figure 9 Other film layers above the cathode layer 30 are not shown. Optionally, additional film layers such as those above the cathode layer 30 may also be provided. Figure 2 The encapsulation layer 50 shown is an example.

[0066] Please continue to refer to this. Figure 9In one optional embodiment of this disclosure, the pixel definition layer 60 further includes a plurality of touch openings K4, and the first connecting metal layer 10 includes a second connecting metal portion 12; along the thickness direction of the display panel, the touch openings K4 penetrate the pixel definition layer 60 and expose the second connecting metal portion 12; the display panel further includes a light-emitting functional layer 32 and a cathode layer 30, the light-emitting functional layer 32 being located at least in the pixel openings K3, and the light-emitting functional layer 32 including an organic light-emitting material. The cathode layer 30 is located on the side of the light-emitting functional layer 32 facing away from the first planarization layer 80; the cathode layer 30 includes a display cathode 33 and a touch electrode 39, along the thickness direction of the display panel, the display cathode 33 overlaps with the pixel openings K3, and the touch electrode 39 is located at least in the touch openings K4.

[0067] This disclosure successfully integrates the touch electrode 39 into the cathode layer of the OLED structure by designing a touch opening K4 on the pixel definition layer 60 and using the second connecting metal portion 12 on the first connecting metal layer 10 as a lead. This structure avoids the need for an additional independent touch sensor layer (such as a separate touch film or a touch layer on the cover glass) on the display panel. It reduces the module thickness, making the display panel thinner and lighter, and also reduces additional materials and bonding processes.

[0068] In this embodiment, the cathode layer is no longer merely an electrode for the light-emitting device, but can be precisely divided into two functionally distinct patterns through patterning (e.g., dry etching): a display cathode 33 and a touch electrode 39. The display cathode area is used for emitting light, while the touch electrode area (located in the touch opening K4) is used for sensing touch signals. This effectively improves the utilization rate of materials and processes. Because the touch electrode is located inside the display panel (close to the light-emitting layer), it has a better signal-to-noise ratio and more sensitive touch performance.

[0069] Figure 10 The diagram shown is a schematic diagram of another film layer at the pixel opening K3 and touch opening K4 in the display panel provided in this embodiment of the present disclosure. Figure 11 The image shown is an enlarged schematic diagram of an undercut space. Please refer to it. Figure 9 , Figure 10 and Figure 11 In one optional embodiment of this disclosure, the first planarization layer 80 includes a first support portion 81 located in the touch opening K4, and the first insulating layer 20 includes a second support portion 23 located in the touch opening K4. Along the thickness direction of the display panel, the edge of the orthographic projection of the second support portion 23 is located outside the edge of the orthographic projection of the first support portion 81, and the first support portion 81 and the second support portion 23 form an undercut space E. Figure 9 and Figure 10 The difference between the embodiments lies in the thickness of the first support portion 81. Figure 9 and Figure 10In the embodiments, the first support portion 81 is on the same layer as the first planarization layer 80, the difference being that Figure 9 The thickness of the first support portion 81 is less than the thickness of the first planarization layer 80 in other areas. Figure 10 The thickness of the first support portion 81 is equal to the thickness of the first flattening layer 80 in other regions. Figure 9 The first support portion 81 in the embodiment can be obtained through a thinning process. Figure 10 In this embodiment, the first support portion 81 does not require a thinning process. The thickness of the first support portion 81 can be set according to actual needs, and this disclosure does not impose specific limitations on it.

[0070] Please refer to Figures 9 to 11 In this embodiment, the first support portion 81 is located on the first planarization layer 80, and the first support portion 81 forms the recessed edge of the undercut space E. The first planarization layer 80 is typically an organic layer, therefore, by utilizing the isotropic etching characteristics of organic films, it is easier to achieve the undercut recess, thereby precisely controlling the geometric discontinuity of the upper touch electrode and optimizing the touch electrode patterning. If the first planarization layer 80 is not reused to form the first support portion 81, an additional layer of organic material is required to form the undercut recessed portion. By reusing the first planarization layer 80, additional materials and deposition / photolithography / etching processes are saved, while the etching differences brought about by its organic characteristics optimize the morphology of the undercut.

[0071] In this disclosure, the second support portion 23 is located on the first insulating layer 20 and is used to form an undercut overhanging eaves. The first insulating layer 20 may be an inorganic layer, whose inorganic properties act as a hard mask to assist in the etching of the first planarization layer 80 and ultimately form an eaves that effectively blocks etching residues. By reusing the first insulating layer 20 to form the second support portion 23, there is no need to add an additional inorganic film layer, which also helps to save additional materials and deposition / photolithography / etching processes.

[0072] Considering that a common layer 99 may be introduced into the display panel to enable the light-emitting elements to emit light, it should be noted that... Figure 9 and Figure 10The diagram only illustrates one common layer 99 in the display panel, but does not limit the number of common layers 99. The common layer 99 may include, for example, a hole layer and an electron layer, located on the upper and lower sides of the light-emitting material layer, respectively. The hole layer receives holes (positive charge carriers) injected from the first anode portion 311 of the display and effectively transfers the holes to the light-emitting material layer. The electron layer receives electrons (negative charge carriers) injected from the cathode 33 of the display and effectively transfers the electrons to the light-emitting material layer 32. When holes and electrons enter the light-emitting material layer 32, they are attracted by electrostatic forces due to their opposite charges, forming an exciton. The exciton is in a high-energy unstable state and rapidly decays from the excited state back to the stable ground state, releasing excess energy in the form of light. This process is called electroluminescence, and the wavelength (color) of the emitted light is determined by the energy level difference of the light-emitting materials doped in the light-emitting material layer. Optionally, the common layer 99 may also include a hole blocking layer and / or an electron blocking layer. Their function is to prevent holes or electrons from penetrating the luminescent material layer and entering the transport layer on the other side, thereby confining holes and electrons within the luminescent material layer and improving luminous efficiency.

[0073] In practical applications, when depositing the common layer 99, a full-surface deposition method is typically used. This means that the common layer 99 extends beyond the pixel opening K3 into the touch opening K4. If the common layers 99 between different pixel openings K3 are continuous, short circuits or crosstalk may occur between different sub-pixels or adjacent sub-pixels, preventing independent pixel driving. Therefore, when the touch electrode 39 and the display cathode 33 are disposed on the same layer, this embodiment introduces an undercut space E formed by the first support portion 81, the second support portion 23, and the second connecting metal portion 12 in the touch opening K4. When depositing the common layer 99, such as the hole layer and the electron layer, due to the evaporation angle limitation of the material and the shielding effect of the undercut structure, the material cannot or is difficult to deposit below the suspended structure. This causes the common layer 99 to be disconnected in the touch opening K4, ensuring that the common layer 99 is physically disconnected and insulated between different pixel openings K3. This cuts off the connection between sub-pixels in different pixel openings K3, ensuring that each sub-pixel can be driven independently.

[0074] In the touch opening K4, the touch electrode 39, by connecting to the lower second connecting metal part 12, can extract touch signals from inside the panel, thereby realizing the in-cell touch function. The edge of the second support part 23 is located outside the edge of the first support part 81, forming a cantilevered or recessed undercut space E. This precise geometry can control the deposition path of the subsequent cathode layer 30 (touch electrode 39), helping to guide the cathode material to uniformly and continuously cross the step and enter the undercut area, avoiding electrode breakage or uneven deposition caused by excessively steep steps, thereby improving manufacturing yield and electrode performance.

[0075] Please continue to refer to this. Figures 9 to 11 In one alternative embodiment of this disclosure, the touch electrode 39 is electrically connected to the second connecting metal portion 12 at least within the undercut space E. The undercut space E is a geometric structure with a suspended, concave feature in the vertical direction. When the touch electrode 39 (cathode layer 30) is deposited by vapor deposition, by controlling the evaporation angle of the material, the cathode material is guided and extended, successfully crossing the step and overlapping with the exposed second connecting metal portion 12 at the bottom of the undercut space E. Concentrating the connection within the undercut space E ensures a stable and low-resistance electrical contact between the touch electrode 39 and the second connecting metal portion 12. In practical applications, by controlling the different evaporation angles of the vapor-deposited common layer 99 and the cathode, the length of the touch electrode 39 extending into the undercut region can be made greater than the extension length of other common layers 99 (such as hole layer and electron layer). This ensures that the touch electrode 39 can reliably connect with the second connecting metal part 12 in the undercut region, thus avoiding problems such as poor contact between the touch electrode 39 and the second connecting metal part 12, which would lead to obstructed touch signal transmission, reduced signal-to-noise ratio, and affected touch accuracy.

[0076] Although the touch electrode 39 needs to be connected to the second connecting metal portion 12, the area covered by the cathode layer 30 is very large. The presence of the undercut space E can precisely define the connection area between the touch electrode 39 and the second connecting metal portion 12. Through the precise connection of the undercut space E, the touch electrode 39 can efficiently and stably lead the sensed charge signal to the touch driving circuit through the second connecting metal portion 12, ensuring the quality of the touch signal.

[0077] Please refer to Figure 9 In one optional embodiment of this disclosure, the thickness of the first insulating layer 20 is H, where H ≥ 1000 angstroms. The first insulating layer 20 includes a first insulating portion 21 and a second insulating portion 22 located below the anode layer 31, and a second support portion 23 for forming an undercut structure.

[0078] The first insulating layer 20 is located between the first connecting metal layer 10 and the anode layer 31, below the anode layer 31. The first insulating portion 21 in the first insulating layer 20 is the direct support layer for the anode and the organic light-emitting material layer above it. If the thickness of the first insulating layer 20 is too thin (e.g., less than 1000 angstroms), its rigidity and physical strength will be insufficient, making it prone to stress deformation, cracking, or damage during subsequent processes (such as cleaning, etching, and evaporation) or long-term use. Therefore, setting H ≥ 1000 angstroms ensures that the first insulating layer 20, as the support layer below the anode layer 31, has sufficient thickness and mechanical strength. This allows the first insulating portion 21 to effectively flatten the minor undulations of the underlying first flattening layer 80, providing a highly flat and robust surface for the anode. At the same time, it ensures that the second insulating portion 22 has sufficient thickness to better resist stress, ensuring the integrity of the anode layer 31 when it slopes up through the first opening K1.

[0079] The second support portion 23 is located in the touch electrode connection area, and its thickness H is directly related to the insulation between electrodes, the support of the structure, and the formation of the undercut morphology. Setting H ≥ 1000 angstroms is beneficial for precisely controlling the geometry of the undercut structure through the etching process. Sufficient thickness provides greater depth for the etching process, making it easier to precisely control the overhang dimensions of the undercut, thereby achieving better etching cleanliness (avoiding touch electrode residue).

[0080] Optionally, the thickness H of the first insulating layer 20 is ≤ 2000 angstroms, for example, it can be directly selected as 2000 angstroms. The first insulating layer 20 can be an inorganic film (such as silicon nitride), which typically has large internal stress, especially compressive stress. If the thickness of the first insulating layer 20 is too large, the accumulated total stress will also increase, which may lead to insufficient adhesion between the film and the underlying first planarization layer 80, eventually resulting in detachment or cracking during subsequent processes or use. Therefore, controlling the thickness of the first insulating layer 20 to below 2000 angstroms can effectively reduce the accumulation of internal stress in the film, significantly enhance the adhesion between the first insulating layer 20 and the first planarization layer 80, thereby avoiding the defect of detachment of the first insulating layer 20 and ensuring the integrity and reliability of the structure.

[0081] Figure 12 The diagram shown illustrates another type of film layer at the pixel opening K3 and touch opening K4 in the display panel provided in this embodiment. Please refer to [the diagram]. Figure 12 In one optional embodiment of this disclosure, the display panel further includes a second planarization layer 90 and a second connecting metal layer 70. The second planarization layer 90 is located between the first planarization layer 80 and the second connecting metal layer 70, and the second connecting metal layer 70 is located between the second planarization layer 90 and the array layer 40. The first connecting metal portion 11 is electrically connected to the second connecting metal layer 70 through a first connecting hole LS1 penetrating the second planarization layer 90. Along the thickness direction of the display panel, the first opening K1 and the first connecting hole LS1 do not overlap.

[0082] If the first opening K1 and the first connecting hole LS1 overlap on the plane, the sidewalls of the two first connecting holes LS1 will be very close, even forming a large, interconnected hole. This overlap weakens the support structure, and the upper deposited thin film (first insulating layer 20 and anode layer 31) may collapse or break under stress, affecting the reliability of the connection between the anode and the array layer 40. Therefore, this disclosure avoids complex overlapping geometry by separating the first connecting holes LS1, which helps maintain the integrity of the anode signal and improves the signal integrity and support yield of the display panel.

[0083] Optionally, the minimum spacing between the first connecting hole LS1 and the first opening K1 is S0, where S0 ≥ 3.15 μm. This significantly increases the lateral distance of the insulator between the first connecting hole LS1 and the first opening K1. This reduces the parasitic capacitance between the sidewalls to an extremely low level, thereby completely eliminating electrical crosstalk and coupling between different signal paths and ensuring high integrity of the display signal. Moreover, the 3.15 μm spacing far exceeds half of the photolithography overlay error, ensuring that even under the most extreme photolithography alignment deviations, the edges of the two holes will not get too close or contact each other, ensuring that the structural isolation is not compromised. This wide spacing ensures that even with large etching deviations, the sidewalls of the two holes will not erode each other, thus maintaining the integrity of the insulator sidewalls, preventing lateral etching or over-etching that may occur during the etching process.

[0084] Furthermore, the wide spacing ensures that the planarization layer (first planarization layer 80 and second planarization layer 90) between the first connection hole LS1 and the first opening K1 has sufficient support width. This effectively avoids stress concentration and local film collapse in the upper structure (such as anode, organic light-emitting material, cathode) due to the first connection hole LS1 being too dense, thereby ensuring the long-term reliability of the pixel device.

[0085] It should be noted that, for example, please refer to... Figure 13 In the case where the first connecting metal portion 11 is directly connected to the transistor in the array layer 40, i.e., without introducing the second connecting metal layer 70, the first connecting metal portion 11 can be electrically connected to the transistor T through the second connecting hole LS2. In this case, the second connecting hole LS2 and the first opening K1 can be configured not to overlap along the thickness direction of the display panel, thereby preventing the anode layer 31 or the first insulating layer 20 from collapsing or breaking under stress, thus maintaining the integrity of the anode signal. The minimum spacing width between the second connecting hole LS2 and the first opening K1 can also be set to be greater than or equal to 3.15 μm to ensure that even with large etching deviations, the sidewalls of the two holes will not erode each other, thus maintaining the integrity of the insulator sidewalls. Figure 13The diagram shown is a schematic diagram of another film layer at the pixel opening K3 and touch opening K4 in the display panel provided in the embodiment of this disclosure.

[0086] Figure 14 The diagram shows one possible arrangement of the touch electrode 39 and the display cathode 33 in a display panel. It should be noted that the specific patterned structure of the cathode layer 30 provided in this embodiment can be selected according to actual conditions; the patterned structure in the accompanying drawings is for illustrative purposes only. Please refer to... Figure 14 In one optional embodiment of this disclosure, the touch electrode 39 includes a plurality of touch electrode blocks 390, and at least two touch electrode blocks 390 are electrically connected through a second connecting metal portion 12. Specifically, one touch electrode block 390 can be electrically connected by overlapping with the second connecting metal portion 12 in the touch opening K4, and another touch electrode block 390 can also be electrically connected by overlapping with the same second connecting metal portion 12 in the touch opening K4, thereby realizing the electrical connection between the two touch electrode blocks 390.

[0087] For example, the touch electrode 39 (patterned from the OLED cathode layer 30) is divided into multiple discrete sensing units (e.g., rhomboid blocks, square blocks, etc.). At least two touch electrode blocks 390 are electrically connected via a first connecting metal portion 11. The touch electrode block 390 (e.g., a rhomboid pattern) is the smallest unit that actually senses changes in human touch capacitance. In a mutual capacitance touch scheme, discrete electrode blocks need to be connected to form touch driving electrodes and touch sensing electrodes; that is, multiple touch electrode blocks 390 can be electrically connected to form touch driving electrodes, while other electrode blocks can be electrically connected to form touch sensing electrodes. The second connecting metal portion 12 acts as a bridge or common trace connecting the various electrode blocks. This layered connection (touch electrode 39 in the cathode layer, second connecting metal portion 12 in other film layers) enables the interleaving and cross-layer connection (bridging structure) of touch driving signals and touch sensing signals, thereby realizing the mutual capacitance touch function. Although the touch electrode 39 (cathode) is conductive, its resistivity is typically higher than that of the dedicated low-resistivity second connecting metal portion 12 (e.g., a Mo / Al / Ti alloy). Shifting long-distance or critical connection paths to the low-resistivity second connecting metal portion 12 reduces signal attenuation and ensures minimal loss of touch signals during transmission. Lower resistance reduces the impact of parasitic capacitance on the signal, improves the signal-to-noise ratio, and reduces RC delay, which is beneficial for ensuring the acquisition speed and uniformity of touch signals on large-size panels. This disclosure utilizes the existing metal layer in OLED manufacturing as a channel for touch wiring (second connecting metal portion 12), achieving the reuse of display and touch functions. Through an undercut structure, the touch electrode block 390 (cathode) can partially overlap with the underlying second connecting metal portion 12, allowing touch traces to be integrated parallel to display pixel traces within the panel, minimizing bezel width and panel thickness.

[0088] Therefore, using the low-resistance second connecting metal portion 12 to pattern and connect the touch electrode blocks 390 of the cathode layer 30 not only provides the structural basis for mutual capacitance touch patterns, but also facilitates low resistance and high signal-to-noise ratio of touch signals on large-size In-cell OLED panels, thereby improving touch performance. Of course, in some other embodiments of this disclosure, the touch electrode 39 may also be embodied as a self-contained touch structure, for example, please refer to Figure 15 , Figure 15The diagram shows another arrangement of the touch electrode 39 and display cathode 33 in the display panel. The touch electrode 39 includes multiple touch electrode blocks 391. The touch electrode 39 (part of the cathode layer 30) is divided into multiple discrete sensing units (touch electrode blocks 391), and each touch electrode block 391 is electrically connected to a different second connecting metal part 12. In the self-capacitive structure, each touch electrode block 391 is itself a sensing line. The touch position is determined by measuring the capacitance change of each sensing line relative to ground or to the driving source. The self-capacitive structure requires that each electrode block can be driven and acquire signals independently. Each touch electrode block 391 is electrically connected to a different second connecting metal part 12, ensuring that each electrode block has its own independent signal path (second connecting metal part 12), thereby achieving independent sensing and independent addressing. Even in the self-capacitive structure, leading the signal out through the low-resistance second connecting metal part 12 is much more efficient than directly using the touch electrode 39 (cathode) for long-distance transmission, thus effectively reducing the RC delay and attenuation of the signal. This is especially important for large-size OLED panels, ensuring that the weak capacitive signals collected by the touch electrode 39 can be transmitted to the driver IC at the edge of the panel for processing with high signal-to-noise ratio (SNR) and high fidelity.

[0089] Furthermore, in the self-capacitive structure, the geometry of the touch electrode block 391 is generally regular, only needing to overlap with the independent second connecting metal portion 12 below through an undercut structure in certain areas. This design allows the touch electrode 39 pattern (cathode) to be relatively simple, with the main complex routing work (leading independent signal lines to the edge) handled by the second connecting metal portion 12. This helps maintain the structural integrity of the pixel opening K3 area while achieving highly integrated touch functionality. Therefore, by assigning an independent second connecting metal portion 12 to each touch electrode block 391, independent sensing functionality of the self-capacitive touch is ensured, and the low-resistance auxiliary metal guarantees the efficiency and reliability of touch signal acquisition.

[0090] It should be noted that, please refer to Figure 15 When the cathode layer 30 is patterned to form the display cathode 33 and the touch electrode 39, in order to ensure that the display cathode 33 can receive the cathode signal, the display cathode 33 can also be electrically connected to the connecting trace L1 by overlapping, and the cathode signal is transmitted through the connecting trace L1. At this time, the connecting trace L1 and the second connecting metal part 12 can be located in the same film layer, so that the connecting trace L1 and the second connecting metal part 12 can be formed in the same production process, and the overlapping area Q0 of the connecting trace L1 and the display cathode 33 can also avoid the pixel opening K3.

[0091] Please refer to Figures 13 to 15When the cathode layer includes both a display cathode and a touch electrode, an isolation gap F can be graphically configured between the display cathode and the touch electrode, and the isolation gap F can be filled with an insulating material (such as PV, RE, or other protective layers). Although both are located on the same physical layer, the insulation configuration ensures that there is no direct electrical connection between the pixel driving current (used for light emission) and the touch acquisition signal (capacitance change). During light emission, the display cathode 33 is affected by high-frequency driving signals or current fluctuations. Through insulation isolation, these driving noises are isolated in the display cathode 33 area and do not directly couple to the touch electrode 39, thereby significantly improving the touch signal-to-noise ratio.

[0092] In some other embodiments of this disclosure, the display cathode 33 can also be reused as the touch electrode 39, and no isolation gap is introduced between the touch electrode 39 and the display cathode 33. For example, please refer to [reference needed]. Figure 16 and Figure 17 , Figure 16 The diagram shown is a schematic diagram of another film layer at the pixel opening K3 and touch opening K4 in the display panel provided in this embodiment of the present disclosure. Figure 17 The diagram shows another arrangement of touch electrodes and display cathodes in a display panel. When the touch electrodes 39 form multiple touch electrode blocks 392, in the area corresponding to each touch electrode block 392, the touch electrode block 392 is time-division multiplexed as both a touch electrode 39 and a display cathode 33. The display panel includes a display phase and a touch phase. In the display phase, the display cathode 33 transmits a common voltage signal to drive pixel emission; in the touch phase, the display cathode 33 transmits touch signals to sense changes in capacitance.

[0093] In this embodiment, the display cathode 33 and the touch electrode 39 are on the same physical layer, with the display cathode 33 reused as the touch electrode 39. The system switches between the display phase and the touch phase. Since the display cathode 33 and the touch electrode 39 are on the same layer, there is no need to add an additional touch electrode layer. This maintains the thinnest characteristic of the in-cell structure, avoids additional material deposition and patterning steps, and reduces manufacturing costs and process complexity.

[0094] The display phase is a high-power, high-noise phase (pixel driving), during which touch functionality is inactive. The touch phase is a low-power, low-noise phase (signal acquisition), during which the display is either off or held. By staggering operation times, severe coupling interference caused by the simultaneous operation of high-noise pixel driving signals and weak touch sensing signals is avoided, thereby improving the touch signal-to-noise ratio. The system's switching frequency (e.g., a 60Hz display frame rate) is typically much higher than the flicker frequency perceptible to the human eye. Within each frame cycle, the system allocates a very short time (e.g., a few microseconds to a few milliseconds) for touch signal acquisition. Users experience a continuous display visually and real-time touch response operationally, achieving functional compatibility.

[0095] At this point, both self-capacitive and mutual-capacitive touch structures can be implemented. When it is a self-capacitive touch structure, during the touch phase, the patterned touch electrode blocks on the cathode layer are sequentially connected to the acquisition circuit to measure their capacitance to ground. When it is a mutual-capacitive touch structure, during the touch phase, the patterned electrode blocks on the cathode layer are grouped into touch driving lines and touch sensing lines, and driving and acquisition are performed in a time-division manner.

[0096] This embodiment utilizes a time multiplexing mechanism to integrate display light emission and touch sensing functions on the same physical layer (cathode layer 30). This effectively improves the integration of the display panel and solves the key technical problem of signal interference through clever driving timing.

[0097] It should be noted that when the display cathode 33 and the touch electrode 39 are time-division multiplexed, the second connecting metal part 12 can also be time-division multiplexed. For example, during the display phase, the second connecting metal part 12 is used to transmit a common voltage signal to the display cathode 33, and during the touch phase, the second connecting metal part 12 is used to transmit touch signals.

[0098] Based on the same inventive concept, this disclosure also provides a display device. Figure 18 The diagram shown is a structural schematic of a display device 200 provided in an embodiment of this disclosure. Please refer to it. Figure 18 The display device 200 includes the display panel 100 in any of the above embodiments. The display device 200 provided in this disclosure can be any electronic device with touch and display functions, such as a display screen, mobile phone, tablet computer, laptop computer, e-reader, or television. The display device 200 provided in this disclosure has the beneficial effects of the display panel provided in this disclosure; for details, please refer to the specific descriptions of the display panel in the above embodiments, which will not be repeated here.

[0099] Understandable, Figure 18The rectangular structure is used as an example to illustrate one shape of the display device 200. In some other embodiments of this disclosure, the display device 200 may also be circular, elliptical or any other feasible shape, and this disclosure does not specifically limit it.

[0100] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0101] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that, include: An array layer, a first interconnecting metal layer, and a first planarization layer, wherein the first interconnecting metal layer is located between the array layer and the first planarization layer; The first connecting metal layer includes a first connecting metal portion; The first planarization layer includes a first opening along the thickness direction of the display panel, the first opening penetrating the first planarization layer and exposing the first connecting metal portion; A first insulating layer is located on the side of the planar layer opposite to the array layer. The first insulating layer includes a first insulating portion and a second insulating portion that are connected to each other. The first insulating portion is located outside the first opening, and the second insulating portion is located in the first opening. The second insulating portion includes a second opening that exposes the first connecting metal portion. An anode layer is located on the side of the first insulating layer away from the array layer. The anode layer includes a first anode portion and a second anode portion connected to each other. The first anode portion is located on the side surface of the first insulating portion away from the array layer, and the second anode portion is located on the side surface of the second insulating portion away from the array layer and is electrically connected to the first connecting metal portion through the second opening.

2. The display panel according to claim 1, characterized in that, It also includes a pixel definition layer, which is located on the side of the anode layer opposite to the array layer; The pixel definition layer includes a plurality of pixel openings. Along the thickness direction of the display panel, the pixel openings penetrate the pixel definition layer and expose the first anode portion, and the pixel definition layer covers the second anode portion.

3. The display panel according to claim 2, characterized in that, Along a direction parallel to the plane of the display panel, there is a first gap between the pixel opening and the first opening, and the width of the first gap is S, where S≥6μm.

4. The display panel according to claim 1, characterized in that, The first anode portion has no contact with the first planarization layer, and the second anode portion has no contact with the first planarization layer.

5. The display panel according to claim 1, characterized in that, Along a direction parallel to the plane of the display panel, the minimum width of the second opening is C, where C ≥ 2 μm.

6. The display panel according to claim 1, characterized in that, The thickness of the second anode portion that overlaps with the second opening along the thickness direction of the display panel is greater than the thickness of the other second anode portions that contact the second insulating portion.

7. The display panel according to claim 1, characterized in that, The second insulating portion is disposed around the second opening, and at least a portion of the second insulating portion is in direct contact with the first connecting metal portion; the width of the second insulating portion in direct contact with the first connecting metal portion is B, where B ≥ 0.9 μm.

8. The display panel according to claim 1, characterized in that, In the first opening, the sidewall of the second insulating part that is in direct contact with the first connecting metal part is the first sidewall. The first sidewall constitutes the inner wall of the second opening. Along the direction from the first anode part to the first connecting metal part, the width of the second opening tends to decrease. The acute angle in the angle between the first sidewall and the first connecting metal part is α, where 0 < α ≤ 60°.

9. The display panel according to claim 1, characterized in that, Along the direction from the first anode portion to the first connecting metal portion, the width of the first opening decreases; in the first opening, the second sidewall of the first flat layer constitutes the inner wall of the first opening, and the acute angle between the second sidewall and the first connecting metal portion is θ, 50°≤θ≤80°.

10. The display panel according to claim 9, characterized in that, Along a direction parallel to the plane where the display panel is located, the minimum width of the first opening is D, where D≤5μm.

11. The display panel according to claim 1, characterized in that, Along the thickness direction of the display panel, the outer contour of the orthographic projection of the first anode portion and the second anode portion as a whole is the first outer contour, and the outer contour of the orthographic projection of the first insulating portion and the second insulating portion as a whole is the second outer contour, and the first outer contour is located within the second outer contour.

12. The display panel according to claim 11, characterized in that, The distance between the first outer contour and the second outer contour is A, where A ≥ 0.5 μm.

13. The display panel according to claim 2, characterized in that, The pixel definition layer also includes multiple touch openings, and the first connecting metal layer includes a second connecting metal portion; along the thickness direction of the display panel, the touch openings penetrate the pixel definition layer and expose the second connecting metal portion; The display panel further includes a light-emitting functional layer and a cathode layer. The light-emitting functional layer is located at least in the pixel opening, and the cathode layer is located on the side of the light-emitting functional layer opposite to the first planarization layer. The cathode layer includes a display cathode and a touch electrode. Along the thickness direction of the display panel, the display cathode overlaps with the pixel opening, and the touch electrode is located at least in the touch opening.

14. The display panel according to claim 13, characterized in that, The first planarization layer includes a first support portion located in the touch opening, and the first insulating layer includes a second support portion located in the touch opening. Along the thickness direction of the display panel, the edge of the orthographic projection of the second support portion is located outside the edge of the orthographic projection of the first support portion, and the first support portion and the second support portion form an undercut space.

15. The display panel according to claim 14, characterized in that, The touch electrode is electrically connected to the second connecting metal portion at least in the undercut space.

16. The display panel according to claim 1, characterized in that, The thickness of the first insulating layer is H, where H ≥ 1000 angstroms.

17. The display panel according to claim 1, characterized in that, The display panel further includes a second planarization layer and a second connecting metal layer, wherein the second planarization layer is located between the first planarization layer and the second connecting metal layer, and the second connecting metal layer is located between the second planarization layer and the array layer; the first connecting metal portion is electrically connected to the second connecting metal layer through a first connecting hole penetrating the second planarization layer. Along the thickness direction of the display panel, the first opening does not overlap with the first connection hole.

18. A display device, characterized in that, Includes the display panel described in any one of claims 1 to 17.

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