Display panel and display device

Abstract

The invention relates to the technical field of display, in particular to a display panel and a display device. The display panel comprises a display area and a non-display area. The display panel comprises a substrate; the preset wire is at least partially located on one side of the substrate in the non-display area; at least part of the interlayer dielectric layer is located on one side, in the non-display area, of the substrate, the interlayer dielectric layer and the preset wires are arranged on the same side, and the orthographic projection of the interlayer dielectric layer on the substrate and the orthographic projection of the preset wires on the substrate are not overlapped; the conductive pattern is at least partially located on the side, away from the substrate, of the preset wire in the non-display area. The orthographic projection of the interlayer dielectric layer on the substrate is not overlapped with the orthographic projection of the preset wire on the substrate, so that the conductive pattern is relatively flat, the probability that the conductive pattern has a relatively large height difference is reduced, and the probability that the conductive pattern is seriously damaged by etching liquid is further reduced.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] The fabrication of the display area of ​​a display panel often involves multiple etching processes. During this process, etching liquids or gases may damage the multilayer films and various structures in the non-display areas, affecting the display performance of the display panel. Summary of the Invention

[0003] Therefore, it is necessary to provide a display panel and display device that address the problem of film layer damage in the prior art.

[0004] To achieve the above objectives, in one aspect, a display panel is provided, the display panel including a display area and a non-display area, the display panel comprising:

[0005] substrate;

[0006] Pre-defined traces, at least a portion of which are located on one side of the substrate within the non-display area;

[0007] An interlayer dielectric layer, at least a portion of which is located on one side of the substrate within the non-display area and is disposed on the same side as the preset trace, wherein the orthographic projection of the interlayer dielectric layer on the substrate does not overlap with the orthographic projection of the preset trace on the substrate.

[0008] In one embodiment, the display panel further includes:

[0009] The conductive pattern, at least a portion of which is located on the side of the preset trace in the non-display area away from the substrate.

[0010] In one embodiment, the orthographic projection of the conductive pattern on the substrate does not overlap with the orthographic projection of the interlayer dielectric layer on the substrate.

[0011] In one embodiment, the orthographic projection of the conductive pattern on the substrate is spaced apart from the orthographic projection of the interlayer dielectric layer on the substrate, and the orthographic projection of the interlayer dielectric layer on the substrate is spaced apart from the orthographic projection of the preset trace on the substrate. The conductive pattern extends from the side of the preset trace away from the substrate to the substrate between the interlayer dielectric layer and the preset trace.

[0012] Optionally, the orthographic projection of the preset trace on the substrate lies within the orthographic projection of the conductive pattern on the substrate.

[0013] In one embodiment, the conductive pattern includes a first conductive pattern and a second conductive pattern, wherein the first conductive pattern is located on the side of the preset trace away from the substrate and extends to the substrate between the interlayer dielectric layer and the preset trace.

[0014] The second conductive pattern is located on the side of the first conductive pattern away from the substrate and extends to the substrate between the interlayer dielectric layer and the first conductive pattern;

[0015] Optionally, the orthographic projection of the first conductive pattern on the substrate lies within the orthographic projection of the second conductive pattern on the substrate.

[0016] In one embodiment, the display panel further includes:

[0017] A pixel definition layer extends from the display area to the non-display area, and is located at least on the side of a portion of the interlayer dielectric layer and a portion of the conductive pattern away from the substrate. The pixel definition layer extends from the side of the interlayer dielectric layer away from the substrate, through the substrate between the interlayer dielectric layer and the preset trace, to the sidewall of the conductive pattern away from the substrate.

[0018] Optionally, the orthographic projection of the pixel definition layer on the substrate does not overlap with the orthographic projection of the preset trace on the substrate.

[0019] In one embodiment, the top surface of the pixel definition layer opposite to the substrate is flush with the top surface of the conductive pattern opposite to the substrate.

[0020] In one embodiment, the orthographic projection of the conductive pattern on the substrate is connected to the orthographic projection of the interlayer dielectric layer on the substrate, and the orthographic projection of the interlayer dielectric layer on the substrate is spaced from the orthographic projection of the preset trace on the substrate.

[0021] In one embodiment, the orthographic projection of the conductive pattern on the substrate overlaps with the orthographic projection of the interlayer dielectric layer on the substrate.

[0022] In one embodiment, the orthographic projection of the interlayer dielectric layer on the substrate is spaced apart from the orthographic projection of the preset trace on the substrate, and the conductive pattern extends from the side of the preset trace away from the substrate, through the side of the substrate between the preset trace and the interlayer dielectric layer, to the side of the interlayer dielectric layer away from the substrate.

[0023] In one embodiment, the conductive pattern includes a first conductive pattern and a second conductive pattern, wherein the first conductive pattern is located on the side of the preset trace away from the substrate and extends to the interlayer dielectric layer, and the second conductive pattern is located on the side of the first conductive pattern away from the substrate and extends to the interlayer dielectric layer.

[0024] Optionally, the orthographic projection of the first conductive pattern on the substrate lies within the orthographic projection of the second conductive pattern on the substrate.

[0025] In one embodiment, the display panel further includes:

[0026] A pixel definition layer extends from the display area to the non-display area, and is located at least on the side of a portion of the interlayer dielectric layer and a portion of the conductive pattern facing away from the substrate;

[0027] Optionally, the orthographic projection of the pixel definition layer on the substrate overlaps with the orthographic projection of the preset trace on the substrate.

[0028] In one embodiment, the display panel further includes:

[0029] The first protective layer is located on the side of the pixel definition layer that faces away from the substrate;

[0030] Optionally, the orthographic projection of the first protective layer on the substrate overlaps with the orthographic projection of the preset trace on the substrate.

[0031] In one embodiment, the display panel includes:

[0032] The second protective layer is located at least on the side of a portion of the interlayer dielectric layer and a portion of the conductive pattern that faces away from the substrate, wherein the orthographic projection of the conductive pattern on the substrate overlaps with the orthographic projection of the interlayer dielectric layer on the substrate.

[0033] In one embodiment, the display panel further includes:

[0034] A first electrode, at least partially located in the display area, and a second protective layer made of the same material as the first electrode.

[0035] In one embodiment, the orthographic projection of the preset trace on the substrate is connected to the orthographic projection of the interlayer dielectric layer on the substrate.

[0036] In one embodiment, the orthographic projection of the conductive pattern on the substrate is connected to the orthographic projection of the interlayer dielectric layer on the substrate.

[0037] In one embodiment, the conductive pattern is flush with the top surface of the substrate opposite to the top surface of the interlayer dielectric layer opposite to the top surface of the substrate.

[0038] In one embodiment, the display panel further includes:

[0039] The conductive pattern, at least a portion of which is located on the side of the preset trace in the non-display area away from the substrate, has an overlapping portion between the orthographic projection of the conductive pattern on the substrate and the orthographic projection of the interlayer dielectric layer on the substrate.

[0040] On the other hand, a display device is also provided, including the display panel described in any of the foregoing embodiments.

[0041] The display panel and display device described in this specification have the following beneficial effects: by setting the orthographic projection of the interlayer dielectric layer on the substrate to not overlap with the orthographic projection of the preset trace on the substrate, the conductive pattern is made flatter, reducing the probability of a large height difference in the conductive pattern, and thus reducing the probability of the etching liquid causing serious damage to the conductive pattern. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a schematic diagram of the display panel provided in the first embodiment;

[0044] Figure 2 This is a schematic diagram of the display panel provided in the second embodiment;

[0045] Figure 3 This is a schematic diagram of the display panel provided in the third embodiment;

[0046] Figure 4 This is a schematic diagram of the display panel provided in the fourth embodiment;

[0047] Figure 5 This is a schematic diagram of the display panel provided in the fifth embodiment;

[0048] Figure 6 This is a schematic diagram of the display panel provided in the sixth embodiment;

[0049] Figure 7 This is a schematic diagram of the display panel provided in the seventh embodiment;

[0050] Figure 8 This is a schematic diagram of the display area of ​​a display panel provided in one embodiment;

[0051] Figure 9 This is a schematic diagram of the related technology provided in one embodiment;

[0052] Figure 10 This is a schematic diagram of the display panel provided in the eighth embodiment.

[0053] Explanation of reference numerals in the attached drawings: Display panel - 100; Substrate - 110; Preset trace - 120; Interlayer dielectric layer - 130; Conductive pattern - 140; First conductive pattern - 141; Second conductive pattern - 142; Pixel definition layer - 150; First protective layer - 160; Second protective layer - 170; Isolation layer - 190.

[0054] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood. Detailed Implementation

[0055] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0057] In each embodiment, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in each embodiment according to the specific circumstances.

[0058] It should be understood that when an element or layer is referred to as "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," or "directly connected to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, or portion. Therefore, without departing from the teachings of this embodiment, the first element, component, region, layer, or portion discussed below may be referred to as the second element, component, region, layer, or portion.

[0059] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, an element or feature described as “below,” “below,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0060] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0061] Embodiments of the embodiments are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures) of this specification. Variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, embodiments of this specification should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of this embodiment.

[0062] In one embodiment, a display panel 100 is provided. The display panel 100 includes a display area and a non-display area. As an example, the non-display area may surround the display area. Figures 1 to 7 ,as well as Figure 10 The following are schematic diagrams illustrating the structure of the non-display area of ​​the display panel 100 provided in several embodiments. Figure 8 This is a schematic diagram of the display area of ​​the display panel 100. It can be understood that conductive structures in the non-display area can be electrically connected to the light-emitting structure of the display area, thereby driving the light-emitting structure to emit light. In this embodiment, the display panel 100 includes a substrate 110, preset traces 120, and an interlayer dielectric layer 130.

[0063] The substrate 110 may extend from the display area to the non-display area. The substrate 110 may include a packaging substrate 110, etc.

[0064] The preset trace 120 may be located at least partially on one side of the substrate 110 in the non-display area. As an example, the preset trace 120 may also extend into the display area. The preset trace 120 may include power lines or drive circuits, etc.

[0065] The interlayer dielectric layer 130 may be at least partially located on one side of the substrate 110 within the non-display area, and may also extend from the display area to the non-display area. The interlayer dielectric layer 130 may include multiple layers. It is understood that multiple conductive structures are provided in the display area. For example, the conductive structures may include transistors and capacitors. Multiple dielectric layers are required between adjacent transistors and capacitors to prevent short circuits or crosstalk in the conductive structures. These multiple dielectric layers form the interlayer dielectric layer 130 in the non-display area.

[0066] In the non-display area, the interlayer dielectric layer 130 and the preset trace 120 can be located on the same layer, and the orthographic projection of the interlayer dielectric layer 130 on the substrate 110 does not overlap with the orthographic projection of the preset trace 120 on the substrate 110. In this case, please refer to [reference needed]. Figures 1 to 3 The interlayer dielectric layer 130 can be spaced apart from the preset trace 120. In another case, please refer to... Figures 4 to 6 The interlayer dielectric layer 130 can be connected to the preset trace 120.

[0067] The display panel may also include conductive patterns 140. Conductive patterns 140 may include structures such as pads or bonding electrodes. Conductive patterns 140 may be electrically connected to conductive structures in the display area. It is understood that, within the display area, in the thickness direction of the display panel, the dielectric layer between the conductive patterns 140 and the preset traces 120 may form an interlayer dielectric layer 130 in the non-display area.

[0068] The conductive pattern 140 may be located at least partially on the side of the preset trace 120 away from the substrate 110 within the non-display area, and may be electrically connected to the preset trace 120. In this case, in the thickness direction of the display panel 100, the conductive pattern 140 may at least cover the side of the preset trace 120 away from the substrate 110.

[0069] This embodiment does not limit the specific positional relationship between the interlayer dielectric layer 130 and the conductive pattern 140. For further understanding, please refer to [link / reference needed]. Figure 1 The orthographic projection of the conductive pattern 140 on the substrate 110 can be spaced apart from the orthographic projection of the interlayer dielectric layer 130 on the substrate 110, or, please refer to Figure 2 and Figure 3 The orthographic projection of the conductive pattern 140 on the substrate 110 may overlap with the orthographic projection of the interlayer dielectric layer 130 on the substrate 110, or, please refer to Figures 4 to 6 The orthographic projection of the conductive pattern 140 on the substrate 110 can be connected with the orthographic projection of the interlayer dielectric layer 130 on the substrate 110. The conductive pattern 140 can have a flat surface facing away from the substrate 110, further reducing the possibility of damage.

[0070] For example, please refer to Figure 8 and Figure 9 In the fabrication process of the display panel 100, an isolation layer 190 and multiple wet etching processes are required to fabricate the light-emitting structure. The composition and fabrication of the isolation layer 190 mentioned in this example are further described in patents CN118251982A, 202410864269.8, PCT / CN2024 / 098407, PCT / CN2024 / 102783, PCT / CN2024 / 098217, PCT / CN2024 / 100935, PCT / CN2024 / 102785, PCT / CN2024 / 099419, PCT / CN2024 / 099072, and CN116685174A for reference. Please refer to [link / reference]. Figure 9When the interlayer dielectric layer 13 extends to at least a portion of the surface of the preset trace 12 away from the substrate 11, the conductive pattern 14 is located on the side of the interlayer dielectric layer 13 away from the substrate 110 and extends to the side of the preset trace 12 away from the substrate 11, thereby electrically connecting to the preset trace 12. The conductive pattern 14 on the side of the interlayer dielectric layer 13 facing the preset trace 12 will be stepped ( Figure 9 As shown at point A), a significant height difference appears. When the first electrode (e.g., a cathode) is formed by vapor deposition, it is also formed on the side of the conductive pattern 14 facing away from the substrate 11. During multiple wet etching processes, when the first electrode cannot block the etching process, the etching liquid damages the conductive pattern 14 beneath the first electrode. Furthermore, the stepped conductive pattern 14 at this location suffers severe damage. For example, the conductive pattern 14 may include a three-layer film of titanium layer-aluminum layer-titanium layer, and the titanium layer facing away from the substrate 11 will suffer severe damage. This will seriously affect the display effect of the display panel.

[0071] In this embodiment, by setting the orthographic projection of the interlayer dielectric layer 130 on the substrate 110 to not overlap with the orthographic projection of the preset trace 120 on the substrate 110, the conductive pattern 140 is made flatter, reducing the probability of a large height difference in the conductive pattern 140, and thus reducing the probability of the etching liquid causing serious damage to the conductive pattern 140.

[0072] In one embodiment, see Figures 1 to 3 The orthographic projection of the interlayer dielectric layer 130 on the substrate 110 is spaced apart from the orthographic projection of the preset trace 120 on the substrate 110. Further details can be found in the following references. Figure 1 The orthographic projection of the conductive pattern 140 on the substrate 110 does not overlap with the orthographic projection of the interlayer dielectric layer 130 on the substrate 110.

[0073] For example, please refer to Figure 1 The orthographic projection of the conductive pattern 140 on the substrate 110 can be spaced apart from the orthographic projection of the interlayer dielectric layer 130 on the substrate 110. In this case, a first opening can be provided between the conductive pattern 140 and the interlayer dielectric layer 130. Figure 1 (at point a). In one possible example, the conductive pattern 140 may extend from the side of the preset trace 120 away from the substrate 110 to the substrate 110 between the interlayer dielectric layer 130 and the preset trace 120. It is understood that the conductive pattern 140 may fill the first opening. In this case, the conductive pattern 140 may cover the sidewall of the preset trace 120 facing the first opening. The orthographic projection of the preset trace 120 on the substrate 110 may also lie within the orthographic projection of the conductive pattern 140 on the substrate 110, that is, the conductive pattern 140 may completely cover the preset trace 120.

[0074] In this embodiment, the orthographic projection of the conductive pattern 140 on the substrate 110 can be spaced apart from the orthographic projection of the interlayer dielectric layer 130 on the substrate 110. First, this allows the conductive pattern 140 to extend into the substrate 110 between the interlayer dielectric layer 130 and the preset trace 120, thereby giving the conductive pattern 140 a flat surface facing away from the substrate 110, further reducing the probability of a large height difference in the conductive pattern 140. Second, this first opening not only facilitates glue removal during encapsulation but also provides a certain expansion space for the interlayer dielectric layer 130 or the conductive pattern 140, alleviating large stresses on the interlayer dielectric layer 130 and the conductive pattern 140. Third, the conductive pattern 140 can cover the surface of the preset trace 120 facing away from the substrate 110 and the sidewall of the preset trace 120 facing the first opening, resulting in a large contact area between the conductive pattern 140 and the preset trace 120, thereby reducing the contact resistance between the conductive pattern 140 and the preset trace 120.

[0075] For example, the conductive pattern 140 may include a first conductive pattern 141 and a second conductive pattern 142. The first conductive pattern 141 is located on the side of the preset trace 120 away from the substrate 110 and extends to the substrate 110 between the interlayer dielectric layer 130 and the preset trace 120. The second conductive pattern 142 is located on the side of the first conductive pattern 141 away from the substrate 110 and extends to the substrate 110 between the interlayer dielectric layer 130 and the first conductive pattern 141.

[0076] Both the first conductive pattern 141 and the second conductive pattern 142 can be electrically connected to the conductive structure of the display area. Furthermore, the conductive pattern 140 may also include a third conductive pattern, a fourth conductive pattern, etc. In this embodiment, the first conductive pattern 141 and the second conductive pattern 142 are only illustrative examples; in actual embodiments, the specific number of film layers included in the conductive pattern 140 is not limited to the number of film layers described above.

[0077] The first conductive pattern 141 and the second conductive pattern 142 can cover the substrate 110 exposed by the first opening. In this case, the first conductive pattern 141 and the second conductive pattern 142 can have flat surfaces facing away from the substrate 110. Furthermore, the orthographic projection of the first conductive pattern 141 on the substrate 110 lies within the orthographic projection of the second conductive pattern 142 on the substrate 110. The second conductive pattern 142 can completely cover the first conductive pattern 141, thereby having a larger contact area between the second conductive pattern 142 and the first conductive pattern 141, thereby reducing the contact resistance between the second conductive pattern 142 and the first conductive pattern 141.

[0078] In addition, as an example, please see Figure 10The orthographic projection of the conductive pattern 140 on the substrate 110 and the orthographic projection of the interlayer dielectric layer 130 on the substrate 110 do not overlap. Alternatively, the orthographic projection of the conductive pattern 140 on the substrate 110 can be connected to the orthographic projection of the interlayer dielectric layer 130 on the substrate 110. In this case, it can also be considered that... Figure 1 The first opening in ( Figure 1 The width at point a) is zero. In this example, by connecting the orthographic projection of the conductive pattern 140 on the substrate 110 with the orthographic projection of the interlayer dielectric layer 130 on the substrate 110, the area of ​​the non-display area can be reduced, which is beneficial to the miniaturization of the display panel.

[0079] In one embodiment, see Figure 1 The display panel 100 also includes a pixel definition layer 150.

[0080] The pixel definition layer 150 can extend from the display area to the non-display area, and is located at least on the side of a portion of the interlayer dielectric layer 130 and a portion of the conductive pattern 140 away from the substrate 110.

[0081] As an example, when the conductive pattern 140 has a first opening between it and the interlayer dielectric layer 130, the pixel definition layer 150 can cover at least a portion of the substrate 110 exposed by the first opening, and can also extend to the side of the conductive pattern 140 facing away from the substrate 110. In this case, the conductive pattern 140 faces the interlayer dielectric layer 130. Further details can be found in the following sections. Figure 10 The top surface of the pixel definition layer 150 facing away from the substrate 110 is flush with the top surface of the conductive pattern 140 facing away from the substrate 110, thereby eliminating the height difference between the pixel definition layer 150 and the conductive pattern 140 and reducing the probability of the conductive pattern 140 being damaged by wet etching.

[0082] The orthographic projection of the pixel definition layer 150 on the substrate 110 does not overlap with the orthographic projection of the preset trace 120 on the substrate 110, thereby preserving a larger surface of the conductive pattern 140 facing away from the substrate 110, which is beneficial for the conductive pattern 140 to be electrically connected to other structures.

[0083] In this embodiment, by setting a pixel definition layer 150 to cover the side of the conductive pattern 140 away from the substrate 110, the pixel definition layer 150 protects at least a portion of the conductive pattern 140 from damage during the wet etching process.

[0084] In one embodiment, see Figures 2 to 3 The orthographic projection of the preset trace 120 on the substrate 110 and the orthographic projection of the interlayer dielectric layer 130 on the substrate 110 are spaced apart, and the orthographic projection of the conductive pattern 140 on the substrate 110 and the orthographic projection of the interlayer dielectric layer 130 on the substrate 110 have an overlapping portion.

[0085] At this time, the conductive pattern 140 extends from the side of the preset trace 120 away from the substrate 110, through the side of the substrate 110 between the preset trace 120 and the interlayer dielectric layer 130, to the side of the interlayer dielectric layer 130 away from the substrate 110.

[0086] In this embodiment, the gap between the preset trace 120 and the interlayer dielectric layer 130 can be small, which is beneficial for miniaturization of the display panel 100. The conductive pattern 140 can also cover the sidewall of the preset trace 120 facing the interlayer dielectric layer 130, thereby providing a larger contact area between the conductive pattern 140 and the preset trace 120, and reducing the contact resistance between the conductive pattern 140 and the preset trace 120.

[0087] For example, the conductive pattern 140 includes a first conductive pattern 141 and a second conductive pattern 142. The first conductive pattern 141 is located on the side of the preset trace 120 away from the substrate 110 and extends to the interlayer dielectric layer 130. The second conductive pattern 142 is located on the side of the first conductive pattern 141 away from the substrate 110 and extends to the interlayer dielectric layer 130. In this case, the orthographic projection of the first conductive pattern 141 on the substrate 110 is within the orthographic projection of the second conductive pattern 142 on the substrate 110. In this example, by setting both the first conductive pattern 141 and the second conductive pattern 142 to extend to the side of the interlayer dielectric layer 130 away from the substrate 110, the contact area between the first conductive pattern 141 and the second conductive pattern 142 is increased, thereby reducing the contact resistance between the conductive pattern 140 and the preset trace 120.

[0088] Furthermore, in this embodiment, the display panel 100 also includes a pixel definition layer 150. The pixel definition layer 150 may be located at least on the side of the interlayer dielectric layer 130 and the conductive pattern 140 facing away from the substrate 110. Since the conductive pattern 140 extends to the side of the interlayer dielectric layer 130 away from the substrate 110, a small height difference appears in the conductive pattern 140. At this time, the pixel definition layer 150 can cover the part with the height difference, protecting the conductive pattern 140 from damage by wet etching. Moreover, the orthographic projection of the pixel definition layer 150 on the substrate 110 does not overlap with the orthographic projection of the preset trace 120 on the substrate 110, thereby preserving a larger surface area of ​​the conductive pattern 140 facing away from the substrate 110, which is beneficial for the conductive pattern 140 to be electrically connected to other structures.

[0089] In one embodiment, see Figure 3 The display panel 100 also includes a first protective layer 160.

[0090] The first protective layer 160 may be located on the side of the pixel definition layer 150 facing away from the substrate 110. As an example, the orthographic projection of the first protective layer 160 onto the substrate 110 overlaps with the orthographic projection of the preset trace 120 onto the substrate 110. In this case, the first protective layer 160 may cover the sidewall of the pixel definition layer 150 facing the conductive line. As an example, the material of the first protective layer 160 may include inorganic materials.

[0091] In this embodiment, by setting the first protective layer 160 to be located on the side of the pixel definition layer 150 away from the substrate 110, the protection of the conductive pattern 140 is increased, and the probability of the conductive pattern 140 being damaged by wet etching is further reduced.

[0092] In one embodiment, see Figures 4 to 6 The orthographic projection of the preset trace 120 on the substrate 110 is connected to the orthographic projection of the interlayer dielectric layer 130 on the substrate 110. At this time, the side of the preset trace 120 facing the interlayer dielectric layer 130 is connected to the side of the interlayer dielectric layer 130 facing the conductive pattern 140. Please refer to... Figure 4 At this point, the orthographic projection of the conductive pattern 140 onto the substrate 110 can be connected to the orthographic projection of the interlayer dielectric layer 130 onto the substrate 110, and the conductive pattern 140 is flat away from the top surface of the substrate 110. Further details can be found in the following sections. Figure 4 The top surface of the conductive pattern 140 facing away from the substrate 110 can also be flush with the top surface of the interlayer dielectric layer 130 facing away from the substrate 110, thereby further reducing the probability of damage to the conductive pattern 140 by wet etching. Alternatively, please refer to... Figure 5 and Figure 6 The orthographic projection of the conductive pattern 140 on the substrate 110 can overlap with the orthographic projection of the interlayer dielectric layer 130 on the substrate 110, thereby increasing the area of ​​the conductive pattern 140 and facilitating the bonding of the conductive pattern 140.

[0093] For example, please refer to Figures 5 to 7 The display panel 100 also includes a second protective layer 170. For example, the second protective layer 170 may be located at least on the side of a portion of the interlayer dielectric layer 130 facing away from the substrate 110, and extend to the side of the conductive pattern 140 facing away from the substrate 110. In this case, the orthographic projection of the second protective layer 170 on the substrate 110, the orthographic projection of the interlayer dielectric layer 130 on the substrate 110, and the orthographic projection of the conductive pattern 140 on the substrate 110 at least partially overlap. Furthermore, the top surface of the second protective layer 170 facing away from the substrate 110 has a first distance from the substrate 110. Figure 4 (h1), the conductive pattern 140 has a second distance between its top surface away from the substrate 110 and the substrate 110. Figure 4The height of the second protective layer 170 can be greater than the height of the conductive pattern 140, so that if the first electrode cannot block the etching liquid, the etching liquid can etch the second protective layer 170, thereby preventing damage to the conductive pattern 140.

[0094] The orthographic projection of the preset trace 120 on the substrate 110 can lie within the orthographic projection of the conductive pattern 140 on the substrate 110, thereby providing a larger contact area between the conductive pattern 140 and the preset trace 120, thus reducing the contact resistance between the conductive pattern 140 and the preset trace 120. Further details can be found in the following sections. Figure 6 The orthographic projection of the pre-set trace 120 on the substrate 110 and the orthographic projection of the second protective layer 170 on the substrate 110 are spaced apart, thereby preserving a larger surface of the conductive pattern 140 facing away from the substrate 110, which is beneficial for the conductive pattern 140 to be electrically connected to other structures.

[0095] In this embodiment, by setting a preset trace 120 to connect the side of the interlayer dielectric layer 130 facing the side of the interlayer dielectric layer 130 facing the conductive pattern 140, it is beneficial to miniaturize the display panel 100. Moreover, in this embodiment, a second protective layer 170 can be set on the side of the conductive pattern 140 facing away from the substrate 110, thereby preventing damage to the conductive pattern 140.

[0096] Furthermore, the material of the second protective layer 170 can be the same as that of the first electrode (e.g., the cathode). In this case, if the first electrode cannot block the etching liquid, the second protective layer 170 can protect the underlying film layer.

[0097] Based on the same inventive concept, this application also provides a display device (not shown), which includes the display panel 100 in the above embodiments.

[0098] It is understood that the display device in the embodiments of this application can be any product or component with display function, such as OLED display device, QLED display device, electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, wearable device, Internet of Things device, etc., and the embodiments disclosed in this application do not limit this.

[0099] In the description of this specification, references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the phrase "this embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment.

[0100] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0101] The embodiments described above are merely examples of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims. The above descriptions are merely preferred embodiments of this disclosure and do not limit the patent scope of this disclosure. Any equivalent structural transformations made based on the inventive concept of this disclosure, utilizing the content of this specification and drawings, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area, and the display panel includes: substrate; Pre-defined traces, at least a portion of which are located on one side of the substrate within the non-display area; An interlayer dielectric layer, at least a portion of which is located on one side of the substrate within the non-display area and is disposed on the same side as the preset trace, wherein the orthographic projection of the interlayer dielectric layer on the substrate does not overlap with the orthographic projection of the preset trace on the substrate.

2. The display panel according to claim 1, characterized in that, The display panel also includes: The conductive pattern, at least a portion of which is located on the side of the preset trace in the non-display area away from the substrate.

3. The display panel according to claim 2, characterized in that, The orthographic projection of the conductive pattern on the substrate does not overlap with the orthographic projection of the interlayer dielectric layer on the substrate.

4. The display panel according to claim 3, characterized in that, The orthographic projection of the conductive pattern on the substrate is spaced apart from the orthographic projection of the interlayer dielectric layer on the substrate, and the orthographic projection of the interlayer dielectric layer on the substrate is spaced apart from the orthographic projection of the preset trace on the substrate. The conductive pattern extends from the side of the preset trace away from the substrate to the substrate between the interlayer dielectric layer and the preset trace. Optionally, the orthographic projection of the preset trace on the substrate lies within the orthographic projection of the conductive pattern on the substrate.

5. The display panel according to claim 4, characterized in that, The conductive pattern includes a first conductive pattern and a second conductive pattern. The first conductive pattern is located on the side of the preset trace away from the substrate and extends to the substrate between the interlayer dielectric layer and the preset trace. The second conductive pattern is located on the side of the first conductive pattern away from the substrate and extends to the substrate between the interlayer dielectric layer and the first conductive pattern; Optionally, the orthographic projection of the first conductive pattern on the substrate lies within the orthographic projection of the second conductive pattern on the substrate.

6. The display panel according to claim 4, characterized in that, The display panel also includes: A pixel definition layer extends from the display area to the non-display area, and is located at least on the side of a portion of the interlayer dielectric layer and a portion of the conductive pattern away from the substrate. The pixel definition layer extends from the side of the interlayer dielectric layer away from the substrate, through the substrate between the interlayer dielectric layer and the preset trace, to the side of the conductive pattern away from the substrate. Optionally, the orthographic projection of the pixel definition layer on the substrate does not overlap with the orthographic projection of the preset trace on the substrate.

7. The display panel according to claim 6, characterized in that, The pixel definition layer is flush with the top surface of the substrate opposite to the top surface of the conductive pattern opposite to the top surface of the substrate.

8. The display panel according to claim 3, characterized in that, The orthographic projection of the conductive pattern on the substrate is connected to the orthographic projection of the interlayer dielectric layer on the substrate, and the orthographic projection of the interlayer dielectric layer on the substrate is spaced from the orthographic projection of the preset trace on the substrate.

9. The display panel according to claim 2, characterized in that, The orthographic projection of the conductive pattern on the substrate overlaps with the orthographic projection of the interlayer dielectric layer on the substrate.

10. The display panel according to claim 9, characterized in that, The orthographic projection of the interlayer dielectric layer on the substrate is spaced apart from the orthographic projection of the preset trace on the substrate. The conductive pattern extends from the side of the preset trace away from the substrate, through the side of the substrate between the preset trace and the interlayer dielectric layer, to the side of the interlayer dielectric layer away from the substrate.

11. The display panel according to claim 9, characterized in that, The conductive pattern includes a first conductive pattern and a second conductive pattern. The first conductive pattern is located on the side of the preset trace away from the substrate and extends to the interlayer dielectric layer. The second conductive pattern is located on the side of the first conductive pattern away from the substrate and extends to the interlayer dielectric layer. Optionally, the orthographic projection of the first conductive pattern on the substrate lies within the orthographic projection of the second conductive pattern on the substrate.

12. The display panel according to claim 9, characterized in that, The display panel also includes: A pixel definition layer extends from the display area to the non-display area, and is located at least on the side of a portion of the interlayer dielectric layer and a portion of the conductive pattern facing away from the substrate; Optionally, the orthographic projection of the pixel definition layer on the substrate overlaps with the orthographic projection of the preset trace on the substrate.

13. The display panel according to claim 12, characterized in that, The display panel also includes: The first protective layer is located on the side of the pixel definition layer that faces away from the substrate; Optionally, the orthographic projection of the first protective layer on the substrate overlaps with the orthographic projection of the preset trace on the substrate.

14. The display panel according to claim 2, characterized in that, The display panel includes: The second protective layer is located at least on the side of a portion of the interlayer dielectric layer and a portion of the conductive pattern that faces away from the substrate, wherein the orthographic projection of the conductive pattern on the substrate overlaps with the orthographic projection of the interlayer dielectric layer on the substrate.

15. The display panel according to claim 14, characterized in that, The display panel also includes: A first electrode, at least partially located in the display area, and a second protective layer made of the same material as the first electrode.

16. The display panel according to claim 1, characterized in that, The orthographic projection of the preset trace on the substrate is connected to the orthographic projection of the interlayer dielectric layer on the substrate.

17. The display panel according to claim 16, characterized in that, The display panel also includes: The conductive pattern, at least a portion of which is located on the side of the preset trace in the non-display area away from the substrate, is connected to the orthographic projection of the conductive pattern on the substrate and the orthographic projection of the interlayer dielectric layer on the substrate.

18. The display panel according to claim 17, characterized in that, The conductive pattern is flush with the top surface of the substrate opposite to the top surface of the interlayer dielectric layer opposite to the top surface of the substrate.

19. The display panel according to claim 16, characterized in that, The display panel also includes: The conductive pattern, at least a portion of which is located on the side of the preset trace in the non-display area away from the substrate, has an overlapping portion between the orthographic projection of the conductive pattern on the substrate and the orthographic projection of the interlayer dielectric layer on the substrate.

20. A display device, characterized in that, Includes the display panel as described in any one of claims 1-19.

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