Superconducting quantum chip, substrate and processing method thereof
By forming a protective layer on the inner wall of the photoresist trench, the problem of unstable morphology of the photoresist mask in deep silicon etching was solved, and high-quality processing of through-silicon vias was achieved, meeting the process requirements.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-29
- Publication Date
- 2026-03-13
AI Technical Summary
During deep silicon etching, as the temperature rises, the energy of plasma acceleration increases, causing the photoresist mask surface to collapse, sidewalls to break and expand, resulting in increased roughness of the inner wall of the through-silicon via, which fails to meet process requirements.
A protective layer is formed on the inner wall of the trench in the photoresist layer. A second trench is formed around the protective layer to protect the photoresist layer from etching. Appropriate materials such as aluminum, titanium nitride, titanium niobium nitride, or silicon dioxide are used, and wet and dry etching techniques are combined to remove the material at the bottom of the protective layer to ensure the morphology of the photoresist layer is stable.
It effectively protects the morphology of the photoresist layer, prevents expansion or breakage, ensures that the parameters of the through-silicon via meet the preset requirements, and improves the etching quality.
Smart Images
Figure CN121666047A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of deep silicon etching technology, and in particular relates to a superconducting quantum chip, substrate and its processing method. Background Technology
[0002] In the fabrication of superconducting quantum chips, the chip substrate is often processed, such as etching trenches, vias, or through holes on the silicon substrate. These can be accomplished using deep silicon etching technology to obtain the target pattern on the substrate.
[0003] Currently, silicon is commonly used as the substrate for superconducting quantum chips. Due to the high selectivity of photoresist to silicon, photoresist is frequently used as a mask in deep silicon etching. Deep silicon etching technology typically employs dry etching, where radio frequency power is a key process parameter, including both Source Power and Bias Power. During the etching process on the silicon substrate, charged ions in the plasma are accelerated by an electric field, physically bombarding the silicon wafer surface. Simultaneously, free radicals from the plasma diffuse to the silicon wafer surface and react with the silicon, thereby performing physicochemical etching.
[0004] However, during deep silicon etching, as the temperature increases, the energy of plasma acceleration increases, which can lead to problems such as mask surface collapse, sidewall fracture, and adhesive expansion. These phenomena can significantly increase the roughness of the inner wall of the through-silicon via, thus failing to meet the process requirements. Summary of the Invention
[0005] The purpose of this application is to provide a method for processing substrates to solve the problems in the prior art where, during deep silicon etching, as the temperature increases, the energy of plasma acceleration increases, leading to the collapse of the resist mask surface, breakage of the resist sidewalls, and resist expansion. This method can protect the resist mask layer during deep silicon etching, giving it a stable morphology, so as to provide a stable constraint on subsequent etching and ensure that the formed silicon vias achieve the expected goals.
[0006] To solve the above-mentioned technical problems, the present invention provides a method for processing a substrate, comprising:
[0007] A substrate having a first photoresist layer disposed on its surface is provided; the first photoresist layer forms a first trench exposing a portion of the substrate.
[0008] A protective layer is formed on the inner wall of the first trench; the protective layer surrounds and forms a second trench;
[0009] The substrate is etched through the second trench in the thickness direction of the substrate.
[0010] Preferably, the method for forming the first photoresist layer on the surface of the substrate further includes:
[0011] The first photoresist layer is patterned to form a first trench that penetrates the first photoresist layer and exposes a portion of the substrate.
[0012] Preferably, the protective layer comprises a layered stop layer and a second photoresist layer;
[0013] The cutoff layer covers the first photoresist layer, and the second photoresist layer covers the surface of the cutoff layer opposite to the first photoresist layer.
[0014] Preferably, the material of the stop layer is one of aluminum, titanium nitride, titanium niobium nitride, and silicon dioxide.
[0015] Preferably, the method for forming a protective layer on the inner wall of the first trench includes:
[0016] The protective layer is formed at the bottom and sidewalls of the first trench;
[0017] Remove the protective layer located at the bottom of the first trench; so that the protective layer located on the sidewall surrounds and forms a second trench, and exposes a portion of the substrate through the second trench.
[0018] Preferably, the method for removing the protective layer located at the bottom of the first trench includes:
[0019] The second photoresist layer located at the bottom of the first trench is etched away to expose a portion of the stop layer;
[0020] The cutoff layer located at the bottom of the first trench is etched away to expose a portion of the substrate.
[0021] Preferably, after etching the substrate through the second trench in the thickness direction of the substrate, the method of processing the substrate further includes:
[0022] Remove the protective layer and the first photoresist layer.
[0023] This application also provides a substrate, comprising:
[0024] The substrate manufactured by the substrate processing method described above is provided with a through hole penetrating two opposing surfaces in the thickness direction.
[0025] This application also provides a superconducting quantum chip, comprising:
[0026] The aforementioned substrate; and
[0027] The first quantum circuit and the second quantum circuit are located on the two opposite surfaces, respectively.
[0028] Preferably, a metal connector is formed within the through hole, the metal connector being used to electrically connect the first quantum circuit and the second quantum circuit.
[0029] Compared with the prior art, this application provides a protective layer on the sidewall of the first trench formed by the first photoresist layer. This protective layer surrounds and forms a second trench. Subsequent processes use the second trench to etch the substrate therein, which can protect the morphology of the first photoresist layer. This ensures that the first photoresist layer is not affected in the subsequent etching process of the substrate, preventing problems such as expansion and breakage. As a result, the parameters of the through-silicon vias formed by deep silicon etching technology meet the preset requirements. Attached Figure Description
[0030] Figure 1 This is a schematic diagram of a method for processing a substrate provided in an embodiment of this application;
[0031] Figure 2 A schematic diagram of the structure of the protective layer formed on the sidewall of the first trench according to an embodiment of this application;
[0032] Figure 3 A schematic diagram of the structure in which the stop layer and the second photoresist layer are formed on the sidewall of the first trench, as provided in the embodiments of this application;
[0033] Figure 4 This is a flowchart illustrating the specific process of fabricating the substrate as provided in an embodiment of this application.
[0034] Explanation of reference numerals in the attached figures: 1 - substrate, 2 - first photoresist layer, 201 - first trench, 3 - protective layer, 31 - stop layer, 32 - second photoresist layer, 301 - second trench. Detailed Implementation
[0035] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0036] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.
[0037] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0038] Deep silicon etching is a microfabrication technique that enables the creation of high aspect ratio three-dimensional structures on silicon materials. This technique has gradually evolved from wet etching to dry etching, in which dry etching utilizes radio frequency power to generate highly reactive ions or electrons to physically bombard and chemically react with the silicon wafer, thereby selectively removing material.
[0039] In practical applications, deep silicon etching technology requires optimization of various process parameters, such as substrate power, chamber pressure, etching / passivation cycle, and gas flow rate, in order to achieve ideal etching morphology, including aspect ratio, sidewall perpendicularity, and surface roughness.
[0040] Current deep silicon etching technology, as exemplified below, involves providing a substrate, forming a mask layer on the front side of the substrate, and forming an etch stop layer on the back side. An opening is made in the mask to expose the substrate surface to be etched. Etching is performed through this opening until the stop layer is reached, forming a via through the two opposing surfaces of the substrate. Finally, the stop layer and mask layer are removed. This method can efficiently fabricate vias on a substrate without damaging other parts of the substrate. Specifically, the etching process employs multiple alternating deposition and etching cycles. For example, C4F8 gas is used for deposition, and SF6 is used for etching. C4F8 dissociates into a plasma to form a fluorine carbide polymer, which is deposited on the silicon surface as a barrier, preventing the chemical reaction between fluorine ions and silicon and improving etching selectivity. SF6 is used as the etching gas, generating sulfur dioxide in the plasma. x F y Ions and F-active free radicals, these ions, under the influence of an electric field, bombard the matrix in a nearly perpendicular direction.
[0041] Currently, due to the high etch selectivity of photoresist to silicon, photoresist is often used as a mask in deep silicon etching. During deep silicon etching, both the source power and bias power can reach tens of kW. The higher the power, the higher the surface temperature of the silicon wafer; the higher the power, the greater the energy of the free radicals in the plasma being accelerated, which may lead to abnormalities in the photoresist mask.
[0042] Normal photoresist masks are non-collapsed and non-expanded. During deep silicon etching, as the temperature rises and the plasma acceleration energy increases, problems such as mask surface collapse, sidewall breakage, and photoresist expansion occur, which undoubtedly significantly increases the roughness of the inner wall of the through-silicon via.
[0043] Please refer to Figure 1 and Figure 2 This invention provides a method for processing a substrate 1, comprising:
[0044] S1: Provide a substrate 1 with a first photoresist layer 2 disposed on its surface;
[0045] S2: A protective layer 3 is formed on the inner wall of the first trench 201;
[0046] S3: In the thickness direction of the substrate 1, the substrate 1 is etched through the second trench 301.
[0047] The photoresist layer forms a first trench 201 that exposes a portion of the substrate 1; the protective layer 3 is located within the first trench 201 and surrounds a second trench 301.
[0048] Specifically, a first photoresist layer 2 is formed on the surface of substrate 1. Optionally, wet cleaning is used to remove contaminants, including particles and organic matter, from the surface of substrate 1. Subsequently, it is rinsed with deionized water and dehydrated and baked to remove water vapor, making the surface of substrate 1 change from hydrophilic to hydrophobic, thereby increasing the adhesion of the substrate 1 surface. Then, the first photoresist layer 2 is uniformly coated on the surface of substrate 1 by static or dynamic coating. The viscosity of the photoresist and the rotation speed of the tray are key parameters that determine the thickness of the first photoresist layer 2. Then, the first photoresist layer 2 is exposed and developed to form a first trench 201 on the first photoresist layer 2 that exposes a portion of substrate 1. It should be noted that the choice of developer and the development time have a significant impact on the quality of the final first trench 201 pattern.
[0049] Then, a protective layer 3 is formed on the inner wall of the first trench 201. The protective layer 3 is adhered to the inner wall of the first trench 201 and is used to protect the sidewalls of the first photoresist layer 2 from being accidentally etched during the etching process of the substrate 1. Furthermore, when a suitable material, such as aluminum, is chosen for part of the protective layer 3, the protective layer 3 can also have a heat dissipation effect. Additionally, the bottom of the protective layer 3 is etched to expose a portion of the substrate 1 located at the bottom; the protective layer 3 surrounds to form a second trench 301, through which the substrate 1 can be etched. It is worth noting that the diameter of the silicon via formed by etching the substrate 1 is pre-defined to be on the micrometer scale, while the thickness of the protective layer 3 is on the nanometer scale, and the etching of the substrate 1 itself has an acceptable over-etching range. Therefore, the thickness of the protective layer 3 will not have a non-negligible negative impact on the trench or via structure to be etched on the substrate 1.
[0050] Furthermore, the method for forming the first photoresist layer 2 on the surface of the substrate 1 further includes: patterning the first photoresist layer 2 to form a first trench 201 that penetrates through and exposes a portion of the substrate 1. That is, photoresist is uniformly applied to the surface of the substrate 1 to form a thin film, which needs to have appropriate thickness and uniformity, and is then soft-baked to remove the solvent in the photoresist and fix the photoresist layer to form the first photoresist layer 2; then, using a high-resolution lithography machine, the pattern on the photomask is projected onto the first photoresist layer 2 through an exposure system; then, the exposed photoresist is developed using a developer to form the pattern of the first trench 201. During the development process, the exposed areas of the positive photoresist will dissolve, and the unexposed areas of the negative photoresist will dissolve, thereby forming the first trench 201.
[0051] In one embodiment of this application, the protective layer 3 includes, as follows: Figure 3 The diagram shows a layered distribution of a stop layer 31 and a second photoresist layer 32; the stop layer 31 covers the first photoresist layer 2, and the second photoresist layer 32 covers the surface of the stop layer 31 away from the surface of the first photoresist layer 2. Specifically, the material of the stop layer 31 is one of aluminum, titanium nitride, titanium niobium nitride, and silicon dioxide.
[0052] For example, if the material of the stop layer 31 is set to aluminum, then the aluminum layer and the second photoresist layer 32 serve to protect the sidewalls of the first trench 201. Metallic aluminum does not react with the fluorine-based gas used for etching silicon; therefore, the aluminum layer adheres to the sidewalls of the first trench 201, preventing the sidewalls of the first photoresist layer 2 from being etched by accelerated free radicals, thus maintaining the morphology of the first photoresist layer 2 and preventing problems such as expansion or breakage. (Under normal circumstances, metallic aluminum does not react directly with fluorine-based gas because in semiconductor manufacturing, etching steps are performed under specific conditions, such as in a plasma environment, where fluorine-based gas reacts with silicon to generate gaseous silicon fluoride (SiF4) which is then removed, but does not react with metallic aluminum.) Furthermore, metallic aluminum has good thermal conductivity, which can effectively dissipate the high temperatures generated by the radio frequency device.
[0053] Please refer to Figure 4 In order to etch the substrate 1 located in the first trench 201, it is necessary to remove the aluminum layer located at the bottom of the first trench 201. Therefore, in order to remove the aluminum layer at the bottom of the first trench 201 without removing the aluminum on the sidewalls, so as to protect the first photoresist layer 2 on the sidewalls, a second photoresist layer 32 is formed on the surface of the aluminum layer. The second photoresist layer 32 located at the bottom of the second trench 301 is removed first, and then the aluminum located at the bottom of the second trench 301 is removed. The remaining second photoresist layer 32 is used to protect the aluminum layer located on the sidewalls from being etched away. In addition, the second photoresist layer 32 is also used to protect the aluminum layer from oxidation. If the aluminum surface is oxidized to form aluminum oxide, then under certain conditions, aluminum oxide can react with fluorides.
[0054] For example, the first photoresist layer 2 can be selected as AZ9260 photoresist with a thickness of 20μm-40μm, the thickness of the stop layer 31 - aluminum film is 100nm, and the second photoresist layer 32 can be selected as S1813 photoresist. Its thickness is roughly determined by the thickness of the first photoresist layer 2 and is proportional to it. For example, 20-micron AZ9260 photoresist corresponds to 300nm-700nm S1813 photoresist, and 40-micron AZ9260 photoresist corresponds to 500-1000nm S1813 photoresist.
[0055] In one embodiment of this application, a method for forming a protective layer 3 on the inner wall of a first trench 201 is provided, comprising:
[0056] Step 1: Form a protective layer 3 at the bottom and sidewalls of the first trench 201;
[0057] Step 2: Remove the protective layer 3 located at the bottom of the first trench 201; so that the protective layer 3 located on the sidewall surrounds the second trench 301 and exposes part of the substrate 1 through the second trench 301.
[0058] The above method utilizes electron beam evaporation deposition to form a protective layer 3 on the sidewalls and bottom of the first trench 201. Even the surface of the first photoresist layer 2 facing away from the substrate 1 is also covered with a protective layer 3. The second photoresist layer 32 can be controlled by adjusting the amount of photoresist and the rotation speed. Furthermore, the second photoresist layer 32 can be non-uniform from top to bottom, such as being thicker at the top and thinner at the bottom. This is still feasible in experiments because the function of the second photoresist layer 32 is solely to protect the aluminum layer located on the sidewalls of the first trench 201, preventing the sidewall filter layer from being etched away by chlorine-based gas during the etching of the bottom aluminum layer. The aluminum layer, in turn, protects the first photoresist layer 2 on the sidewalls of the first trench 201, ensuring it is not affected during the etching of the substrate 1. This maintains the shape of the first trench 201 formed by the first photoresist layer 2 and improves heat dissipation performance.
[0059] In one embodiment of this application, a method for removing the protective layer 3 located at the bottom of the first trench 201 is provided:
[0060] Step 1: Etch away the second photoresist layer 32 located at the bottom of the first trench 201 to expose part of the stop layer 31;
[0061] Step 2: Etch away the stop layer 31 located at the bottom of the first trench 201 to expose part of the substrate 1.
[0062] For example, oxygen plasma in the plasma reaction chamber is used to etch the second photoresist layer 32, thereby removing the second photoresist layer 32 located at the bottom of the first trench 201 and exposing the stop layer 31 located at the bottom of the first trench 201. It is worth noting that the second photoresist layer 32 located on the sidewall of the first trench 201 is not etched, and the second photoresist layer 32 on the sidewall of the first trench 201 can continue to cover the surface of the stop layer 31.
[0063] After removing the second photoresist layer 32 located at the bottom of the first trench 201, the exposed stop layer 31 in this area also needs to be removed to expose the substrate 1 at the bottom of the second trench 301. For example, the material of the stop layer 31 is aluminum, and it can be removed by aluminum etching solution or by ICP-chlorine gas etching.
[0064] Using an aluminum etching solution is a wet etching technique that selectively etches aluminum using a specific chemical solution. This solution typically contains components that react chemically with aluminum, dissolving it while having minimal impact on other materials such as the silicon substrate 1 or the photoresist. This method allows for precise removal of aluminum material from the bottom of the first trench 201 without affecting the second photoresist layer 32 located on the sidewalls and the substrate 1 at the bottom.
[0065] ICP – Chlorine-based Gas Etching: ICP stands for Inductively Coupled Plasma, a dry etching technique. In ICP etching, a chlorine-based gas (chlorine or hydrogen chloride) is used as the reactant gas to generate plasma. The active chlorine atoms in the plasma react chemically with the aluminum material to produce volatile aluminum chloride, thus removing the aluminum. This method can remove aluminum material either bulk or selectively.
[0066] The choice between these two methods depends on the specific process requirements, material properties, and the desired selectivity and uniformity. Wet etching generally offers better selectivity and control, while dry etching can be performed without contact with chemicals, reducing potential chemical contamination and corrosion problems.
[0067] Furthermore, after the process of "etching substrate 1 through the second trench 301 in the thickness direction of substrate 1", the method for processing substrate 1 further includes:
[0068] Remove the protective layer 3 and the first photoresist layer 2.
[0069] By using deep silicon etching technology, trenches, vias, or through holes are etched on the silicon substrate 1, and finally the protective layer 3 and the first photoresist layer 2 are removed to make the substrate 1 independent, so that the substrate 1 can be used alone for manufacturing or production.
[0070] This invention provides a substrate 1, which is manufactured by the substrate 1 processing method described above. The substrate 1 is provided with a through hole that penetrates two opposing surfaces in the thickness direction.
[0071] This invention provides a superconducting quantum chip, including a substrate 1 as described above, and a first quantum circuit and a second quantum circuit located on two opposite surfaces of the substrate 1.
[0072] Furthermore, a metal connector is formed within the through-hole, which is used to electrically connect the first quantum circuit and the second quantum circuit.
[0073] Metal connectors placed within the vias create vertical connection paths, enabling electrical connection between the first and second quantum circuits located on different surfaces of substrate 1. The metal connectors can be made of various materials, such as copper, tungsten, or aluminum, and are filled using techniques such as electroplating, chemical vapor deposition, or physical vapor deposition to achieve electrical connection. The choice of filling process has a significant impact on the performance and reliability of the quantum circuits; therefore, the optimal solution must be determined by comprehensively considering material properties, process compatibility, and the requirements of the final application.
[0074] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," or "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0075] The above description, based on the embodiments shown in the drawings, details the structure, features, and effects of this application. The above description is only a preferred embodiment of this application, but this application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of this application, or modifications to equivalent embodiments, that do not exceed the spirit covered by the specification and drawings, should be within the protection scope of this application.
Claims
1. A method for processing a substrate, characterized in that, include: A substrate (1) with a first photoresist layer (2) disposed on its surface is provided; the first photoresist layer (2) forms a first trench (201) exposing a portion of the substrate (1); A protective layer (3) is formed on the inner wall of the first trench (201); the protective layer (3) surrounds the formation of the second trench (301); The substrate (1) is etched in the thickness direction of the substrate (1) through the second trench (301).
2. The method for processing a substrate according to claim 1, characterized in that, The method for forming a first photoresist layer (2) on the surface of the substrate (1) further includes: The first photoresist layer (2) is patterned to form a first trench (201) that penetrates the first photoresist layer (2) and exposes a portion of the substrate (1).
3. The method for processing a substrate according to claim 1, characterized in that, The protective layer (3) includes a layered stop layer (31) and a second photoresist layer (32); The cutoff layer (31) covers the first photoresist layer (2), and the second photoresist layer (32) covers the surface of the cutoff layer (31) away from the first photoresist layer (2).
4. The method for processing a substrate according to claim 3, characterized in that, The material of the stop layer (31) is one of aluminum, titanium nitride, titanium niobium nitride, and silicon dioxide.
5. The method for processing a substrate according to claim 3, characterized in that, The method for forming a protective layer (3) on the inner wall of the first trench (201) includes: The protective layer (3) is formed at the bottom and sidewalls of the first trench (201); Remove the protective layer (3) located at the bottom of the first trench (201); so that the protective layer (3) located on the sidewall surrounds the formation of the second trench (301), and exposes a portion of the substrate (1) through the second trench (301).
6. The method for processing a substrate according to claim 5, characterized in that, The method for removing the protective layer (3) located at the bottom of the first trench (201) includes: The second photoresist layer (32) located at the bottom of the first trench (201) is etched away to expose part of the stop layer (31); The cutoff layer (31) located at the bottom of the first trench (201) is etched away to expose a portion of the substrate (1).
7. The method for processing a substrate according to claim 1, characterized in that, After etching the substrate (1) through the second trench (301) in the thickness direction of the substrate (1), the method of processing the substrate (1) further includes: Remove the protective layer (3) and the first photoresist layer (2).
8. A substrate, characterized in that, include: The substrate (1) manufactured by the substrate processing method according to any one of claims 1-7 is provided with a through hole penetrating two opposing surfaces in the thickness direction.
9. A superconducting quantum chip, characterized in that, include: The substrate (1) according to claim 8; and The first quantum circuit and the second quantum circuit are located on the two opposite surfaces, respectively.
10. The superconducting quantum chip according to claim 9, characterized in that, A metal connector is formed within the through hole, and the metal connector is used to electrically connect the first quantum circuit and the second quantum circuit.