Semiconductor device with transferable substrate and preparation method thereof

Abstract

The invention discloses a semiconductor device with a transferable substrate and a preparation method thereof. The semiconductor device comprises a base substrate; the semiconductor device structure layer is positioned on one side of the basic substrate; the peelable intermediate layer is located between the basic substrate and the semiconductor device structure layer; wherein the peelable intermediate layer has electric penetrability and can separate the basic substrate from the semiconductor device structure layer, so that the semiconductor device structure layer can be transferred to a target substrate, the manufacturing cost of the device is reduced, and the integrated application scene of the semiconductor device is expanded.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device with a transferable substrate and a method for fabricating the same. Background Technology

[0002] As a representative of third-generation semiconductor materials, silicon carbide (SiC) has advantages over silicon (Si), such as a wider bandgap, a higher critical breakdown electric field, and higher thermal conductivity. Therefore, SiC semiconductor devices have significant advantages in high-power and high-temperature applications.

[0003] Currently, taking SiC MOSFETs as an example, the substrate material of SiC semiconductor devices is usually SiC. In terms of application scenarios, SiC substrates are difficult to be compatible with mainstream silicon-based CMOS processes. The rigidity of traditional SiC devices cannot meet the demand for flexible power electronic devices in emerging fields such as wearable electronics and flexible energy systems. Furthermore, the production cost of SiC substrate materials is relatively high, which cannot meet the demand for reducing device costs. Summary of the Invention

[0004] This invention provides a semiconductor device with a transferable substrate and a method for fabricating the same, which reduces device manufacturing costs and expands the integrated application scenarios of semiconductor devices.

[0005] In a first aspect, embodiments of the present invention provide a semiconductor device with a transferable substrate, comprising:

[0006] Basic substrate;

[0007] A semiconductor device structure layer is located on one side of the base substrate;

[0008] A peelable intermediate layer is located between the base substrate and the semiconductor device structure layer; wherein the peelable intermediate layer is electrically permeable and enables separation of the base substrate and the semiconductor device structure layer so that the semiconductor device structure layer can be transferred to a target substrate.

[0009] Optionally, the peelable intermediate layer comprises at least two stacked two-dimensional material layers, with adjacent two-dimensional material layers bonded together by van der Waals forces.

[0010] Optionally, the two-dimensional material layer includes at least one of graphene, hexagonal boron nitride, molybdenum disulfide, or tungsten disulfide.

[0011] Optionally, the base substrate includes a single-crystal silicon carbide substrate, a silicon substrate, a sapphire substrate, or a gallium arsenide substrate.

[0012] Optionally, the semiconductor device structure layer includes:

[0013] A semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body also includes a first region and a well region; the first region is disposed on the first surface, and the well region is disposed on the side of the first region away from the first surface, and at least covers one sidewall of the first region;

[0014] A gate is disposed on the side of the first surface away from the second surface, and the orthographic projection of the gate on the second surface overlaps with the orthographic projection of the first region and the well region covering the sidewall of the first region on the second surface.

[0015] An insulating layer covers the surface of the gate and is at least partially located between the first surface and the gate;

[0016] The source electrode is located on the first surface and forms an ohmic contact with the first region.

[0017] Optionally, the semiconductor device structure layer includes:

[0018] A semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body also includes a first region and a well region; the first region is disposed on the first surface, and the well region is disposed on the side of the first region away from the first surface; the first surface is also provided with a gate trench.

[0019] The gate is located within the gate trench;

[0020] The source electrode is located on the first surface and forms an ohmic contact with the first region.

[0021] Optionally, the target substrate includes at least one of a silicon substrate, a flexible polymer substrate, a glass substrate, a ceramic substrate, and a metal substrate that has undergone back-side fabrication.

[0022] Secondly, embodiments of the present invention provide a method for fabricating a semiconductor device with a transferable substrate, comprising:

[0023] Provide a base substrate;

[0024] A peelable intermediate layer is formed on the surface of the base substrate;

[0025] A semiconductor device structure layer is formed on the surface of the peelable intermediate layer away from the base substrate.

[0026] Optionally, after forming the semiconductor device structure layer, the following steps are also included:

[0027] The base substrate and the semiconductor device structure layer are separated at the peelable intermediate layer by at least one of mechanical peeling, laser irradiation, heat treatment or chemical treatment; the separated semiconductor device structure layer is then transferred and fixed to the target substrate.

[0028] Optionally, forming the peelable intermediate layer includes: forming at least two stacked two-dimensional material layers on the surface of the base substrate by at least one of high-temperature pyrolysis, chemical vapor deposition epitaxy, or wafer-level transfer; wherein the bonding force between two adjacent two-dimensional material layers is less than the bonding force between the two-dimensional material layer and the base substrate and / or between the two-dimensional material layer and the semiconductor device structure layer.

[0029] The semiconductor device provided in this invention achieves selective interface peeling between the base substrate and the semiconductor device structure layer by setting a peelable intermediate layer with electrical permeability and controllable peeling characteristics between the base substrate and the semiconductor device structure layer. This enables the recycling of the base substrate and significantly reduces the overall manufacturing cost. Furthermore, the peeled semiconductor device structure layer can be flexibly transferred and fixed to various target substrates according to application requirements, expanding the integrated application scenarios of the semiconductor device. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the structure of a semiconductor device with a transferable substrate provided in an embodiment of the present invention;

[0031] Figure 2 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0032] Figure 3 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention;

[0033] Figure 4 This is a schematic flowchart of a semiconductor device fabrication method provided in an embodiment of the present invention;

[0034] Figures 5-6 This is a schematic diagram of an intermediate structure for the separation and transfer of a semiconductor device, provided as an embodiment of the present invention. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] The fabrication of SiC semiconductor devices primarily relies on the homoepitaxial growth of SiC material on a single-crystal SiC substrate, followed by the formation of the device structure using micro- and nano-fabrication processes. However, the production cost of single-crystal SiC substrates is high, and due to the strong covalent bonds formed between the epitaxial layer and the substrate, substrate peeling and reuse are not possible, resulting in low material utilization. If SiC material is epitaxially grown on a lower-cost heterogeneous substrate such as silicon, significant lattice mismatch and differences in thermal expansion coefficients can lead to high-density defects in the epitaxial layer, which can even cause thin film cracking in severe cases, making it difficult to meet the requirements for fabricating high-performance power devices.

[0037] Furthermore, rigid SiC substrates are incompatible with mainstream silicon-based CMOS processes, hindering the heterogeneous integration of SiC semiconductor devices and control circuits; the rigidity of traditional SiC devices also fails to meet the demands of emerging fields such as wearable electronics and flexible energy systems for flexible power electronic devices.

[0038] In view of this, Figure 1 This is a schematic diagram of the structure of a semiconductor device with a transferable substrate provided in an embodiment of the present invention. See also... Figure 1 ,include:

[0039] Base substrate 110;

[0040] Semiconductor device structure layer 130 is located on one side of base substrate 110;

[0041] A peelable intermediate layer 120 is located between the base substrate 110 and the semiconductor device structure layer 130; wherein the peelable intermediate layer 120 is electrically permeable and enables the base substrate 110 and the semiconductor device structure layer 130 to be separated so that the semiconductor device structure layer 130 can be transferred to the target substrate.

[0042] Specifically, the base substrate 110 is a material that satisfies the lattice matching of the semiconductor device structure layer 130 to ensure high-quality epitaxial growth. For example, the base substrate 110 may include a single-crystal silicon carbide substrate, a silicon substrate, a sapphire substrate, or a gallium arsenide substrate.

[0043] For SiC-based semiconductor devices, the base substrate 110 can be a single-crystal SiC substrate to meet the requirements of homoepitaxial growth of SiC films. For silicon-based semiconductor devices, the base substrate 110 can be a single-crystal silicon substrate to meet the requirements of homoepitaxial growth. For gallium nitride-based semiconductor devices, the base substrate 110 can be a sapphire substrate to meet the requirements of epitaxial growth. For III-V compound semiconductor devices, the base substrate 110 can be a gallium arsenide substrate to meet the requirements of epitaxial growth.

[0044] A peelable intermediate layer with separability and electrical penetration characteristics is formed on the base substrate 110. The peelable intermediate layer 120 can achieve controllable separation between the base substrate 110 and the device structure layer in subsequent processes, and allow carriers to tunnel efficiently in its thickness direction. Thus, after the semiconductor device structure layer 130 is transferred to the target substrate, it can still maintain good electrical characteristics and ensure that the device performance is not affected.

[0045] Furthermore, the peelable intermediate layer 120 can be a thin layer. For example, the peelable intermediate layer 120 includes at least two two-dimensional material layers, but the number of two-dimensional material layers cannot be too many, otherwise it will affect the orientation and crystal quality of the epitaxial layer in the base substrate 110 and the semiconductor device structure layer 130, causing device performance defects. The two-dimensional material layers can be at least one of graphene, hexagonal boron nitride, molybdenum disulfide, or tungsten disulfide. The two-dimensional material layers are bonded by van der Waals forces, while the interface between the peelable intermediate layer 120 and the base substrate 110 and the epitaxial layer forms a stronger interaction. Therefore, when external forces such as moderate mechanical stress, thermal stimulation, or laser pulses are applied, separation preferentially occurs between the two-dimensional material layers, achieving highly selective interface peeling. Exemplarily, in an optional embodiment, the peelable intermediate layer 120 can be composed of a bilayer of graphene. The first layer is grown in situ on the base substrate 110 by chemical vapor deposition (CVD), and the second layer is superimposed by a polymer-free dry transfer method. The thickness of the two graphene layers is between 0.7nm and 1.4nm, which can maintain good exfoliation performance while avoiding disturbance to the crystal orientation and crystal integrity of the upper epitaxial material.

[0046] An epitaxial structure is formed on the side of the peelable intermediate layer 120 away from the base substrate 110. The semiconductor device structure layer 130 can be obtained by performing processes such as ion implantation, CVD, etching, and metal deposition on the epitaxial structure. The semiconductor device structure layer 130 includes functional regions of the semiconductor device. For example, the semiconductor device structure layer 130 may include an epitaxial layer, a first region of a first conductivity type, a well region of a second conductivity type, a gate, and a source, etc. The first conductivity type can be N-type, the second conductivity type can be P-type, or the first conductivity type is P-type and the second conductivity type is N-type.

[0047] By applying mechanical stress to the peelable intermediate layer 120, the semiconductor device structure layer 130 can be completely separated from the base substrate 110. The base substrate 110 can be restored to a clean and flat state through standard surface treatment processes, such as chemical mechanical polishing and plasma cleaning, enabling multiple cycles of use. This allows for the peeling and recycling of the base substrate 110, significantly reducing overall manufacturing costs.

[0048] The stripped semiconductor device structure layer 130 can be flexibly transferred and fixed to various target substrates according to application requirements. For example, it can be bonded to a silicon substrate with completed back-side processing to achieve heterogeneous integration with mainstream CMOS processes, transferred to a flexible polymer substrate, such as polyimide, transferred to a glass substrate, transferred to a ceramic substrate, or transferred to a metal substrate.

[0049] The semiconductor device provided in this embodiment of the invention achieves selective interface peeling between the base substrate 110 and the semiconductor device structure layer 130 by providing a peelable intermediate layer 120 with electrical permeability and controllable peeling characteristics between the base substrate 110 and the semiconductor device structure layer 130. This enables the recycling of the base substrate 110 and significantly reduces the overall manufacturing cost. Furthermore, the peeled semiconductor device structure layer 130 can be flexibly transferred and fixed to various target substrates according to application requirements, expanding the integrated application scenarios of the semiconductor device.

[0050] Optionally, the peelable intermediate layer 120 includes at least two stacked two-dimensional material layers, with adjacent two-dimensional material layers bonded together by van der Waals forces.

[0051] Specifically, the peelable intermediate layer 120 can be formed on the surface of the base substrate 110 through high-temperature pyrolysis, CVD epitaxy, or wafer-level transfer. The two-dimensional material layer is a layered crystal structure material, optionally including at least one of graphene, hexagonal boron nitride, molybdenum disulfide, or tungsten disulfide. The atoms in the same layer of the two-dimensional material layer are tightly bonded by strong covalent bonds or ionic-covalent mixed bonds, while adjacent layers interact only through weak van der Waals forces. The peelable intermediate layer 120 includes at least two two-dimensional material layers to ensure the peeling process. Multiple two-dimensional material layers can effectively buffer the lattice disturbances to the epitaxial layers in the semiconductor device structure layer 130 during epitaxy. Furthermore, during subsequent peeling, the separation interface will preferentially occur between the two-dimensional material layers, avoiding peeling damage to the surfaces of adjacent base substrate 110 and semiconductor device structure layer 130 during the separation process, thus preventing impact on the reusability of the base substrate 110 and device performance.

[0052] Optionally, the semiconductor device structure layer 130 includes functional regions of the semiconductor device. For example, the semiconductor device structure layer 130 may include an epitaxial layer 131, a first region 132 of a first conductivity type, a well region 133 of a second conductivity type, a gate 134, and a source 136, etc., wherein the first conductivity type can be N-type, the second conductivity type can be P-type, or the first conductivity type is P-type and the second conductivity type is N-type.

[0053] Figure 2 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention. See also... Figure 2In this embodiment of the invention, the semiconductor device can be a planar semiconductor device, and the semiconductor device structure layer 130 may include:

[0054] The semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body also includes a first region 132 and a well region 133; the first region 132 is disposed on the first surface, and the well region 133 is disposed on the side of the first region 132 away from the first surface, and at least covers one sidewall of the first region 132.

[0055] Gate 134 is disposed on the side of the first surface away from the second surface. The orthographic projection of gate 134 on the second surface overlaps with the orthographic projection of the first region 132 and the well region 133 covering the sidewall of the first region 132 on the second surface.

[0056] An insulating layer 135 covers the surface of the gate 134 and is at least partially located between the first surface and the gate 134;

[0057] The source electrode 136 is located on the first surface and forms an ohmic contact with the first region 132.

[0058] Specifically, the semiconductor body may include an epitaxial layer 131, a well region 133, and a first region 132. The epitaxial layer 131 is located on the side of the peelable intermediate layer 120 away from the base substrate 110. The epitaxial layer 131 can be formed on the surface of the peelable intermediate layer 120 by remote epitaxial growth.

[0059] The surface of the epitaxial layer 131 away from the base substrate 110 serves as the first surface of the semiconductor body. A first region 132 is disposed on the first surface, and a well region 133 is disposed on the side of the first region 132 away from the first surface. The well region 133 is not only located directly below the first region 132 but also covers at least a portion of the sidewalls of the first region 132, forming a surrounding doped structure, which helps to suppress short-channel effects and improve device reliability. The well region 133 and the first region 132 can be formed by epitaxial growth, ion implantation, or vapor deposition.

[0060] A gate 134 is also disposed on the first surface. The orthographic projection of the gate 134 on the second surface at least overlaps with the orthographic projections of the first region 132 and the well region 133 covering the sidewalls of the first region 132 on the second surface. Therefore, the gate 134 can regulate the carrier distribution at the boundary between the first region 132 and the well region 133. When an appropriate gate voltage is applied, an inversion layer is induced near the bottom and sidewalls of the first region 132, thereby forming a conductive channel between the first region 132 and the adjacent well region 133. An insulating layer 135 covers the surface of the gate 134. A source 136 is disposed on the first surface of the semiconductor body. For example, the source 136 can be formed by sputtering or other methods. The source 136 forms an ohmic contact with the first region 132 to ensure good current injection efficiency.

[0061] Figure 3 For a schematic diagram of another semiconductor device provided in an embodiment of the present invention, see [link to schematic diagram]. Figure 3 In this embodiment of the invention, the semiconductor device can be a trench-type semiconductor device, and the semiconductor device structure layer 130 may include:

[0062] The semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body also includes a first region 132 and a well region 133; the first region 132 is disposed on the first surface, and the well region 133 is disposed on the side of the first region 132 away from the first surface; the first surface is also provided with a gate trench 134.

[0063] Gate 134 is located within the gate 134 trench;

[0064] The source electrode 136 is located on the first surface and forms an ohmic contact with the first region 132.

[0065] Specifically, the semiconductor body may include an epitaxial layer 131, a well region 133, and a first region 132. The surface of the epitaxial layer 131 away from the base substrate 110 serves as the first surface of the semiconductor body. The first region 132 is disposed on the first surface, and the well region 133 is disposed on the side of the first region 132 away from the first surface.

[0066] A gate 134 trench is also provided on the first surface, which can be formed by an etching process. The gate 134 trench extends from the first surface into the epitaxial layer 131, passing through the first region 132 and the well region 133.

[0067] A gate 134 is disposed in the trench of the gate 134. For example, a first insulating layer 135 is disposed between the trench of the gate 134 and the gate 134. The first insulating layer 135 can be obtained by oxidizing the inner wall and bottom of the trench of the gate 134, and can be called the gate 134 oxide layer. The gate 134 oxide layer can be a high dielectric constant (K) material. The gate 134 can be polysilicon. The well regions 133 on both sides of the gate 134 can form vertical conductive channels.

[0068] A source electrode 136 is disposed on the first surface of the semiconductor body. For example, the source electrode 136 can be formed by sputtering or other methods. The source electrode 136 is a metal conductive layer, which can be titanium (Ti), nickel (Ni), or silver (Ag). The source electrode 136 forms an ohmic contact with the first region 132.

[0069] It should be noted that the embodiments of the present invention exemplify one form of planar semiconductor device and trench semiconductor device, but are not a limitation on the specific structure. In other embodiments, the structure of the semiconductor device can be designed in different ways, which are not limited here.

[0070] It should be noted that the embodiments of the present invention use planar semiconductor devices and trench semiconductor devices as examples to illustrate the specific implementation of the semiconductor device structure layer 130. However, these examples are for illustrative purposes only and are not intended to limit the specific structure. In fact, the technical solution of the present invention is applicable to the design of various types of semiconductor device structures.

[0071] Optionally, the target substrate includes at least one of the following: a silicon substrate with completed back-side fabrication, a flexible polymer substrate, a glass substrate, a ceramic substrate, and a metal substrate. The silicon substrate with completed back-side fabrication can refer to a substrate that has undergone back-side thinning, drain fabrication, and other processes. Flexible polymer substrates include flexible substrates such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polydimethylsiloxane (PDMS). Glass substrates can be used for optoelectronic integrated devices. Ceramic substrates are suitable for high-temperature power electronic device applications. Metal substrates can significantly improve heat dissipation performance in high-power density applications, thereby allowing for higher current densities and more compact designs.

[0072] Figure 4 This is a schematic flowchart of a semiconductor device fabrication method provided in an embodiment of the present invention. See also... Figure 4 ,include:

[0073] S110, a base substrate 110 is provided; wherein the base substrate 110 is a material that satisfies the lattice matching of the semiconductor device structure layer 130 to ensure high-quality epitaxial growth. For example, the base substrate 110 may include a single-crystal silicon carbide substrate, a silicon substrate, a sapphire substrate, or a gallium arsenide substrate.

[0074] For SiC-based semiconductor devices, the base substrate 110 can be a single-crystal SiC substrate to meet the requirements of homoepitaxial growth of SiC films. For silicon-based semiconductor devices, the base substrate 110 can be a single-crystal silicon substrate to meet the requirements of homoepitaxial growth. For gallium nitride-based semiconductor devices, the base substrate 110 can be a sapphire substrate to meet the requirements of epitaxial growth. For III-V compound semiconductor devices, the base substrate 110 can be a gallium arsenide substrate to meet the requirements of epitaxial growth.

[0075] S120, A peelable intermediate layer 120 is formed on the surface of the base substrate 110;

[0076] Specifically, a peelable intermediate layer with separability and electrical penetration characteristics is formed on the base substrate 110. The peelable intermediate layer 120 can be formed on the surface of the base substrate 110 by means of high-temperature pyrolysis, CVD epitaxy, or wafer-level transfer. In order not to affect the orientation and crystal quality of the epitaxial layer 131 in the semiconductor device structure layer 130 and the base substrate 110, the peelable intermediate layer 120 can be a thin layer. For example, the peelable intermediate layer 120 includes at least two two-dimensional material layers, wherein the two-dimensional material layers can be at least one of graphene, hexagonal boron nitride, molybdenum disulfide, or tungsten disulfide. The two-dimensional material layers are bonded to each other by van der Waals forces, while the interface between the peelable intermediate layer 120 and the base substrate 110 and the epitaxial layer 131 forms a stronger interaction. Therefore, when external forces such as moderate mechanical stress, thermal stimulation, or laser pulse are applied, separation preferentially occurs between the two-dimensional material layers, achieving highly selective interface peeling. For example, in an optional embodiment, the peelable intermediate layer 120 may be composed of bilayer graphene. The first layer is grown in situ on the base substrate 110 by CVD, and the second layer is superimposed by a polymer-free dry transfer method. The thickness of the two graphene layers is between 0.7 nm and 1.4 nm, which can maintain good peeling performance while avoiding disturbance to the crystal orientation and crystal integrity of the upper epitaxial material.

[0077] Optionally, the bonding force between two adjacent two-dimensional material layers is less than the bonding force between the two-dimensional material layer and the base substrate 110 and / or between the two-dimensional material layer and the semiconductor device structure layer 130. Therefore, during the subsequent peeling process, the separation interface will preferentially occur between the two-dimensional material layers, avoiding peeling damage to the surfaces of the adjacent base substrate 110 and semiconductor device structure layer 130 caused by the peelable intermediate layer 120 during the separation process, which would affect the reusability of the base substrate 110 and the device performance.

[0078] S130, a semiconductor device structure layer 130 is formed on the surface of the peelable intermediate layer 120 away from the base substrate 110.

[0079] Specifically, an epitaxial structure is formed on the side of the peelable intermediate layer 120 away from the base substrate 110. The semiconductor device structure layer 130 can be obtained by performing processes such as ion implantation, CVD, etching, and metal deposition on the epitaxial structure. The semiconductor device structure layer 130 includes functional regions of the semiconductor device. For example, the semiconductor device structure layer 130 may include an epitaxial layer 131, a first region 132 of a first conductivity type, a well region 133 of a second conductivity type, a gate 134, and a source 136, etc. The first conductivity type can be N-type, the second conductivity type can be P-type, or the first conductivity type is P-type and the second conductivity type is N-type.

[0080] Optionally, after forming the semiconductor device structure layer 130, the following may also be included:

[0081] The base substrate 110 and the semiconductor device structure layer 130 are separated at the peelable intermediate layer 120 by at least one of mechanical peeling, laser irradiation, heat treatment or chemical treatment. Figures 5-6 This is a schematic diagram of an intermediate structure for the separation and transfer of a semiconductor device according to an embodiment of the present invention. See also... Figures 5-6 In one specific embodiment, separation is achieved using a mechanical peeling method. A heat-release adhesive tape 210 is attached to the surface of the source electrode 136 in the semiconductor device structural layer 130, followed by the application of mechanical stress in the perpendicular or shear direction. Since the peelable intermediate layer 120 consists of at least two two-dimensional material layers, and these layers are bonded only by van der Waals forces, the bonding force is lower than the interaction force between the peelable intermediate layer 120 and the adjacent upper and lower interfaces. Therefore, the stress concentrates between the two-dimensional material layers, allowing the entire semiconductor device structural layer 130 to peel off from the base substrate 110 without damaging the device functional layers or the surface of the base substrate 110. After separation, the heat-release adhesive tape 210 is removed.

[0082] The base substrate 110 can be restored to a clean and flat state through standard surface treatment processes, such as chemical mechanical polishing and plasma cleaning, enabling multiple cycles of use. This allows for the peeling and recycling of the base substrate 110, significantly reducing overall manufacturing costs. The peeled semiconductor device structure layer 130 can be flexibly transferred and fixed to various target substrates 220 according to application requirements. These include, for example, silicon substrates, flexible polymer substrates, glass substrates, ceramic substrates, or metal substrates that have already undergone back-side processing.

[0083] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device with a transferable substrate, characterized in that, include: Basic substrate; A semiconductor device structure layer is located on one side of the base substrate; A peelable intermediate layer is located between the base substrate and the semiconductor device structure layer; wherein the peelable intermediate layer is electrically permeable and enables separation of the base substrate and the semiconductor device structure layer so that the semiconductor device structure layer can be transferred to a target substrate.

2. The semiconductor device with a transferable substrate according to claim 1, characterized in that, The peelable intermediate layer comprises two stacked two-dimensional material layers, with adjacent two-dimensional material layers bonded together by van der Waals forces.

3. The semiconductor device with a transferable substrate according to claim 2, characterized in that, The two-dimensional material layer includes at least one of graphene, hexagonal boron nitride, molybdenum disulfide, or tungsten disulfide.

4. The semiconductor device with a transferable substrate according to claim 1, characterized in that, The base substrate includes a single-crystal silicon carbide substrate, a silicon substrate, a sapphire substrate, or a gallium arsenide substrate.

5. The semiconductor device with a transferable substrate according to claim 1, characterized in that, The semiconductor device structure layer includes: A semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body also includes a first region and a well region; the first region is disposed on the first surface, and the well region is disposed on the side of the first region away from the first surface, and at least covers one sidewall of the first region; A gate is disposed on the side of the first surface away from the second surface, and the orthographic projection of the gate on the second surface overlaps with the orthographic projection of the first region and the well region covering the sidewall of the first region on the second surface. An insulating layer covers the surface of the gate and is at least partially located between the first surface and the gate; The source electrode is located on the first surface and forms an ohmic contact with the first region.

6. The semiconductor device with a transferable substrate according to claim 1, characterized in that, The semiconductor device structure layer includes: A semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body also includes a first region and a well region; the first region is disposed on the first surface, and the well region is disposed on the side of the first region away from the first surface; the first surface is also provided with a gate trench. The gate is located within the gate trench; The source electrode is located on the first surface and forms an ohmic contact with the first region.

7. The semiconductor device with a transferable substrate according to claim 1, characterized in that, The target substrate includes at least one of a silicon substrate, a flexible polymer substrate, a glass substrate, a ceramic substrate, and a metal substrate that has undergone back-side fabrication.

8. A method for fabricating a semiconductor device with a transferable substrate, characterized in that, include: Provide a base substrate; A peelable intermediate layer is formed on the surface of the base substrate; A semiconductor device structure layer is formed on the surface of the peelable intermediate layer away from the base substrate.

9. The method for fabricating a semiconductor device with a transferable substrate according to claim 8, characterized in that, After forming the semiconductor device structure layer, the process also includes: The base substrate and the semiconductor device structure layer are separated at the peelable intermediate layer by at least one of mechanical peeling, laser irradiation, heat treatment or chemical treatment; the separated semiconductor device structure layer is then transferred and fixed to the target substrate.

10. The method for fabricating a semiconductor device with a transferable substrate according to claim 8 or 9, characterized in that, The formation of the peelable intermediate layer includes: forming at least two stacked two-dimensional material layers on the surface of the base substrate by at least one of high-temperature pyrolysis, chemical vapor deposition epitaxy, or wafer-level transfer; wherein the bonding force between two adjacent two-dimensional material layers is less than the bonding force between the two-dimensional material layer and the base substrate and / or between the two-dimensional material layer and the semiconductor device structure layer.

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