Semiconductor structure and preparation method thereof

Abstract

The invention discloses a semiconductor structure and a preparation method thereof, and the preparation method comprises the steps: providing a substrate, forming a plurality of embedded metal columns at the upper part of the substrate, the metal columns being formed through an ALD technology, and the upper surfaces of the metal columns being flush with the upper surface of the substrate; forming a protective layer on the upper surfaces of the substrate and the metal columns; a mask layer with multiple openings is formed on the protective layer, the multiple openings correspond to the multiple metal columns in a one-to-one mode, the orthographic projection of the openings on the substrate coincides with the orthographic projection of the metal columns on the substrate, or the orthographic projection of the openings on the substrate is located in the orthographic projection of the metal columns on the substrate; performing hydrogen ion implantation treatment on the metal column by taking the mask layer as a mask; removing the mask layer and the protective layer; and performing a thermal annealing process on the metal column. According to the technical scheme, the resistance of the metal column can be effectively reduced, and the conductivity of the metal column is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor structure and its fabrication method. Background Technology

[0002] When forming high aspect ratio metal pillars (such as tungsten pillars) using CVD (Chemical Vapor Deposition), defects such as voids are easily generated, causing dishing on the surface of the metal pillars during subsequent CMP (Chemical Mechanical Polishing) processes. While ALD (Atomic Layer Deposition) can reduce voids, ALD-formed metal pillars have smaller grain sizes, more interfaces, and stronger electron scattering. S High sheet resistance affects device speed.

[0003] In related technologies, after forming a metal pillar using the ALD process, thermal annealing for 1 hour in a hydrogen (H2) atmosphere at 500°C and 0.1 MPa can remove impurities at grain boundaries, lower the grain boundary migration energy barrier, increase grain size, and reduce Ro. S Hydrogen diffuses from the surface of the metal pillar into the depth under the influence of temperature. However, excessively high temperatures may cause the device with the metal pillar to fail, while lower temperatures will result in shallower diffusion. For high aspect ratio processes, the hydrogen concentration is lower at greater depths, resulting in less grain coarsening.

[0004] Studies have also shown that heat treatment following metal deposition in an H2 atmosphere can suppress oxidation at the metal interface. For example, in the case of sequential deposition of titanium nitride (TiN), tungsten, and neodymium (Ru) layers using an ALD process, followed by heat treatment in a hydrogen-argon mixed gas atmosphere at 400°C-600°C, the hydrogen eliminates oxygen (impurities) at the interface between the neodymium and tungsten layers, thus reducing sheet resistance. However, this process is highly temperature-dependent; the higher the temperature, the better the hydrogen's effect on eliminating oxygen (impurities) at the neodymium and tungsten layer interface, but excessively high temperatures may lead to device failure.

[0005] Therefore, improvements are needed to at least partially address the aforementioned problems. Summary of the Invention

[0006] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0007] To at least partially solve the above problems, according to a first aspect of the present invention, a method for fabricating a semiconductor structure is provided, comprising: A substrate is provided, on which a plurality of embedded metal pillars are formed, wherein the metal pillars are formed by an ALD process and the upper surface of the metal pillars is flush with the upper surface of the substrate; A protective layer is formed on the upper surface of the substrate and the metal pillar; A mask layer with multiple openings is formed on the protective layer, wherein each of the multiple openings corresponds one-to-one with the position of a multiple of the metal pillars, and the orthographic projection of the opening on the substrate coincides with the orthographic projection of the metal pillar on the substrate, or the orthographic projection of the opening on the substrate is located within the orthographic projection of the metal pillar on the substrate. The metal column is subjected to hydrogen ion implantation using the mask layer as a mask. Remove the mask layer and the protective layer; The metal pillar is subjected to a thermal annealing process.

[0008] For example, the metal pillar may be made of at least one of W, Cu, V, Ni and Ru.

[0009] For example, forming a plurality of embedded metal pillars on the upper part of the substrate includes: Multiple columnar grooves are formed on the upper part of the base; A diffusion barrier layer is formed on the inner wall of the trench and the upper surface of the substrate; The trench is filled with metal material by an ALD process, and the metal material also covers the upper surface of the diffusion barrier layer. The material located above the substrate is removed by a CMP process, so that the upper surface of the remaining metal material is flush with the upper surface of the substrate.

[0010] For example, the diffusion barrier layer is made of TiN.

[0011] For example, the protective layer is made of silicon nitride.

[0012] For example, the hydrogen ion implantation process is a single ion implantation step, and the ion implantation depth is located at half the height of the metal column.

[0013] For example, the hydrogen ion implantation process consists of multiple ion implantation steps, with the implantation depth increasing progressively; or, The hydrogen ion implantation process consists of multiple ion implantation steps, with the implantation depth decreasing progressively. The maximum depth of ion implantation is less than the height of the metal column.

[0014] For example, the temperature of the hot annealing process is 300℃-400℃.

[0015] For example, the thermal annealing process is performed in a nitrogen atmosphere; or, The thermal annealing process is carried out in a mixed gas atmosphere of hydrogen and argon.

[0016] This application also provides a semiconductor structure, which is prepared by the preparation method described above.

[0017] According to the semiconductor structure and its fabrication method of the present invention, a protective layer is first formed on the surface of the metal pillar to prevent oxidation of the metal pillar. Then, hydrogen ion implantation and thermal annealing are performed on the metal pillar, which can effectively increase the depth of hydrogen ion penetration into the metal pillar. Hydrogen ions can reduce the grain boundary barrier by eliminating impurities (O, F, etc.) at the grain boundaries, which is conducive to grain growth and synthesis. Thus, grain growth in a larger area can be achieved, the sheet resistance can be reduced, and the conductivity of the metal pillar can be improved. Moreover, after hydrogen ion implantation, thermal annealing can be performed at a lower temperature to promote the diffusion of hydrogen ions, which is not dependent on high temperature and can significantly reduce the failure risk caused by high temperature. Attached Figure Description

[0018] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions, thereby explaining the apparatus and principles of the invention. In the drawings, Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of this application; Figures 2-11 This is a cross-sectional schematic diagram of the structure corresponding to each step of the method for fabricating a semiconductor structure according to an embodiment of this application.

[0019] Explanation of reference numerals in the attached figures: 100 - Substrate, 110 - Polycrystalline silicon layer, 120 - Silicon oxide layer, 121 - Trench, 200 - Diffusion barrier layer, 300 - Metal material, 310 - Metal pillar, 400 - Protective layer, 500 - Mask layer, 510 - Opening. Detailed Implementation

[0020] The following description provides numerous specific details to offer a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with this application.

[0021] It should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0022] It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part.

[0023] Spatial relation terms such as "below," "under," "below," "under," "above," and "above" are used here for convenience to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of devices in use and operation.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0025] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of this application. Thus, variations in the shown shape are contemplated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes shown herein, but include shape deviations due to, for example, manufacturing processes. Consequently, the figures are substantially schematic, and their shapes are not intended to show the actual shape of the device and are not intended to limit the scope of this application.

[0026] See attached document Figure 1 An exemplary method for fabricating a semiconductor structure according to an embodiment of this application will be described. The fabrication method includes the following steps: S10: Provide a substrate, on which multiple embedded metal pillars are formed. The metal pillars are formed by an ALD process, and the upper surface of the metal pillars is flush with the upper surface of the substrate.

[0027] S20: A protective layer is formed on the upper surface of the substrate and the metal pillar.

[0028] S30: A mask layer with multiple openings is formed on the protective layer. The multiple openings correspond one-to-one with the positions of multiple metal pillars, and the orthographic projection of the openings on the substrate coincides with the orthographic projection of the metal pillars on the substrate, or the orthographic projection of the openings on the substrate is located within the orthographic projection of the metal pillars on the substrate.

[0029] S40: Hydrogen ion implantation is performed on a metal column using a mask layer as a mask.

[0030] S50: Remove the mask layer and protective layer.

[0031] S60: Perform a hot annealing process on the metal column.

[0032] According to the semiconductor structure fabrication method of this application embodiment, a protective layer is first formed on the surface of the metal pillar to prevent oxidation of the metal pillar. Then, hydrogen ion implantation and thermal annealing are performed on the metal pillar. This can effectively increase the depth of hydrogen ion penetration into the metal pillar. Hydrogen ions can reduce the grain boundary barrier by eliminating impurities (such as O, F, etc.) at the grain boundaries, which is conducive to grain growth and synthesis. As a result, grain growth in a larger area can be achieved, the sheet resistance can be reduced, and the conductivity of the metal pillar can be improved. Moreover, after hydrogen ion implantation, thermal annealing can be performed at a lower temperature to promote the diffusion of hydrogen ions. This method is not dependent on high temperature and can significantly reduce the failure risk caused by high temperature.

[0033] The following is a reference to the appendix. Figures 2-11 An exemplary description will be given of a method for fabricating a semiconductor structure according to an embodiment of this application (i.e., steps S10-S60 described above).

[0034] In step S10, firstly, see Figure 2Multiple columnar trenches 121 are formed on the upper part of the substrate 100. Exemplarily, a patterned mask layer is first formed on the upper surface of the substrate 100. This mask layer has multiple opening patterns, exemplarily circular, and the multiple opening patterns are arranged in an array. Then, using this mask layer as a mask, the substrate 100 is etched using a dry etching process to form multiple columnar trenches 121 on the upper part of the substrate 100. Exemplarily, the trenches 121 can be cylindrical. Then, the mask layer is removed. In this embodiment, the substrate 100 includes a polysilicon layer 110 and a silicon oxide layer 120 located on the polysilicon layer 110. The trenches 121 are formed in the silicon oxide layer 120, and the depth of the trenches 121 is less than the thickness of the silicon oxide layer 120. Exemplarily, the substrate 100 may also include a substrate and at least one material layer formed on the substrate. The trenches 121 are formed in the uppermost material layer, which can be an insulating layer.

[0035] Then, see appendix. Figure 3 A diffusion barrier layer 200 is formed on the inner wall of trench 121 and the upper surface of substrate 100. Exemplarily, the diffusion barrier layer 200 can be integrally formed on the inner wall of trench 121 and the upper surface of substrate 100 using deposition processes such as CVD (Chemical Vapor Deposition) or ALD. The diffusion barrier layer 200 is used to prevent the diffusion of atoms in the subsequently formed metal pillars 310, ensuring the stability of the semiconductor structure's structure and performance during subsequent processing and operation. Exemplarily, the diffusion barrier layer 200 is made of TiN (titanium nitride).

[0036] Then, see appendix. Figure 4 The trench 121 is filled with metal material 300 using an ALD process, and the metal material 300 also covers the upper surface of the diffusion barrier layer 200. The ALD process offers high uniformity and excellent conformability, and can be used to fill trenches with high aspect ratios, forming a high-density, low-porosity film layer, thereby effectively reducing defects such as pores. For example, the metal material 300 may include at least one of W, Cu, V, Ni, and Ru; that is, the subsequently formed metal pillar 310 may also be made of at least one of W, Cu, V, Ni, and Ru.

[0037] Then, see appendix. Figure 5The material above the substrate 100 is removed using a CMP process, making the upper surface of the remaining metal material 300 flush with the upper surface of the substrate 100. Specifically, the metal material 300 and the diffusion barrier layer 200 are ground using a CMP process until the upper surface of the substrate 100 (i.e., the upper surface of the silicon oxide layer 120) is exposed. At this point, the upper surface of the remaining metal material 300 is flush with the upper surface of the substrate 100. The remaining metal material 300 consists of multiple metal pillars 310 located in the multiple trenches 121, and the remaining diffusion barrier layer 200 is located between the metal pillars 310 and the substrate 100. For example, the height of the metal pillars 310 (… Figure 5 The height in the vertical direction can be 1000nm-2000nm.

[0038] In step S20, see Appendix Figure 6 A protective layer 400 is formed on the upper surfaces of the substrate 100 and the metal pillars 310 to prevent oxidation of the upper surfaces of the metal pillars 310. Specifically, a protective layer 400 can be deposited integrally on the upper surfaces of the substrate 100 and the metal pillars 310 (including the upper surface of the diffusion barrier layer 200) using a deposition process such as CVD. For example, the protective layer 400 can be made of silicon nitride.

[0039] In step S30, see Appendix Figure 7 A mask layer 500 with multiple openings 510 is formed on the protective layer 400. For example, the mask layer 500 can be a photoresist layer. A photoresist layer can be first formed on the protective layer 400 by spin coating, and then patterned using photolithography to form the multiple openings 510. The multiple openings 510 correspond one-to-one with the positions of the multiple metal pillars 310. The orthographic projection of the openings 510 onto the substrate 100 (i.e.,...) Figure 7 The projection of the metal column 310 in the vertical direction onto the base 100 (i.e., the projection of the metal column 310 in the vertical direction onto the base 100) Figure 7 The projections of the opening 510 onto the substrate 100 in the vertical direction coincide, or the orthographic projection of the opening 510 onto the substrate 100 lies within the orthographic projection of the metal pillar 310 onto the substrate 100. That is, the area of ​​the opening 510 is less than or equal to the area of ​​the upper surface of the metal pillar 310, and from a top-down view, the range of the opening 510 does not exceed the range of the upper surface of its corresponding metal pillar 310. This configuration ensures that when hydrogen ion implantation is performed using the mask layer 500 as a mask, hydrogen ions can be effectively implanted into the metal pillar 310, without implanting into the diffusion barrier layer 200 and the substrate 100.

[0040] In step S40, see Appendix Figure 8Hydrogen ion implantation was performed on the metal pillar 310 using a mask layer 500 as a mask. Hydrogen ion implantation was achieved using an ion implanter; different types of ion implanters can cover a wide energy range (0.1 keV-1500 keV). Theoretically, implantation at any depth can be achieved by obtaining suitable energy and angle conditions through simulation software. By performing hydrogen ion implantation on the metal pillar 310, effective control over the implantation depth, concentration, and implantation angle can be achieved, thereby introducing hydrogen ions into the lattice matrix of the metal pillar 310. This allows for grain growth in a larger area (e.g., implanting hydrogen ions at different depths within the metal pillar 310), reducing sheet resistance, improving conductivity, and solving the problem of hydrogen not being able to penetrate deep into high aspect ratio processes. Furthermore, hydrogen ion implantation can be followed by thermal annealing at a lower temperature to promote hydrogen ion diffusion, eliminating the need for high temperatures and significantly reducing the risk of failure caused by high temperatures.

[0041] For example, in step S40, the hydrogen ion implantation process is a single ion implantation step, and the ion implantation depth is located at half the height of the metal pillar 310, that is, a single ion implantation is performed to implant hydrogen ions to the middle position of the metal pillar 310. During the subsequent thermal annealing process, the implanted hydrogen ions can diffuse from the middle position to the upper and lower sides, achieving large-scale grain growth, thereby reducing sheet resistance and improving conductivity.

[0042] For example, in step S40, the hydrogen ion implantation process can be multiple ion implantation steps, with the ion implantation depth increasing or decreasing successively. When the ion implantation depth increases successively, the implantation energy also increases successively; when the ion implantation depth decreases successively, the implantation energy also decreases successively. It should be noted that the maximum ion implantation depth is less than the height of the metal pillar 310 to avoid hydrogen ion implantation into the diffusion barrier layer 200 and the substrate 100. The implantation depth refers to the distance between the position of the hydrogen ion implanted in the metal pillar 310 and the upper surface of the metal pillar 310. For example, the hydrogen ion implantation process can be three ion implantation steps: the first implantation depth is one-quarter of the height of the metal pillar 310, the second implantation depth is one-half of the height of the metal pillar 310, and the third implantation depth is three-quarters of the height of the metal pillar 310; or, the first implantation depth is three-quarters of the height of the metal pillar 310, the second implantation depth is one-half of the height of the metal pillar 310, and the third implantation depth is one-quarter of the height of the metal pillar 310. By implanting hydrogen ions at different depths multiple times, the implanted hydrogen ions can diffuse to various positions of the metal pillar 310 during the subsequent thermal annealing process, achieving grain growth over a larger area, thereby reducing sheet resistance and improving conductivity.

[0043] In step S50, firstly, see Appendix Figure 9 Remove the mask layer 500. Specifically, the mask layer 500 is a photoresist layer, which can be removed using a photoresist removal process such as ashing.

[0044] Then, see appendix. Figure 10 Remove the protective layer 400. Specifically, the protective layer 400 can be removed by wet etching or by CMP.

[0045] Then, see appendix. Figure 11 The metal pillar 310 is subjected to a thermal annealing process. That is, the structure (including the substrate 100, the diffusion barrier layer 200 and the metal pillar 310) obtained after removing the protective layer 400 is sent to a thermal annealing equipment to perform a thermal annealing process, so as to promote the diffusion of hydrogen ions implanted into the metal pillar 310, promote the removal of impurities (such as O, F, etc.) by hydrogen ions, lower the grain boundary migration barrier, and make it easier for grains to synthesize and grow. At the same time, it can also repair the lattice damage caused by ion implantation.

[0046] For example, the temperature of the hot annealing process is 300°C-400°C. Hydrogen ions injected into the metal column 310 can diffuse effectively at this temperature, which is significantly lower than the temperature of hot annealing or heat treatment in related technologies. Therefore, the risk of failure caused by high temperature can be significantly reduced.

[0047] For example, the thermal annealing process can be performed in a nitrogen atmosphere, or in a mixed gas atmosphere of hydrogen and argon. Thermal annealing in a nitrogen atmosphere is a mature process, simple to operate, and relatively low in cost. Thermal annealing in a mixed gas atmosphere of hydrogen and argon allows the hydrogen in the mixed gas to enter the metal column 310, removing impurities. The combined effect of the hydrogen in the mixed gas and the injected hydrogen ions is more conducive to achieving large-scale grain growth, thereby reducing sheet resistance and improving conductivity.

[0048] This concludes the introduction of the relevant steps in the semiconductor structure fabrication method according to the embodiments of this application. In addition to the steps described above, the fabrication method of this embodiment may include other steps during, before, or after the aforementioned steps. These steps can all be implemented using various processes in the prior art, and will not be elaborated upon here.

[0049] This application also provides a semiconductor structure (i.e.) Figure 11 The semiconductor structure shown is prepared by the preparation method described above.

[0050] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above exemplary embodiments are merely illustrative and are not intended to limit the scope of this application. Various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of this application. All such changes and modifications are intended to be included within the scope of this application as claimed in the appended claims.

[0051] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0052] Similarly, it should be understood that, in order to streamline this application and aid in understanding one or more of the various inventive aspects, features of this application may sometimes be grouped together in a single embodiment, figure, or description thereof in the description of exemplary embodiments of this application. However, this approach should not be construed as reflecting an intention that the claimed application requires more features than are expressly recited in each claim. Rather, as reflected in the corresponding claims, its inventive point lies in solving the corresponding technical problem with features fewer than all features of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of this application.

[0053] Those skilled in the art will understand that, apart from the mutual exclusion of features, all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or apparatus so disclosed can be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature serving the same, equivalent, or similar purpose.

[0054] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features but not others included in other embodiments, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0055] It should be noted that the above embodiments are illustrative of this application and not restrictive of this application, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, on which a plurality of embedded metal pillars are formed, wherein the metal pillars are formed by an ALD process and the upper surface of the metal pillars is flush with the upper surface of the substrate; A protective layer is formed on the substrate and the metal pillar; A mask layer with multiple openings is formed on the protective layer, wherein each of the multiple openings corresponds one-to-one with the position of a multiple of the metal pillars, and the orthographic projection of the opening on the substrate coincides with the orthographic projection of the metal pillar on the substrate, or the orthographic projection of the opening on the substrate is located within the orthographic projection of the metal pillar on the substrate. The metal column is subjected to hydrogen ion implantation using the mask layer as a mask. Remove the mask layer and the protective layer; The metal pillar is subjected to a thermal annealing process.

2. The preparation method according to claim 1, characterized in that, The metal pillar is made of at least one of W, Cu, V, Ni, and Ru.

3. The preparation method according to claim 1, characterized in that, The plurality of metal pillars embedded in the upper part of the substrate include: Multiple columnar grooves are formed on the upper part of the base; A diffusion barrier layer is formed on the inner wall of the trench and the upper surface of the substrate; The trench is filled with metal material by an ALD process, and the metal material also covers the upper surface of the diffusion barrier layer. The material located above the substrate is removed by a CMP process, so that the upper surface of the remaining metal material is flush with the upper surface of the substrate.

4. The preparation method according to claim 3, characterized in that, The diffusion barrier layer is made of TiN.

5. The preparation method according to claim 1, characterized in that, The protective layer is made of silicon nitride.

6. The preparation method according to claim 1, characterized in that, The hydrogen ion implantation process is a single ion implantation step, and the ion implantation depth is located at half the height of the metal column.

7. The preparation method according to claim 1, characterized in that, The hydrogen ion implantation process involves multiple ion implantation steps, with the implantation depth increasing progressively; or, The hydrogen ion implantation process consists of multiple ion implantation steps, with the implantation depth decreasing progressively. The maximum depth of ion implantation is less than the height of the metal column.

8. The preparation method according to claim 1, characterized in that, The temperature of the hot annealing process is 300℃-400℃.

9. The preparation method according to claim 1 or 8, characterized in that, The thermal annealing process is carried out under a nitrogen atmosphere; or... The thermal annealing process is carried out in a mixed gas atmosphere of hydrogen and argon.

10. A semiconductor structure, characterized in that, The semiconductor structure is prepared by any one of claims 1-9.

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