Semiconductor device and preparation method thereof, chip and electronic equipment

Abstract

The invention provides a semiconductor device and a preparation method thereof, a chip and electronic equipment. The method comprises the following steps: providing a substrate, and patterning the substrate to form a contact hole in the substrate; a barrier layer is formed, the barrier layer at least covers the inner wall of the contact hole, and the material of the barrier layer is NiSix; executing a deposition process to form a conductive material layer, filling part of the contact hole with the conductive material layer, and covering the substrate with the conductive material layer; executing an etching process, and removing a part of thickness of the conductive material layer to form a conductive layer; and the deposition process and the etching process are repeatedly executed at least once to form at least one conductive layer, and the conductive layer and the barrier layer located in the contact hole form the contact plug. Holes can be prevented from being formed in the contact plug, and the contact resistance of the contact plug is reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device, its fabrication method, a chip, and an electronic device. Background Technology

[0002] Silicon carbide (SiC) has become an ideal substrate material for manufacturing high-voltage, high-frequency, high-temperature, high-power semiconductor devices (such as metal-oxide-semiconductor field-effect transistors, junction field-effect transistors, Schottky barrier diodes, and PIN junction diodes) due to its excellent properties such as high critical breakdown electric field, high saturation electron drift velocity, and high thermal conductivity.

[0003] In semiconductor device manufacturing processes, to achieve vertical conductive structures and reduce on-resistance, deep substrate vias (DSVs) are typically etched into the substrate, and contact plugs are formed within these vias. As a critical structure for vertical interconnection and substrate connection in semiconductor devices, the filling quality of these contact plugs directly impacts the device's electrical performance and long-term reliability.

[0004] However, current contact plugs are prone to forming holes, which leads to increased contact resistance and even semiconductor device failure, reducing the yield of semiconductor devices. Summary of the Invention

[0005] In view of the above-mentioned technical problems, the present application provides a semiconductor device and its preparation method, chip, and electronic device, which can prevent the formation of holes in the contact plug and reduce the contact resistance of the contact plug.

[0006] To achieve the above objectives, the embodiments of this application provide the following technical solutions:

[0007] A first aspect of this application provides a semiconductor device comprising:

[0008] A substrate is provided, and the substrate is patterned to form contact holes in the substrate;

[0009] A barrier layer is formed, the barrier layer at least covering the inner wall of the contact hole, wherein the barrier layer is made of NiSi. x ;

[0010] A deposition process is performed to form a conductive material layer, which fills a portion of the contact holes and covers the substrate;

[0011] An etching process is performed to remove a portion of the conductive material layer to form a conductive layer;

[0012] The deposition process and the etching process are repeated at least once to form at least one conductive layer, wherein the conductive layer and the barrier layer located within the contact hole constitute a contact plug.

[0013] In one possible implementation, the step of performing the deposition process to form a conductive material layer includes:

[0014] A chemical vapor deposition process is performed to form a conductive material layer that fills part of the contact hole and covers the top surface of the substrate. The conductive material layer also forms a recessed area within the contact hole. The minimum thickness of the conductive material layer located within the contact hole is less than the thickness of the conductive material layer located on the top surface of the substrate, along a direction perpendicular to the substrate.

[0015] In one possible implementation, the step of performing the etching process includes:

[0016] An etching process is performed to remove a portion of the conductive material layer covering the substrate and a portion of the conductive material layer located within the contact hole to form the conductive layer; wherein the conductive layer located on the substrate has a flat surface.

[0017] In one possible implementation, the step of repeating the deposition process and the etching process at least once includes:

[0018] The deposition process and the etching process are repeated twice to form a two-layer conductive layer, wherein the three-layer conductive layer and the barrier layer stacked within the contact hole constitute the contact plug.

[0019] In one possible implementation, the total thickness of the conductive layer and the barrier layer on the substrate is 0.1 μm to 0.3 μm.

[0020] In one possible implementation, after repeating the deposition process and the etching process at least once to form at least one conductive layer, the fabrication method further includes:

[0021] The conductive layer and the barrier layer located on the substrate are partially removed, and the remaining conductive layer and barrier layer on the substrate constitute the interconnect block of the interconnect layer.

[0022] A second aspect of this application provides a semiconductor device, which is fabricated by the method described in the first aspect. The semiconductor device includes:

[0023] A substrate having contact holes therein;

[0024] A contact plug is disposed within a contact hole. The contact plug comprises a barrier layer and at least two conductive layers stacked together, wherein the barrier layer is disposed on the inner wall of the contact hole, and the barrier layer is made of NiSi material. x .

[0025] In one possible implementation, the semiconductor device further includes an interconnect block disposed on the substrate; wherein the film layer of the interconnect block is the same as the film layer of the contact plug, and the two film layers are formed synchronously.

[0026] A third aspect of this application provides a chip including the semiconductor device described in the second aspect.

[0027] A fourth aspect of this application provides an electronic device including the chip described in the third aspect.

[0028] In the semiconductor devices, fabrication methods, chips, and electronic devices provided in this application, a barrier layer is formed on the inner wall of the contact hole, and the barrier layer is made of NiSi. x By using the alloying process of Ni and Si in the substrate, a barrier layer can be formed on the top surface of the substrate and the inner wall of the contact hole. The barrier layer has excellent step coverage ability and can cover the top surface of the substrate and the inner wall of the contact hole more uniformly and continuously. This can ensure the uniform deposition of the conductive layer formed later in the contact hole and prevent the conductive material of the conductive layer from diffusing into the substrate. At the same time, the low resistivity of the barrier layer can reduce the contact resistance of the contact plug.

[0029] Meanwhile, by depositing conductive material layers in stages and combining them with etching steps, stress is gradually released and the filling quality of the conductive layer within the contact holes is optimized. For example, after the initial deposition, the conductive material layer is etched back to reduce substrate warpage; secondary or even tertiary depositions further fill the voids within the contact holes; and finally, stress is eliminated through multiple etch-back cycles, preventing the formation of voids within the resulting contact plugs and improving step coverage, thereby increasing the contact resistance of the contact plugs and improving the yield of semiconductor devices. Attached Figure Description

[0030] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0031] Figure 1 A process flow diagram of the method for fabricating a semiconductor device provided in the embodiments of this application;

[0032] Figure 2 A schematic diagram of a substrate provided in the method for fabricating a semiconductor device according to an embodiment of this application;

[0033] Figure 3 This is a schematic diagram illustrating the formation of contact holes in a method for fabricating a semiconductor device according to an embodiment of this application.

[0034] Figure 4 This is a schematic diagram illustrating the formation of a barrier layer in a method for fabricating a semiconductor device according to an embodiment of this application.

[0035] Figure 5 This is a schematic diagram showing the first deposition process performed in the method for fabricating a semiconductor device according to an embodiment of this application.

[0036] Figure 6 This is a schematic diagram showing the first etching process performed in the fabrication method of the semiconductor device provided in the embodiments of this application.

[0037] Figure 7 This is a schematic diagram showing the second deposition process performed in the method for fabricating a semiconductor device according to an embodiment of this application.

[0038] Figure 8 This is a schematic diagram showing the second etching process performed in the method for fabricating a semiconductor device according to an embodiment of this application.

[0039] Figure 9 This is a schematic diagram showing the third deposition process performed in the method for fabricating the semiconductor device provided in the embodiments of this application.

[0040] Figure 10 This is a schematic diagram showing the third etching process performed in the method for fabricating the semiconductor device provided in the embodiments of this application.

[0041] Figure 11 This is a schematic diagram of the formation of interconnect blocks in the fabrication method of the semiconductor device provided in the embodiments of this application.

[0042] Explanation of reference numerals in the attached figures:

[0043] 100: Substrate; 110: Substrate; 120: Epitaxial layer; 130: Contact hole; 140: Recessed area;

[0044] 200: Barrier layer;

[0045] 300: Contact plug; 310: Conductive material layer; 320: Conductive layer;

[0046] 400: Interconnect block.

[0047] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0048] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0049] As described in the background section, contact holes in related technologies have a large aspect ratio, for example, greater than 5. Currently, contact plugs are mainly formed in contact holes using chemical vapor deposition or electroplating processes.

[0050] In related technologies, the following two methods are mainly used for metal filling of contact holes with high aspect ratios:

[0051] (1) PVD Hot-AL filling process: The flowability of Al atoms is enhanced by high temperature (usually >300℃), which makes them better fill the pores. This method is suitable for shallow hole structures with an aspect ratio <1, but for contact holes with a high aspect ratio >5, there are still problems of incomplete filling and high porosity, which leads to a significant increase in contact resistance.

[0052] (2) Electroplated Cu filling process: Cu ions are reduced to form a copper film on the wafer surface by electrochemical deposition. This method requires the pre-deposition of a Ti / Cu seed layer (Ti as the adhesion layer and Cu as the conductive layer) by chemical vapor deposition (PVD). However, due to the high aspect ratio geometry of the holes, it is difficult for PVD to form a continuous seed layer at the bottom of the holes, resulting in uneven Cu filling. In addition, the strong diffusion and deep energy level characteristics of Cu may contaminate the production line equipment, threatening the electrical performance and yield of subsequent devices.

[0053] To address the aforementioned technical problems, embodiments of this application provide a semiconductor device and its fabrication method, chip, and electronic device, which involves forming a barrier layer on the inner wall of a contact hole, wherein the barrier layer is made of NiSi. x By using the alloying process of Ni and Si in the substrate, a barrier layer can be formed on the top surface of the substrate and the inner wall of the contact hole. The barrier layer has excellent step coverage ability and can cover the top surface of the substrate and the inner wall of the contact hole more uniformly and continuously. This can ensure the uniform deposition of the conductive layer formed later in the contact hole and prevent the conductive material of the conductive layer from diffusing into the substrate. At the same time, the low resistivity of the barrier layer can reduce the contact resistance of the contact plug.

[0054] Meanwhile, by depositing conductive material layers in stages and combining them with etching steps, stress is gradually released and the filling quality of the conductive layer within the contact holes is optimized. For example, after the initial deposition, the conductive material layer is etched back to reduce substrate warpage; secondary or even tertiary depositions further fill the voids within the contact holes; and finally, stress is eliminated through multiple etch-back cycles, preventing the formation of voids within the resulting contact plugs and improving step coverage, thereby increasing the contact resistance of the contact plugs and improving the yield of semiconductor devices.

[0055] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0056] Please refer to Figure 1 This application provides a method for fabricating a semiconductor device, comprising the following steps:

[0057] Step S100: Provide a substrate and pattern the substrate to form contact holes in the substrate.

[0058] Please refer to Figure 2 In some embodiments of this application, the substrate 100 may include a substrate 110 and an epitaxial layer 120. Exemplarily, the substrate 110 and the epitaxial layer 120 are stacked, that is, the epitaxial layer 120 is disposed on the substrate 110. The substrate 110 is made of silicon carbide (SiC).

[0059] Please refer to Figure 3 The substrate 100 is patterned using a patterning process to form contact holes 130 within the substrate 100. Exemplarily, a mask layer with mask openings is formed on the epitaxial layer 120. Using the mask layer as a mask, an etching process is performed to remove a portion of the thickness of the epitaxial layer 120 to form the contact holes 130. The contact holes 130 extend perpendicularly to the substrate 110.

[0060] It should be noted that the contact hole 130 can be rectangular or an inverted trapezoid. In the following embodiments, the shape of the contact hole 130 is described as trapezoidal, and for example, the top dimension of the contact hole 130 is larger than the bottom dimension of the contact hole 130.

[0061] Step S200: Form a barrier layer, which at least covers the inner wall of the contact hole, wherein the barrier layer is made of NiSi. x .

[0062] Please refer to Figure 4 For example, a precursor layer is formed by a deposition process. The precursor layer at least covers the inner wall of the contact hole 130. Alternatively, the precursor layer covers the inner wall of the contact hole 130 and extends to the outside of the contact hole 130 and covers the top surface of the substrate 100. It should be noted that when the substrate 100 includes a substrate 110 and an epitaxial layer 120, the precursor layer covers the top surface of the epitaxial layer 120.

[0063] Subsequently, an annealing process is performed, during which the precursor layer reacts with the substrate 100 to form a barrier layer 200. The barrier layer 200 is made of NiSi. x Compared to related technologies where the barrier layer 200 is made of titanium nitride and deposited using conventional processes, the barrier layer 200 exhibits superior step coverage capabilities. It can more uniformly and continuously cover the top surface of the substrate 100 and the inner wall of the contact hole 130. This ensures that the subsequently formed conductive layer can be uniformly deposited within the contact hole 130, while preventing the conductive material of the conductive layer from diffusing into the substrate 100. Furthermore, the low resistivity of the barrier layer 200 can reduce the resistance of the subsequently formed contact plug 300 (see reference). Figure 10 ( ) contact resistance.

[0064] It should be noted that the barrier layer 200 has a low resistivity, which can be understood as being on the order of 10. -5 Ω⋅cm.

[0065] Step S300: Perform a deposition process to form a conductive material layer. The conductive material layer fills part of the contact holes and covers the substrate. See the attached diagram for its structure. Figure 5 .

[0066] Step S400: Perform an etching process to remove a portion of the conductive material layer to form a conductive layer. Please refer to the diagram for its structure. Figure 6 .

[0067] Step S500: Repeat the deposition and etching processes at least once to form at least one conductive layer, wherein the conductive layer and the barrier layer located within the contact hole constitute a contact plug. Please refer to the connection structure. Figure 10 .

[0068] This application embodiment utilizes a phased deposition of the conductive material layer 310, combined with etching steps, to gradually release stress and optimize the filling quality of the conductive layer 320 within the contact hole 130. For example, after the initial deposition, the conductive material layer 310 is etched back to reduce substrate warpage; secondary or even tertiary depositions further fill the contact hole 130; and finally, stress is eliminated through multiple etch-back cycles, preventing the formation of voids within the formed contact plug 300 and improving step coverage, thereby increasing the contact resistance of the contact plug 300 and improving the yield of the semiconductor device.

[0069] In one possible implementation, the steps of performing a deposition process to form a conductive material layer include:

[0070] Please refer to Figure 5 A chemical vapor deposition process is performed to form a conductive material layer 310. The conductive material layer 310 fills a portion of the contact hole 130 and covers the substrate 100. A recessed region 140 is formed within the contact hole 130 of the conductive material layer 310. The minimum thickness of the conductive material layer 310 located within the contact hole 130 is less than the thickness of the conductive material layer 310 located on the top surface of the substrate 100, along a direction perpendicular to the substrate 100. The conductive material layer 310 is made of tungsten (W). Figure 5 Taking the orientation shown as an example, the vertical distance between the lowest point of the recessed area 140 and the bottom of the contact hole 130 is the minimum thickness of the conductive material layer 310 located within the contact hole 130.

[0071] This embodiment controls the process parameters of the deposition process so that the minimum thickness of the conductive material layer 310 located in the contact hole 130 is less than the thickness of the conductive material layer 310 located on the top surface of the substrate 100. In this way, while ensuring that the conductive material layer 310 formed in the contact hole 130 does not form voids, the aspect ratio of the area enclosed by the conductive layer formed after each deposition and etching and the inner wall of the contact hole 130 is reduced as much as possible. This provides a good foundation for the next deposition process, avoids the formation of "overhanging protrusions" at the opening of the contact hole 130, avoids voids in the final contact plug 300, and improves the yield of semiconductor devices.

[0072] Please refer to Figure 6 In one possible implementation, the steps of performing the etching process include:

[0073] An etching process is performed to remove a portion of the conductive material layer covering the substrate and a portion of the conductive material layer located within the contact hole to form a conductive layer; wherein the conductive layer located on the substrate has a flat surface.

[0074] Therefore, this embodiment of the application performs a deposition process and an etching process simultaneously, using a full-surface etching process to simultaneously remove the conductive material layer 310 located within the contact hole 130 and the conductive material layer 310 located on the top surface of the substrate 100. This ensures that the conductive layer 320 on the substrate 100 has a flat surface, avoiding a "protrusion" phenomenon at the top opening of the contact hole 130, thus providing a smoother surface for the next deposition process. This prevents gaps in the final contact plug 300 and improves the yield of the semiconductor device.

[0075] In one possible implementation, the steps of repeating the deposition and etching processes at least once include:

[0076] The deposition and etching processes are repeated twice to form a two-layer conductive layer, wherein the conductive layer and the barrier layer located in the contact hole constitute a contact plug.

[0077] After completing the first deposition and first etching processes, please refer to... Figure 7 A second deposition process is performed to deposit a conductive material layer 310 of a certain thickness on the conductive layer 320 formed in the first deposition.

[0078] Please refer to Figure 8 A second etching process is performed to remove a portion of the second conductive material layer 310 to form a second conductive layer 320. A full-surface etching process is used to simultaneously remove the conductive material layer 310 located within the contact hole 130 and the conductive material layer 310 located on the top surface of the substrate 100.

[0079] After completing the second deposition and second etching processes, please refer to... Figure 9 A second etching process is performed to deposit a conductive material layer 310 of a certain thickness on the conductive layer 320 formed in the second etching process.

[0080] Please refer to Figure 10 A third etching process is performed to remove a portion of the conductive material layer 310 formed in the third etching process, thereby forming the third conductive layer 320. A full-surface etching process is used to simultaneously remove the conductive material layer 310 located within the contact hole 130 and the conductive material layer 310 located on the top surface of the substrate 100, so that the barrier layer 200 formed within the contact hole 130 and the three conductive layers 320 constitute the contact plug 300.

[0081] Given that the conductive material layer 310 is a high-stress film (e.g., stress greater than 1300 MPa), if a single deposition and etching process is used, it will cause significant warpage of the substrate 100 (e.g., warpage greater than 300 μm), severely affecting the processing stability of subsequent processes. It should be noted that the warpage of the substrate 100 can be understood as the distance between the highest and lowest points of the substrate 100.

[0082] This embodiment employs multiple deposition and etching processes, performed alternately, to gradually release stress and optimize the filling quality of the conductive layer 320 within the contact hole 130. For example, after the initial deposition, the conductive material layer is etched back to reduce substrate warpage; secondary or even tertiary depositions further fill the voids within the contact hole 130; and finally, stress is eliminated through multiple etch-back cycles, preventing the formation of voids within the formed contact plug 300 and improving step coverage, thereby increasing the contact resistance of the contact plug 300 and improving the yield of the semiconductor device. In this embodiment, through the above improvements, the warpage of the substrate 100 is reduced from greater than 300 μm to approximately 50 μm.

[0083] In one possible implementation, the total thickness of the conductive layer 320 and the barrier layer 200 on the substrate 100 is 0.1 μm to 0.3 μm. For example, the total thickness of the conductive layer 320 and the barrier layer 200 on the substrate 100 is 0.1 μm, 0.2 μm, 0.3 μm, and any value within the area enclosed by two adjacent values.

[0084] It should be noted that the thickness of the conductive layer 320 on the substrate 100 refers to the thickness of the conductive layer 320 of all layers on the substrate 100.

[0085] In this embodiment of the application, by reasonably adjusting the thickness of the conductive layer 320 and the barrier layer 200 located on the substrate 100, the overall thickness of the semiconductor device can be reduced, which facilitates the development of semiconductor devices towards integration and miniaturization.

[0086] Please refer to Figure 11 In one possible implementation, after repeating the deposition and etching processes at least once to form at least one conductive layer, the method for fabricating a semiconductor device further includes:

[0087] Part of the conductive layer and barrier layer located on the substrate are removed, and the remaining conductive layer and barrier layer on the substrate constitute the interconnect block of the interconnect layer.

[0088] For example, a portion of the conductive layer 320 and barrier layer 200 on the substrate 100 are etched using a patterning process, such that the remaining conductive layer 320 and barrier layer 200 constitute the interconnect blocks of the interconnect layer (not shown in the figure). Compared with related technologies, which completely remove the conductive layer 320 and barrier layer 200 on the substrate 100 and then re-form the interconnect layer, this simplifies the process flow. For example, it simplifies the deposition and etching processes of the interconnect material layer. In this embodiment, the conductive layer 320 and barrier layer 200 on the substrate 100 can be directly defined as the target interconnect pattern with only one patterning etching. This significantly shortens the process cycle, reduces equipment usage time and consumable consumption, and directly reduces the manufacturing cost of semiconductor devices.

[0089] Furthermore, this application utilizes the fact that the conductive layer 320 (such as W) and the barrier layer 200 are themselves high-performance thin films with low resistivity, good adhesion and barrier properties, which greatly improves the performance of the interconnect layer.

[0090] This application also provides a semiconductor device, which is prepared by the semiconductor device preparation method described in any of the above embodiments.

[0091] The semiconductor device includes a substrate 100, which includes a substrate 110 and an epitaxial layer 120 stacked on the substrate 110. The epitaxial layer 120 is disposed on the substrate 110. The substrate 100 has a contact hole 130 extending in a direction perpendicular to the substrate 100, and the bottom of the contact hole 130 is located within the epitaxial layer 120.

[0092] A contact plug 300 is disposed within a contact hole 130. The contact plug 300 includes a stacked barrier layer 200 and at least two conductive layers 320. The barrier layer 200 is disposed on the inner wall of the contact hole 130, and the at least two conductive layers 320 are sequentially stacked on the barrier layer 200. The barrier layer 200 is made of NiSi material. x .

[0093] Therefore, the semiconductor device provided in this application embodiment is fabricated by the preparation method described in any of the above embodiments, and is prepared by at least two deposition and etching processes. This allows for the gradual release of stress and optimization of the filling quality of the conductive layer 320 within the contact hole 130. For example, after the first deposition, the conductive material layer is etched back to reduce substrate warpage; secondary or even tertiary depositions further fill the voids within the contact hole; and finally, stress is eliminated through multiple etch-back cycles, preventing the formation of voids within the formed contact plug and improving step coverage, thereby increasing the contact resistance of the contact plug and improving the yield of the semiconductor device.

[0094] In one possible implementation, the semiconductor device further includes an interconnect block 400 disposed on the substrate 100, wherein the film layer of the interconnect block 400 is the same as the film layer of the contact plug 300, and the two film layers are formed synchronously.

[0095] In other words, the interconnect block 400 also includes a stacked barrier layer and at least two conductive layers, and the barrier layer and at least two conductive layers of the interconnect block 400 are prepared simultaneously with the barrier layer and at least two conductive layers of the contact plug 300.

[0096] This simplifies the semiconductor device manufacturing process. For example, it simplifies the deposition and etching processes of interconnect material layers. In this embodiment, only one patterning etching is needed to directly define the conductive layer 320 and the barrier layer 200 on the substrate 100 as the target interconnect pattern. This significantly shortens the process cycle, reduces equipment usage time and material consumption, and directly reduces the manufacturing cost of semiconductor devices.

[0097] This application provides a chip that includes the semiconductor device described in any of the above embodiments. For example, the chip may be a memory chip such as DRAM or SRAM, an image sensor chip, or a processor chip.

[0098] Since the chip provided in this embodiment includes the semiconductor device described in any of the above embodiments, it has all the beneficial effects of a semiconductor device, and will not be described in detail here.

[0099] This application also provides an electronic device, including a smartphone, computer, server, or data center computing unit. The electronic device includes the chip described in the foregoing embodiments of this application, and therefore possesses all the beneficial effects of the chip; further details will not be elaborated upon here.

[0100] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0101] It should be noted that the terms "one embodiment," "embodiment," "exemplary embodiment," "some embodiments," etc., mentioned in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the knowledge scope of those skilled in the art.

[0102] In the context of this application, when a layer / element is referred to as being "on top of" another layer / element, the layer / element can be directly on top of the other layer / element, or there can be an intermediate layer / element between them. Furthermore, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element can be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0103] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise expressly specified. "Several" means one or more, unless otherwise expressly specified.

[0104] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0105] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, and the substrate is patterned to form contact holes in the substrate; A barrier layer is formed, the barrier layer at least covering the inner wall of the contact hole, wherein the barrier layer is made of NiSi. x ; A deposition process is performed to form a conductive material layer, which fills a portion of the contact holes and covers the substrate; An etching process is performed to remove a portion of the conductive material layer to form a conductive layer; The deposition process and the etching process are repeated at least once to form at least one conductive layer, wherein the conductive layer and the barrier layer located within the contact hole constitute a contact plug.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of performing the deposition process to form a conductive material layer includes: A chemical vapor deposition process is performed to form a conductive material layer that fills part of the contact hole and covers the top surface of the substrate. The conductive material layer also forms a recessed area within the contact hole. The minimum thickness of the conductive material layer located within the contact hole is less than the thickness of the conductive material layer located on the top surface of the substrate, along a direction perpendicular to the substrate.

3. The method for fabricating a semiconductor device according to claim 2, characterized in that, The steps of performing the etching process include: An etching process is performed to remove a portion of the conductive material layer covering the substrate and a portion of the conductive material layer located within the contact hole to form the conductive layer; wherein the conductive layer located on the substrate has a flat surface.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The step of repeating the deposition process and the etching process at least once includes: The deposition process and the etching process are repeated twice to form a two-layer conductive layer, wherein the three-layer conductive layer and the barrier layer stacked within the contact hole constitute the contact plug.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The total thickness of the conductive layer and the barrier layer located on the substrate is 0.1μm-0.3μm.

6. The method for fabricating a semiconductor device according to any one of claims 1-5, characterized in that, After repeating the deposition process and the etching process at least once to form at least one conductive layer, the fabrication method further includes: The conductive layer and the barrier layer located on the substrate are partially removed, and the remaining conductive layer and barrier layer on the substrate constitute the interconnect block of the interconnect layer.

7. A semiconductor device, characterized in that, The semiconductor device is prepared by the method for preparing a semiconductor device according to any one of claims 1-6, and the semiconductor device comprises: A substrate having contact holes therein; A contact plug is disposed within a contact hole. The contact plug comprises a barrier layer and at least two conductive layers stacked together, wherein the barrier layer is disposed on the inner wall of the contact hole, and the barrier layer is made of NiSi material. x .

8. The semiconductor device according to claim 7, characterized in that, The semiconductor device further includes an interconnect block disposed on the substrate; wherein the film layer of the interconnect block is the same as the film layer of the contact plug, and the two film layers are formed synchronously.

9. A chip, characterized in that, Includes the semiconductor device as described in claim 7 or 8.

10. An electronic device, characterized in that, Includes the chip described in claim 9.

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