Semiconductor structure

Abstract

The embodiment of the invention provides a semiconductor structure, which comprises a plurality of rows of first word lines and a plurality of first conductive lines, and each first conductive line corresponds to each first word line in an odd-numbered row or an even-numbered row and is connected with the first word line in the odd-numbered row or the even-numbered row; the plurality of first conductive contacts are arranged corresponding to the first conductive wires, and the plurality of second conductive contacts are arranged corresponding to the first conductive contacts and are isolated from each other; each second conductive contact is connected to each first contact pad; wherein a minimum distance D0 is formed between the adjacent first conductive contacts in the first direction, a minimum distance D1 is formed between the adjacent second conductive contacts in the first direction, the minimum distance D0 is smaller than the minimum distance D1, in the second direction, each first conductive contact has a minimum length L0, each second conductive contact has a minimum length L1, and the minimum length L0 is smaller than the minimum length D1. The minimum length L0 is less than the minimum length L1. The semiconductor structure provided by the embodiment of the invention has a simpler interconnection mode, and the process flow is simplified while the signal density is increased.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor structure. Background Technology

[0002] Memory is used to store data in modern computing architectures. Dynamic random access memory (DRAM) has the advantages of simple structure, low cost and high speed, and is widely used in personal computers, servers and various electronic devices as main memory.

[0003] As data continues to grow rapidly, the increase in DRAM density is slowing down, leading to a widening gap between memory demand and DRAM capacity. Increasing packaging density to improve integration and thus obtain higher storage capacity has become an important goal of integrated circuit manufacturing at this stage, and memory with tight packaging urgently needs to be developed. Summary of the Invention

[0004] This disclosure provides a semiconductor structure with higher integration.

[0005] The technical spirit of this disclosure aims to solve problems not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0006] An exemplary embodiment of this disclosure provides a semiconductor structure, including: a first memory cell array, the first memory array including multiple rows of first word lines extending along a first direction, each first word line being isolated from each other; a first interconnect region including multiple first conductive lines extending along the first direction, each first conductive line corresponding to and connected to each first word line in an odd-numbered or even-numbered row; a first conductive contact assembly disposed in the first interconnect region, the first conductive contact assembly including multiple first conductive contacts, each first conductive contact corresponding to each first conductive line, and each first conductive contact extending along a second direction and connected to each first conductive line; and a second interconnect region adjacent to the first memory cell array in the first direction. The system comprises a column and a first interconnection area, and a second interconnection area with a second conductive contact assembly, the second conductive contact assembly including multiple second conductive contacts, each second conductive contact corresponding to and isolated from each first conductive contact; the second interconnection area with multiple first contact pads, each second conductive contact extending along a second direction and connected to each first contact pad; wherein, in the first direction, there is a minimum spacing D0 between adjacent first conductive contacts, and in the first direction, there is a minimum spacing D1 between adjacent second conductive contacts, the minimum spacing D0 being less than the minimum spacing D1; in the second direction, each first conductive contact has a minimum length L0, and each second conductive contact has a minimum length L1, the minimum length L0 being less than the minimum length L1.

[0007] According to an example embodiment of the present disclosure, in a first direction, each first conductive contact in a first conductive contact assembly has an average width W0, and each second conductive contact in a second conductive contact assembly has an average width W1, wherein the average width W0 of each first conductive contact is less than the average width W1 of each second conductive contact.

[0008] According to an example embodiment of this disclosure, a first conductive contact assembly includes a first column of first conductive contact assemblies and a second column of first conductive contact assemblies arranged at intervals along a third direction. Each first conductive contact in the first column of first conductive contact assemblies is connected to a first conductive line in an odd-numbered row, and each first conductive contact in the second column of first conductive contact assemblies is connected to a first conductive line in an even-numbered row. In a first direction, at least one first conductive contact in the first column of first conductive contact assemblies and the second conductive contact assemblies has a maximum distance D2 between it and a corresponding second conductive contact. The first conductive contact and the second conductive contact with the maximum distance D2 form a first reference row. The maximum distance between each first conductive contact in the second column of first conductive contact assemblies arranged adjacent to the first reference row and each corresponding second conductive contact is less than the maximum distance D2.

[0009] According to an example embodiment of the present disclosure, each first conductive contact and each second conductive contact disposed adjacent to the first reference row respectively form a first reference row and a second reference row. The first conductive contact and the second conductive contact in the first reference row have a maximum spacing D3, and the first conductive contact and the second conductive contact in the second reference row have a maximum spacing D4. The maximum spacing D3 is greater than the maximum spacing D4, and both the maximum spacing D3 and the maximum spacing D4 are less than the maximum spacing D2.

[0010] According to an example embodiment of the present disclosure, in a first direction, at least one first conductive contact and a corresponding second conductive contact in a second column of first conductive contact combinations and second conductive contact combinations have a maximum distance D5 between them. The first conductive contact and the second conductive contact with the maximum distance D5 form a second reference row. The maximum distance between each first conductive contact in a first column of first conductive contact combinations arranged adjacent to the second reference row and each corresponding second conductive contact is less than the maximum distance D5.

[0011] According to an example embodiment of this disclosure, each first conductive contact and each second conductive contact disposed adjacent to the second reference row respectively form a third reference row and a fourth reference row. The first conductive contact and the second conductive contact in the third reference row have a maximum spacing D6, and the first conductive contact and the second conductive contact in the fourth reference row have a maximum spacing D7. The maximum spacing D6 is greater than the maximum spacing D7, and both the maximum spacing D6 and the maximum spacing D7 are less than the maximum spacing D5.

[0012] According to an example embodiment of this disclosure, the first memory cell array further includes multiple columns of first lines extending in a third direction, each first line being isolated from the others; a third interconnect region, the third interconnect region including multiple second conductive lines extending in a third direction, each second conductive line corresponding to and connected to each first line in an odd or even column; a fourth interconnect region, the fourth interconnect region being disposed adjacent to the first cell array and the third interconnect region in a third direction, some second conductive lines being disposed in the third interconnect region, and some second conductive lines extending from the third interconnect region to the fourth interconnect region; a third conductive contact assembly, the third conductive contact assembly including multiple third conductive contacts, each third conductive contact including multiple third conductive contacts disposed in the third interconnect region and multiple third conductive contacts disposed in the fourth interconnect region, each third conductive contact being connected to a corresponding first conductive line; the third interconnect region being provided with a fourth conductive contact assembly, the fourth conductive contact assembly including multiple fourth conductive contacts, each fourth conductive contact corresponding to and connected to each third conductive contact.

[0013] According to an example embodiment of this disclosure, in a third-party direction, each third conductive contact in the third conductive contact assembly has an average width W2, and each fourth conductive contact in the fourth conductive contact assembly has an average width W3, wherein the average width W2 of each third conductive contact is less than the average width W3 of each fourth conductive contact.

[0014] According to an example embodiment of this disclosure, in the third direction Y, the spacing between each third conductive contact and its corresponding fourth conductive contact is the same.

[0015] According to an example embodiment of this disclosure, in a third direction, each second conductive line located in the third interconnect region has a length L3, and there are at least two second conductive lines extending to the fourth interconnect region between adjacent second conductive lines in the third interconnect region. Each second conductive line extending to the fourth interconnect region has a different length and is greater than the length L3. Each second conductive line located in the third interconnect region has a maximum spacing Dmax between it and its corresponding fourth conductive contact. The sum of the maximum spacing Dmax and the length L3 is between the length values ​​of each second conductive line extending to the fourth interconnect region.

[0016] According to one example embodiment of this disclosure, the number of rows of the first word lines in the first memory cell array is less than the number of columns of the first bit lines in the third interconnect region.

[0017] According to an exemplary embodiment of this disclosure, it further includes a plurality of third conductive lines, each of which includes portions disposed in a first interconnect region and a second interconnect region and portions disposed in a third interconnect region and a fourth interconnect region. Each third conductive line disposed in the first interconnect region and the second interconnect region is respectively connected to each first conductive contact and each second conductive contact. Each third conductive line disposed in the third interconnect region and the fourth interconnect region is respectively connected to each corresponding third conductive contact and each fourth conductive contact.

[0018] According to an example embodiment of the present disclosure, the semiconductor structure further includes a second memory cell array, which includes multiple rows of isolated second word lines extending along a first direction, each second word line being connected to a corresponding second conductive contact.

[0019] According to an example embodiment of the present disclosure, the semiconductor structure further includes a second memory cell array, which includes multiple rows of mutually isolated second bit lines extending along a third direction, each second bit line being correspondingly connected to a fourth conductive contact.

[0020] In the semiconductor structure provided in this disclosure, each first conductive contact is arranged with a relatively small spacing in the first interconnect region, and each second conductive contact is arranged with a relatively large spacing in the second interconnect region. While ensuring good isolation between adjacent conductive contacts, a simpler interconnection method can be set in the second interconnect region. For example, only a single contact pad is set to connect with each second conductive contact to realize the transmission of signals in the second interconnect region, thereby increasing signal density and simplifying the process flow. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure.

[0022] Figure 1A A simplified schematic plan view of a semiconductor structure provided in an embodiment of this disclosure.

[0023] Figure 1B A cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure.

[0024] Figures 2-3 A simplified schematic plan view of a semiconductor structure provided in an embodiment of this disclosure.

[0025] Figure 4A A simplified schematic plan view of a semiconductor structure provided in an embodiment of this disclosure.

[0026] Figure 4B Cross-sectional view of a semiconductor structure provided in the embodiments of this disclosure.

[0027] Figures 5-6 A simplified schematic plan view of a semiconductor structure provided in an embodiment of this disclosure.

[0028] Figure 7A A cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure.

[0029] Figure 7B A cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure.

[0030] The accompanying drawings have illustrated specific embodiments of the present disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of the present disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0031] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are merely for explaining the relevant disclosure and not for limiting the disclosure. It should also be noted that, for ease of description, only relevant parts are shown in the accompanying drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit this disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict. It should be noted that the terms "first, second, third" involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described.

[0032] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0033] Figure 1A This is a simplified schematic plan view of the semiconductor structure 1 provided in an embodiment of the present disclosure. Figure 1B for Figure 1A A cross-sectional view obtained by using line A1-A2 as the section. Combined with... Figure 1A and Figure 1BThe semiconductor structure 1 includes a first memory cell array 10, in which multiple rows of parallel word lines are provided, for example, multiple rows of first word lines 110 extending along a first direction X. Each first word line 110 is parallel to and isolated from the others. The semiconductor structure 1 also includes a first interconnect region 11, in which multiple conductive lines extending along the first direction X are provided, such as first conductive lines 120. Each first conductive line 120 is parallel to each other in the first direction X and is connected to either the odd-numbered rows of first word lines 110 or the even-numbered rows of first word lines 110, and is correspondingly arranged. That is, another row of first word lines 110 that is not connected to any of the first conductive lines 120 is also provided between each of the first conductive lines 120. Each first conductive line 120 can also be connected to each of the first word lines 110. Figure 1A The example provided illustrates how each first conductive line 120 is connected to each first word line 110 in either an odd-numbered or even-numbered row. It should be noted that first word lines not connected to each first conductive line 120 are connected via conductive lines in other interconnection areas. A first conductive contact assembly FC is provided in the first interconnection area 11. The first conductive contact assembly FC includes a combination of multiple conductive contacts corresponding to each first conductive line 120, such as first conductive contacts 140, 141, 142, and 143. These conductive contacts are numbered differently to indicate that they are connected to different first conductive lines 120.

[0034] In the first direction X, there is a gap between adjacent first conductive contacts. For example, there is a gap between first conductive contacts 140 and 141, a gap between first conductive contacts 141 and 142, and similarly, a gap between first conductive contacts 142 and 143. The gaps between adjacent first conductive contacts may be approximately the same or different, and have a minimum gap, for example, a minimum gap D0. Figure 1A The diagram illustrates a minimum distance D0 between first conductive contacts 142 and 143. This minimum distance D0 can also be the distance between other adjacent first conductive contacts. The value of the minimum distance D0 is greater than 0 and less than the length of each first conductive line 120 extending in the first direction X. The distance between these first conductive contacts refers to the distance between the center points of each first conductive contact, or it can refer to the distance between the same edges of each first conductive contact or the distance between the opposite edges of adjacent first conductive contacts.

[0035] Semiconductor structure 1 includes a second interconnect region 20, which is disposed adjacent to the first memory cell array 10 and the first interconnect region 11 in a first direction X. A second conductive contact assembly SC is disposed in the second interconnect region 20. The second conductive contact assembly SC includes multiple second conductive contacts corresponding to each first conductive contact. For example, a second conductive contact 201 corresponding to a first conductive contact 140, a second conductive contact 202 corresponding to a first conductive contact 141, a second conductive contact 203 corresponding to a first conductive contact 142, and a second conductive contact 204 corresponding to a first conductive contact 143. The second conductive contacts are isolated from each other by a dielectric layer (not shown).

[0036] In the first direction X, adjacent second conductive contacts are arranged at intervals. For example, there is a gap between second conductive contact 201 and second conductive contact 202, a gap between second conductive contact 202 and third conductive contact 203, and similarly, a gap between second conductive contact 203 and second conductive contact 204. The spacing between adjacent second conductive contacts can be approximately the same or different, and has a minimum spacing, for example, a minimum spacing D1. Figure 1A The diagram illustrates a minimum distance D1 between second conductive contacts 201 and 202. This minimum distance D1 can also be the distance between other adjacent second conductive contacts. The value of the minimum distance D1 is greater than 0 and less than the length of the second interconnection region 20 extending in the first direction X. The distances between these second conductive contacts refer to the distance between the center points of each second conductive contact, or the distance between the same edges of each second conductive contact, or the distance between the opposite edges of adjacent second conductive contacts. The minimum distance D0 between each first conductive contact is less than the minimum distance D1 between each second conductive contact.

[0037] See also Figure 1A and Figure 1B The second interconnection region 20 is further provided with a plurality of first contact pads 210, and each second conductive contact extends along the second direction Z and is connected to the corresponding first contact pad 210. Each second conductive contact has a corresponding length in the second direction Z, and the lengths of the second conductive contacts may be approximately the same or different, and have a minimum length. For example, the second conductive contact 201 has a minimum length L1.

[0038] Each first conductive contact extends along the second direction Z to connect with its corresponding first conductive line 120. The second direction Z is perpendicular to the first direction X. Each first conductive contact has a corresponding length in the second direction Z. The lengths of the first conductive contacts may be approximately the same or different, and each has a minimum length. For example, the first conductive contact 140 has a minimum length L0. Each second conductive contact extends along the second direction Z to connect with its corresponding first contact pad 210. The minimum length L0 is less than the minimum length L1.

[0039] In the above embodiments, the first conductive contacts in the first conductive contact assembly FC are arranged in the first interconnection region 11 with a relatively small spacing, and the second conductive contacts in the second conductive contact assembly SC are arranged in the second interconnection region 20 with a relatively large spacing. On the basis of ensuring good isolation between adjacent conductive contacts, a simpler interconnection method can be set in the second interconnection region 20. For example, only a single contact pad 210 is set to connect with each second conductive contact to realize the transmission of signals in the second interconnection region 20, thereby increasing the signal density and simplifying the process flow.

[0040] The first interconnect region 11 may be located above or below the first memory cell array 10. In some embodiments, the first interconnect region 11 is located above or below the edge portion of the first memory cell array 10, that is, the first interconnect region 11 is the region corresponding to the end of each first word line 110. The total number of rows of first word lines 110 in the first memory cell array 10 may be an even number, such as 512 rows, 1024 rows or more.

[0041] In the second direction Z, the projection of each first conductive line 120 overlaps with the projection of its corresponding connected first character line 110, and the projection of each first character line 110 lies within the projection of each first conductive line 120. In the second direction Z, the projection of each second conductive contact overlaps with the projection of its corresponding connected first contact pad 210, and the projection of each second conductive contact lies within the projection of each first contact pad 210.

[0042] See also Figure 1B In the second direction Z, each first conductive line 120 is connected to its corresponding first word line 110 through a contact plug 130 to form a connection channel between each first conductive line 120 and each first word line 110; each first contact pad 210 is also provided with a contact plug 220 to form a channel connecting the second conductive 210 in a direction away from the second conductive contact assembly SC.

[0043] See also Figure 1A and Figure 1BThe first storage cell array 10 also includes multiple columns of first bit lines 111. Each column of first bit lines 111 extends along a third direction Y and is spaced apart from each other in a first direction X. The first direction X and the third direction Y are perpendicular to each other. Each column of first bit lines 111 extends in a second direction Z, and its extension length does not exceed the extension length of each contact plug 130 in the second direction Z. The second direction Z and the third direction Y are perpendicular to each other. The multiple columns of first bit lines 111 and the multiple rows of first word lines 110 are perpendicular to each other or have a certain angle between them. Figure 1A Taking the first bit line 111 and the first word line as perpendicular to each other as an example, but not limited to this. In some embodiments, each first bit line 111 is positioned closer to the first conductive contact combination FC than each first word line 110. The total number of columns of the first bit lines 111 in the first memory cell array 10 can be an even number, for example, 512 columns, 1024 columns or more.

[0044] See also Figure 1B The first memory cell array 10 also includes a plurality of spaced active regions 112 extending along the second direction Z. One end of each active region 112 in the second direction Z is connected to the first word line 111 of each column, and the other end of each active region 112 in the second direction Z is connected to a capacitor array. The capacitor array comprises a lower electrode 152, an upper electrode 150, and a dielectric layer 152 disposed between the upper and lower electrodes, and is used to store charge. In other embodiments, the capacitor array may also be other types of capacitor memory arrays. Each row of first word lines 110 simultaneously surrounds part of the sidewalls of the plurality of active regions 112 in the first direction X, thereby forming a memory that realizes data reading and storage through the storage and detection of charge in the capacitor array, such as a DRAM memory using a vertical channel transistor. The first conductive contact assembly FC is connected to each first word line 110 to control the opening and closing of the electron flow channel in the active region 112 between the first word line 111 of each column and the capacitor array. The second conductive contact assembly SC is connected to each second conductive line 210 to transmit the current signal in the second interconnection region 20.

[0045] In some embodiments of this disclosure, such as Figure 2 As shown, Figure 2 The diagram shows a simplified planar view of semiconductor structure 1. Each first conductive contact in semiconductor structure 1 has a corresponding width in the first direction X. The widths of the first conductive contacts may be approximately the same or different, and these first conductive contacts have an average width, for example, W0. Each second conductive contact also has a corresponding width in the first direction X. The widths of the second conductive contacts may be approximately the same or different, and these second conductive contacts have an average width, for example, W1. The average width W0 of each first conductive contact is less than the average width W1 of each second conductive contact.

[0046] refer to Figures 1A-1B , Figure 2 as well as Figure 3 , Figure 3 The diagram provided is a simplified schematic plan view of semiconductor structure 1. In some embodiments of this disclosure, the first conductive contact assembly FC further includes first conductive contacts 144, 145, and 146, and the second conductive contact assembly SC further includes second conductive contacts 205, 206, and 207. The first conductive contact assembly FC may also include more first conductive contacts, and the second conductive contact assembly SC may also include more second conductive contacts. The number of first and second conductive contacts is not limited to the number shown in the figures. The first conductive contacts in the first conductive contact assembly FC can be divided into a first column first conductive contact assembly FCC and a second column first conductive contact assembly SCC according to their arrangement. The first column first conductive contact assembly FCC includes multiple first conductive contacts arranged along the third direction Y. Each first conductive contact in the first column first conductive contact assembly FCC is connected to the first conductive line 120 in the odd-numbered rows, such as first conductive contact 140, first conductive contact 142, first conductive contact 144, and first conductive contact 146. The second column conductive contact assembly SCC includes multiple first conductive contacts arranged along the third direction Y. Each first conductive contact in the second column first conductive contact assembly SCC is connected to the first conductive line 120 in the even-numbered rows, such as first conductive contact 141, first conductive contact 143, and first conductive contact 145. The first conductive contacts in the first column first conductive contact combination FCC and the first conductive contacts in the second column first conductive contact combination SCC are staggered in the first direction X and have a minimum spacing D0.

[0047] See also Figure 3 In some embodiments, the first column of first conductive contact combination FCC includes at least one first conductive contact and its corresponding second conductive contact having a maximum distance between them. For example, the first conductive contact 142 and the second conductive contact 203 have a maximum distance D2. The combination of the first conductive contact 142, the second conductive contact 203, and the space between the first conductive contact 142 and the second conductive contact 203 is regarded as the first reference row. At this time, two first conductive contacts 141 and 143 of the second column of first conductive contact combination SCC are respectively provided on both sides of the first reference row. The first conductive contact 141 and its corresponding second conductive contact 202 have a maximum distance between them, and the first conductive contact 143 and its corresponding second conductive contact 204 have a maximum distance between them. Both of these maximum distances are less than the maximum distance D2.

[0048] In some embodiments, each of the first conductive contacts and each of the second conductive contacts located adjacent to the first reference row respectively forms a first reference row and a second reference row, for example, such as Figure 3 As shown, the first conductive contact 141 and the second conductive contact 202 form a first reference row, and the first conductive contact 143 and the second conductive contact 204 form a second reference row. There is a maximum distance D3 between the first conductive contact and the second conductive contact in the first reference row, and there is a maximum distance D4 between the first conductive contact and the second conductive contact in the second reference row. D3 is greater than D4, and both D3 and D4 are less than D2.

[0049] See also Figure 3 In some embodiments, at least one first conductive contact combination SCC in the second column includes a maximum distance between a first conductive contact and its corresponding second conductive contact. For example, the first conductive contact 145 and the second conductive contact 206 have a maximum distance D5. The combination of the first conductive contact 145, the second conductive contact 206, and the space between the first conductive contact 145 and the second conductive contact 206 is regarded as the second reference row. At this time, two first conductive contacts 144 and 146 in the first column first conductive contact combination FCC are respectively provided on both sides of the second reference row. The first conductive contact 144 has a maximum distance between its corresponding second conductive contact 205, and the first conductive contact 146 has a maximum distance between its corresponding second conductive contact 207. Both of these maximum distances are less than the maximum distance D5.

[0050] In some embodiments, each of the first conductive contacts and each of the second conductive contacts located adjacent to the second reference row respectively forms a third reference row and a fourth reference row, for example, such as Figure 3 As shown, the first conductive contact 144 and the second conductive contact 205 form a third reference row, and the first conductive contact 146 and the second conductive contact 207 form a fourth reference row. The first conductive contact and the second conductive contact in the third reference row have a maximum distance D6 between them, and the first conductive contact and the second conductive contact in the fourth reference row have a maximum distance D7 between them. D6 is greater than D7, and both D6 and D7 are less than D5.

[0051] In the above embodiments, the first reference row, the second reference row, and each reference row refer to a virtual row formed by a set of corresponding first conductive contacts and second conductive contacts along the first direction X, used to mark the positions of the corresponding first conductive contacts and second conductive contacts.

[0052] In the above embodiments, when the conductive contacts in the first interconnect region 11 and the second interconnect region 20 are arranged, the first column of first conductive contacts with the largest spacing and their corresponding second conductive contacts are taken as the first reference row, and the second column of first conductive contacts with the largest spacing and their corresponding second conductive contacts are taken as the second reference row. The second column of first conductive contacts and the first column of first conductive contacts and their corresponding second conductive contacts are arranged on both sides adjacent to the first reference row and the second reference row, respectively, to form each reference row. By controlling the spacing between each conductive contact in each reference row, the space utilization rate in the first interconnect region 11 and the second interconnect region 20 is maximized, and short circuits between each conductive contact and the generation of parasitic capacitance are avoided.

[0053] The semiconductor structure 1 provided in this embodiment further includes a plurality of conductive contacts connected to the first line 111 of each column along the third direction Y, such as Figure 4A and Figure 4B As shown, Figure 4A This is a simplified schematic plan view of the semiconductor structure 1 provided in an embodiment of the present disclosure. Figure 4B for Figure 4A The cross-sectional view is obtained along line B1-B2. In the third direction Y, the semiconductor structure 1 also includes a third interconnect region 12, which includes multiple isolated, parallel columns of bit lines 111 in the third direction Y. A fourth interconnect region 30 is disposed adjacent to the first memory cell array 10 and the third interconnect region in the third direction Y, and the bit lines in the first memory cell array 10 do not extend into the fourth interconnect region 30.

[0054] The third interconnect region 12 includes multiple second conductive lines 121 extending along the third direction Y. These first conductive lines 121 are correspondingly disposed and connected to the first line 111 of the odd or even columns. Each second conductive line 121 extends along the third direction Y and is spaced apart along the first direction X. Some of the second conductive lines 121 do not extend beyond the third interconnect region 12 in the third direction Y, while some of the second conductive lines 121 extend from the third interconnect region 12 to the fourth interconnect region 30 in the third direction Y. The second conductive lines 121 and the first conductive lines 120 together can form the first layer of conductive lines in the semiconductor structure 1, which represents conductive lines located in different regions formed by the same conductive line fabrication process.

[0055] See also Figure 4A and Figure 4BThe semiconductor structure 1 also includes a third conductive contact assembly TR, which comprises multiple third conductive contacts, such as third conductive contacts 160 to 165. Each third conductive contact is correspondingly disposed with each second conductive line 121. Some third conductive contacts are disposed in the third interconnect region 12, and some third conductive contacts are disposed in the fourth interconnect region 30, such as third conductive contacts 160 and 163 disposed in the third interconnect region 12. The remaining third conductive contacts are disposed in the fourth interconnect region 30. A fourth conductive contact assembly FR is also disposed in the fourth interconnect region, which comprises multiple fourth conductive contacts, such as fourth conductive contacts 301 to 306. Each fourth conductive contact is correspondingly disposed with each third conductive contact in the third direction Y and is electrically connected to each other.

[0056] See also Figure 4A and Figure 4B The second conductive line 121 is connected to its corresponding first word line 111 via a contact plug 131, and the third conductive contact 160 is directly connected to the second conductive line 121. The fourth conductive contact 301 corresponding to the third conductive contact 160 extends in the second direction Z to the second contact pad 211 corresponding to the fourth conductive contact 301. The second contact pad 211 is a conductive line disposed in the fourth interconnect region 30, and together with each of the first contact pads 210 disposed in the second interconnect region 20, it can form the same layer conductive line of the semiconductor structure 1. It represents that the first contact pad 210 and the second contact pad 211 are connected pads located in different regions formed by the same connected pad manufacturing process.

[0057] In some embodiments, the third interconnection region 12 is the region where the ends of each first line 111 are located in the third direction Y. The projections of each first conductive line 121 and the corresponding first line 111 in the second direction Z have an overlapping region. The projections of each third conductive contact and each first conductive line 121 in the second direction Z also have an overlapping region, and the projections of each third conductive contact are located within the projections of each first conductive line 121.

[0058] See also Figure 5 , Figure 5 The diagram shows a simplified plan view of semiconductor structure 1. Each third conductive contact in semiconductor structure 1 has a corresponding width in the third direction Y. The widths of the third conductive contacts may be approximately the same or different, and these third conductive contacts have an average width, such as W2. Each fourth conductive contact also has a corresponding width in the third direction Y. The widths of the fourth conductive contacts may be approximately the same or different, and these fourth conductive contacts have an average width, such as W3. The average width W2 of each third conductive contact is smaller than the average width W3 of each fourth conductive contact.

[0059] See also Figure 6 , Figure 6 In a simplified schematic plan view of semiconductor structure 1, in the third direction Y, each third conductive contact is disposed near the same end of each second conductive line 121. For example, each second conductive line 121 may be located near the end of the fourth interconnect region 30 or extend to the end of the fourth interconnect region 30. In the third direction Y, each third conductive contact has a spacing between it and its corresponding fourth conductive contact. These spacings are the same or substantially the same, for example, the spacing D8 between the third conductive contact 161 and the fourth conductive contact 302.

[0060] In some embodiments, the spacing between each third conductive contact and its corresponding fourth conductive contact may be partially the same or all different, and the spacing between each third conductive contact and its corresponding fourth conductive contact in the embodiments of this disclosure is not limited thereto.

[0061] In the third direction Y, at least two second conductive lines 121 extending from the third interconnect region 12 to the fourth interconnect region 30 are disposed between adjacent second conductive lines 121 in the third interconnect region 12. In the embodiments of this disclosure, an example is given where two second conductive lines 121 extending from the third interconnect region 12 to the fourth interconnect region 30 are disposed between adjacent second conductive lines 121 located in the third interconnect region 12. Figure 6 As shown, the second conductive line 121 corresponding to the third conductive contact 163 is disposed in the third interconnection region 12 and does not extend from the third interconnection region 12 to the fourth interconnection region 30, and has a length L3. Another third conductive contact adjacent to the third conductive contact and located in the third interconnection region 12 is the third conductive contact 160. Between the third conductive contact 160 and the third conductive contact 163, there are also third conductive contacts 161 and 162. The length of the second conductive line 121 corresponding to the third conductive contact 161 in the third direction Y is L4, and the length of the second conductive line 121 corresponding to the third conductive contact 162 in the third direction Y is L5. L4 is less than L5 and greater than L3.

[0062] In some embodiments, each second conductive line 121 disposed in the third interconnection region 12 has a maximum spacing between it and its corresponding fourth conductive contact, for example, as shown in the figure. Figure 6 As shown, the fourth contact pad 304 and its corresponding second conductive line 121 are used as an example for explanation. The distance between the end edge of the second conductive line 121 corresponding to the third conductive contact 163 in the third interconnection region 12 and the end edge of the corresponding fourth conductive contact 304 away from the third conductive contact 163 is the maximum distance Dmax, and the sum of Dmax and L3 is between L4 and L5.

[0063] In the above embodiments, each third conductive contact has a portion arranged in the third interconnect region and a portion arranged in the fourth interconnect region, thereby effectively avoiding short circuits between adjacent third conductive contacts or other adverse factors affecting electrical properties. At the same time, a fourth interconnect region is provided outside the third interconnect region, adjacent to the third interconnect region. The fourth conductive contacts in the fourth interconnect region maintain a predetermined distance from the third conductive contacts, so as to maximize the space utilization of the third interconnect region and the fourth interconnect region, avoid short circuits between conductive contacts and the generation of parasitic capacitance, and provide design ideas and practices for further increasing device density or wiring density, which can further improve the integration of semiconductor structure.

[0064] In some embodiments, the number of rows of the first word lines in the first memory cell array 10 is less than the number of columns of the first word lines. For example, the first memory cell array 10 includes 512 rows of first word lines and 1024 columns of first word lines.

[0065] See also Figures 1A-1B as well as Figure 4A and Figure 4B The semiconductor structure 1 also includes multiple third conductive lines 122, including portions of third conductive lines 122 disposed in the first interconnect region 11 and the second interconnect region 20, and portions of third conductive lines 122 disposed in the third interconnect region 12 and the fourth interconnect region 30. Each third conductive line 122 disposed in the first interconnect region 11 is correspondingly disposed with and connected to each first conductive contact. Each third conductive line 122 disposed in the second interconnect region 20 is correspondingly disposed with and connected to each second conductive contact. Each third conductive line 122 disposed in the third interconnect region 12 and the fourth interconnect region 30 extends from the third interconnect region 12 into the fourth interconnect region 30, and is connected to its corresponding third and fourth conductive contacts. That is, each third conductive contact and its corresponding fourth conductive contact are interconnected via the third conductive lines 122 extending in the third interconnect region 12 and the fourth interconnect region 30.

[0066] In some embodiments, each third conductive line 122 in the first interconnect region 11 has the same or approximately the same width in the first direction X, and the projected area of ​​each third conductive line 122 in the first interconnect region 11 in the second direction Z is greater than the projected area of ​​each corresponding first conductive contact, and the projection of each first conductive contact is located within the projection of each third conductive line 122.

[0067] In some embodiments, each of the third conductive lines 122 located in the second interconnection region 20 has the same or approximately the same width in the first direction X, and the projected area of ​​each of the third conductive lines 122 in the first interconnection region 11 in the second direction Z is greater than the projected area of ​​each corresponding second conductive contact, and the projection of each second conductive contact is located within the projection of each third conductive line 122.

[0068] In some embodiments, the dimensions of each third conductive line 122 located in the first interconnect region 11 and each third conductive line 122 located in the second interconnect region 20 may be the same or different. Figure 1A and Figure 1B The third conductive lines 122 located in the first interconnect region 12 are different in size from the third conductive lines 122 located in the second interconnect region 20.

[0069] In some embodiments, each third conductive line 122 corresponding to each third conductive contact and each fourth conductive contact has the same or approximately the same extension length in the third direction Y, and in the second direction Z, the projections of each third conductive contact and each fourth conductive contact are located within the projection of each corresponding third conductive line 122.

[0070] See also Figure 7A and Figure 7B , Figure 7A A cross-sectional view of the semiconductor structure 1 provided in this embodiment of the present disclosure along a section parallel to the second direction Z. Figure 7B This is a cross-sectional view of the semiconductor structure 1 along a section parallel to the second direction Z. The semiconductor structure 1 also includes a second memory cell array 10', which has a structure similar to the first memory cell array 10, for example, including multiple rows of second word lines 110' arranged parallel to the first direction X and second bit lines 111' arranged parallel to the third direction Y.

[0071] See also Figure 7A In some embodiments, an interconnect region 11' is provided below the second word line 110'. The interconnect region 11' is connected to each second word line 110' in the odd or even rows of each second memory cell array 10'. An interconnect channel is formed between the interconnect region 11' and the second interconnect region 20 to connect to each corresponding first word line 110 in the first memory cell array 10. For example, a connection channel is formed by connecting the first contact pad 210 of the second conductive contact 201 and the contact plug 220, thereby forming a connection channel for each second word line 110' in the second memory cell array 10' in the second interconnect region 20.

[0072] See also Figure 7BIn some embodiments, an interconnection region 12' is further provided below the second memory cell array 10'. The interconnection region 12' is connected to each second bit line 111' of the odd or even columns in each second memory cell array 10'. An interconnection channel is formed between the interconnection region 12' and the second interconnection region 30, which is connected to the corresponding first bit line 111 in the first memory cell array 10. For example, a connection channel is formed by connecting the second contact pad 211 of the fourth conductive contact 301 and the contact plug 320, so as to realize the interconnection between the first bit line 111 and the second bit line 110'.

[0073] In some embodiments, the first contact pad 210 and the second contact pad 211 may be formed in the same process step. In some embodiments, the first contact pad 210 and the second contact pad 211 are located between the capacitor array and the first word line 110, and the top surfaces of the second interconnect region 20 and the fourth interconnect region 30 are higher than the top surface of the capacitor array. By setting the first contact pad 210 and the second contact pad 211, it is possible to avoid the second conductive contact and the fourth conductive contact extending a long length in the second interconnect region 20 or the fourth interconnect region 30, further reducing the process difficulty. In other embodiments, the second interconnect region 20 and the fourth interconnect region 30 may also only have second conductive contacts and fourth conductive contacts extending along the second direction Z.

[0074] In some embodiments, the first memory cell array 10 and the second memory cell array 10' have a bonding surface formed by using a direct bonding or hybrid bonding process, thereby realizing the connection relationship between each word line and each bit line in the first memory cell array 10 and the second memory cell array 10'.

[0075] In some embodiments, the semiconductor structure 1 further includes a logic cell array (not shown), which has portions connected to each of the second conductive lines 122 in the first interconnect region 11, portions connected to each of the second conductive lines 122 in the second interconnect region 20, and portions connected to each of the second conductive lines 122 located in the third interconnect region 12 and the fourth interconnect region 30, thereby enabling corresponding operations to be performed on each of the first word lines 110 and each of the first bit lines 111 in the first memory cell array 10 and each of the second word lines 110' and each of the second bit lines 111' in the second memory cell array 10'.

[0076] In the above embodiments, the first memory cell array 10 and the second memory cell array 10' can be memory cell arrays composed of DRAM memory cells, NAND memory cells or other memory cells, and the logic cell array can be any suitable digital, analog and / or mixed-signal circuit structure used to facilitate the operation of the memory structure.

[0077] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, comprising: A first memory cell array, the first memory array including multiple rows of first word lines extending along a first direction, each of the first word lines being isolated from each other; The first interconnection region includes a plurality of first conductive lines extending along the first direction, each of the first conductive lines being correspondingly disposed to and connected to each of the first word lines in the odd-numbered or even-numbered rows. A first conductive contact assembly is disposed in the first interconnection area. The first conductive contact assembly includes a plurality of first conductive contacts, each of which is disposed corresponding to each of the first conductive lines, and each of the first conductive contacts extends along the second direction and is connected to each of the first conductive lines. A second interconnect region is disposed adjacent to the first memory cell array and the first interconnect region in the first direction. The second interconnect region is provided with a second conductive contact combination. The second conductive contact combination includes a plurality of second conductive contacts, each of which is disposed corresponding to and isolated from each of the first conductive contacts. The second interconnection region is provided with a plurality of first contact pads, and each second conductive contact extends along the second direction and is connected to each of the first contact pads; wherein, there is a minimum spacing D0 between each of the first conductive contacts adjacent in the first direction, and there is a minimum spacing D1 between each of the second conductive contacts adjacent in the first direction, wherein the minimum spacing D0 is less than the minimum spacing D1; in the second direction, each of the first conductive contacts has a minimum length L0, and each of the second conductive contacts has a minimum length L1, wherein the minimum length L0 is less than the minimum length L1.

2. The semiconductor structure according to claim 1, characterized in that, In the first direction, each first conductive contact in the first conductive contact assembly has an average width W0, and each second conductive contact in the second conductive contact assembly has an average width W1, wherein the average width W0 of each first conductive contact is less than the average width W1 of each second conductive contact.

3. The semiconductor structure according to claim 1, characterized in that, The first conductive contact assembly includes a first column of first conductive contact assemblies and a second column of first conductive contact assemblies arranged at intervals along a third direction. Each first conductive contact in the first column of first conductive contact assemblies is connected to each first conductive line in an odd-numbered row. Each first conductive contact in the second column of first conductive contact assemblies is connected to each first conductive line in an even-numbered row. In the first direction, at least one first conductive contact in the first column of first conductive contact assemblies and the second conductive contact assemblies has a maximum distance D2 between it and a corresponding second conductive contact. The first conductive contact and the second conductive contact with the maximum distance D2 form a first reference row. The maximum distance between each first conductive contact in the second column of first conductive contact assemblies arranged adjacent to the first reference row and each corresponding second conductive contact is less than the maximum distance D2.

4. The semiconductor structure according to claim 3, characterized in that, Each first conductive contact and each second conductive contact arranged adjacent to the first reference row respectively form a first reference row and a second reference row. The first conductive contact and the second conductive contact in the first reference row have a maximum distance D3, and the first conductive contact and the second conductive contact in the second reference row have a maximum distance D4. The maximum distance D3 is greater than the maximum distance D4, and both the maximum distance D3 and the maximum distance D4 are less than the maximum distance D2.

5. The semiconductor structure according to claim 3, characterized in that, In the first direction, at least one first conductive contact and a corresponding second conductive contact in the second column first conductive contact combination and the second conductive contact combination have a maximum spacing D5. The first conductive contact and the second conductive contact with the maximum spacing D5 form a second reference row. The maximum spacing between each first conductive contact in the first column first conductive contact combination arranged adjacent to the second reference row and each corresponding second conductive contact is less than the maximum spacing D5.

6. The semiconductor structure according to claim 5, characterized in that, Each first conductive contact and each second conductive contact arranged adjacent to the second reference row respectively form a third reference row and a fourth reference row. The first conductive contact and the second conductive contact in the third reference row have a maximum distance D6 between them, and the first conductive contact and the second conductive contact in the fourth reference row have a maximum distance D7 between them. The maximum distance D6 is greater than the maximum distance D7, and both the maximum distance D6 and the maximum distance D7 are less than the maximum distance D5.

7. The semiconductor structure according to claim 1, characterized in that, The first storage cell array also includes multiple columns of first bit lines extending along a third direction, with each first bit line isolated from the others; The third interconnection region includes a plurality of second conductive lines extending along the third direction, each of the second conductive lines being correspondingly disposed to and connected to each of the first bit lines in the odd or even column; A fourth interconnect region is disposed adjacent to the first memory cell array and the third interconnect region in a third direction, a portion of the second conductive line is disposed in the third interconnect region, and a portion of the second conductive line extends from the third interconnect region to the fourth interconnect region; The third conductive contact assembly includes multiple third conductive contacts, each of which includes multiple third conductive contacts disposed in the third interconnection area and multiple third conductive contacts disposed in the fourth interconnection area, and each of the third conductive contacts is connected to a corresponding first conductive line. The third interconnection area is provided with a fourth conductive contact assembly, which includes a plurality of fourth conductive contacts, each of which is correspondingly provided with and connected to each of the third conductive contacts.

8. The semiconductor structure according to claim 7, characterized in that, In the third direction, each of the third conductive contacts in the third conductive contact assembly has an average width W2, and each of the fourth conductive contacts in the fourth conductive contact assembly has an average width W3, wherein the average width W2 of each third conductive contact is less than the average width W3 of each fourth conductive contact.

9. The semiconductor structure according to claim 7, characterized in that, On the third direction Y, the spacing between each third conductive contact and its corresponding fourth conductive contact is the same.

10. The semiconductor structure according to claim 7, characterized in that, In the third direction, each of the second conductive lines located in the third interconnection region has a length L3. Between each of the adjacent second conductive lines in the third interconnection region, there are at least two second conductive lines extending to the fourth interconnection region. Each of the second conductive lines extending to the fourth interconnection region has a different length and is greater than the length L3. Each of the second conductive lines located in the third interconnection region has a maximum spacing Dmax between it and its corresponding fourth conductive contact. The sum of the maximum spacing Dmax and the length L3 is between the length values ​​of each of the second conductive lines extending to the fourth interconnection region.

11. The semiconductor structure according to claim 7, characterized in that, The number of rows of the first word lines in the first memory cell array is less than the number of columns of the first bit lines in the third interconnect region.

12. The semiconductor structure according to claim 7, characterized in that, It also includes multiple third conductive lines, each of which includes portions disposed in the first interconnect region and the second interconnect region and portions disposed in the third interconnect region and the fourth interconnect region. Each of the third conductive lines disposed in the first interconnect region and the second interconnect region is respectively connected to each of the first conductive contacts and each of the second conductive contacts. Each of the third conductive lines disposed in the third interconnection region and the fourth interconnection region is respectively connected to the corresponding third conductive contact and the corresponding fourth conductive contact.

13. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a second memory cell array, which includes multiple rows of isolated second word lines extending along the first direction, and each second word line is connected to a corresponding second conductive contact.

14. The semiconductor structure according to claim 7, characterized in that, The semiconductor structure further includes a second memory cell array, which includes multiple rows of isolated second bit lines extending along the third direction, and each second bit line is correspondingly connected to each of the fourth conductive contacts.

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