Semiconductor device

Abstract

A semiconductor device includes: a semiconductor element portion including a semiconductor element; a first wiring portion on a first surface of the semiconductor element portion; a support substrate on the first wiring portion; a bonding layer between the first wiring portion and the support substrate; and a second wiring portion on a second surface of the semiconductor element portion opposite the first surface of the semiconductor element portion. The bonding layer includes a pattern layer. The pattern layer includes a first pattern including an insulating material and a second pattern having a thermal conductivity greater than that of the first pattern and electrically insulated from the first wiring portion.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device, and more specifically, to a semiconductor device having an improved structure. Background Technology

[0002] Semiconductor devices can perform a wide range of functions in a small size, and are therefore widely used in various electronics industries. As progress is made in the electronics industry, continuous research is being conducted to improve various attributes such as speed, functionality, reliability, and integration.

[0003] Semiconductor devices generate heat when they operate. If this heat is not adequately dissipated, the performance of the semiconductor device will degrade or be inhibited. As the integration density of semiconductor devices increases, more heat is generated within them, which may lead to greater performance degradation. Therefore, ongoing research is being conducted to ensure adequate dissipation of the heat generated during semiconductor device operation. Summary of the Invention

[0004] This disclosure provides a semiconductor device that can improve performance and reliability.

[0005] A semiconductor device according to an embodiment includes: a semiconductor element portion including a semiconductor element; a first wiring portion located on a first surface of the semiconductor element portion; a support substrate located on the first wiring portion; a bonding layer located between the first wiring portion and the support substrate; and a second wiring portion located on a second surface of the semiconductor element portion opposite to the first surface of the semiconductor element portion. The bonding layer includes a patterning layer. The patterning layer includes a first pattern and a second pattern, the first pattern including an insulating material, and the second pattern having a higher thermal conductivity than the first pattern and being electrically insulating from the first wiring portion.

[0006] A semiconductor device according to an embodiment includes: a semiconductor element portion including a semiconductor element; a first wiring portion located on a first surface of the semiconductor element portion; a support substrate located on the first wiring portion; a bonding layer located between the first wiring portion and the support substrate; and a second wiring portion located on a second surface of the semiconductor element portion opposite to the first surface of the semiconductor element portion. The bonding layer includes a first insulating layer located on the first wiring portion and a conductive pattern located on the first insulating layer.

[0007] A semiconductor device according to an embodiment includes: a semiconductor element portion including a semiconductor element; a front wiring portion located on a front surface of the semiconductor element portion; a support substrate located on the front wiring portion; an intermediate layer located between the front wiring portion and the support substrate; and a rear wiring portion located on a rear surface of the semiconductor element portion. The intermediate layer includes a patterned layer. The patterned layer includes an insulating pattern and a heat dissipation pattern, the insulating pattern including an insulating material, and the heat dissipation pattern including a conductive material and electrically insulated from the front wiring portion.

[0008] According to an embodiment, an intermediate layer located between the first wiring portion and the support substrate (e.g., a bonding layer configured to join the first wiring portion and the support substrate) may include a heat dissipation pattern (e.g., a second pattern) to improve the effective thermal conductivity of the intermediate layer (e.g., the bonding layer) and form a heat dissipation path toward the support substrate. Therefore, the heat dissipation characteristics of the semiconductor device can be improved. Since the heat dissipation pattern (e.g., the second pattern) can be electrically insulated from the first wiring portion, the heat dissipation characteristics can be improved without increasing the wiring path and the resistance of the wiring. Therefore, the performance and reliability of the semiconductor device can be improved. Attached Figure Description

[0009] Figure 1 This is a cross-sectional view showing a semiconductor device according to an embodiment.

[0010] Figure 2 yes Figure 1 An enlarged cross-sectional view of part A in the diagram.

[0011] Figure 3 It is shown Figure 1 A top view of a portion of the patterned layer of the bonding layer included in the semiconductor device shown.

[0012] Figures 4 to 12 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0013] Figure 13 This is a cross-sectional view showing a portion of a semiconductor device according to another embodiment.

[0014] Figure 14 This is a cross-sectional view showing a portion of a semiconductor device according to another embodiment.

[0015] Figure 15 This is a top view showing a partial portion of a patterned layer of a bonding layer included in a semiconductor device according to another embodiment.

[0016] Figure 16 This is a top view showing a partial portion of a patterned layer of a bonding layer included in a semiconductor device according to another embodiment.

[0017] Figure 17 This is a top view showing a partial portion of a patterned layer of a bonding layer included in a semiconductor device according to another embodiment.

[0018] Figure 18 This is a cross-sectional view showing a portion of a semiconductor device according to an embodiment.

[0019] Figure 19 This is a cross-sectional view showing a portion of a semiconductor device according to another embodiment. Detailed Implementation

[0020] Embodiments of this disclosure will be described more fully below with reference to the accompanying drawings to enable those skilled in the art to readily practice this disclosure. This disclosure may be implemented in various different forms and is not limited to the embodiments provided herein.

[0021] Parts unrelated to the description have been omitted in order to clearly describe this disclosure, and throughout this specification, the same or similar parts are indicated by the same reference numerals.

[0022] Furthermore, since the dimensions and / or thicknesses of the parts, regions, components, units, layers, films, substrates, etc. shown in the accompanying drawings may be arbitrarily shown for better understanding and ease of illustration, this disclosure is not limited to the dimensions and / or thicknesses shown. In the accompanying drawings, the thicknesses of parts, regions, components, units, layers, films, substrates, etc., may be enlarged or exaggerated for ease of illustration and / or simplicity.

[0023] It will be understood that when a component, such as a part, region, structure, unit, layer, film, substrate, etc., is referred to as being "on" another component, it can be directly on the other component, or there may be an intermediate component. In contrast, when a component is referred to as being "directly on" another component, there is no intermediate component. Furthermore, when a component is referred to as being "on" or "above" a reference component, the component can be positioned on or below the reference component, and not necessarily "on" or "above" the reference component in the opposite direction of gravity.

[0024] Furthermore, throughout this specification, unless explicitly stated otherwise, the words “comprising,” “including,” or “containing,” and variations such as “including,” “comprising,” “containing,” “containing,” or “comprising” will be understood to imply the inclusion of other components, rather than the exclusion of any other components. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms. The term “and / or” includes any and all combinations of one or more related enumerated items. The term “connection” may be used herein to refer to a physical connection and / or an electrical connection, and may refer to a direct or indirect physical connection and / or electrical connection. The term “exposed” may be used to define the relationship between a particular layer or surface, but does not require that layer or surface be free of other elements or layers in the finished device. When viewed along a line extending in a particular direction or in a plane perpendicular to a particular direction, components or layers described with reference to “overlapping” in a particular direction may at least partially obscure each other. The terms “first,” “second,” etc., may be used herein simply to distinguish one component, element, etc., from another component, element, etc.

[0025] Furthermore, throughout the specification, the phrases “in a plane,” “in a plane,” “in a top view,” or “in a top view” can indicate the view of a portion from above or at the top, and the phrases “in a section” or “in a section view” can indicate the view of a section taken along the vertical direction from the side.

[0026] In the following text, see references Figures 1 to 12 The semiconductor device and its manufacturing method according to the embodiments will be described in detail.

[0027] Figure 1 This is a cross-sectional view showing a semiconductor device 100 according to an embodiment.

[0028] refer to Figure 1 The semiconductor device 100 according to an embodiment may include a semiconductor element portion 10, a first wiring portion 20, a support substrate 40, an intermediate layer (e.g., a bonding layer 30), and a second wiring portion 50. The semiconductor element portion 10 may include a semiconductor element 110. The first wiring portion 20 may be disposed on a first surface 101 of the semiconductor element portion 10. The support substrate 40 may be disposed on the first wiring portion 20. The intermediate layer (e.g., the bonding layer 30) may be disposed between the first wiring portion 20 and the support substrate 40. The second wiring portion 50 may be disposed on a second surface 102 of the semiconductor element portion 10, the second surface 102 of the semiconductor element portion 10 being opposite to the first surface 101 of the semiconductor element portion 10. The semiconductor device 100 according to an embodiment may further include a connection bump 60 electrically connected to the second wiring portion 50.

[0029] For example, the first surface 101 of the semiconductor element portion 10 may be the front surface or the upper surface of the semiconductor element portion 10, while the second surface 102 of the semiconductor element portion 10 may be the rear surface or the lower surface of the semiconductor element portion 10. The first wiring portion 20 may be referred to as the front wiring portion, while the second wiring portion 50 may be referred to as the rear wiring portion.

[0030] In an embodiment, the semiconductor element portion 10 may include any of a variety of semiconductor elements 110. Figure 1 In its description, semiconductor element 110 is shown and described by way of example as a transistor and semiconductor element portion 10 includes the transistor. In embodiments, multiple semiconductor elements 110 (e.g., multiple transistors) may be included, and multiple semiconductor elements 110 (e.g., multiple transistors) may be individually or in combination with other elements to form various logic elements, such as AND elements, OR elements, NOR elements, inverters, etc.

[0031] However, the embodiments are not limited thereto. Semiconductor element 110 may include not only active elements (such as transistors) but also passive elements such as capacitors, resistors, inductors, etc. In some embodiments, semiconductor element 110 included in semiconductor element portion 10 may be formed into elements other than logic elements. Various other modifications are possible.

[0032] In the embodiments, the semiconductor element 110 of the transistor can have any of a variety of structures. For example, the semiconductor element 110 can be a field-effect transistor (FET) with a three-dimensional structure, such as a fin structure, a gate-all-around (GAA) structure, or a multi-bridge channel (MBC) structure. When the semiconductor element 110 has a three-dimensional structure, leakage current can be reduced and excellent performance can be achieved. However, the embodiments are not limited to this, and the semiconductor element 110 can be formed from a transistor having a structure other than those described above.

[0033] For example, semiconductor element 110 may include an active region 120, a gate structure 130, source and drain patterns 140, and an upper insulating layer 150.

[0034] The active region 120 may include a semiconductor layer, a semiconductor region, and / or a semiconductor substrate having or formed of a semiconductor material. The portion of the active region 120 that overlaps with the gate structure 130 may form the channel region of the semiconductor element 110.

[0035] In an embodiment, the active region 120 may include a plurality of channel layers 122. The plurality of channel layers 122 may be spaced apart from each other in the thickness direction (Z-axis direction in the figures) of the semiconductor device 100. For example, the thickness direction may be perpendicular to the first surface of the supporting substrate 40. The plurality of channel layers 122 may be spaced apart from each other at fixed intervals in a first direction (X-axis direction in the figures) and a second direction (Y-axis direction in the figures). For example, the first direction and / or the second direction may be parallel to the first surface of the supporting substrate 40.

[0036] Each of the plurality of channel layers 122 may include a channel pattern having a nanosheet shape with a thickness on the nanometer scale (e.g., less than 1 µm, for example, 1 nm to 10 nm). The channel pattern of the channel layer 122 may include a semiconductor material or a semiconductor pattern formed of a semiconductor material. However, the embodiments are not limited thereto, and the shapes of the plurality of channel layers 122 may be modified differently, and / or the thickness of the channel layer 122 may be less than 1 nm or may be greater than 10 nm.

[0037] The channel layer 122 may include an epitaxial layer having a semiconductor material or formed of a semiconductor material. For example, the channel layer 122 may include at least one of group IV semiconductors, group III-V compound semiconductors, or group II-VI compound semiconductors, or be formed of at least one of group IV semiconductors, group III-V compound semiconductors, or group II-VI compound semiconductors. For example, the channel layer 122 may include at least one of Si, Ge, SiGe, SiC, GaAs, InAs, or InP (e.g., Si, Ge, or SiGe) or be formed of at least one of Si, Ge, SiGe, SiC, GaAs, InAs, or InP (e.g., Si, Ge, or SiGe).

[0038] exist Figure 1 In the illustration, an active region 120 is shown as including a plurality of channel layers 122. In some embodiments, the active region 120 may further include a lower pattern. The lower pattern may be disposed at the lower portion of the plurality of channel layers 122 adjacent to the second wiring portion 50. (Reference: After removing the semiconductor substrate 10p...) Figure 4 In at least a portion of the process of the semiconductor substrate 10p, a portion may be left to form a lower pattern. Multiple lower patterns may be spaced apart from each other at fixed intervals in a first direction (X-axis direction in the figures). The lower patterns may have a shape extending longitudinally in a second direction (Y-axis direction in the figures), or may include multiple portions spaced apart from each other at fixed intervals in the second direction. The lower patterns may include the same material as the channel layer 122, or may include a material different from the material of the channel layer 122.

[0039] In embodiments, the shape or material of portions included in the active region 120 (e.g., channel layer 122 or underpattern), the number of channel layers 122, etc., can be modified differently.

[0040] A gate structure 130 may be disposed on the active region 120. The gate structure 130 may extend in a second direction (the Y-axis direction in the figure). A plurality of gate structures 130 may be spaced apart from each other in a first direction (the X-axis direction in the figure).

[0041] The gate structure 130 may include a gate electrode 132, a gate insulating layer 134, a gate spacer 136, and a gate capping layer 138.

[0042] The gate electrode 132 may completely (or at least partially) surround each of the plurality of channel layers 122 and may be disposed on the active region 120 including the plurality of channel layers 122. The gate electrode 132 may extend in a second direction (the Y-axis direction in the figures). In some embodiments, a gate separation portion may be included, such that the gate electrode 132 includes a plurality of portions spaced apart from each other in the second direction.

[0043] A gate insulating layer 134 may be disposed between the gate electrode 132 and the channel layer 122. Between the plurality of channel layers 122, the gate insulating layer 134 may be disposed on the upper surface, lower surface, and two surfaces in a first direction (the X-axis direction in the figures) of the gate electrode 132. On the active region 120 including the plurality of channel layers 122, the gate insulating layer 134 may include a portion disposed between the active region 120 and the gate electrode 132, and a portion disposed between the gate electrode 132 and the gate spacer 136.

[0044] In some embodiments, internal spacers may be provided between the portions of the plurality of channel layers 122 where the gate electrode 132 and the gate insulating layer 134 are disposed and the source and drain patterns 140. The internal spacers may include or be formed of an insulating material. The internal spacers may include the same material as the gate spacer 136, or may include a different material than the gate spacer 136.

[0045] In the active region 120, a gate spacer 136 may be disposed on the side surface of the gate electrode 132. For example, in the active region 120, the gate spacer 136 may be disposed on the gate insulating layer 134 on the side surface of the gate electrode 132. The gate spacer 136 may electrically insulate the gate electrode 132 from the source and drain patterns 140 and / or electrically insulate the gate electrode 132 from the first connection contact portion 24. The gate spacer 136 may extend in a second direction (the Y-axis direction in the figure) on both side surfaces of the gate electrode 132 in a first direction (the X-axis direction in the figure).

[0046] The gate capping layer 138 can be disposed on the upper surface of the gate electrode 132 disposed on the active region 120. Figure 1 In the illustration, a gate spacer 136 is shown disposed on a side surface of the gate capping layer 138, but the embodiment is not limited thereto. In some embodiments, the gate capping layer 138 may be disposed on the gate spacer 136. In an embodiment, the upper surface of the gate capping layer 138 may be disposed on the same plane as the upper surface of the upper insulating layer 150 (e.g., the upper surface of the gate capping layer 138 and the upper surface of the upper insulating layer 150 are coplanar). However, the embodiment is not limited thereto, and the upper surface of the gate capping layer 138 may be disposed on a different plane from the upper surface of the upper insulating layer 150.

[0047] The gate electrode 132 may include or be formed of a conductive material. For example, the gate electrode 132 may include at least one of a metal, metal alloy, metal nitride, metal silicide, or doped semiconductor material, or be formed of at least one of a metal, metal alloy, metal nitride, metal silicide, or doped semiconductor material. The metal, metal alloy, metal nitride, or metal silicide included in the gate electrode 132 may include at least one of copper, aluminum, tungsten, molybdenum, titanium, tantalum, nickel, gold, tin, manganese, or cobalt, or be formed of at least one of copper, aluminum, tungsten, molybdenum, titanium, tantalum, nickel, gold, tin, manganese, or cobalt. The doped semiconductor material may be doped with an n-type dopant or a p-type dopant. For example, the doped semiconductor material may be a polycrystalline semiconductor material doped with an n-type dopant or a p-type dopant. The gate electrode 132 may also include a metal oxide or metal nitride in which the above-mentioned materials are oxidized. The gate electrode 132 may include a single layer or may include multiple electrode layers.

[0048] The gate insulating layer 134 may include, or be formed of, an oxide, nitride, or a high-dielectric-constant material. The high-dielectric-constant material may have a dielectric constant higher than that of silicon oxide (SiO2). x The dielectric material has a dielectric constant of . For example, the gate insulating layer 134 may include silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon oxynitride (SiON) x ), hafnium oxide (HfO) x ), aluminum oxide (AlO) x ) or tantalum oxide (TaO) x At least one of the following or made of silicon dioxide (SiO2) x Silicon nitride (SiN) x ), silicon oxynitride (SiON) x ), hafnium oxide (HfO) x ), aluminum oxide (AlO)x ) or tantalum oxide (TaO) x At least one of the following can be formed: gate insulating layer 134 may include a single layer or may include multiple insulating layers.

[0049] Gate spacer 136 may include silicon oxide (SiO2). x Silicon nitride (SiN) x ) or silicon oxynitride (SiON) x At least one of the above materials or a material comprising carbon, or made of silicon dioxide (SiO2). x Silicon nitride (SiN) x ) or silicon oxynitride (SiON) x It is formed of at least one of the above materials or a material including carbon. For example, the gate spacer 136 may include or be formed of a low-dielectric-constant material. The gate spacer 136 may include a single layer or may include multiple layers. The gate capping layer 138 may include silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon oxynitride (SiON) x ), silicon carbide (SiCN) x ) or silicon dioxide (SiOCN) x At least one of the following or made of silicon dioxide (SiO2) x Silicon nitride (SiN) x ), silicon oxynitride (SiON) x ), silicon carbide (SiCN) x ) or silicon dioxide (SiOCN) x At least one of the following is formed: The gate capping layer 138 may include a single layer or may include multiple layers.

[0050] However, the embodiments are not limited thereto, and the gate electrode 132, gate insulating layer 134, gate spacer 136 or gate capping layer 138 may have any of a variety of structures, or may include any of a variety of materials or be formed of any of a variety of materials.

[0051] The source and drain patterns 140 can be disposed on both sides of the active region 120 and / or the gate structure 130. For example, the source and drain patterns 140 can be configured to be adjacent to both sides of the active region 120 in a first direction (the X-axis direction in the figures). The source and drain patterns 140 can form the source and drain regions of the semiconductor element 110.

[0052] The source and drain patterns 140 may include or be formed from an epitaxial layer formed by a selective epitaxial growth (SEG) process at a portion of the active region 120 where a portion has been removed. The source and drain patterns 140 may have angular shapes, but embodiments are not limited thereto. The source and drain patterns 140 may have any of a variety of shapes such as polygonal, circular, elliptical, or rounded shapes.

[0053] For example, the source and drain patterns 140 may include at least one of Si, SiGe, or SiC, or be formed from at least one of Si, SiGe, or SiC, and may also include dopants such as arsenic (As) or phosphorus (P). In some embodiments, the source and drain patterns 140 may include multiple portions with different materials or different compositions. However, the embodiments are not limited thereto, and the source and drain patterns 140 may include any of a variety of materials or have any of a variety of structures.

[0054] The upper insulating layer 150 may cover the source and drain patterns 140 outside the gate spacer 136 or be located on the source and drain patterns 140. At least a portion of the upper insulating layer 150 may be formed prior to the process of forming the source and drain patterns 140, and the source and drain patterns 140 may be grown and formed in the space defined by the upper insulating layer 150. However, embodiments are not limited thereto, and the manufacturing order of the source and drain patterns 140 and the upper insulating layer 150 may be modified differently.

[0055] For example, the upper insulating layer 150 may include silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon oxynitride (SiON) x At least one of the following: or a low dielectric constant material, or made of silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon oxynitride (SiON) x The upper insulating layer 150 may be formed from at least one of the following materials: a low dielectric constant material or a high dielectric constant material. However, the embodiments are not limited thereto, and the upper insulating layer 150 may include any of a variety of materials. The upper insulating layer 150 may include a single layer or may include multiple layers. In an embodiment, an etch stop layer may be further provided between the source and drain patterns 140 and the upper insulating layer 150. In an embodiment, at least a portion of the upper insulating layer 150 may be formed from the front insulating layer 22.

[0056] The first wiring portion 20 may be disposed on the first surface 101 of the semiconductor element portion 10. For example, the first wiring portion 20 may be disposed on the gate structure 130 and the upper insulating layer 150 disposed on the source and drain patterns 140. The first wiring portion 20 may be a signal wiring portion disposed on the first surface 101 of the semiconductor element portion 10 and transmitting signals to the semiconductor element 110.

[0057] The first wiring portion 20 may include a front insulating layer 22, a first connecting contact portion 24, a first interlayer insulating layer 26, a first wiring layer 28, and a first contact path 29.

[0058] The front insulating layer 22 may be disposed on the upper surface of the gate structure 130 and the upper surface of the upper insulating layer 150 disposed on the source and drain patterns 140. The first connection contact portion 24 may include a gate connection contact portion and a drain connection contact portion. The gate connection contact portion may pass through, extend to, or penetrate the front insulating layer 22 and the gate capping layer 138 to be electrically connected to the gate electrode 132 (e.g., in direct contact with it). The drain connection contact portion may pass through, extend to, or penetrate the front insulating layer 22 and the upper insulating layer 150 to be electrically connected to the drain pattern 140d (e.g., in direct contact with it). In some embodiments, the first connection contact portion 24 may further include a source connection contact portion. The source connection contact portion may pass through, extend to, or penetrate the front insulating layer 22 and the upper insulating layer 150 to be electrically connected to the source pattern 140s (e.g., in direct contact with it).

[0059] exist Figure 1 In the illustration, source and drain patterns 140 of a plurality of semiconductor elements 110 are arranged as an example, having a drain pattern 140d, a source pattern 140s, and a drain pattern 140d, and a first connection contact portion 24 includes a gate connection contact portion, a drain connection contact portion, and a source connection contact portion. When the first connection contact portion 24 may include a source connection contact portion, power can be supplied to the upper surface of the source pattern 140, and the freedom of circuit design can be increased. However, the embodiment is not limited thereto. The first connection contact portion 24 may include a gate connection contact portion and a drain connection contact portion, and may not include a source connection contact portion. The arrangement of the source and drain patterns 140 of the plurality of semiconductor elements 110 can be modified differently.

[0060] The first interlayer insulating layer 26 and the first wiring layer 28 can be disposed on the front insulating layer 22 and the first connection contact portion 24. For example, a plurality of first wiring layers 28 may be spaced apart from each other by the first interlayer insulating layer 26 and may be electrically connected to each other by a first contact passage 29 passing through, extending to, or penetrating the first interlayer insulating layer 26. The first contact passage 29 may be formed in the same process as the first wiring layers 28, or may be formed in a different process than the process in which the first wiring layers 28 are formed. One of the plurality of first wiring layers 28 adjacent to the first connection contact portion 24 may be electrically connected to (e.g., in direct contact with) the first connection contact portion 24. Through the first connection contact portion 24, the first wiring layers 28, and the first contact passage 29, the first wiring portion 20 may be connected to form a desired path for transmitting signals to the semiconductor element 110. For example, the first connection contact portion 24, the first wiring layers 28, and the first contact passage 29 may form front signal wiring for transmitting signals to the semiconductor element 110.

[0061] The first connection contact portion 24, the first wiring layer 28, and / or the first contact path 29 may include or be formed of a conductive material. At least two of the first connection contact portion 24, the plurality of first wiring layers 28, and the first contact path 29 may include the same material or may include different materials. The first connection contact portion 24 and / or the first wiring layer 28 may include a single layer or may include multiple layers.

[0062] For example, the first connection contact portion 24, the first wiring layer 28, and / or the first contact passage 29 may include at least one of copper, aluminum, tungsten, molybdenum, titanium, tantalum, nickel, gold, tin, manganese, or cobalt, or be formed from at least one of copper, aluminum, tungsten, molybdenum, titanium, tantalum, nickel, gold, tin, manganese, or cobalt, or include an alloy having the above materials or be formed from an alloy having the above materials. The front insulating layer 22 or the first interlayer insulating layer 26 may include any one of a variety of insulating materials or be formed from any one of a variety of insulating materials to electrically insulate the first wiring layers 28 that are not electrically connected to each other.

[0063] A support substrate 40 may be disposed on the first wiring portion 20. In the process of forming the second wiring portion 50, the support substrate 40 may mechanically or structurally support the semiconductor element portion 10 and the first wiring portion 20. The support substrate 40 may be referred to as a holding substrate, a disposal substrate, a carrier substrate, etc.

[0064] In this embodiment, the support substrate 40 may be a semiconductor substrate comprising or formed of a semiconductor material. For example, the support substrate 40 may be a semiconductor substrate formed of a semiconductor material, or a semiconductor substrate comprising a base substrate and a semiconductor layer formed on the base substrate. For example, the support substrate 40 may include a single-crystal or polycrystalline semiconductor (e.g., Si, Ge, or SiGe) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, or be formed of a single-crystal or polycrystalline semiconductor (e.g., Si, Ge, or SiGe) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. For example, the support substrate 40 may be a silicon substrate.

[0065] An intermediate layer may be disposed between the first wiring portion 20 and the support substrate 40. For example, the intermediate layer may be a bonding layer 30 that joins the first wiring portion 20 and the support substrate 40. The intermediate layer may be referred to as an intermediate insertion layer, insertion layer, intervention layer, etc. The bonding layer 30 will be described in more detail later.

[0066] The second wiring portion 50 may be disposed on the second surface 102 of the semiconductor element portion 10. The second wiring portion 50 may be a power wiring portion disposed on the second surface 102 of the semiconductor element portion 10 and transmitting power to the semiconductor element 110. The second wiring portion 50 may be referred to as a rear-side power distribution network or a rear-side power distribution network (BSPDN).

[0067] The second wiring portion 50 may include a rear insulating layer 52, a second connection contact portion 54, a second interlayer insulating layer 56, a second wiring layer 58, and a second contact passage 59.

[0068] The rear insulating layer 52 may be disposed on the lower surfaces of the gate structure 130 and the active region 120, as well as on the lower surfaces of the source and drain patterns 140. The second connection contact portion 54 may include a source connection contact portion. The source connection contact portion may pass through, extend into, or penetrate the rear insulating layer 52 to be electrically connected to (e.g., in direct contact with) the source pattern 140s.

[0069] A second interlayer insulating layer 56 and a second wiring layer 58 may be disposed on a rear insulating layer 52 and a second connection contact portion 54. A plurality of second wiring layers 58 may be spaced apart from each other by the second interlayer insulating layer 56 and may be electrically connected to each other by a second contact passage 59 passing through, extending into, or penetrating the second interlayer insulating layer 56. The second contact passage 59 may be formed in the same process as the second wiring layers 58, or may be formed in a different process than that used to form the second wiring layers 58. One of the plurality of second wiring layers 58 adjacent to the second connection contact portion 54 may be electrically connected to (e.g., in direct contact with) the second connection contact portion 54. The second wiring portion 50 may be connected to have a desired path for transmitting power to the semiconductor element 110 via the second connection contact portion 54, the second wiring layers 58, and the second contact passage 59. For example, the second connection contact portion 54, the plurality of second wiring layers 58, and the second contact passage 59 may form a rear power wiring for transmitting power to the semiconductor element 110.

[0070] The outermost wiring layer among the plurality of second wiring layers 58 may include pads 58p. Pads 58p may be bonding pads disposed on the lower surface of the second wiring portion 50 and electrically connected to the connecting bump 60, external circuitry, etc.

[0071] The second connection contact portion 54, the second wiring layer 58, and / or the second contact passage 59 may include or be formed of a conductive material. At least two of the second connection contact portion 54, the plurality of second wiring layers 58, and the second contact passage 59 may include the same material or may include different materials. The second connection contact portion 54 and / or the second wiring layer 58 may include a single layer or may include multiple layers.

[0072] For example, the second connection contact portion 54, the second wiring layer 58, and / or the second contact passage 59 may include at least one of copper, aluminum, tungsten, molybdenum, titanium, tantalum, nickel, gold, tin, manganese, or cobalt, or be formed from at least one of copper, aluminum, tungsten, molybdenum, titanium, tantalum, nickel, gold, tin, manganese, or cobalt, or include an alloy having the above materials or be formed from an alloy having the above materials. The rear insulating layer 52 or the second interlayer insulating layer 56 may include any one of a variety of insulating materials or be formed from any one of a variety of insulating materials to electrically insulate the second wiring layers 58 that are not electrically connected to each other.

[0073] exist Figure 1In the example shown, the thickness of the second wiring layer 58 is greater than the thickness of the first wiring layer 28. When the second wiring layer 58, which transmits power, has a thickness greater than the thickness of the first wiring layer 28, which transmits signals, power can be stably transmitted through the second wiring layer 58. However, the embodiment is not limited to this, and the thickness of the second wiring layer 58 may be the same as or less than the thickness of the first wiring layer 28.

[0074] The semiconductor device 100 may include wiring or structures configured to transmit signals from the second wiring portion 50 to the first wiring portion 20. In an embodiment, signals may be supplied to the first wiring portion 20 via a portion of a plurality of second wiring layers 58 and / or a portion of the semiconductor element portion 10.

[0075] For example, the second wiring portion 50 may further include signal wiring for transmitting signals other than subsequent power wiring. For example, the semiconductor element portion 10 may include through-contact portions (e.g., through-silicon vias (TSVs)) that pass through, extend into, or penetrate the semiconductor element portion 10, and the signal wiring of the second wiring portion 50 and the first wiring portion 20 may be electrically connected to each other through these through-contact portions. In some embodiments, the signal wiring of the second wiring portion 50 and the first wiring portion 20 may be electrically connected to each other through wiring, circuitry, etc., included in the semiconductor element portion 10. In some embodiments, the first wiring portion 20 may further include pads for transmitting signals to the semiconductor element portion 10. As described above, the structure for transmitting signals to the first wiring portion 20 may be modified differently.

[0076] Connecting bumps 60 can be disposed on pads 58p of the second wiring layer 58. Through connecting bumps 60, semiconductor device 100 can be fixed and electrically connected to packaging substrate, printed circuit board, interposer, semiconductor chip, semiconductor package, etc.

[0077] The connecting bump 60 may include at least one of copper, aluminum, tungsten, nickel, tin, titanium, tantalum, indium, molybdenum, manganese, cobalt, magnesium, rhenium, beryllium, gallium, or ruthenium, or be formed from at least one of copper, aluminum, tungsten, nickel, tin, titanium, tantalum, indium, molybdenum, manganese, cobalt, magnesium, rhenium, beryllium, gallium, or ruthenium, or comprise an alloy having the above materials or be formed from an alloy having the above materials. However, the embodiments are not limited thereto.

[0078] exist Figure 1 The diagram illustrates, by way of example, the structure of the semiconductor element portion 10, the first wiring portion 20, the second wiring portion 50, and the connecting bump 60; however, the embodiment is not limited thereto. Therefore, the structure and arrangement of components related to power transmission and components related to signal transmission can be modified differently depending on the type, variety, design, etc., of the semiconductor device 100.

[0079] refer to Figure 2 and Figure 3 as well as Figure 1 The intermediate layer (e.g., bonding layer 30) included in the semiconductor device 100 according to the embodiment will be described in more detail.

[0080] Figure 2 yes Figure 1 An enlarged cross-sectional view of part A in the diagram. Figure 3 It is shown Figure 1 A top view of a portion of the patterned layer 310 of the bonding layer 30 included in the semiconductor device 100 shown.

[0081] refer to Figures 1 to 3 According to the embodiment, the intermediate layer (e.g., bonding layer 30) may include a pattern layer 310. The pattern layer 310 may include a first pattern 312 and a second pattern 314. The bonding layer 30 may include a first insulating layer 320 disposed between the first wiring portion 20 and the pattern layer 310, and further includes a second insulating layer 330 disposed between the pattern layer 310 and the support substrate 40.

[0082] In an embodiment, pattern layer 310 may include a first pattern 312 and a second pattern 314. The first pattern 312 may include or be formed of an insulating material. The second pattern 314 may have a higher thermal conductivity than the first pattern 312 and may be electrically insulated from the first wiring portion 20. The second pattern 314 may include or be formed of a conductive material (e.g., a metal or metal alloy). The first pattern 312 may be an insulating pattern including or formed of an insulating material. The second pattern 314 may be a heat dissipation pattern that provides a heat dissipation path. The second pattern 314 may be a pattern that is not connected to the first wiring portion 20 and / or the second wiring portion 50 and does not contribute to electrical connection. The second pattern 314 may be referred to as a heat dissipation pattern, a conductive pattern, a metal pattern, a floating pattern, a floating conductive pattern, a floating metal pattern, a dummy pattern, a dummy conductive pattern, a dummy metal pattern, etc.

[0083] In an embodiment, the patterned layer 310 can be formed by the following operation: forming a preliminary insulating layer 310p comprising or formed of an insulating material (see reference). Figure 6 The opening 314p is formed by removing a portion of the initial insulating layer 310p (see reference). Figure 7The initial insulating layer 310p is filled or supplied with conductive material in the opening 314p. The remaining portion of the initial insulating layer 310p can form a first pattern 312, and the portion of the conductive material at least partially filled in the opening 314p can form a second pattern 314. As described above, a patterned layer 310 including the first pattern 312 and the second pattern 314 can be formed by a simple manufacturing process. The manufacturing method of the patterned layer 310 will be described in more detail later in the section on the manufacturing method of the semiconductor device 100.

[0084] In the cross-sectional view, the side surface of the second pattern 314 may have a sloping surface, such that the width of the second pattern 314 decreases toward the first wiring portion 20. This may be because, in the process of forming the opening 314p, an etching process can be performed on the surface of the initial insulating layer 310p opposite to the first wiring portion 20. However, the embodiments are not limited to this, and the side surface of the second pattern 314 may be a vertical surface and the second pattern 314 may have a substantially uniform width. Various other modifications are possible.

[0085] The first pattern 312 may include oxides, nitrides, oxynitrides, etc., or be formed of oxides, nitrides, oxynitrides, etc. For example, the first pattern 312 may include silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon oxynitride (SiON) x ) etc. or made of silicon dioxide (SiO) x Silicon nitride (SiN) x ), silicon oxynitride (SiON) x (and so on)

[0086] The second pattern 314, which includes a conductive material, may comprise a metal or a metal alloy, or be formed of a metal or a metal alloy. For example, the second pattern 314 may comprise at least one of copper, aluminum, tungsten, molybdenum, titanium, tantalum, nickel, gold, tin, manganese, or cobalt, or be formed of at least one of these materials, or may comprise an alloy having or being formed of an alloy having the aforementioned materials. When the second pattern 314 comprises a conductive material (e.g., a metal or a metal alloy), the second pattern 314 may have a relatively high thermal conductivity.

[0087] As described above, in the embodiments, the pattern layer 310 may include a first pattern 312 and a second pattern 314 disposed on the same plane or at the same height and comprising different materials (e.g., the first pattern 312 and the second pattern 314 are coplanar).

[0088] As described herein, the phrase "the first pattern 312 and the second pattern 314 are disposed in the same plane or at the same height" can mean that at least a portion of the first pattern 312 and at least a portion of the second pattern 314 are disposed at the same location in the thickness direction (Z-axis direction in the figures) of the semiconductor device 100 (e.g., the first pattern 312 and the second pattern 314 at least partially overlap each other in the X-axis direction). In some embodiments, the phrase "the first pattern 312 and the second pattern 314 are disposed in the same plane or at the same height" can mean that at least a portion of the side surface of the second pattern 314 is adjacent to (e.g., in contact with) at least a portion of the side surface of the first pattern 312, or that the first surface L1 of the first pattern 312 and the first surface L2 of the second pattern 314 can form a coplanar or continuous surface, or that the second surface S1 of the first pattern 312 and the second surface S2 of the second pattern 314 can form a coplanar or continuous surface.

[0089] In the specification, the first surface L1 of the first pattern 312 or the first surface L2 of the second pattern 314 may be a surface adjacent to the first wiring portion 20 (e.g., a surface adjacent to the first insulating layer 320). The second surface S1 of the first pattern 312 or the second surface S2 of the second pattern 314 may be opposite to the first surface L1 of the first pattern 312 or the first surface L2 of the second pattern 314, and may be a surface adjacent to the support substrate 40z (e.g., a surface adjacent to the second insulating layer 330).

[0090] The first insulating layer 320 may be disposed between the first wiring portion 20 and the pattern layer 310, and the second insulating layer 330 may be disposed between the pattern layer 310 and the support substrate 40.

[0091] The first insulating layer 320 may be at least disposed between the second pattern 314 of the pattern layer 310 and the first wiring portion 20, and may separate the second pattern 314 of the pattern layer 310 and the first wiring portion 20 to have a gap and / or electrically insulate the second pattern 314 of the pattern layer 310 and the first wiring portion 20. In the preliminary insulating layer 310p (reference...) Figure 6 An opening 314p is formed in the (reference) Figure 7 In the process of ), the first insulating layer 320 can be used as an etch stop layer. Therefore, the first insulating layer 320 can be referred to as an electrical insulating layer, an etch stop layer, etc.

[0092] In an embodiment, the first insulating layer 320 may include a portion disposed between the first pattern 312 and the first wiring portion 20 and a portion disposed between the second pattern 314 and the first wiring portion 20, and may be completely disposed between the pattern layer 310 and the first wiring portion 20.

[0093] The second insulating layer 330 may be disposed at least between the first pattern 312 of the pattern layer 310 and the support substrate 40, and physically and structurally bond the first wiring portion 20 and the support substrate 40 (e.g., the pattern layer 310 and the support substrate 40). Therefore, the second insulating layer 330 may be referred to as a bonding insulating layer. The second insulating layer 330 can be formed by insulating layer bonding, wherein the first insulating bonding portion 331 on the pattern layer 310 (refer to...) Figure 10 ) and the second insulating bonding portion 332 on the support substrate 40 (reference) Figure 10 They are joined together. This will be described in more detail later in the method of manufacturing semiconductor device 100.

[0094] In an embodiment, the second insulating layer 330 may include a portion disposed between the first pattern 312 and the support substrate 40 and a portion disposed between the second pattern 314 and the support substrate 40, and may be completely disposed between the pattern layer 310 and the support substrate 40.

[0095] The first insulating layer 320 may include an insulating material different from the insulating material of the first pattern 312, and / or the second insulating layer 330 may include an insulating material different from the insulating material of the first pattern 312. For example, the first insulating layer 320 may include an insulating material different from the insulating material of the first pattern 312 and can be stably used as an etch stop layer, and the second insulating layer 330 may include an insulating material different from the insulating material of the first pattern 312 and can be stably used as a bonding insulating layer. However, the embodiments are not limited thereto, and the first insulating layer 320 and / or the second insulating layer 330 may include the same insulating material as the first pattern 312.

[0096] For example, the first insulating layer 320 and the second insulating layer 330 may comprise the same material. Thus, the manufacturing process can be simplified by using the same or similar manufacturing processes to form the first insulating layer 320 and the second insulating layer 330.

[0097] In some embodiments, the first insulating layer 320 and the second insulating layer 330 may comprise different materials. For example, the first insulating layer 320 may comprise an insulating material with a dielectric constant lower than that of the second insulating layer 330, and this may improve the properties of the first insulating layer 320 used as an electrical insulating layer. For example, the second insulating layer 330 may comprise an insulating material with better bonding properties compared to the first insulating layer 320, and this may improve the properties of the second insulating layer 330 used as a bonding insulating layer.

[0098] However, the embodiments are not limited thereto. In some embodiments, the dielectric constant of the second insulating layer 330 may be less than that of the first insulating layer 320, and / or the first insulating layer 320 may have better bonding properties compared to the second insulating layer 330.

[0099] In embodiments, the first insulating layer 320 and / or the second insulating layer 330 may comprise or be formed of an oxide, nitride, or carbide material. For example, the first insulating layer 320 and / or the second insulating layer 330 may comprise silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon carbide (SiCN) x ), silicon dioxide (SiOC) x ), silicon oxynitride (SiON) x ), silicon dioxide (SiOCN) x ) or aluminum nitride (AlN) x At least one of the following or made of silicon dioxide (SiO2) x Silicon nitride (SiN) x ), silicon carbide (SiCN) x ), silicon dioxide (SiOC) x ), silicon oxynitride (SiON) x ), silicon dioxide (SiOCN) x ) or aluminum nitride (AlN) x At least one of the following is formed. In an embodiment, the first insulating layer 320 and the second insulating layer 330 may comprise the same material, such as silicon carbide (SiCN). x For example, the first insulating layer 320 may include a material with a dielectric constant less than that of the first pattern 312, and may improve the properties of the first insulating layer 320 used as an electrical insulating layer. However, embodiments are not limited to the materials of the first insulating layer 320 and / or the second insulating layer 330.

[0100] In an embodiment, the second pattern 314 included in the patterned layer 310 of the bonding layer 30 may have high thermal conductivity, thereby improving the effective thermal conductivity of the bonding layer 30 and forming a heat dissipation path through the second pattern 314.

[0101] The bonding layer 30 may be an intermediate layer disposed between the first wiring portion 20 and the support substrate 40. If the thermal conductivity of the bonding layer 30 is low, the heat flow through the bonding layer 30 will be degraded or suppressed. In an embodiment, even if the second pattern 314 is spaced from the first wiring portion 20 and / or the support substrate 40 by the first insulating layer 320 and / or the second insulating layer 330, heat can still be easily dissipated through thermal conduction via the thin first insulating layer 320 and / or the second insulating layer 330 through or to the second pattern 314. That is, the second pattern 314 disposed between the first insulating layer 320 and the second insulating layer 330 can form a heat dissipation path for heat to dissipate in the direction toward the support substrate 40.

[0102] More specifically, the semiconductor element portion 10 and / or the first wiring portion 20 may generate a relatively large amount of heat during operation of the semiconductor device 100. The second pattern 314 can form a heat dissipation path when the heat generated at the semiconductor element portion 10 and / or the first wiring portion 20 can dissipate to the support substrate 40 through the first wiring portion 20 and the bonding layer 30. The support substrate 40 may have a relatively large thickness. Therefore, when a heat dissipation path toward the support substrate 40 is provided, heat can be effectively dissipated through the support substrate 40. For reference, the first wiring layer 28 of the first wiring portion 20 may have a smaller thickness than the second wiring layer 58 of the second wiring portion 50, and a relatively large amount of heat may be generated at the first wiring portion 20, but the embodiments are not limited thereto.

[0103] As described above, in this embodiment, a heat dissipation path can be provided in the direction toward the support substrate 40, achieving improved heat dissipation characteristics compared to a comparative example where heat dissipates only along a path toward the second wiring portion and / or the connecting bumps. Furthermore, the bonding layer 30 can be formed using a relatively simple manufacturing process.

[0104] In an embodiment, the second pattern 314 can be electrically insulated from the first wiring portion 20, the semiconductor element portion 10, and / or the second wiring portion 50 via the first insulating layer 320. Therefore, the second pattern 314 can have any of a variety of structures, simplifying the structure of the first wiring portion 20, the semiconductor element portion 10, and / or the second wiring portion 50 and increasing design freedom. That is, heat dissipation characteristics can be improved without increasing the wiring paths and resistance of the first wiring portion 20, the semiconductor element portion 10, and / or the second wiring portion 50.

[0105] On the other hand, in a comparative example where the heat dissipation pattern is electrically connected to the first wiring portion, the semiconductor element portion, the second wiring portion, and / or the connecting bumps, the first wiring portion, the semiconductor element portion, and / or the second wiring portion may include additional wiring or structures connected to the heat dissipation pattern, and the number of connecting bumps may increase. Therefore, the structure or arrangement of the first wiring portion, the semiconductor element portion, the second wiring portion, and / or the connecting bumps may become more complex, or the design freedom may be degraded or reduced. That is, the wiring path, the resistance of the wiring, etc., may increase.

[0106] In this embodiment, a second pattern 314 comprising conductive material can be partially formed in the top view, reducing the cost of the process for forming the patterned layer 310. A first pattern 312 comprising insulating material and having stable connection characteristics with the first insulating layer 320 and / or the second insulating layer 330 can be disposed around the periphery (e.g., edge, side, or end) of the second pattern 314. The patterned layer 310 comprising the second pattern 314 can have stable connection characteristics with the first insulating layer 320 and / or the second insulating layer 330. Therefore, the structural stability of the bonding layer 30 can be improved.

[0107] In an embodiment, the pattern layer 310 may be disposed between the first insulating layer 320 and the second insulating layer 330 to have a sandwich structure. The pattern layer 310 may be spaced apart and / or electrically insulated from the first wiring portion 20 by the first insulating layer 320, and may be spaced apart and / or electrically insulated from the support substrate 40 by the second insulating layer 330 and stably bonded to the support substrate 40.

[0108] In this embodiment, the thickness of the pattern layer 310 may be greater than the thickness T3 of the first insulating layer 320, and / or may be greater than the thickness T4 of the second insulating layer 330. More specifically, the thickness T1 of the first pattern 312 may be greater than the thickness T3 of the first insulating layer 320, and / or may be greater than the thickness T4 of the second insulating layer 330. The thickness T2 of the second pattern 314 may be greater than the thickness T3 of the first insulating layer 320, and / or may be greater than the thickness T4 of the second insulating layer 330. The thicknesses T1 of the first pattern 312, T2 of the second pattern 314, T3 of the first insulating layer 320, or T4 of the second insulating layer 330 may refer to the thickness in the thickness direction (Z-axis direction in the figures) of the semiconductor device 100, such as the maximum thickness.

[0109] Therefore, a patterned layer 310 including a first pattern 312 and a second pattern 314 can be stably formed. However, the embodiments are not limited thereto. The thickness T1 of the first pattern 312 may be substantially the same as or less than the thickness T3 of the first insulating layer 320, and / or may be substantially the same as or less than the thickness T4 of the second insulating layer 330. The thickness T2 of the second pattern 314 may be substantially the same as or less than the thickness T3 of the first insulating layer 320, and / or may be substantially the same as or less than the thickness T4 of the second insulating layer 330.

[0110] In a top view, the area of ​​the first pattern 312 can be larger than the area of ​​the second pattern 314. For example, in a top view, the ratio of the area of ​​the second pattern 314 to the total area of ​​the first pattern 312 and the second pattern 314 can be 10% or greater (e.g., 20% or greater, 30% or greater as an example) and less than 50%. The second pattern 314 can have a relatively small area as described above, and therefore, the time and cost of forming the second pattern 314 can be reduced. However, the embodiments are not limited to this. In a top view, the area of ​​the first pattern 312 can be the same as or smaller than the area of ​​the second pattern 314.

[0111] The thickness T3 of the first insulating layer 320 can be the same as or greater than the thickness T4 of the second insulating layer 330. When the thickness T3 of the first insulating layer 320 is the same as the thickness T4 of the second insulating layer 330, the first insulating layer 320 and the second insulating layer 330 can be formed under the same process conditions, thereby simplifying the manufacturing process. When the thickness T3 of the first insulating layer 320 is greater than the thickness T4 of the second insulating layer 330, the pattern layer 310 including the second pattern 314 and the first wiring portion 20 can be stably electrically insulated from each other. However, the embodiments are not limited to this, and the thickness T3 of the first insulating layer 320 can be less than the thickness T4 of the second insulating layer 330.

[0112] In the thickness direction (Z-axis direction in the figures) of the semiconductor device 100, the ratio (W / T2) of the width W of the second pattern 314 to the thickness T2 of the second pattern 314 can be 0.5 or greater. The width W of the second pattern 314 can be the line width perpendicular to the extension direction of the second pattern 314 in the top view. For example, when the second pattern 314 has a line shape (e.g., as shown in the figure), the width W can be the line width. Figure 3 When the second pattern 314 has a line shape or strip shape (as shown), the width W can refer to the line width of the line shape, such as the maximum width. For example, when the second pattern 314 has a closed shape (e.g., as shown), the width W can refer to the line width of the line shape, such as the maximum width. Figure 15 or Figure 16When the island shape is shown, the width W of the second pattern 314 can refer to the length. In some embodiments, when the second pattern 314 has a closed shape (e.g., as shown in the image), the width W can refer to the length. Figure 17 When referring to the grid shape shown, the width W of the second pattern 314 can refer to the line width of the extended portion, such as the maximum width.

[0113] When the ratio (W / T2) of the width W of the second pattern 314 to the thickness T2 of the second pattern 314 is 0.5 or greater, the second pattern 314 can have a relatively small thickness T2, and the total length of the heat dissipation path can be reduced, while ensuring that the area of ​​the second pattern 314 reaches a certain level or greater. Therefore, heat dissipation characteristics can be improved. For example, the ratio (W / T2) of the width W of the second pattern 314 to the thickness T2 of the second pattern 314 can be 1 or greater. That is, the width W of the second pattern 314 can be the same as or greater than the thickness T2 of the second pattern 314. However, the embodiments are not limited to this. In some embodiments, the width W of the second pattern 314 can be less than the thickness T2 of the second pattern 314, or the ratio (W / T2) of the width W of the second pattern 314 to the thickness T2 of the second pattern 314 can be less than 0.5.

[0114] In an embodiment, at least a partial portion of the second surface S2 of the second pattern 314 may include a portion protruding or extending from the second surface S1 of the first pattern 312 toward the support substrate 40 (e.g., the second insulating layer 330). Therefore, the thickness (e.g., average thickness) of the portion of the second insulating layer 330 disposed between the second pattern 314 and the support substrate 40 can be less than the thickness (e.g., average thickness) of the portion of the second insulating layer 330 disposed between the first pattern 312 and the support substrate 40. Therefore, the distance between the second pattern 314 and the support substrate 40 can be reduced, and the areas of the second pattern 314 and the support substrate 40 facing each other can be increased. Therefore, the heat dissipation characteristics through the second pattern 314 can be improved.

[0115] exist Figure 1 and Figure 2In the example shown, each of the second surface S1 of the first pattern 312 and the second surface S2 of the second pattern 314 has a flat surface, and a step ST is provided between the second surface S1 of the first pattern 312 and the second surface S2 of the second pattern 314. Furthermore, as an example, the first surface L1 of the first pattern 312 and the first surface L2 of the second pattern 314 have flat surfaces, and the first surface L1 of the first pattern 312 and the first surface L2 of the second pattern 314 can be arranged on the same plane without a step. However, the embodiment is not limited to this, and the shape, arrangement, etc., of the second surface S1 of the first pattern 312, the second surface S2 of the second pattern 314, the first surface L1 of the first pattern 312, or the first surface L2 of the second pattern 314 can be modified differently. Reference will be made later. Figure 13 and Figure 14 Other embodiments are described, including the second surface S1 of the first pattern 312 and the second surface S2 of the second pattern 314.

[0116] In embodiments, the second pattern 314 can have any of a variety of planar shapes. For example, the second pattern 314 can be as follows: Figure 3 The pattern shown is a strip shape having a linear shape or including portions of a linear shape. Therefore, the second pattern 314 can be stably topographically formed into an area with a certain level or larger. Figure 3 In the illustration, as an example, an entire portion of the second pattern 314 extends in one direction and has a consistent line width. However, the embodiment is not limited to this, and the second pattern 314 may include width-changing portions, or may include portions extending in different directions. Figure 3 The example shown contains multiple second patterns 314 with the same width, but multiple second patterns 314 with different widths may be included. Various other modifications are possible.

[0117] According to an embodiment, an intermediate layer (e.g., a bonding layer 30 configured to join the first wiring portion 20 and the support substrate 40) disposed between the first wiring portion 20 and the support substrate 40 may include a heat dissipation pattern (e.g., a second pattern 314), which can improve the effective thermal conductivity of the intermediate layer (e.g., the bonding layer 30) and form a heat dissipation path toward the support substrate 40. Therefore, the heat dissipation characteristics of the semiconductor device 100 can be improved with a simple structure. Since the heat dissipation pattern (e.g., the second pattern 314) can be electrically insulated from the first wiring portion 20, the heat dissipation characteristics can be improved without increasing the wiring path and resistance of the first wiring portion 20. Therefore, the performance and reliability of the semiconductor device 100 can be improved.

[0118] The first pattern 312 may also be included around the second pattern 314, which can reduce the process cost of forming an intermediate layer (e.g., bonding layer 30) including the second pattern 314 and improve the structural stability of the intermediate layer (e.g., bonding layer 30). Since the pattern layer 310 including the first pattern 312 and the second pattern 314 is disposed between the first insulating layer 320 and the second insulating layer 330 in the intermediate layer (e.g., bonding layer 30), the pattern layer 310 can be stably bonded to the support substrate 40 in a state where the pattern layer 310 is spaced apart from and / or electrically insulated from the first wiring portion 20 and the support substrate 40.

[0119] refer to Figures 4 to 12 The method of manufacturing the semiconductor device 100 according to the embodiments will be described in detail.

[0120] Figures 4 to 12 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device 100 according to an embodiment.

[0121] like Figure 4 As shown, a semiconductor element portion 10 can be formed on a semiconductor substrate 10p.

[0122] Semiconductor substrate 10p may be a semiconductor substrate comprising or formed of semiconductor material. For example, semiconductor substrate 10p may be a semiconductor substrate formed of semiconductor material, or a semiconductor substrate comprising a base substrate and a semiconductor layer formed on the base substrate. For example, semiconductor substrate 10p may include a single-crystal or polycrystalline semiconductor (such as Si, Ge, or SiGe) substrate, a silicon-on-insulator (SiO2) substrate, or a germanium-on-insulator (CHI) substrate, or be formed from a single-crystal or polycrystalline semiconductor (such as SiO2, Ge, or SiGe) substrate, a SiO2 substrate, or a CHI substrate. For example, semiconductor substrate 10p may be a silicon substrate.

[0123] The process of forming a transistor (i.e., semiconductor element 110 included in semiconductor element portion 10) will be described simply.

[0124] First, a stacked structure in which multiple channel layers 122 and multiple sacrificial layers are alternately stacked can be formed on the semiconductor substrate 10p. For example, the multiple channel layers 122 and multiple sacrificial layers can be formed by an epitaxial growth process. The sacrificial layers can be removed in a subsequent process to provide space for the gate insulating layer 134 and the gate electrode 132. The sacrificial layer can include a material that is etch-selective relative to the etch material used to etch the channel layer 122, or is formed of a material that is etch-selective relative to the etch material used to etch the channel layer 122. For example, the channel layer 122 can include or be formed of Si, and the sacrificial layer can include or be formed of SiGe.

[0125] A dummy gate can be formed on the active region 120. In subsequent processes, the dummy gate can be replaced by the gate insulating layer 134 and the gate electrode 132. For example, the dummy gate may include or be formed of polysilicon (Si). In some embodiments, gate spacers 136 may be further formed on both sides of the dummy gate.

[0126] The active region 120 can be etched using an etching process that uses a dummy gate and / or gate spacer 136 as a mask. At the etched portions of the active region 120, source and drain patterns 140 can be formed from the upper surface of the semiconductor substrate 10p and / or the channel layer 122 using a selective epitaxial growth process. The upper insulating layer 150 can be formed before and / or after the formation of the source and drain patterns 140. That is, the process order of the source and drain patterns 140 and the upper insulating layer 150 can be modified differently.

[0127] The dummy gate and sacrificial layer can be removed sequentially, and then a gate insulating layer 134 and a gate electrode 132 can be formed in the space where the dummy gate and sacrificial layer are removed. The gate insulating layer 134 can be conformally formed in the space where the dummy gate and sacrificial layer are removed, and the gate electrode 132 can fill the space on the gate insulating layer 134. A gate capping layer 138 can be formed on the gate electrode 132 and / or the gate insulating layer 134 disposed on the active region 120.

[0128] Subsequently, as Figure 5 As shown, a first wiring portion 20 can be formed on the first surface 101 of the semiconductor element portion 10. More specifically, a front insulating layer 22 can be formed, a first connection contact portion 24 electrically connected to at least a portion of the gate electrode 132 and the source and drain patterns 140 can be formed, and a first interlayer insulating layer 26, a first wiring layer 28, and a first contact passage 29 can be formed. For the process of forming the front insulating layer 22 or the first interlayer insulating layer 26, any of various processes (e.g., deposition processes, etc.) can be performed. For the process of forming the first connection contact portion 24, the first wiring layer 28, or the first contact passage 29, any of various processes (e.g., deposition processes, electroplating processes, etc.) can be performed.

[0129] Subsequently, as Figures 6 to 9 As shown, a preliminary bonding layer 30p can be formed on the first wiring portion 20.

[0130] More specifically, such as Figure 6 As shown, a first insulating layer 320 and a preliminary insulating layer 310p can be formed on the first wiring portion 20. For the process of forming the first insulating layer 320 or the preliminary insulating layer 310p, any of various processes (e.g., deposition processes, etc.) can be performed.

[0131] Subsequently, as Figure 7 As shown, the initial insulating layer 310p can be removed (reference). Figure 6 A portion of the initial insulating layer 310p is used to form an opening 314p. The portion of the initial insulating layer 310p other than the opening 314p can form a first pattern 312.

[0132] For example, a mask having an opening portion corresponding to the opening 314p can be formed on the preliminary insulating layer 310p, and the portion of the preliminary insulating layer 310p corresponding to the opening 314p can be removed through the opening portion. Therefore, the opening 314p can be formed. After the opening 314p is formed, the mask can be removed.

[0133] For example, a mask with an opening can be formed by photolithography, and the removal of a portion of the initial insulating layer 310p can be performed by etching (e.g., dry etching). However, the embodiments are not limited thereto, and the mask can be formed by any of a variety of processes, the removal of a portion of the initial insulating layer 310p can be performed by any of a variety of processes, or the removal of the mask can be performed by any of a variety of processes.

[0134] Subsequently, as Figure 8 As shown, a conductive material (e.g., a metal or metallic material) can at least partially fill the opening 314p to form a second pattern 314. Therefore, a patterned layer 310 including a first pattern 312 and a second pattern 314 can be formed. For the process of at least partially filling the opening 314p with conductive material, any of various processes (e.g., deposition processes, electroplating processes, etc.) can be performed. Following the process of filling the opening 314p with conductive material, a chemical mechanical polishing (CMP) process can be performed.

[0135] For example, by utilizing the hardness difference between the first pattern 312 and the second pattern 314, a step ST can be formed at the boundary between the second surface S1 of the first pattern 312 and the second surface S2 of the second pattern 314 after a chemical mechanical polishing process. In some embodiments, a material that etches the first pattern 312 beyond the second pattern 314 can be used in the chemical mechanical polishing process, allowing the step ST to be formed at the boundary between the second surface S1 of the first pattern 312 and the second surface S2 of the second pattern 314. In some embodiments, by adjusting the process conditions of the chemical mechanical polishing process, the step ST can be formed at the boundary between the second surface S1 of the first pattern 312 and the second surface S2 of the second pattern 314. The step ST can be formed at the boundary between the second surface S1 of the first pattern 312 and the second surface S2 of the second pattern 314 by various methods other than those described above. However, the embodiments are not limited to these, and the second surface S1 of the first pattern 312 and the second surface S2 of the second pattern 314 can have structures other than those described above after a chemical mechanical polishing process. Reference will be made later. Figure 13 and Figure 14 This will be described in detail.

[0136] Subsequently, as Figure 9 As shown, a second insulating layer 330 can be formed on the patterned layer 310 (see reference). Figure 11 The first insulating bonding portion 331 is used to form the preliminary bonding layer 30p. The first insulating bonding portion 331 may be part of the second insulating layer 330. For the process of forming the first insulating bonding portion 331, any of a variety of processes (e.g., deposition process, etc.) can be used.

[0137] Subsequently, as Figure 10 As shown, a second insulating layer 330 (reference) is disposed on the support substrate 40. Figure 11 The second insulating bonding portion 332 and the first insulating bonding portion 331 of the second insulating layer 330 disposed on the pattern layer 310 can be bonded to each other. Therefore, the pattern layer 310 and the support substrate 40 can be bonded by the second insulating layer 330 including the first insulating bonding portion 331 and the second insulating bonding portion 332.

[0138] For the process of forming the second insulating bonding portion 332 on the support substrate 40, any of various processes (e.g., deposition processes, etc.) can be performed. For the process of bonding the patterned layer 310 and the support substrate 40 using the first insulating bonding portion 331 and the second insulating bonding portion 332, any of various processes can be performed, such as bonding processes using heat and pressure, etc.

[0139] Subsequently, as Figure 11As shown, in the thickness direction of the semiconductor device (Z-axis direction in the attached figure), 10p of the semiconductor substrate can be removed (reference). Figure 10 At least a partial portion of the semiconductor substrate 10p. For example, for a process of removing at least a partial portion of the semiconductor substrate 10p, any of a variety of processes (etching process, chemical mechanical polishing process, etc.) can be used.

[0140] exist Figure 11 In the illustration, semiconductor substrate 10p is shown to be completely removed and no semiconductor substrate 10p is left. However, the embodiments are not limited to this. In embodiments, the portion of semiconductor substrate 10p adjacent to the active region 120 and / or gate structure 130 may not be removed to form the following pattern.

[0141] Subsequently, as Figure 12 As shown, a second wiring portion 50 can be formed on the second surface 102 of the semiconductor element portion 10. More specifically, a back insulating layer 52 can be formed, a second connection contact portion 54 electrically connected to at least one of the source and drain patterns 140 (e.g., the source pattern) can be formed, and a second interlayer insulating layer 56, a second wiring layer 58, and a second contact passage 59 can be formed. For the process of forming the back insulating layer 52 or the second interlayer insulating layer 56, any of various processes (e.g., deposition processes, etc.) can be performed. For the process of forming the second connection contact portion 54, the second wiring layer 58, or the second contact passage 59, any of various processes (e.g., deposition processes, electroplating processes, etc.) can be performed. Connection bumps 60 can be formed on the pads 58p of the second wiring portion 50. For the process of forming the connection bumps 60, any of various processes can be performed.

[0142] According to an embodiment, a patterned layer 310 comprising a first pattern 312 and a second pattern 314 can be formed by patterning an initial insulating layer 310p to form an opening 314p and filling the opening 314p at least partially with conductive material. Therefore, a semiconductor device 100 with improved performance and reliability can be formed through a simple manufacturing process.

[0143] In the following text, see references Figures 13 to 19 The semiconductor device according to the additional embodiments will be described in more detail. With regard to elements not described in detail below, it will be understood that the element is at least similar to a corresponding element already described elsewhere in this disclosure. The parts not described above will be described in detail.

[0144] Figure 13 This is a cross-sectional view showing a portion of a semiconductor device according to another embodiment. Figure 13 Showing with Figure 2 The corresponding part.

[0145] refer to Figure 13 In the patterned layer 310 of the bonding layer 30 according to the embodiment, at least a portion of the second surface S2 of the second pattern 314 may include a portion protruding or extending from the second surface S1 of the first pattern 312 toward the support substrate 40 (e.g., the second insulating layer 330). The second surface S1 of the first pattern 312 and the second surface S2 of the second pattern 314 may be surfaces adjacent to the support substrate 40 (e.g., surfaces adjacent to the second insulating layer 330). For example, the second surface S2 of the second pattern 314 may have a convex shape toward the support substrate 40 (e.g., the second insulating layer 330), while the second surface S1 of the first pattern 312 may have a concave shape.

[0146] In this embodiment, the thickness (e.g., average thickness) of a portion of the second insulating layer 330 disposed between the second pattern 314 and the support substrate 40 can be less than the thickness (e.g., average thickness) of a portion of the second insulating layer 330 disposed between the first pattern 312 and the support substrate 40. Therefore, the heat dissipation characteristics through the second pattern 314 can be improved. Since a step is not required between the second surface S1 of the first pattern 312 and the second surface S2 of the second pattern 314, the stability of the structure can be further improved.

[0147] Chemical mechanical polishing process performed to form the first pattern 312 and the second pattern 314 (see reference) Figure 8 As described above, the second surface S1 of the first pattern 312 may have a concave shape, while the second surface S2 of the second pattern 314 may have a convex shape.

[0148] For example, due to the hardness difference between the first pattern 312 and the second pattern 314, after a chemical mechanical polishing (CMP) process, the second surface S1 of the first pattern 312 may have a concave shape, while the second surface S2 of the second pattern 314 may have a convex shape. In some embodiments, a material that etches the first pattern 312 beyond the second pattern 314 may be used in the CMP process, such that after the CMP process, the second surface S1 of the first pattern 312 may have a concave shape, while the second surface S2 of the second pattern 314 may have a convex shape. In some embodiments, by adjusting the process conditions of the CMP process, the second surface S1 of the first pattern 312 may have a concave shape, while the second surface S2 of the second pattern 314 may have a convex shape after the CMP process. Various methods other than those described above can also result in the second surface S1 of the first pattern 312 having a concave shape and the second surface S2 of the second pattern 314 having a convex shape.

[0149] Figure 14This is a cross-sectional view showing a portion of a semiconductor device according to another embodiment. Figure 14 Showing with Figure 2 The corresponding part.

[0150] refer to Figure 14 In the patterned layer 310 of the bonding layer 30 according to the embodiment, the second surface S1 of the first pattern 312 adjacent to the second insulating layer 330 can be disposed on the same plane as the second surface S2 of the second pattern 314 adjacent to the second insulating layer 330. Therefore, the thickness (e.g., average thickness) of the portion of the second insulating layer 330 disposed between the second pattern 314 and the support substrate 40 can be substantially the same as the thickness (e.g., average thickness) of the portion of the second insulating layer 330 disposed between the first pattern 312 and the support substrate 40.

[0151] Figure 15 This is a top view showing a portion of the patterned layer of the bonding layer included in a semiconductor device according to another embodiment. Figure 15 Showing with Figure 3 The corresponding part.

[0152] refer to Figure 15 The second pattern 314 included in the pattern layer 310 of the bonding layer may have an island shape. For example, a plurality of second patterns 314 may be spaced apart from each other at a fixed interval in each of a first direction (X-axis direction in the figure) and a second direction (Y-axis direction in the figure). When the second pattern 314 may have an island shape, the second pattern 314 can be uniformly arranged and the heat dissipation path through the second pattern 314 can be uniformly provided.

[0153] exist Figure 15 In the illustration, the second pattern 314 is shown as having a closed shape (e.g., a rectangular shape). However, the embodiments are not limited to this, and the second pattern 314 can have any of a variety of shapes, such as a circular shape, an elliptical shape, a polygonal shape other than a rectangular shape, an irregular shape, etc.

[0154] exist Figure 15 In the illustration, as an example, multiple second patterns 314 are shown positioned at the same location in each of the first direction (X-axis direction in the illustration) and the second direction (Y-axis direction in the illustration). However, the embodiment is not limited to this. Figure 16As shown, the positions of the second pattern 314 in the first column (e.g., the positions of the second pattern 314 in the second direction) and the positions of the second pattern 314 in the second column (e.g., the positions of the second pattern 314 in the second direction) can be different from each other. Each of the first and second columns can extend in the second direction, and the first and second columns can be adjacent to each other in the first direction. In some embodiments, the positions of multiple second patterns 314 can be modified differently.

[0155] Figure 17 This is a top view showing a portion of the patterned layer of the bonding layer included in a semiconductor device according to another embodiment. Figure 17 Showing with Figure 3 The corresponding part.

[0156] refer to Figure 17 The second pattern 314 included in the pattern layer 310 of the bonding layer may have a grid shape. For example, a plurality of first patterns 312 may be spaced apart from each other at a fixed interval in each of a first direction (X-axis direction in the figure) and a second direction (Y-axis direction in the figure), and the second pattern 314 may be disposed on the entire portion excluding the plurality of first patterns 312. The second pattern 314 may be a single portion disposed in the portion where the plurality of first patterns 312 are not disposed. For example, the second pattern 314 may include a plurality of portions extending in the first direction and a plurality of portions extending in the second direction. When the second pattern 314 may have a grid shape, the second pattern 314 may be configured to have a large area and the heat dissipation path through the second pattern 314 may be uniformly provided.

[0157] exist Figure 17 In the illustration, the first pattern 312 is shown as having a closed shape (e.g., a rectangular shape). However, the embodiments are not limited to this, and the first pattern 312 can have any of a variety of shapes, such as a circular shape, an elliptical shape, a polygonal shape other than a rectangular shape, an irregular shape, etc. Figure 17 The illustration, as an example, shows a plurality of first patterns 312 positioned at the same location in each of a first direction (the X-axis direction in the illustration) and a second direction (the Y-axis direction in the illustration). However, the embodiments are not limited thereto. In some embodiments, the positions of the first patterns 312 in the first column (e.g., the positions of the first patterns 312 in the second direction) and the positions of the first patterns 312 in the second column (e.g., the positions of the first patterns 312 in the second direction) may be different from each other. Each of the first and second columns may extend in the second direction, and the first and second columns may be adjacent to each other in the first direction.

[0158] The shape and position of multiple first patterns 312 can be modified differently, and the shape and position of second patterns 314 can be modified differently.

[0159] Figure 18 This is a cross-sectional view showing a portion of a semiconductor device according to an embodiment. Figure 18 Showing with Figure 3 The corresponding part.

[0160] refer to Figure 18 According to an embodiment, the bonding layer 30 may include a pattern layer 310, a first insulating layer 320, a second insulating layer 330a, and an additional pattern layer 340. The pattern layer 310 may include a first pattern 312 and a second pattern 314. The first insulating layer 320 may be disposed between the first wiring portion 20 and the pattern layer 310. The second insulating layer 330a may be disposed on the second surface S1 of the first pattern 312 adjacent to the support substrate 40, around the periphery (e.g., edge, end, or side) of the second pattern 314. The additional pattern layer 340 may be disposed between the pattern layer 310 and the support substrate 40, and between the second insulating layer 330a and the support substrate 40. The additional pattern layer 340 may include an insulating portion 342 and a conductive portion 344. The insulating portion 342 may be disposed between the support substrate 40 and the second insulating layer 330a disposed on the first pattern 312. The conductive portion 344 may be disposed between the second pattern 314 and the support substrate 40.

[0161] In an embodiment, the patterned layer 310 and the second insulating layer 330a can be bonded to the additional patterned layer 340 by a hybrid bonding that includes insulating layer bonding and conductive bonding (e.g., metallic bonding).

[0162] For example, the insulating portion 342 of the additional pattern layer 340 may include a first insulating portion 342a and a second insulating portion 342b. The second insulating portion 342b may include a material different from that of the first insulating portion 342a. The first insulating portion 342a may be a bonding insulating layer disposed on a first side adjacent to the pattern layer 310 and / or the second insulating layer 330a.

[0163] In an embodiment, the first insulating portion 342a and the second insulating portion 342b of the additional patterned layer 340a may include materials, structures, shapes, etc., corresponding to the second insulating layer 330a and the first pattern 312, respectively. Therefore, the additional patterned layer 340 can be formed using the same or similar process conditions as those used to form the patterned layer 310 and the second insulating layer 330a. This simplifies the process.

[0164] exist Figure 18In the example shown, the thickness of the additional pattern layer 340 is less than the thickness of the second pattern 314 or the sum of the thickness of the first pattern 312 and the thickness of the second insulating layer 330a. Therefore, by including the additional pattern layer 340, the heat dissipation path can be reduced. However, the embodiment is not limited to this, and the thickness of the additional pattern layer 340 may be the same as or greater than the sum of the thickness of the second pattern 314 or the thickness of the first pattern 312 and the thickness of the second insulating layer 330a.

[0165] Each of the second insulating layer 330a and the first insulating portion 342a of the additional patterned layer 340 can be a bonding insulating layer configured to physically and structurally bond the patterned layer 310 and the support substrate 40. The second insulating layer 330a can be a first insulating bonding portion disposed on the patterned layer 310 (e.g., on the first pattern 312), while the first insulating portion 342a of the additional patterned layer 340 can be a second insulating bonding portion disposed on the support substrate 40. The second insulating layer 330a, as the first insulating bonding portion, and the first insulating portion 342a of the additional patterned layer 340, as the second insulating bonding portion, can be bonded to each other to form an insulating layer bond.

[0166] In embodiments, the second insulating layer 330a and / or the first insulating portion 342a may comprise or be formed of an oxide, nitride, or carbide material. For example, the second insulating layer 330a and / or the first insulating portion 342a may comprise silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon carbide (SiCN) x ), silicon dioxide (SiOC) x ), silicon oxynitride (SiON) x ), silicon dioxide (SiOCN) x ) or aluminum nitride (AlN) x At least one of the following or made of silicon dioxide (SiO2) x Silicon nitride (SiN) x ), silicon carbide (SiCN) x ), silicon dioxide (SiOC) x ), silicon oxynitride (SiON) x ), silicon dioxide (SiOCN) x ) or aluminum nitride (AlN) x At least one of the following is formed. In an embodiment, the second insulating layer 330a and the first insulating portion 342a may comprise the same material, such as silicon carbide (SiCN). xHowever, the embodiments are not limited to the materials of the second insulating layer 330a and / or the first insulating portion 342a.

[0167] The second insulating portion 342b may include oxides, nitrides, oxynitrides, etc., or be formed of oxides, nitrides, oxynitrides, etc. For example, the second insulating portion 342b may include silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon oxynitride (SiON) x ) etc. or made of silicon dioxide (SiO) x Silicon nitride (SiN) x ), silicon oxynitride (SiON) x The second insulating portion 342b may include the same material as the first pattern 312. However, the embodiments are not limited thereto, and the second insulating portion 342b may include a material different from the material of the first pattern 312.

[0168] The second pattern 314 and the conductive portion 344 of the additional pattern layer 340 can be a bonding conductive layer (e.g., a bonding metal layer) configured to physically and structurally bond the pattern layer 310 and the support substrate 40. The second pattern 314 can be a first conductive bonding portion included in the pattern layer 310, while the conductive portion 344 of the additional pattern layer 340 can be a second conductive bonding portion disposed on the support substrate 40. The second pattern 314 as the first conductive bonding portion and the conductive portion 344 of the additional pattern layer 340 as the second conductive bonding portion can be bonded to each other to form a conductive bond (e.g., a metal bond).

[0169] In a top view, the conductive portion 344 may at least partially overlap with the second pattern 314 (e.g., in the Z-axis direction). For example, in a top view, the conductive portion 344 may be positioned at the same location as the second pattern 314 and may have a planar shape substantially the same as the planar shape of the second pattern 314. Therefore, a conductive bond (e.g., a metallic bond) formed by using the second pattern 314 and the conductive portion 344 can be stably formed.

[0170] In the cross-sectional view, the side surface of the conductive portion 344 may have a sloped surface, such that the width of the conductive portion 344 decreases toward the supporting substrate 40. This may be because, in the process of forming the opening for the conductive portion 344, an etching process can be performed on the surface opposite to the supporting substrate 40. Therefore, the side surface of the second pattern 314 and the side surface of the conductive portion 344 may have opposite slope directions or orientations. However, the embodiments are not limited to this, and the side surface of the conductive portion 344 may have a vertical surface, and the conductive portion 344 may have a substantially uniform width. Various other modifications are possible.

[0171] The conductive portion 344 of the additional pattern layer 340, comprising a conductive material, may include or be formed of a metal. For example, the conductive portion 344 may include at least one of copper, aluminum, tungsten, molybdenum, titanium, tantalum, nickel, gold, tin, manganese, or cobalt, or may include or be formed of an alloy having the aforementioned materials. When the conductive portion 344 comprises a conductive material (e.g., a metal or metal alloy), the conductive portion 344 may have a relatively high thermal conductivity. In an embodiment, the second pattern 314 and the conductive portion 344 may include the same material, such as copper. However, the embodiments are not limited thereto.

[0172] The patterned layer 310 and the second insulating layer 330a can be stably bonded to the additional patterned layer 340 disposed on the support substrate 40 via a hybrid bonding process. The second pattern 314 can be connected to the support substrate 40 via a conductive portion 344 of the additional patterned layer 340 that is connected (e.g., directly connected) to the support substrate 40. That is, heat dissipation in the direction toward the support substrate 40 can be effectively achieved via the conductive portion 344 of the additional patterned layer 340 that is connected (e.g., directly connected) to the support substrate 40.

[0173] exist Figure 18 In its description, the insulating portion 342 of the additional patterned layer 340 is shown and described by way of example as including a first insulating portion 342a and a second insulating portion 342b. In some embodiments, such as Figure 19 As shown, the insulating portion 342 of the additional pattern layer 340 may include a first insulating portion 342a and may not include a second insulating portion 342b (see reference). Figure 18 That is, the insulating portion 342 of the additional patterned layer 340 can be formed of the first insulating portion 342a, which includes the same material as the second insulating layer 330a. Therefore, the thickness of the additional patterned layer 340 can be further reduced, and the heat dissipation path can be further reduced. Various other modifications are possible.

[0174] While some examples have been described in conjunction with what are now considered to be practical embodiments, it should be understood that this disclosure is not limited to the disclosed embodiments, and that this disclosure is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: The semiconductor element portion includes semiconductor elements; A first wiring portion, the first wiring portion being located on a first surface of the semiconductor element portion; A supporting substrate, the supporting substrate being located on the first wiring portion; A bonding layer is located between the first wiring portion and the supporting substrate; as well as The second wiring portion is located on a second surface of the semiconductor element portion opposite to the first surface of the semiconductor element portion. The bonding layer includes a pattern layer. The pattern layer includes a first pattern and a second pattern. The first pattern includes an insulating material, and the second pattern has a higher thermal conductivity than the first pattern and is electrically insulated from the first wiring portion.

2. The semiconductor device according to claim 1, wherein, The second pattern includes a conductive material.

3. The semiconductor device according to claim 2, wherein, The second pattern includes metal or metal alloy.

4. The semiconductor device according to claim 1, wherein, The first pattern and the second pattern overlap each other at least partially in a first direction parallel to the first surface of the supporting substrate.

5. The semiconductor device according to claim 1, further comprising: A first insulating layer is located between the second pattern and the first wiring portion and electrically insulates the second pattern and the first wiring portion from each other.

6. The semiconductor device according to claim 5, wherein, The first insulating layer comprises an insulating material that is different from the insulating material of the first pattern.

7. The semiconductor device according to claim 1, wherein, In a top view, the second pattern has a line shape or a closed shape.

8. The semiconductor device according to claim 1, wherein, In the top view, the area of ​​the first pattern is larger than the area of ​​the second pattern; or The ratio of the width to the thickness of the second pattern is 0.5 or greater.

9. The semiconductor device according to claim 1, wherein, Compared to the second surface of the first pattern adjacent to the supporting substrate, at least a portion of the second surface of the second pattern adjacent to the supporting substrate extends further toward the supporting substrate in a first direction perpendicular to the first surface of the supporting substrate; or Wherein, a step exists at the boundary between the second surface of the second pattern and the second surface of the first pattern; or The second surface of the second pattern has a convex shape extending toward the supporting substrate, and the second surface of the first pattern has a concave shape.

10. The semiconductor device of claim 1, further comprising: A first insulating layer is located between the pattern layer and the first wiring portion; as well as A second insulating layer is located between the patterned layer and the support substrate.

11. The semiconductor device according to claim 10, wherein, The first insulating layer and the second insulating layer comprise the same material.

12. The semiconductor device according to claim 10, wherein, The dielectric constant of the first insulating layer is less than the dielectric constant of the first pattern or the dielectric constant of the second insulating layer.

13. The semiconductor device according to claim 1, further comprising: A first insulating layer is located between the pattern layer and the first wiring portion; A second insulating layer is located at the periphery of the second pattern and on a second surface of the first pattern adjacent to the supporting substrate; as well as An additional patterned layer, the additional patterned layer including an insulating portion located between the second insulating layer and the support substrate and a conductive portion located between the second pattern and the support substrate.

14. The semiconductor device according to claim 13, wherein, The insulating portion of the additional patterned layer includes a first insulating portion, the first insulating portion comprising the same material as the second insulating layer; or The insulating portion of the additional patterned layer includes a second insulating portion, which comprises a material different from that of the first insulating portion.

15. The semiconductor device according to claim 1, wherein, The semiconductor element includes: An active region comprising a plurality of channel layers spaced apart from each other in a direction perpendicular to a first surface of the supporting substrate; A gate structure including a gate electrode and a gate insulating layer, the gate electrode at least partially surrounding each of the plurality of channel layers, the gate insulating layer being located between the plurality of channel layers and the gate electrode; and Source and drain patterns, the source and drain patterns being located on opposite sides of the active region.

16. A semiconductor device, the semiconductor device comprising: The semiconductor element portion includes semiconductor elements; A first wiring portion, the first wiring portion being located on a first surface of the semiconductor element portion; A supporting substrate, the supporting substrate being located on the first wiring portion; A bonding layer is located between the first wiring portion and the supporting substrate; as well as The second wiring portion is located on a second surface of the semiconductor element portion opposite to the first surface of the semiconductor element portion. The bonding layer includes a first insulating layer located on the first wiring portion and a conductive pattern located on the first insulating layer.

17. The semiconductor device according to claim 16, wherein, The conductive pattern overlaps at least partially with the first insulating layer in a first direction perpendicular to the first surface of the supporting substrate.

18. The semiconductor device according to claim 16, wherein, The bonding layer also includes an insulating pattern located around the conductive pattern.

19. A semiconductor device, the semiconductor device comprising: The semiconductor element portion includes semiconductor elements; A front wiring portion, wherein the front wiring portion is located on the front surface of the semiconductor element portion; A support substrate, the support substrate being located on the front wiring portion; An intermediate layer, the intermediate layer being located between the front wiring portion and the support substrate; as well as The rear wiring portion is located on the rear surface of the semiconductor element portion. The intermediate layer includes a pattern layer, and The pattern layer includes an insulating pattern and a heat dissipation pattern. The insulating pattern includes an insulating material, and the heat dissipation pattern includes a conductive material and is electrically insulated from the front wiring portion.

20. The semiconductor device of claim 19, further comprising: A first insulating layer is located between the heat dissipation pattern and the front wiring portion, and electrically insulates the heat dissipation pattern and the front wiring portion from each other.

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