Semiconductor device and semiconductor package

Abstract

The invention discloses a semiconductor device and a semiconductor package. The semiconductor device includes a first semiconductor die having a front side and a back side opposite to the front side, and including a first active element disposed adjacent to the front side of the first semiconductor die. The semiconductor device also includes a second semiconductor die having a first side bonded to the backside of the first semiconductor die and a second side opposite the first side. The second semiconductor die includes a passive element for managing power delivery of the first semiconductor die.

Description

Technical Field

[0001] This invention relates to semiconductor technology, and more particularly to a semiconductor device with power delivery that minimizes parasitic effects. Background Technology

[0002] Various semiconductor chips / dies require power to operate, such as high-performance computing (HPC) chips / dies. Therefore, it is necessary to improve the power supply for these semiconductor chips / dies.

[0003] While existing semiconductor devices with power delivery within semiconductor chips / dies are well-known and generally fulfill their intended purpose, they are not satisfactory in all respects. For example, these semiconductor devices may include non-ideal arrangements or configurations, resulting in parasitic losses that degrade power delivery performance. Summary of the Invention

[0004] In some embodiments, a semiconductor device is provided. The semiconductor device includes a first semiconductor die having a front side and a back side opposite to the front side, and includes a plurality of first active elements disposed adjacent to the front side of the first semiconductor die. The semiconductor device also includes a second semiconductor die having a first side bonded to the back side of the first semiconductor die and a second side opposite to the first side. The second semiconductor die includes passive elements for managing power supply to the first semiconductor die.

[0005] In some embodiments, a semiconductor device is provided. The semiconductor device includes a first semiconductor die having a front side and a back side opposite to the front side, and includes a first processing unit and a second processing unit adjacent to the front side. The semiconductor device also includes a second semiconductor die having a first side bonded to the first semiconductor die and a second side opposite to the first side, and includes a first power conversion unit and a second power conversion unit. The first power conversion unit and the second power conversion unit are configured to receive a first input voltage and a second input voltage from the second side of the second semiconductor die, respectively, and to provide a first output voltage to the first processing unit and a second output voltage to the second processing unit, respectively.

[0006] In some embodiments, a semiconductor package is provided. The semiconductor package includes a package substrate including power input pads and signal input / output pads formed on a upper surface of the package substrate. The semiconductor package also includes a first conductive connector electrically coupled to the power input pads and a second conductive connector electrically coupled to the signal input / output pads. The semiconductor package further includes a stacked structure including an upper semiconductor die and a lower semiconductor die. The upper semiconductor die includes a plurality of first transistors and has a front side and a back side opposite to the front side. The lower semiconductor die includes a plurality of capacitors. The lower semiconductor die has a first side bonded to the back side of the upper semiconductor die and a second side opposite to the first side. The second side of the lower semiconductor die is electrically coupled to the power input pads of the package substrate via the first conductive connector. Attached Figure Description

[0007] Figure 1 These are cross-sectional schematic diagrams of semiconductor packages according to some embodiments;

[0008] Figure 2 These are some examples Figure 1 A schematic cross-sectional view of a semiconductor device with power delivery within a semiconductor package shown.

[0009] Figure 3 These are cross-sectional schematic diagrams of semiconductor packages according to some embodiments;

[0010] Figure 4 These are some examples Figure 3 A schematic cross-sectional view of a semiconductor device with power delivery within a semiconductor package shown.

[0011] Figure 5A These are block diagrams of passive circuits in semiconductor chips according to some embodiments;

[0012] Figure 5B These are block diagrams of power conversion circuits in semiconductor chips according to some embodiments;

[0013] Figure 6 These are schematic cross-sectional views of semiconductor devices with power delivery according to some embodiments;

[0014] Figure 7 These are schematic cross-sectional views of semiconductor devices with power delivery according to some embodiments;

[0015] Figure 8 These are schematic cross-sectional views of semiconductor devices with power delivery according to some embodiments;

[0016] Figure 9A This is a schematic cross-sectional view of an exemplary three-dimensional (3D) cylindrical capacitor according to some embodiments;

[0017] Figure 9B These are schematic cross-sectional views of exemplary three-dimensional (3D) crown-shaped capacitors according to some embodiments;

[0018] Figure 10 These are schematic cross-sectional views of semiconductor devices with power delivery according to some embodiments;

[0019] Figure 11 These are schematic cross-sectional views of semiconductor devices with power delivery according to some embodiments.

[0020] Symbol explanation:

[0021] 10,10a: Semiconductor package

[0022] 100: Packaging substrate

[0023] 100T: Upper surface

[0024] 102P: Power Input Pin

[0025] 102S: Signal Input / Output Pads

[0026] 104P: Second conductive connector

[0027] 104S: First conductive connector

[0028] 110, 110a, 110b, 110c, 110d: Semiconductor devices

[0029] 200,200': First semiconductor die

[0030] 200a: Front

[0031] 200b: Dorsal side

[0032] 202: Base

[0033] 202a: Front surface

[0034] 202b: Backside surface

[0035] 204: Active Components

[0036] 204a, 204b, 204c: Processing Units

[0037] 206, 210, 214, 308, 312: Insulation layer

[0038] 208: Multi-layer internal connection structure; Back-end manufacturing process (BEOL) layer

[0039] 208L: Metal layer

[0040] 212, 310: Redirect Line Layer (RDL) Structure

[0041] 216P, 310P: Power connection pads

[0042] 216S, 310S: Signal bonding pads

[0043] 300: Second semiconductor die

[0044] 300P, 300S: Semiconductor chips

[0045] 301: First side

[0046] 302, 315: Base

[0047] 302', 306: Passive circuits

[0048] 302C': Three-dimensional (3D) cylindrical or crown-shaped capacitor

[0049] 302a: First surface

[0050] 302b: Second surface

[0051] 303: Second side

[0052] 304a: First metal wiring

[0053] 304b: Second metal wiring

[0054] 306a': First passive circuit

[0055] 306a, 306b, 306c: Power conversion unit

[0056] 307: Second Passive Component

[0057] 314P: Power Input Pin

[0058] 314S: Signal Input / Output Pads

[0059] 400: Top cover base

[0060] D1,D1': Distance

[0061] D3: Anterior distance

[0062] D4: Backside Distance

[0063] I',I1,I2: Interface

[0064] T1, T2, T3, T4, T5: Through-substrate vias (TSV)

[0065] BE: Lower electrode

[0066] BEE: Bottom Extension

[0067] Cd: Dielectric film layer

[0068] TE: Upper electrode

[0069] TEE: Top extension

[0070] Vin: Input voltage; first voltage

[0071] Vin1: First input voltage

[0072] Vin2: Second input voltage

[0073] Vin3: Third input voltage

[0074] Vout: Output voltage; second voltage

[0075] Vout1: First output voltage

[0076] Vout2: Second output voltage

[0077] Vout3: Third output voltage Detailed Implementation

[0078] The following describes the manufacture and use of embodiments of the present invention. However, it will be readily apparent that the embodiments of the present invention provide many suitable inventive concepts and can be implemented in a wide range of specific contexts. The specific embodiments disclosed are merely illustrative of making and using the present invention in particular ways and are not intended to limit the scope of the invention. Furthermore, the same reference numerals are used in the drawings and descriptions of the embodiments of the present invention to denote the same or similar components. The above repetition of reference numerals is for simplicity and clarity and does not imply any relationship between the different embodiments and / or configurations discussed.

[0079] In the fabrication of semiconductor devices, semiconductor wafers (chips) are formed, each containing semiconductor dies. A semiconductor die contains hundreds or thousands of transistors performing one or more electronic functions. Each semiconductor die, diced from the semiconductor wafer, typically has the same electronic function and has a front side (sometimes called the active side) containing multiple transistors. Each individual die is then encapsulated in a semiconductor package to provide structural support and / or environmental isolation.

[0080] Semiconductor grains typically include a substrate. The substrate includes a front side (sometimes called the active surface) on which / within which semiconductor transistors are disposed, and a back side formed of bulk semiconductor material (e.g., silicon). The front side of the substrate is formed using various semiconductor fabrication processes, including deposition, patterning, doping, thermal processing, and planarization. In deposition processes, various materials are grown or deposited on the substrate, for example, by chemical vapor deposition, atomic layer deposition, evaporation sputtering, thermal oxidation, nitriding, or similar methods. In patterning processes, photolithography and etching processes (e.g., dry etching or wet etching) are used to remove unwanted material to form a specific structure. After forming the semiconductor transistor near the front side of the substrate, a middle-end-of-line (MEOL) layer and / or a back-end-of-line (BEOL) layer are formed above the semiconductor transistor and on the front side of the substrate. In other words, the back-end-of-line (BEOL) layer is adjacent to the front surface of the substrate and opposite the back surface of the substrate.

[0081] Please refer to Figure 1 and Figure 2 , Figure 1 A schematic cross-sectional view of a semiconductor package 10 according to some embodiments is shown, while Figure 2 Illustrations based on some embodiments Figure 1 This is a cross-sectional schematic diagram of a semiconductor device 110 for power delivery within a semiconductor package 10. (See diagram below.) Figure 1 As shown, in some embodiments, the semiconductor package 10 includes a package substrate 100, such as a package board or interposer. A plurality of pads are formed on the upper surface 100T of the package substrate 100. In some embodiments, these pads may include one or more signal input / output pads, one or more power input pads, and one or more ground pads. For simplicity, only two signal input / output pads 102S (or signal pads) and two power input pads 102P (or power pads, including power input pads and ground pads) are shown here.

[0082] In some embodiments, the semiconductor package 10 further includes a semiconductor device 110 formed on the substrate 100 and conductive connectors (e.g., a first conductive connector 104S and a second conductive connector 104P) formed between the semiconductor device 110 and the substrate 100. In some embodiments, the first conductive connector 104S and the second conductive connector 104P may include solder balls, bumps, or conductive pillars, and are used to assemble the semiconductor device 110 onto the package substrate 100. For example, the first conductive connector 104S and the second conductive connector 104P may include solder balls, such as... Figure 1As shown in the diagram. For simplicity, only two first conductive connectors 104S and two second conductive connectors 104P are shown here. The first conductive connectors 104S and the second conductive connectors 104P are respectively connected to the signal input / output pad 102S and the power input pad 102P.

[0083] In some embodiments, the semiconductor element 110 (also referred to herein as a die stack structure) includes a first semiconductor die 200 (also referred to herein as an upper semiconductor die) and a second semiconductor die 300 (also referred to herein as a lower semiconductor die) stacked below the first semiconductor die 200. In some embodiments, the first semiconductor die 200 is a logic circuit die, an analog circuit die, or a memory die, and includes one or more active elements 204 (e.g., transistors) Figure 2 (As shown). In some embodiments, the first semiconductor die 200 includes a machine learning processor or a deep learning processor, containing those active elements. In some other embodiments, the active element 204 in the first semiconductor die 200 may be a transistor for controlling or switching higher-order memory devices, such as, but not limited to, for dynamic random access memory (DRAM) or high-bandwidth memory (HBM).

[0084] Unlike the first semiconductor die 200, the second semiconductor die 300 is a passive circuit die, including passive circuit 306 (such as...). Figure 2 As shown in the diagram, passive circuitry 306 includes passive elements (not shown) (e.g., capacitors and / or inductors). In some other embodiments, the second semiconductor die 300 is a power conversion circuit die containing one or more passive elements electrically coupled to one or more active elements within the second semiconductor die 300. In some embodiments, more than 30% of the die area of ​​the second semiconductor die 300 is used to form passive elements. In some embodiments, more than 80% of the die area of ​​the second semiconductor die 300 is used to form passive elements.

[0085] In some embodiments, the capacitors in the passive circuit die or power conversion circuit die are three-dimensional (3D) cylindrical or crown-shaped capacitors formed compatible with semiconductor fabrication processes. In some embodiments, three-dimensional (3D) cylindrical or crown-shaped capacitors have smaller dimensions and larger capacitance values ​​than conventional MLCC (multilayer ceramic capacitor) capacitors. Furthermore, the capacitance values ​​of cylindrical or crown-shaped capacitors are larger than those of conventional semiconductor capacitors (e.g., planar MIM or MIS type capacitors).

[0086] like Figure 9A and Figure 9BThe diagrams illustrate, for example but not limited to, cross-sectional views of exemplary three-dimensional (3D) cylindrical (or concave) and crown-type capacitors. A unit cell of a three-dimensional (3D) cylindrical or crown-type capacitor may include an upper electrode TE, a lower electrode BE, a top extension TEE electrically connected to the upper electrode TE and extending to the lower electrode BE, a bottom extension BEE electrically connected to the lower electrode BE and laterally surrounding the top extension TEE, and a dielectric film layer Cd, such as a high-k film (e.g., lanthanum oxide, hafnium oxide, or zirconium oxide film), formed between the top extension TEE and the bottom extension BEE. The capacitance per unit area of ​​a three-dimensional (3D) cylindrical or crown-type capacitor is approximately 10 to 100 times greater than that of a conventional semiconductor capacitor. Furthermore, the capacitance per unit area of ​​a three-dimensional (3D) cylindrical or crown-type capacitor is more than 100 times greater than the parasitic capacitance per unit area compared to any possible capacitor in a logic die. Similarly, the capacitance per unit area of ​​a three-dimensional (3D) cylindrical or crown-shaped capacitor is more than 100 times larger than that of a conventional semiconductor capacitor embedded in a logic die (e.g., a planar MIM or MIS capacitor). In some embodiments, the unit cells of a three-dimensional (3D) cylindrical or crown-shaped capacitor can be arranged in any suitable array shape, such as a rectangular array or a hexagonal array, when viewed from above.

[0087] The first semiconductor die 200 has a front side 200a and a back side 200b opposite to the front side 200a. In some embodiments, the first semiconductor die 200 is flipped so that the front side 200a faces the second semiconductor die 300. Furthermore, the second semiconductor die 300 has a first side 301 that engages with the front side 200a of the first semiconductor die 200 and a second side 303 opposite to the first side 301. A first conductive connector 104S and a second conductive connector 104P are coupled to the second side 303 of the second semiconductor die 300, such that the semiconductor device 110 is assembled onto the package substrate 100 via the first and second conductive connectors 104S and 104P.

[0088] Figure 2 Detailed portions of a first semiconductor die 200 and a second semiconductor die 300 in a semiconductor device 110 according to some embodiments are illustrated. More specifically, the first semiconductor die 200 includes a substrate 202 having a front surface (sometimes referred to as an active surface) 202a and a back surface 202b corresponding to the front surface 200a and back surface 200b of the first semiconductor die 200, such that the front surface 202a is opposite to the back surface 202b. Typically, an active element 204 (e.g., a transistor) formed in the first semiconductor die 200 is adjacent to the front surface 202a of the substrate 202.

[0089] In some embodiments, the first semiconductor die 200 further includes insulating layers 206, 210, and 214 sequentially formed over the front surface 202a. Insulating layer 206 includes an interlayer dielectric (ILD) layer and one or more inter-metal dielectric (IMD) layers. For simplicity, only a single layer (i.e., insulating layer 206) is shown. A multilayer interconnect structure 208 is formed within insulating layer 206 and electrically coupled to active element 204. The multilayer interconnect structure 208 includes one or more metal layer stacks and one or more conductive vias located within insulating layer 206. The metal layers (which may be referred to as MEOL and / or BEOL) in each stack are vertically aligned and electrically coupled to each other through conductive vias between adjacent metal layers. Insulating layer 210 includes a redistribution layer (RDL) structure 212 formed therein. Insulating layer 214 may be referred to as a passivation sheath. The insulating layer 214 can be made of inorganic or organic materials. Bonding pads can be formed within the insulating layer 214. For simplicity, only two signal bonding pads 216S and two power bonding pads 216P are shown here.

[0090] The second semiconductor die 300 includes a device layer 302, which has a first surface 302a and a second surface 302b corresponding to a first side 301 and a second side 303 of the second semiconductor die 300, such that the first surface 302a is opposite to the second surface 302b. Through-substrate vias (TSVs) T1 and T2 and a passive circuit 306 containing passive elements are formed in the device layer 302, wherein the passive circuit 306 can be electrically connected to an external circuit through the through-substrate vias (TSVs) T1 and T2.

[0091] In some embodiments, the second semiconductor die 300 further includes an insulating layer 308 formed on a first surface 302a of the device layer 302. The insulating layer 308 may be referred to as a passivation layer of the second semiconductor die 300. The insulating layer 308 may be made of inorganic or organic materials. Bonding pads may be formed in the insulating layer 308. These bonding pads are electrically coupled to through-substrate vias (TSVs) T1 and T2 formed within the device layer 302. For simplicity, only two signal bonding pads 310S and two power bonding pads 310P are shown.

[0092] In some embodiments, the second semiconductor die 300 further includes an insulating layer 312 formed on the second surface 302b of the substrate 302. A redistribution layer (RDL) structure 310 having signal and power pads is formed within the insulating layer 312. The redistribution layer (RDL) structure 310 having signal and power pads (e.g., signal input / output pads 314S and power input pads 314P) is electrically coupled to the signal bonding pads 310S and power bonding pads 310P within the insulating layer 308 through through-substrate vias (TSVs) T1 and T2 formed in the device layer 302.

[0093] In some embodiments, signal input / output pads 314S and power input pads 314P are respectively coupled to the first conductive connector 104S and the second conductive connector 104P. In this way, power can be supplied from the power input pad 102P of the package substrate 100 to the first semiconductor die 200 through the second conductive connector 104P, the power input pad 314P, the through-substrate via (TSV) T2 formed in the substrate 302, the passive circuit 306, and the power pad 310P. Furthermore, a signal source can be supplied from the first semiconductor die 200 to the package substrate 100, or from the package substrate 100 to the first semiconductor die 200, through the first conductive connector 104S, the signal input / output pads 314S, the through-substrate via (TSV) T1 formed in the substrate 302, and the signal pad 310S.

[0094] In some embodiments, the thickness of the signal input / output pad 314S and / or the power input pad 314P is greater than the thickness of each metal layer 208L in the multilayer interconnect structure 208. In some embodiments, the signal input / output pad 314S and / or the power input pad 314P protrudes above the insulating layer 310.

[0095] In some embodiments, the flipped first semiconductor die 200 is bonded to the second semiconductor die 300 via a hybrid bonding process, thereby forming a hybrid bonding interface I' between the front side 200a of the first semiconductor die 200 and the first side 301 of the second semiconductor die 300. The hybrid bonding involves at least two types of bonding, including metal-to-metal bonding and non-metal-to-non-metal bonding (or dielectric-to-dielectric bonding). In these cases, metal-to-metal bonding involves direct contact between signal bonding pads 310S and 216S, and direct contact between power bonding pads 310P and 216P. Furthermore, dielectric-to-dielectric bonding involves direct contact and / or covalent bonding between insulating layers 308 and 214. The bonding process is not limited to the examples listed above, and other suitable bonding methods may also be used.

[0096] Passive circuit 306 can be used as a voltage regulator or voltage converter between the power supply and the point of load (i.e., active element 204). In a semiconductor device 110 with power delivery, the parasitic losses between the point of load in the first semiconductor die 200 and the passive circuit 306 in the second semiconductor die 300 may vary with the distance D1 between the active element 204 and the second semiconductor die 300. Therefore, power delivery efficiency can be enhanced by shortening the distance D1. Figure 2 As shown, since the passive circuit 306 is integrated within the second semiconductor die 300, which is bonded to the first semiconductor die 200 (which includes the active element 204), the distance D1 can be shorter than in cases where the passive circuit is buried or disposed in a package or intermediate substrate, requiring the power delivery path to span a longer distance in the package or intermediate substrate (e.g., package substrate 100).

[0097] In this embodiment, passive circuitry 306 manages the supply of power to the first semiconductor die 200. Passive circuitry 306 receives input power from the power source and then provides regulated or converted power supply to the load points in the first semiconductor die 200. In some embodiments, the regulated or converted power supply may serve as a stable power source for the operation of the load points in the first semiconductor die 200.

[0098] Please refer to Figure 3 and Figure 4 , Figure 3 A cross-sectional schematic diagram of a semiconductor package 10a according to some embodiments is shown, and Figure 4 Illustrations based on some embodiments Figure 3 The diagram shows a cross-sectional view of a semiconductor device 110a that provides power delivery within a semiconductor package 10a. Figure 3 and Figure 4 The same as Figure 1 and Figure 2 The components use the same reference numerals and their descriptions may be omitted. In some embodiments, Figure 3 and Figure 4 The semiconductor package 10a shown is similar to Figure 1 and Figure 2 The semiconductor package 10 shown is illustrated. More specifically, the semiconductor package 10a includes a package substrate 100, a semiconductor device 110a formed on the package substrate 100, and conductive connectors (e.g., a first conductive connector 104S and a second conductive connector 104P) formed between the semiconductor device 110a and the package substrate 100. However, the semiconductor device 110a has a different... Figure 1 and Figure 2 The configuration and / or structure of the semiconductor device 110 shown.

[0099] like Figure 3 As shown, semiconductor device 110a includes a first semiconductor die 200' (also referred to herein as the upper semiconductor die) and a second semiconductor die 300 (also referred to herein as the lower semiconductor die) stacked below the first semiconductor die 200'. A cover substrate 400 is stacked above the first semiconductor die 200'. Similar to the first semiconductor die 200, the first semiconductor die 200' is a logic circuit die, an analog circuit die, or a memory die, and includes one or more active elements 204 formed therein. For example, the first semiconductor die 200' includes a machine learning processor or a deep learning processor, which contains those active elements.

[0100] Unlike the first semiconductor die 200, the first semiconductor die 200' is not flipped in the configuration of the semiconductor device 110a. Therefore, the back side 200b of the first semiconductor die 200' faces the second semiconductor die 300, while the front side 200a of the first semiconductor die 200' faces the upper cover substrate 400.

[0101] In some embodiments, the first side 301 of the second semiconductor die 300 is bonded to the back side 200b of the first semiconductor die 200', and the second side 303 opposite to the first side 301 of the second semiconductor die 300 is bonded to the upper surface 100T of the package substrate 100 via first and second conductive connectors 104S and 104P, and is bonded to the back side 200b of the first semiconductor die 200'. Figure 3 As shown.

[0102] Figure 4 Further details are illustrated of a first semiconductor die 200' and a second semiconductor die 300 within a semiconductor device 110a according to some embodiments. More specifically, the first semiconductor die 200' includes a substrate 202 having a front surface 202a and a back surface 202b, and includes an active element 204 formed adjacent to the front surface 202a of the substrate 202. In some embodiments, the die 200' further includes an insulating layer 206 (which includes a multilayer interconnect structure 208 formed therein and electrically coupled to the active element 204) and an insulating layer 214 (which includes signal bonding pads 216S and power bonding pads 216P formed therein and electrically coupled to the active element 204). The insulating layers 206 and 214 are formed above the front surface 202a and the back surface 202b of the substrate 202, respectively.

[0103] In some embodiments, the substrate 202 includes through-substrate vias (TSVs) T3 and T4 formed therein, wherein the active element 204 and the multilayer interconnect structure 208 can be electrically connected to through-substrate vias (TSVs) T1 and T2 within the second semiconductor die 300 vias (TSVs) T3 and T4. In some embodiments, the through-substrate via (TSV) T3 is electrically connected to a metal layer 208L within the multilayer interconnect structure 208. For simplicity, only two through-substrate vias (TSVs) T3 and two through-substrate vias (TSVs) T4 are shown. In some embodiments, the through-substrate vias (TSVs) can penetrate some dielectric layers (e.g., silicon oxide layers, silicon nitride layers, etc.) formed during the fabrication of the first semiconductor die 200' and the second semiconductor die 300. Therefore, through-substrate vias (TSVs) T1, T2, T3, and T4 may include different types of connectors, such as through-silicon vias, through-oxide vias (TOVs), through-glass vias (TGVs), or through-dielectric vias (TDVs).

[0104] In some embodiments, these through-substrate vias (TSVs) T3 and T4 are formed within the substrate 202 prior to the bonding fabrication process. For example... Figure 4 As shown, the through-substrate via (TSV) T3 connects to the lowest metal layer 208L of the multilayer interconnect structure 208, which is adjacent to the active element 204. Compared to Figure 2 The illustrated embodiment (which performs some signal transmission through metal layers 208L located in each layer of the multilayer interconnect structure 208) allows some signal transmission from the active element 204 to be performed only through a few metal layers 208L located in the lower layers of the multilayer interconnect structure 208. In this way, in Figure 4 In this embodiment, the transmission speed is faster than Figure 2 Examples of implementations.

[0105] In some embodiments, the first semiconductor die 200' is bonded to the second semiconductor die 300 using a hybrid bonding process, thereby forming a hybrid bonding interface I1 between the back side 200b of the first semiconductor die 200' and the first side 301 of the first and second semiconductor dies 300. In this way, signal bonding pads 310S and 216S are in direct contact, and power bonding pads 310P and 216P are in direct contact. Furthermore, insulating layer 308 and insulating layer 214 are in direct contact and / or covalently bonded. In some embodiments, the front side 200a of the first semiconductor die 200 is attached to the upper cover substrate 400, thereby forming an interface I2 between the upper surface of the insulating layer 206 (i.e., the front side 200a of the first semiconductor die 200) and the lower surface of the upper cover substrate 400, such as... Figure 3 and Figure 4 As shown. In some embodiments, the upper cover substrate 400 is a support substrate made of a Si substrate, a glass substrate, or other suitable material. In some embodiments, the upper cover substrate 400 does not have conductors, active elements, or passive elements.

[0106] According to some embodiments, in the above-described semiconductor device 110a configuration, the front-side distance D3 measured from the uppermost metal layer 208L of the multilayer interconnect structure 208 to the active element 204 is approximately in the range of 5 μm to 15 μm. In some embodiments, the front-side distance D3 is greater than approximately 15 μm to meet the requirements of higher-order back-end process (BEOL) / middle-end process (MEOL) wiring. In some embodiments, the back-side distance D4 measured from the power input pad 314P to the active element 204 is approximately in the range of 4 μm to 10 μm. In some embodiments, the back-side distance D4 is large enough to accommodate the minimum thickness of the second semiconductor die 200, for example, greater than approximately 3 μm. In some embodiments, the back-side distance D4 is smaller than the front-side distance D3. For example, the back-side distance D4 is less than approximately 10 μm.

[0107] Similar to the semiconductor device 110 with power delivery, parasitic losses between the load points (i.e., active elements 204) in the first semiconductor die 200' increase as the distance D1' between the first semiconductor die 200' and the second semiconductor die 300 including the passive circuit 306 increases. In some embodiments, the distance D1' is in the range of about 1 μm to about 5 μm. To thin the space between the substrate 202, insulating layer 214, and insulating layer 308, the minimum value of the distance D1' is greater than 1 μm. The maximum value of the distance D1' is less than 5 μm to shorten the distance from the passive circuit 306 of the second semiconductor die 300 to the active element 204 of the first semiconductor die 200'. Compared to Figure 2The configuration of the semiconductor device 110 shown allows for a shorter distance D1' because the passive circuitry 306 integrated within the second semiconductor die 300 is bonded to the back side of the first semiconductor die 200, and the distance contributed by the thickness of the back-end fabrication (BEOL) layer 208 can be excluded from the distance D1'. This improves the power delivery efficiency of the semiconductor device 110a.

[0108] Figure 4 Implementation examples and Figure 2 Compared to the previous embodiment, Figure 2 The redistribution layer (RDL) structure 212 is removed. Power and signal transmission can be achieved using through-substrate vias (TSVs), signal bonding pads 216S, and power bonding pads 216P formed within the substrate 202. This reduces the overall fabrication cost of the semiconductor device 110. However, this should not be considered a limitation. In some embodiments, an additional redistribution layer (RDL) structure may be formed between the substrate 202 and the insulating layer 214. The additional redistribution layer (RDL) structure reduces the wiring complexity of power and signal transmission.

[0109] Figure 5A Illustrations based on some embodiments Figure 4 A block diagram of the passive circuit 306 in the second semiconductor die 300 is shown. Figure 5A As shown, passive circuitry 306 is embedded or integrated within the second semiconductor die 300. Passive circuitry 306 may include passive elements (not shown), such as capacitors or inductors. Passive circuitry 306 is used to receive input power from a power source (such as...). Figure 8(As shown) and regulates or converts the power supply provided through the second side of the second semiconductor die 300. In other words, the passive circuit 306 receives a first voltage (i.e., input voltage, Vin) from the power supply and then provides a second voltage (i.e., output voltage, Vout) to the active element 204 (not shown). In some embodiments, the first voltage is different from the second voltage. For example, the first voltage (Vin) is higher or lower than the second voltage (Vout). In some embodiments, the passive circuit 306 does not have any inductors. In these cases, the values ​​of the first voltage (Vin) and the second voltage (Vout) are integers. For example, the ratio of the first voltage to the second voltage (Vin:Vout) can be 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, etc. In some other embodiments, the values ​​of the first voltage (Vin) and the second voltage (Vout) are not integers, and the ratio of the first voltage (Vin) to the second voltage (Vout) is a substantially irreducible fraction (or a simplest fraction). For example, but not limited to, the first voltage can be 5.4 volts, while the second voltage can be 1.8 volts or 3.6 volts. Therefore, the ratio of the first voltage to the second voltage, reduced to an irreducible fraction, is 3:1 or 3:2.

[0110] In some embodiments, the passive circuit 306 may include passive elements (e.g., capacitors or inductors) and active elements (e.g., transistors for controlling the aforementioned passive elements). The active elements within the passive circuit 306 are used to control the operation of the passive elements within the passive circuit 306, and are different from the active elements 204 within the first semiconductor die 200'. In some embodiments, the active elements 204 of the first semiconductor die 200' are used for high-performance computing, and therefore the fabrication process node of the active elements 204 of the first semiconductor die 200' is more advanced than that of the active elements 204 of the second semiconductor die 200'.

[0111] In some embodiments, the passive circuit 306 includes a capacitor as a passive element and a transistor for controlling the passive element. The capacitance per unit area of ​​the passive circuit 306 is at least 10 times or greater than the capacitance per unit area of ​​the first semiconductor die 200', and it may employ an embedded capacitor, such as a MIM or MIS capacitor. In some embodiments, the capacitance per unit area of ​​the passive circuit 306 may exceed 1 nF / mm². 2 In some embodiments, the area ratio between passive and active components in the second semiconductor die 300 is greater than the area ratio between passive and active components in the first semiconductor die 200'. The area ratio calculation does not include parasitic passive components.

[0112] In some other embodiments, Figure 4The passive circuit 306 within the second semiconductor die 300 shown can be replaced by the first passive circuit 306' and the second passive element 307 (which includes a thin-film inductor) formed on one side of the first passive circuit 306', such as... Figure 5B As shown. The first passive circuit 306' includes one or more passive elements (e.g., capacitors, not shown) and one or more active elements (e.g., transistors, not shown) electrically connected to the passive elements. Furthermore, the thin-film inductor is made of a magnetic material. The first passive circuit 306' and the second passive element 307 can serve as a power conversion circuit. In some embodiments, the second passive element 307 (e.g., a thin-film inductor made of a magnetic material) is formed by additional deposition and patterning processes compared to forming the passive circuit 306a.

[0113] Similar to Figure 5A The passive circuit 306 shown is... Figure 5B The first passive circuit 306' and the second passive element 307 shown are used to receive a first voltage (i.e., input voltage, Vin) from a power source (not shown), and then provide a second voltage (i.e., output voltage, Vout) to the active element 204 (not shown). In some embodiments, the first voltage is different from the second voltage. For example, the first voltage (Vin) is higher or lower than the second voltage (Vout). Figure 5B In this context, power conversion circuits with thin-film inductors can perform precise voltage regulation during voltage conversion.

[0114] Figure 6 A schematic cross-sectional view of a semiconductor device 110b having a power supply according to some embodiments is shown. Figure 6 The same as Figure 4 The components use the same reference numerals and their descriptions may be omitted. In some embodiments, Figure 6 The semiconductor device 110b shown is similar to Figure 4 The semiconductor device 110a is shown. However, unlike the semiconductor device 110a, the power supply (not shown) can be supplied from the package substrate 100 (such as...). Figure 3 The power input pad 102P (as shown) is connected via the second conductive connector 104P (as shown). Figure 3As shown, the power input pad 314P and the first metal wiring 304a in the second semiconductor die 300, the passive circuit 306 and the second metal wiring 304b in the second semiconductor die 300, and the power bonding pad 310P in the second semiconductor die 300 provide voltage to the first semiconductor die 200'. The interconnects in the second semiconductor die 300 for signal transmission and power delivery are different. Signals are transmitted directly at high speed through through-substrate vias (TSVs) (e.g., through-substrate via (TSV) T1), while power is transmitted through metal-via wiring (e.g., the first metal wiring 304a and the second metal wiring 304b) as a connection between passive elements (e.g., capacitors or inductors) in the passive circuit 306 and active elements (e.g., transistors for controlling capacitors or inductors) in the passive circuit 306.

[0115] Figure 7 A schematic cross-sectional view of a semiconductor device 110c having power delivery according to some embodiments is shown. Figure 7 The same as Figure 4 The components use the same reference numerals and their descriptions may be omitted. In some embodiments, Figure 7 The semiconductor device 110c shown is similar to Figure 4 The semiconductor device 110a is shown. However, unlike the semiconductor device 110a, power (not shown) can be supplied from the power input pad 102P of the package substrate 100 (e.g., ...). Figure 3 (As shown) Voltage is supplied to the first semiconductor die 200' via the second conductive connector 104P and power input pad 314P, passive circuit 306 and through-substrate via (TSV) T2, and power bonding pad 310P in the second semiconductor die 300P. Additionally, a signal is transmitted from the package substrate 100 (e.g., ... Figure 3 The signal input / output pads 102S (as shown) are transmitted through a through-substrate via (TSV) T1 between them to the first semiconductor die 200', and then through the first conductive connector 104S and another second semiconductor die 300S, via signal input / output pads 314S, through-substrate via (TSV) T1, and signal bonding pads 310S. In some embodiments, the dimensions of the second semiconductor dies 300P and 300S are smaller than... Figure 3 and Figure 4The dimensions of the second semiconductor die 300 are shown. Furthermore, the upper surfaces of the second semiconductor dies 300P and 300S are substantially flush with each other, and the lower surfaces of the second semiconductor dies 300P and 300S are substantially flush with each other. In some embodiments, the second semiconductor die 300P is electrically connected only to the power delivery pad and is referred to as a voltage regulator die or voltage converter die (or integrated passive device (IPD) die) to manage power delivery to the first semiconductor die 200'. In some embodiments, the second semiconductor die 300S has only a through-substrate via (TSV) (e.g., through-substrate via (TSV) T1) formed therein, without any circuitry, and is referred to as a support die, which may be made of silicon. In these cases, the dimensions of the lower semiconductor die are not limited to being substantially the same as the dimensions of the upper semiconductor die. Furthermore, other areas for signal connections may be replaced by a support die having a through-substrate via (TSV). However, it is not limited to this. In some other embodiments, the second semiconductor die 300S may include a through-substrate via (TSV) (e.g., through-substrate via (TSV) T1) and additional functional circuitry to further control or modulate signals from the semiconductor die 200', and then transmit the processed signals to the signal pad 310S.

[0116] Figure 8 A block diagram illustrating a semiconductor device 110b having a power supply according to some embodiments is shown. Figure 8 The same as Figure 3 and Figure 4 The components use the same reference numerals and their descriptions may be omitted. In some embodiments, Figure 8 The semiconductor device 110b shown is similar to Figure 3 and Figure 4 The semiconductor device 110a is shown. More specifically, the semiconductor device 110b includes a first semiconductor die 200, a second semiconductor die 300 stacked below the first semiconductor die 200, and a top cover substrate 400 stacked above the first semiconductor die 200. Furthermore, the front side 200a of the first semiconductor die 200 is bonded to the top cover substrate 400, while the back side 200b of the first semiconductor die 200 is bonded to the first side 301 of the second semiconductor die 300.

[0117] In some embodiments, the first semiconductor die 200 in the semiconductor device 110b includes at least two sets of processing units disposed therein. For example, the first semiconductor die 200 may include a first set of processing units (e.g., three processing units 204a), a second set of processing units (e.g., two processing units 204b), and a third set of processing units (e.g., three processing units 204c), such as... Figure 8As shown.

[0118] In some embodiments, each of the processing units 204a, 204b, and 204c includes one or more active elements 204 (illustrated in...). Figure 3 For example, transistors. Furthermore, processing units 204a, 204b, and 204c can receive different output voltages from each other from the second semiconductor die 300. More specifically, each processing unit 204a receives a first output voltage (Vout1), each processing unit 204b receives a second output voltage (Vout2) different from the first output voltage (Vout1), and each processing unit 204c receives a third output voltage (Vout3) different from the first output voltage (Vout1) and the second output voltage (Vout2).

[0119] However, it is understood that the number of processing unit groups and the number of processing units in each group depend on the design requirements, and are not limited to... Figure 8 The example shown.

[0120] Furthermore, the second semiconductor die 300 in the semiconductor device 110b includes at least two sets of power conversion units disposed therein. One set of power conversion units corresponds to and is electrically coupled to one set of processing units. For example, the second semiconductor die 300 may include a first set of power conversion units (e.g., three power conversion units 306a), a second set of power conversion units (e.g., two power conversion units 306b), and a third set of power conversion units (e.g., three power conversion units 306c), such as... Figure 8 As shown.

[0121] In some embodiments, power conversion units 306a, 306b, and 306c each include an active element (e.g., a transistor) and a passive element (e.g., a cylindrical or crown capacitor, or a thin-film inductor). Furthermore, each of power conversion units 306a, 306b, and 306c receives an input voltage from a power source (not shown) electrically coupled to a second side 303 of the second semiconductor die 300. For example, each power conversion unit 306a receives a first input voltage (Vin1), each power conversion unit 306b receives a second input voltage (Vin2), and each power conversion unit 306c receives a third input voltage (Vin3). In some embodiments, the first input voltage (Vin1) is substantially the same as the second input voltage (Vin2) and the third input voltage (Vin3) (varying within a range of + / -10%). In other words, the first, second, and third input voltages share the same input voltage. Subsequently, power conversion units 306a, 306b, and 306c each provide an output voltage to a corresponding processing unit in the first semiconductor die 200. In some embodiments, the output voltage is lower than the input voltage. In this embodiment, power conversion units 306a, 306b, and 306c are integrated into a single second semiconductor die 300. Integrating multiple power conversion units into a single second semiconductor die 300 reduces manufacturing costs and improves the flexibility of the output voltage.

[0122] In the configuration of the semiconductor device 110b described above, different output voltages can be provided to different processing units through different power conversion units. In this way, it is easier to control different output voltage domains.

[0123] According to the embodiments described above, the semiconductor device includes a lower semiconductor die integrating passive circuitry or power conversion circuitry and an upper semiconductor die that receives and is coupled to power through the lower semiconductor die. Therefore, the distance from the power source to the upper semiconductor die can be shortened, thereby reducing parasitic losses between the load point in the upper semiconductor die and the passive circuitry / power conversion circuitry in the lower semiconductor die. Furthermore, since the lower semiconductor die is coupled to the back side (relative to the active side) of the upper semiconductor die, power can be delivered to the load point in the upper semiconductor die over the shortest possible distance. This further reduces parasitic losses and improves power delivery efficiency. According to the embodiments described above, since different processing units (load points) can receive different output voltages (provided by different power conversion units), different output voltage domains can be controlled more easily. Furthermore, since different voltage conversion units can share the input voltage (provided by the power source), the input voltage can be delivered under high-voltage conditions. Therefore, the input power supply current can be reduced. This reduces or mitigates parasitic IR voltage drop, and power consumption is also reduced.

[0124] In some embodiments, different manufacturing process sequences may be performed. Figure 10 A schematic cross-sectional view of a semiconductor device 110d having a power supply according to some embodiments is shown. Figure 10 The same as Figure 3 and Figure 4 Components use the same designation and their descriptions may be omitted. Figure 10 In this embodiment, a through-substrate via (TSV) T2 for connecting the power input pad 314P is formed prior to the bonding fabrication process. In this embodiment, components related to power delivery are shown, while other components are omitted. The second semiconductor die 300 includes a passive circuit 302', and the passive circuit 302' includes a three-dimensional (3D) cylindrical or crown-shaped capacitor 302C', which may employ the aforementioned... Figure 9A or Figure 9B The structure is shown. In this embodiment, the second semiconductor die 300 includes a wiring layer 316, which is a redistribution layer (RDL) or back-end fabrication process (BEOL) of the second semiconductor die 200', and is electrically coupled to a three-dimensional (3D) cylindrical or crown capacitor 302C'. A through-substrate via (TSV) T2 is formed during the fabrication of the second semiconductor die 300 and is electrically coupled to the wiring layer 316. After a bonding fabrication process between the first semiconductor die 200' and the second semiconductor die 300 using power bonding pads 216P and 310P, the substrate 315 of the second semiconductor die 300 is thinned from the second surface 302b of the second semiconductor die 300 to expose the formed through-substrate via (TSV) T2. Subsequently, an insulating layer 312 is formed to cover the second surface 302b, and a power input pad 314P is formed within the insulating layer 312 and electrically connected to the through-substrate via (TSV) T2. In this embodiment, the through-substrate via (TSV) T2 is formed before the bonding fabrication process and exposed after the bonding fabrication process. In some embodiments, each of the through-substrate via (TSV) T2 has tapered sidewalls, but it can also be implemented as vertical sidewalls. For example, each of the through-substrate via (TSV) T2 has a first end adjacent to the first semiconductor die 200' and a second end away from the first semiconductor die 200'. The width of the first end of each through-substrate via (TSV) T2 is greater than the width of the second end.

[0125] More specifically, in some embodiments, the second semiconductor die 300 further includes an additional through-substrate via (TSV) T5 electrically coupled to a three-dimensional (3D) cylindrical or crown-type capacitor 302C'. The additional through-substrate via (TSV) T5 is formed within the passive circuit 302' and electrically coupled to the upper and lower electrodes of the three-dimensional (3D) cylindrical or crown-type capacitor 302C'. In some embodiments, the length of the additional through-substrate via (TSV) T5 in the vertical direction is shorter than the length of the through-substrate via (TSV) T2. In some embodiments, the additional through-substrate via (TSV) T5 is electrically connected to the through-substrate via (TSV) T2 via a wiring layer 316.

[0126] Figure 11 A schematic cross-sectional view of a semiconductor device 110e having a power supply according to some embodiments is shown. Figure 11 The same as Figure 3 and Figure 4 Components use the same designation and their descriptions may be omitted. Figure 11 In the embodiment shown, except that the through-substrate via (TSV) T2 has an inverted tapering shape, its structure is substantially similar to Figure 10 The embodiment shown. In this embodiment, the through-substrate via (TSV) T2 is formed after a bonding fabrication process between the first semiconductor die 200' and the second semiconductor die 300. After the bonding fabrication process, the substrate 315 of the second semiconductor die 300 is thinned from its second surface 302b. Then, the through-substrate via (TSV) T2 is formed within the second semiconductor die 300 and extends through the substrate 315 to electrically couple the wiring layer 316. The through-substrate via (TSV) T2 may have an upper surface coplanar with the surface 302b of the substrate 315, which is located away from the first semiconductor die 200'. In some embodiments, an insulating layer 312 is formed to cover the second surface 302b of the second semiconductor die 300, and a power input pad 314P is formed within the insulating layer 312 and electrically coupled to the through-substrate via (TSV) T2. In this embodiment, the through-substrate via (TSV) T2 is formed after a bonding fabrication process. The through-substrate via (TSV) T2 also has an inverted tapering shape. For example, the width of the first end of the through-substrate via (TSV) T2 adjacent to the first semiconductor die 200' is smaller than the width of the second end of the through-substrate via (TSV) T2 away from the first semiconductor die 200'.

[0127] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can modify and combine the above-described embodiments without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: The first semiconductor die has a front side and a back side opposite to the front side, and includes a plurality of first active elements disposed adjacent to the front side of the first semiconductor die. The second semiconductor die has a first side bonded to the back side of the first semiconductor die and a second side relative to the first side, wherein the second semiconductor die includes a plurality of passive elements for managing power supply to the first semiconductor die.

2. The semiconductor device of claim 1, wherein the plurality of passive elements are configured to receive input power from a power source and to regulate or convert the power supply provided via the second side of the second semiconductor die.

3. The semiconductor device of claim 2, wherein the first semiconductor die comprises: The substrate has a front surface and a back surface that correspond to the front side and the back side of the first semiconductor die, respectively, wherein the plurality of first active elements are formed adjacent to the front surface; A first insulating layer is formed on the back side surface; as well as A first power pad is formed within the first insulating layer, wherein the first power pad is used to receive the power supply after it has been regulated or converted by the plurality of passive components.

4. The semiconductor device of claim 3, wherein the first semiconductor die further comprises: A second insulating layer is formed on the front surface of the substrate; and A multilayer internal connection structure is formed within the second insulating layer, wherein the multilayer internal connection structure includes multiple metal layers.

5. The semiconductor device of claim 4, further comprising: The top cover substrate covers the top of the second insulating layer, wherein the top cover substrate does not have active elements, passive elements, or conductors.

6. The semiconductor device of claim 4, wherein the second semiconductor die comprises: The device layer has a first surface and a second surface, which correspond to the first side and the second side of the second semiconductor die, respectively. A third insulating layer is formed on the first surface of the device layer and is in direct contact with the first insulating layer; The second power bonding pad is formed within the third insulating layer and is in direct contact with the first power bonding pad, wherein the second power bonding pad is used to receive the power supply after being converted by the plurality of passive components. as well as A power input pad is formed on the second surface of the device layer to receive the input power, wherein the thickness of the power input pad is greater than the thickness of each of the plurality of metal layers in the multilayer interconnect structure.

7. The semiconductor device as claimed in claim 6, The first semiconductor die further includes a first signal bonding pad formed within the first insulating layer; and in, The second semiconductor die also includes a second signal bonding pad formed within the third insulating layer and in direct contact with the first signal bonding pad; and a signal input / output pad formed on the second surface of the device layer and electrically coupled to a signal source.

8. The semiconductor device of claim 1, wherein the plurality of passive elements comprises a three-dimensional cylindrical or crown-shaped capacitor.

9. The semiconductor device of claim 1, wherein the second semiconductor die further comprises a plurality of second active elements electrically coupled to the plurality of passive elements.

10. The semiconductor device of claim 9, further comprising: Multiple thin-film inductors are formed on the second side of the second semiconductor die and are made of magnetic material.

11. The semiconductor device of claim 1, wherein the plurality of passive elements comprises a plurality of inductors.

12. The semiconductor device of claim 1, wherein the distance between one of the plurality of first active elements and the second semiconductor die is in the range of 1 μm to 5 μm.

13. The semiconductor device of claim 6, wherein the distance between one of the plurality of first active elements and the power input pad is in the range of 4 μm to 10 μm.

14. A semiconductor device, comprising: A first semiconductor die has a front side and a back side opposite to the front side, the first semiconductor die including a first processing unit and a second processing unit adjacent to the front side; The second semiconductor die has a first side bonded to the first semiconductor die and a second side opposite to the first side, and includes a first power conversion unit and a second power conversion unit. The first power conversion unit and the second power conversion unit are used to receive a first input voltage and a second input voltage from the second side of the second semiconductor die, respectively, and to provide a first output voltage to the first processing unit and a second output voltage to the second processing unit, respectively.

15. The semiconductor device of claim 14, wherein the first power conversion unit and the second power conversion unit are configured to receive the first input voltage and the second input voltage from a power source, wherein the first input voltage is substantially the same as the second input voltage.

16. A semiconductor package, comprising: A package substrate, including power input pads and signal input / output pads, is formed on the upper surface of the package substrate; The first conductive connector and the second conductive connector are electrically coupled to the power input pad and the signal input / output pad, respectively: Stacked structures, including: The upper semiconductor die includes a plurality of first transistors and has a front side and a back side relative to the front side; as well as The lower semiconductor die includes a plurality of capacitors and has a first side attached to the back side of the upper semiconductor die and a second side relative to the first side. The second side is electrically coupled to the power input pad of the package substrate via the first conductive connector.

17. The semiconductor package of claim 16, wherein the lower semiconductor die is electrically coupled to the signal input / output pad of the package substrate, and the lower semiconductor die further comprises: Semiconductor substrate; as well as A first through-substrate via and a second through-substrate via are formed within the semiconductor substrate and are electrically coupled to the first conductive connector and the second conductive connector, respectively.

18. The semiconductor package of claim 17, wherein the first through-substrate via is configured to receive a signal source provided from the upper semiconductor die or the substrate, and the second through-substrate via is configured to receive power provided from the power input pad of the substrate.

19. The semiconductor package of claim 17, wherein both the first through-substrate via and the second through-substrate via comprise: The first end is adjacent to the semiconductor die above and has a first size; as well as The second end, located away from the semiconductor grain above, has a second size different from the first size.

20. The semiconductor package of claim 16, further comprising a support die substantially flush with the lower semiconductor die and coupled to the back side of the upper semiconductor die, wherein the support die is electrically coupled to the signal input / output pad of the package substrate via the second conductive connector.

Images