Back power supply chip packaging structure and preparation method thereof

Abstract

According to the back power supply chip packaging structure and the preparation method thereof provided by the invention, the PN-type semiconductor heat dissipation assembly comprising the N-type semiconductor and the P-type semiconductor is formed on one side of the signal connection layer of the back power supply chip, so that a cold end and a hot end with temperature difference can be formed through the PN-type semiconductor heat dissipation assembly by utilizing a semiconductor heat dissipation principle; therefore, the size of the packaging structure is reduced, and the performance of the semiconductor device can be improved at the same time.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing technology and relates to a back-side power supply chip packaging structure and its preparation method. Background Technology

[0002] Currently, in advanced 2.5D or 3D semiconductor packaging, most methods use wiring on the front side of the chip to supply power to the chip, forming a power supply network. However, signal networks also exist in this area. Placing the power supply network on the front side of the chip causes the power supply network and signal network to share space. Since the power supply network often occupies a large space, reducing the overall package size is becoming increasingly challenging. This has led the industry to explore the feasibility of moving the power supply network to the back side of the chip, making backside power supply (Backside PDN) a hot technical topic.

[0003] In existing stacked integrated circuits, signal lines and power lines are vertically stacked and connected to form a two- or more-layered semiconductor device with active electronic components. Compared to two-dimensional systems, three-dimensional systems with increased chip density may exhibit high IR voltage drop (e.g., voltage drop), and the increased IR voltage drop leads to increased power consumption and the generation of a large amount of heat. If excessive heat cannot be dissipated in time, the sustained high temperature generated by the heat can damage the chip, thereby affecting the chip structure and performance.

[0004] Therefore, it is necessary to provide a back-side power supply chip packaging structure and its fabrication method. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a back-side power supply chip packaging structure and its preparation method, so as to solve the problem of heat dissipation in the back-side power supply chip packaging structure in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a method for fabricating a back-side power supply chip package structure, comprising the following steps:

[0007] Provide substrate;

[0008] An N-type semiconductor and a P-type semiconductor are formed in the substrate at intervals, and the first ends of the N-type semiconductor and the P-type semiconductor are exposed on the first surface of the substrate.

[0009] A first redistribution layer is formed on a first surface of the substrate, and the first redistribution layer is electrically connected to both the N-type semiconductor and the P-type semiconductor.

[0010] Thin the substrate from its second side to expose the second ends of the N-type semiconductor and the P-type semiconductor;

[0011] A second redistribution layer is formed on the second surface of the substrate, and the second redistribution layer is electrically connected to the N-type semiconductor and the P-type semiconductor;

[0012] A rear power supply chip is provided, the rear power supply chip including a power connection layer and a signal connection layer located on opposite sides;

[0013] The back power supply chip is bonded to the first redistribution layer, and the signal connection layer is electrically connected to the first redistribution layer;

[0014] A molding compound is formed on the first redistribution layer, the molding compound covering the back power supply chip;

[0015] A metal pillar is formed in the molding layer, and the first end of the metal pillar is electrically connected to the first redistribution layer. The electrically connected N-type semiconductor, P-type semiconductor, first redistribution layer, second redistribution layer and metal pillar together constitute a PN-type semiconductor heat dissipation component.

[0016] Thin the molding layer to expose the second end of the metal pillar and the power connection layer;

[0017] A third redistribution layer is formed on the encapsulation layer, and the third redistribution layer is electrically connected to the second end of the metal pillar and the power connection layer.

[0018] Metal bumps are formed on the third redistribution layer, and the metal bumps are electrically connected to the third redistribution layer.

[0019] Optionally, the method further includes the step of forming an isolation layer located on the sidewalls of the N-type semiconductor and the P-type semiconductor in the substrate.

[0020] Optionally, the isolation layer includes a silicon oxide layer and / or a silicon nitride layer.

[0021] Optionally, the PN-type semiconductor heat dissipation assembly is formed by stacking from bottom to top and electrically connecting each other.

[0022] Optionally, the number of layers of the PN-type semiconductor heat dissipation assembly stacked from bottom to top and electrically connected to each other includes N layers, where 2≤N≤10.

[0023] The present invention also provides a rear-side power supply chip packaging structure, the rear-side power supply chip packaging structure comprising:

[0024] Substrate;

[0025] An N-type semiconductor and a P-type semiconductor, wherein the N-type semiconductor and the P-type semiconductor both penetrate the substrate and are spaced apart;

[0026] A first redistribution layer is located on a first surface of the substrate and is electrically connected to both the N-type semiconductor and the P-type semiconductor.

[0027] A second redistribution layer is located on a second surface of the substrate and is electrically connected to the N-type semiconductor and the P-type semiconductor.

[0028] A rear-side power supply chip, comprising a power connection layer and a signal connection layer located on opposite sides, the rear-side power supply chip being bonded to the first redistribution layer, and the signal connection layer being electrically connected to the first redistribution layer;

[0029] A molding compound layer is located on the first redistribution layer, covering the back power supply chip and exposing the signal connection layer;

[0030] A metal pillar penetrates the molding layer, and a first end of the metal pillar is electrically connected to the first redistribution layer. The electrically connected N-type semiconductor, P-type semiconductor, first redistribution layer, second redistribution layer, and metal pillar together constitute a PN-type semiconductor heat dissipation assembly.

[0031] The third rewiring layer is located on the molding layer and is electrically connected to the second end of the metal pillar and the power connection layer.

[0032] A metal bump is located on the third redistribution layer and is electrically connected to the third redistribution layer.

[0033] Optionally, it includes the PN-type semiconductor heat dissipation assembly stacked from bottom to top and electrically connected to each other.

[0034] Optionally, the number of layers of the PN-type semiconductor heat dissipation assembly stacked from bottom to top and electrically connected to each other includes N layers, where 2≤N≤10.

[0035] Optionally, it may also include an isolation layer located on the sidewalls of the N-type semiconductor and the P-type semiconductor.

[0036] Optionally, the isolation layer includes a silicon oxide layer and / or a silicon nitride layer.

[0037] As described above, the back-side power supply chip packaging structure and its fabrication method of the present invention form a PN-type semiconductor heat dissipation component including N-type semiconductors and P-type semiconductors on one side of the signal connection layer of the back-side power supply chip. By utilizing the semiconductor heat dissipation principle, the PN-type semiconductor heat dissipation component forms a cold end and a hot end with a temperature difference to effectively dissipate heat from the back-side power supply chip, thereby reducing the size of the packaging structure while improving the performance of the semiconductor device. Attached Figure Description

[0038] Figure 1 The diagram shows the heat dissipation principle of the back-side power supply chip package structure prepared according to the present invention.

[0039] Figure 2 The diagram shows a process flow diagram for preparing the back-side power supply chip packaging structure in Embodiment 1 of the present invention.

[0040] Figures 3 to 13 The diagram shown is a schematic representation of the structure presented during the fabrication of the back-side power supply chip packaging structure in Embodiment 1 of the present invention.

[0041] Figures 14-16 The diagram shown is a schematic representation of the structure presented during the fabrication of the back-side power supply chip packaging structure in Embodiment 2 of the present invention.

[0042] Explanation of reference numerals in the attached figures

[0043] 100 substrate

[0044] 101 N-type semiconductor

[0045] 102 P-type semiconductor

[0046] 103 Isolation Layer

[0047] 210 First Rerouting Layer

[0048] 220 Second Rerouting Layer

[0049] 230 Third Rerouting Layer

[0050] 300 Backside Power Supply Chip

[0051] 301 Signal Connection Layer

[0052] 302 Power Connection Layer

[0053] 400 sealing layer

[0054] 500 metal columns

[0055] 600 metal bumps Detailed Implementation

[0056] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0057] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0058] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, when a layer is referred to as “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0059] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0060] The back-side power supply chip packaging structure provided in this application forms a PN-type semiconductor heat dissipation component, including the N-type semiconductor and the P-type semiconductor, on one side of the signal connection layer of the back-side power supply chip. By utilizing the semiconductor heat dissipation principle, the PN-type semiconductor heat dissipation component forms a cold end and a hot end with a temperature difference to effectively dissipate heat from the back-side power supply chip, thereby reducing the size of the packaging structure while improving the performance of the semiconductor device.

[0061] Among them, see Figure 1The working principle of the PN-type semiconductor heat dissipation component is illustrated. The power supply provides the energy required for electron flow. After the power is turned on, electrons start from the negative electrode (-), pass through the P-type semiconductor element and absorb heat, and release heat when they reach the N-type semiconductor element. Thus, each time an electron passes through an NP module, heat is transferred from one side to the other, creating a temperature difference and forming a hot and cold end. When the cold end comes into contact with the heat source, heat can be dissipated from the heat source.

[0062] Example 1

[0063] The following is in conjunction with the instruction manual. Figures 2 to 13 The following section provides a further description of the back-side power supply chip packaging structure and its fabrication method as described in this embodiment.

[0064] First, refer to Figure 2 and Figure 3 Step S1 is performed to provide substrate 100.

[0065] Specifically, the material of the substrate 100 may include glass, semiconductor, etc. The size of the substrate 100 is not limited here, but is preferably wafer-level, so as to improve production efficiency through subsequent processes such as dicing.

[0066] Next, refer to Figure 2 , Figures 3-5 In step S2, an N-type semiconductor 101 and a P-type semiconductor 102 are formed in the substrate 100 at intervals, and the first ends of the N-type semiconductor 101 and the P-type semiconductor 102 are exposed on the first surface of the substrate 100.

[0067] Specifically, the N-type semiconductor 101 and the P-type semiconductor 102 can be formed by ion implantation after forming a patterned mask. The order in which the N-type semiconductor 101 and the P-type semiconductor 102 are formed is not limited here. Figure 3 In this embodiment, the N-type semiconductor 101 is first formed using ion implantation, and then referred to... Figure 4 The P-type semiconductor 102 is formed using ion implantation. The dopant used in the N-type semiconductor 101 may include As, P, or other N-type dopants, or combinations thereof; the dopant used in the P-type semiconductor 102 may include B, Ga, In, or other P-type dopants, or combinations thereof. The depth of ion implantation and the doping concentration of the N-type semiconductor 101 and the P-type semiconductor 102 are not limited here.

[0068] In this embodiment, see Figure 6 and Figure 7Preferably, an isolation layer 103 is formed in the substrate 100 on the sidewalls of the N-type semiconductor 101 and the P-type semiconductor 102 to achieve electrical isolation. The step of forming the isolation layer 103 may include etching, deposition, and polishing steps to form the isolation layer 103 on the sidewalls of the N-type semiconductor 101 and the P-type semiconductor 102. The etching method may include dry etching, wet etching, or a combination thereof, and is not limited thereto. The deposition method may include atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or a combination thereof. The polishing method may include chemical mechanical polishing (CMP).

[0069] Next, refer to Figure 2 and Figure 8 Step S3 is executed, in which a first redistribution layer 210 is formed on the first surface of the substrate 100, and the first redistribution layer 210 is electrically connected to both the N-type semiconductor 101 and the P-type semiconductor 102.

[0070] Specifically, the first redistribution layer 210 includes metal wiring and a dielectric layer. The dielectric layer may be formed from polymers such as polybenzoxazole (PBO) and polyimide, or from inorganic dielectric materials such as silicon nitride and silicon oxide. The metal wiring may include materials such as aluminum, copper, tungsten, or alloys thereof. No excessive restrictions are placed here regarding the fabrication, specific structure, and material selection of the first redistribution layer 210.

[0071] Next, refer to Figure 2 and Figure 9 Step S4 is executed, thinning the substrate 100 from its second surface to expose the second ends of the N-type semiconductor 101 and the P-type semiconductor 102. The method for thinning the substrate 100 may include chemical mechanical polishing (CMP), etc., and is not excessively limited here.

[0072] Next, refer to Figure 2 and Figure 10 In step S5, a second redistribution layer 220 is formed on the second surface of the substrate 100, and the second redistribution layer 220 is electrically connected to the N-type semiconductor 101 and the P-type semiconductor 102.

[0073] Specifically, the second redistribution layer 220 includes metal wiring and a dielectric layer. The dielectric layer can be formed from polymers such as polybenzoxazole (PBO) and polyimide, or from inorganic dielectric materials such as silicon nitride and silicon oxide. The metal wiring can include materials such as aluminum, copper, tungsten, or alloys thereof. No excessive restrictions are placed here regarding the fabrication, specific structure, and material selection of the second redistribution layer 220. The second redistribution layer 220 allows the spaced N-type semiconductor 101 and P-type semiconductor 102 to be electrically connected, facilitating the subsequent formation of a closed circuit.

[0074] Next, refer to Figure 2 and Figure 11 Step S6 is executed, providing a rear power supply chip 300, which includes a power connection layer 302 and a signal connection layer 301 located on opposite sides. The specific structure and type of the rear power supply chip 300 are not excessively limited here.

[0075] Next, refer to Figure 2 and Figure 11 In step S7, the back power supply chip 300 is bonded to the first redistribution layer 210, and the signal connection layer 301 is electrically connected to the first redistribution layer 210.

[0076] Specifically, along the horizontal direction, the signal connection layers 301 of the multiple back power supply chips 300 can be electrically connected through the first redistribution layer 210, and through the first redistribution layer 210, the heat generated by the back power supply chip 300 can be transferred to the N-type semiconductor 101 and the P-type semiconductor 102 to achieve good heat dissipation.

[0077] Next, refer to Figure 2 and Figure 12 Step S8 is executed, forming a molding compound 400 on the first redistribution layer 210, the molding compound 400 covering the back power supply chip 300.

[0078] Specifically, the method of forming the molding compound 400 may include, but is not limited to, compression molding, transfer molding and spin coating. The material of the molding compound 400 may include, but is not limited to, epoxy resin and polyamide. No excessive restrictions are placed here on the material and preparation method of the molding compound 400.

[0079] Next, refer to Figure 2 and Figure 12In step S9, a metal pillar 500 is formed in the molding layer 400, and the first end of the metal pillar 500 is electrically connected to the first redistribution layer 210; wherein, the electrically connected N-type semiconductor 101, P-type semiconductor 102, first redistribution layer 210, second redistribution layer 220 and metal pillar 500 combine to form a heat dissipation assembly for the PN-type semiconductor 101, as shown below. Figure 13 In the diagram, the lines with arrows indicate the circuit path of the PN-type semiconductor heat dissipation component.

[0080] Specifically, the metal pillar 500 can be formed by etching and electroplating, and the metal pillar 500 can provide a current path for the N-type semiconductor 101, the P-type semiconductor 102 and the semiconductor.

[0081] Next, refer to Figure 2 and Figure 12 In step S10, the molding layer 400 is thinned to expose the second end of the metal pillar 500 and the power connection layer 302.

[0082] Specifically, the thinning method can be CMP, but it is not limited to this. During polishing, the second end of the metal pillar 500 and the power connection layer 302 can be exposed, facilitating subsequent electrical connections.

[0083] Next, refer to Figure 2 and Figure 13 In step S11, a third redistribution layer 230 is formed on the molding layer 400. The third redistribution layer 230 is electrically connected to the second end of the metal pillar 500 and the power connection layer 302.

[0084] Specifically, the third redistribution layer 230 includes metal wiring and a dielectric layer. The dielectric layer may be formed from polymers such as polybenzoxazole (PBO) and polyimide, or from inorganic dielectric materials such as silicon nitride and silicon oxide. The metal wiring may include materials such as aluminum, copper, tungsten, or alloys thereof. No excessive restrictions are placed here regarding the fabrication, specific structure, and material selection of the third redistribution layer 230.

[0085] Next, refer to Figure 2 and Figure 13 In step S12, a metal bump 600 is formed on the third redistribution layer 230, and the metal bump 600 is electrically connected to the third redistribution layer 230.

[0086] Specifically, the metal bump 600 may include, for example, solder ball bumps, C4 metal bumps 600, copper pillar bumps, etc. The specific type and material of the metal bump 600 are not limited here.

[0087] See Figures 3 to 13 This embodiment also provides a back-side power supply chip packaging structure. The back-side power supply chip packaging structure can be prepared by the above-described preparation method, but is not limited thereto. In this embodiment, the back-side power supply chip packaging structure is directly prepared by the above-described preparation process. Therefore, the material, preparation method and structure of the back-side power supply chip packaging structure can be referred to the above-described preparation method.

[0088] The back-side power supply chip packaging structure includes:

[0089] Substrate 100;

[0090] N-type semiconductor 101 and P-type semiconductor 102, both of which penetrate the substrate 100 and are spaced apart;

[0091] A first redistribution layer 210 is located on a first surface of the substrate 100, and the first redistribution layer 210 is electrically connected to both the N-type semiconductor 101 and the P-type semiconductor 102.

[0092] A second redistribution layer 220 is located on a second surface of the substrate 100 and is electrically connected to the N-type semiconductor 101 and the P-type semiconductor 102.

[0093] The back power supply chip 300 includes a power connection layer 302 and a signal connection layer 301 located on opposite sides. The back power supply chip 300 is bonded to the first redistribution layer 210, and the signal connection layer 301 is electrically connected to the first redistribution layer 210.

[0094] A molding layer 400 is located on the first redistribution layer 210, covers the back power supply chip 300, and exposes the signal connection layer 301;

[0095] A metal pillar 500 penetrates the molding layer 400, and the first end of the metal pillar 500 is electrically connected to the first redistribution layer 210. The electrically connected N-type semiconductor 101, P-type semiconductor 102, first redistribution layer 210, second redistribution layer 220 and metal pillar 500 together constitute a heat dissipation assembly for PN-type semiconductor 101.

[0096] The third redistribution layer 230 is located on the molding layer 400 and is electrically connected to the second end of the metal pillar 500 and the power connection layer 302.

[0097] A metal bump 600 is located on the third redistribution layer 230 and is electrically connected to the third redistribution layer 230.

[0098] It also includes an isolation layer 103 located on the sidewalls of the N-type semiconductor 101 and the P-type semiconductor 102, the isolation layer 103 may include a silicon oxide layer and / or a silicon nitride layer.

[0099] Example 2

[0100] See Figures 3 to 16 This embodiment also provides a back-side power supply chip packaging structure with a stacked structure and its fabrication method. The main difference between this embodiment and Embodiment 1 is that the back-side power supply chip packaging structure includes PN-type semiconductor heat dissipation components stacked from bottom to top and electrically connected to each other, in order to further improve heat dissipation performance. The following only describes the differences; other information regarding the back-side power supply chip packaging structure, materials, and fabrication steps can be found in Embodiment 1 and will not be repeated here.

[0101] Among them, see Figure 14 In this embodiment, based on the requirements of Embodiment 1, Figure 10 The structures prepared in, such as Figure 15 In this context, the structure is denoted as A. Based on this structure A, metal pillars 500 are fabricated that are electrically connected to the first redistribution layer 210 and penetrate the substrate 100 and the second redistribution layer 220, to form a structure as described above. Figure 15 The structure denoted as B in the diagram is used to provide a current path for the stacked PN-type semiconductor heat dissipation components via the metal pillar 500.

[0102] Among them, see Figure 15 In this embodiment, the A structure and the B structure are stacked by bonding to form a four-layer PN-type semiconductor heat dissipation component that is stacked from bottom to top and electrically connected to each other. However, the number of stacked PN-type semiconductor heat dissipation components is not excessively limited here. For example, it may include N layers of PN-type semiconductor heat dissipation components stacked from bottom to top, wherein the range of N can be 2≤N≤10, etc. The value of N is not limited here.

[0103] In summary, the back-side power supply chip packaging structure and its fabrication method of the present invention form a PN-type semiconductor heat dissipation component including N-type semiconductors and P-type semiconductors on one side of the signal connection layer of the back-side power supply chip. By utilizing the semiconductor heat dissipation principle, the PN-type semiconductor heat dissipation component forms a cold end and a hot end with a temperature difference to effectively dissipate heat from the back-side power supply chip, thereby reducing the size of the packaging structure while improving the performance of the semiconductor device.

[0104] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a back-side power supply chip packaging structure, characterized in that, Includes the following steps: Provide substrate; An N-type semiconductor and a P-type semiconductor are formed in the substrate at intervals, and the first ends of the N-type semiconductor and the P-type semiconductor are exposed on the first surface of the substrate. A first redistribution layer is formed on a first surface of the substrate, and the first redistribution layer is electrically connected to both the N-type semiconductor and the P-type semiconductor. Thin the substrate from its second side to expose the second ends of the N-type semiconductor and the P-type semiconductor; A second redistribution layer is formed on the second surface of the substrate, and the second redistribution layer is electrically connected to the N-type semiconductor and the P-type semiconductor; A rear power supply chip is provided, the rear power supply chip including a power connection layer and a signal connection layer located on opposite sides; The back power supply chip is bonded to the first redistribution layer, and the signal connection layer is electrically connected to the first redistribution layer; A molding compound is formed on the first redistribution layer, the molding compound covering the back power supply chip; A metal pillar is formed in the molding layer, and the first end of the metal pillar is electrically connected to the first redistribution layer. The electrically connected N-type semiconductor, P-type semiconductor, first redistribution layer, second redistribution layer and metal pillar together constitute a PN-type semiconductor heat dissipation component. Thin the molding layer to expose the second end of the metal pillar and the power connection layer; A third redistribution layer is formed on the encapsulation layer, and the third redistribution layer is electrically connected to the second end of the metal pillar and the power connection layer. Metal bumps are formed on the third redistribution layer, and the metal bumps are electrically connected to the third redistribution layer.

2. The method for fabricating the back-side power supply chip packaging structure according to claim 1, characterized in that: It also includes the step of forming an isolation layer in the substrate located on the sidewalls of the N-type semiconductor and the P-type semiconductor.

3. The method for fabricating the back-side power supply chip packaging structure according to claim 1, characterized in that: The isolation layer includes a silicon oxide layer and / or a silicon nitride layer.

4. The method for fabricating the back-side power supply chip packaging structure according to claim 1, characterized in that: The PN-type semiconductor heat dissipation assembly is formed by stacking the components from bottom to top and electrically connecting them to each other.

5. The method for fabricating the back-side power supply chip packaging structure according to claim 4, characterized in that: The number of layers of the PN-type semiconductor heat dissipation assembly, which is stacked from bottom to top and electrically connected to each other, includes N layers, where 2≤N≤10.

6. A rear-side power supply chip packaging structure, characterized in that, The rear power supply chip packaging structure includes: Substrate; An N-type semiconductor and a P-type semiconductor, wherein the N-type semiconductor and the P-type semiconductor both penetrate the substrate and are spaced apart; A first redistribution layer is located on a first surface of the substrate and is electrically connected to both the N-type semiconductor and the P-type semiconductor. A second redistribution layer is located on a second surface of the substrate and is electrically connected to the N-type semiconductor and the P-type semiconductor. A rear-side power supply chip, comprising a power connection layer and a signal connection layer located on opposite sides, the rear-side power supply chip being bonded to the first redistribution layer, and the signal connection layer being electrically connected to the first redistribution layer; A molding compound layer is located on the first redistribution layer, covering the back power supply chip and exposing the signal connection layer; A metal pillar penetrates the molding compound, and a first end of the metal pillar is electrically connected to the first redistribution layer, wherein the electrically connected N-type semiconductor, P-type semiconductor, first redistribution layer, and [other components] are [connected to the molding compound]. The second redistribution layer and the metal pillars together constitute a PN-type semiconductor heat dissipation assembly. The third rewiring layer is located on the molding layer and is electrically connected to the second end of the metal pillar and the power connection layer. A metal bump is located on the third redistribution layer and is electrically connected to the third redistribution layer.

7. The back-side power supply chip packaging structure according to claim 6, characterized in that: It includes the PN-type semiconductor heat dissipation assembly that is stacked from bottom to top and electrically connected to each other.

8. The back-side power supply chip packaging structure according to claim 7, characterized in that: The number of layers of the PN-type semiconductor heat dissipation assembly, which is stacked from bottom to top and electrically connected to each other, includes N layers, where 2≤N≤10.

9. The back-side power supply chip packaging structure according to claim 6, characterized in that: It also includes an isolation layer located on the sidewalls of the N-type semiconductor and the P-type semiconductor.

10. The back-side power supply chip packaging structure according to claim 6, characterized in that: The isolation layer includes a silicon oxide layer and / or a silicon nitride layer.

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