Semiconductor element structure with transistor and resistor and manufacturing method thereof

Abstract

The invention discloses a semiconductor element structure with a transistor and a resistor and a manufacturing method thereof. The semiconductor device structure includes: a substrate; the transistor and the resistor are arranged in the substrate; a plurality of isolation structures disposed in the substrate; the dielectric layer is arranged on the substrate; and an interconnection structure disposed over the transistor and the resistor and electrically connected to the transistor and the resistor. The transistor is disposed between one pair of the plurality of isolation structures, and the resistor is disposed between another pair of the plurality of isolation structures.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Patent Application No. 18 / 823,948 (priority date: September 4, 2024), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a semiconductor device structure and a method for manufacturing the same, and more specifically, to a semiconductor device structure having a transistor and a resistor and a method for manufacturing the same. Background Technology

[0004] Semiconductor components are used in a wide range of electronic applications, including personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components continues to shrink to meet the ever-increasing demands for computing power. However, the challenges brought about by this shrinking size are becoming increasingly frequent and impactful. Therefore, challenges remain in improving quality, yield, performance, and reliability while reducing complexity.

[0005] The manufacturing and integration of semiconductor devices involves many complex steps and operations. The integration of semiconductor devices is becoming increasingly complex. This increased complexity in manufacturing and integrating semiconductor devices can lead to defects. For example, smaller resistors formed using conventional processes may exhibit insufficient chip resistance. Therefore, continuous improvement of semiconductor device structure and manufacturing processes is necessary to address these defects and enhance performance.

[0006] The discussion in the prior art paragraph is for background information only. The statements in the discussion of the prior art paragraph are not an admission that the content disclosed in this paragraph constitutes prior art to this disclosure, and nothing in the discussion of the prior art paragraph shall be construed as an admission that any part of this application, including the part in the discussion of the prior art paragraph, constitutes prior art to this disclosure. Summary of the Invention

[0007] One aspect of this disclosure provides a semiconductor device structure. This semiconductor device structure includes: a substrate; a transistor and a resistor disposed in the substrate; a plurality of isolation structures disposed in the substrate, wherein the transistor is disposed between one pair of the plurality of isolation structures, and the resistor is disposed between another pair of the plurality of isolation structures; a dielectric layer disposed on the substrate; and an interconnect structure disposed on the transistor and the resistor and electrically connected to the transistor and the resistor.

[0008] In some embodiments, the transistor includes: a gate electrode; a plurality of source / drain regions disposed on both sides of the gate electrode; and a first portion of the dielectric layer disposed between the gate electrode and the substrate.

[0009] In some embodiments, the resistor includes: a resistive electrode; a well region disposed below the resistive electrode; and a second portion of the dielectric layer disposed between the resistive electrode and the well region.

[0010] In some embodiments, one of the plurality of isolation structures is disposed between the transistor and the resistor, and the isolation structure is closer to the resistor than to the transistor.

[0011] In some embodiments, the interconnect structure includes: a plurality of conductive contacts disposed on corresponding plurality of source / drain regions of the transistor; a plurality of conductive vias disposed on the resistor electrode of the resistor and electrically connected to the resistor electrode of the resistor; and a plurality of conductive layers disposed on the plurality of conductive contacts and the plurality of conductive vias and electrically connected to the plurality of source / drain regions of the transistor and the resistor electrode of the resistor.

[0012] In some embodiments, the plurality of conductive contacts penetrate the dielectric layer and enter the plurality of source / drain regions.

[0013] In some embodiments, each of the plurality of conductive contacts includes: a conductive via surrounded by a barrier layer.

[0014] In some embodiments, the barrier layer includes a first thickness on the plurality of sidewalls of the respective plurality of conductive vias and a second thickness under the plurality of bottom surfaces of the respective plurality of conductive vias.

[0015] In some embodiments, the first thickness of the barrier layer is less than the second thickness of the barrier layer.

[0016] In some embodiments, the semiconductor device structure further includes: an inter-dielectric layer disposed between the dielectric layer and the conductive layer, and surrounding the plurality of conductive contacts and the plurality of conductive vias of the interconnect structure.

[0017] Another aspect of this disclosure provides a semiconductor device structure. This semiconductor device structure includes: a plurality of source / drain regions disposed in a substrate; a dielectric layer disposed above the source / drain regions; and a conductive contact penetrating the dielectric layer and entering the source / drain regions. The conductive contact includes: a conductive via; and a barrier layer covering a plurality of sidewalls and a bottom surface of the conductive via. A first thickness of the barrier layer on the plurality of sidewalls of the conductive via is less than a second thickness of the barrier layer below the bottom surface of the conductive via.

[0018] In some embodiments, the semiconductor device structure further includes: an interlayer dielectric layer disposed on the dielectric layer and surrounding the conductive contact; and a conductive layer disposed on the interlayer dielectric layer.

[0019] In some embodiments, the semiconductor device structure further includes: an isolation structure disposed in the substrate to define a first active region and a second active region; and a conductive structure disposed in the substrate and on the isolation structure.

[0020] In some embodiments, the semiconductor device structure further includes: a gate electrode disposed in the first active region and located between the plurality of source / drain regions, and a resistor electrode disposed in a well region in the second active region.

[0021] In some embodiments, the gate electrode is electrically connected to the resistive electrode via the conductive structure.

[0022] In some embodiments, a first portion of the dielectric layer is disposed between the gate electrode and the substrate, and a second portion of the dielectric layer is disposed between the resistive electrode and the well region.

[0023] Another aspect of this disclosure provides a semiconductor device structure. This semiconductor device structure includes: a substrate having a plurality of isolation structures therein, wherein the plurality of isolation structures define a first active region and a second active region of the substrate; a plurality of source / drain regions disposed in the first active region, and a well region disposed in the second active region; a gate electrode and a resistor electrode disposed in the substrate, wherein the gate electrode is disposed between one pair of the plurality of source / drain regions, and the resistor electrode is disposed above the well region; a dielectric layer disposed on the substrate, wherein a first portion of the dielectric layer is disposed between the gate electrode and the substrate, and a second portion of the dielectric layer is disposed between the resistor electrode and the substrate; an interlayer dielectric layer disposed on the dielectric layer, the gate electrode, and the resistor electrode; a plurality of conductive contacts disposed on the plurality of source / drain regions; and a plurality of conductive layers disposed on the interlayer dielectric layer.

[0024] In some embodiments, each of the plurality of conductive contacts includes: a lower portion protruding into a corresponding source / drain region; and an upper portion disposed on the lower portion and between a top surface of the substrate and the conductive layer.

[0025] In some embodiments, the lower portions of the plurality of conductive contacts in the substrate do not directly contact any of the plurality of isolation structures in the substrate.

[0026] In some embodiments, the plurality of lower portions of the plurality of conductive contacts include a first critical dimension, and the plurality of upper portions of the plurality of conductive contacts include a second critical dimension, wherein the second critical dimension is greater than the first critical dimension.

[0027] In some embodiments, the first critical dimension of the plurality of lower portions gradually decreases at locations where the distance from the top surface of the substrate increases, and the second critical dimension of the plurality of upper portions remains constant.

[0028] In some embodiments, the plurality of outer peripheral surfaces of the plurality of lower portions of the plurality of conductive contacts are discontinuous with the plurality of outer peripheral surfaces of the plurality of upper portions of the plurality of conductive contacts.

[0029] In some embodiments, the well region is adjacent to the plurality of isolation structures in the second active region.

[0030] In some embodiments, the semiconductor device structure further includes a plurality of conductive vias disposed on and electrically connected to the resistive electrode.

[0031] In some embodiments, the plurality of conductive contacts, the plurality of conductive vias, and the conductive layer together constitute an interconnect structure.

[0032] Another aspect of this disclosure provides a semiconductor device structure. This semiconductor device structure includes: a source / drain region disposed in a substrate; a conductive layer disposed on the substrate; and a conductive contact including: a lower portion protruding into the source / drain region; and an upper portion disposed on the lower portion and between the top surface of the substrate and the conductive layer.

[0033] In some embodiments, the lower portion of the conductive contact includes a first critical dimension, and the upper portion of the conductive contact includes a second critical dimension, wherein the second critical dimension is greater than the first critical dimension.

[0034] In some embodiments, the semiconductor device structure further includes a plurality of isolation structures disposed in the substrate, wherein the lower portion of the conductive contact in the substrate does not directly contact any of the plurality of isolation structures in the substrate.

[0035] In some embodiments, the first critical dimension of the lower portion gradually decreases at locations where the distance from the top surface of the substrate increases, while the second critical dimension of the upper portion remains constant.

[0036] In some embodiments, an outer peripheral surface of the lower portion of the conductive contact is discontinuous with an outer peripheral surface of the upper portion of the conductive contact.

[0037] Another aspect of this disclosure provides a method for manufacturing a semiconductor device. This method includes: providing a semiconductor substrate; forming a plurality of isolation structures and a well region in the semiconductor substrate; recessing the semiconductor substrate to form a plurality of openings between the plurality of isolation structures; depositing a dielectric layer on the semiconductor substrate to form a first opening and a second opening in the substrate, wherein the dielectric layer extends into the first opening and the second opening; forming an electrode layer on the dielectric layer, wherein the electrode layer fills the first opening and the second opening; performing one or more ion implantation processes on the electrode layer; and polishing the electrode layer to form a gate. A gate electrode and a resistor electrode are formed; multiple source / drain regions are formed on the semiconductor substrate and on opposite sides of the gate electrode; an interlayer dielectric layer is formed on the dielectric layer; the interlayer dielectric layer and the dielectric layer are etched to form a third opening and a fourth opening in the interlayer dielectric layer, and an etched interlayer dielectric layer is formed on the semiconductor substrate; multiple conductive contacts are formed in the third opening, and multiple conductive vias are formed in the fourth opening; and an interconnect structure is formed on the etched interlayer dielectric layer, the multiple conductive contacts and the multiple conductive vias.

[0038] In some embodiments, forming the plurality of conductive contacts in the third opening and forming the plurality of conductive vias in the fourth opening includes: forming a sacrificial liner on a plurality of sidewalls of the third opening; performing an etching process to form a contact hole communicating with the third opening in the source / drain region; removing the sacrificial liner to form a fifth opening; and filling the fourth opening, the fifth opening and the contact hole with a conductive material.

[0039] In some embodiments, the conductive contact includes: a lower portion disposed in the source / drain region; and an upper portion disposed above the lower portion, wherein the upper portion is located between a top surface of the semiconductor substrate and the interconnect structure.

[0040] In some embodiments, the lower portion includes a first critical dimension, and the upper portion includes a second critical dimension, wherein the second critical dimension is larger than the first critical dimension.

[0041] In some embodiments, the first critical dimension of the lower portion gradually decreases at locations where the distance from the top surface of the substrate increases, while the second critical dimension of the upper portion remains constant.

[0042] This disclosure provides embodiments of semiconductor device structures. The semiconductor device structure includes transistors (e.g., P-type metal-oxide-semiconductor transistors or N-type metal-oxide-semiconductor transistors) and resistors, which are connected in series and formed by an integration process. Specifically, the gate electrode of the transistor and the resistive electrode of the resistor are formed in the semiconductor substrate by the same process steps. Therefore, the resistor can exhibit high sheet resistance without the need for additional masks or process steps. This reduces associated costs and improves the performance of the semiconductor device structure.

[0043] The technical features and advantages of this disclosure have been broadly summarized above, thus providing a preferred understanding of the detailed description of this disclosure that follows. Other features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0044] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the accompanying drawings in conjunction with the embodiments and claims. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features can be arbitrarily increased or decreased.

[0045] Figure 1 This is a cross-sectional view illustrating the semiconductor device structure of some embodiments of this disclosure.

[0046] Figure 2 yes Figure 1 Circuit diagram of semiconductor element structure.

[0047] Figure 3 This is a cross-sectional view illustrating a modified semiconductor device structure according to some embodiments of the present disclosure.

[0048] Figure 4 This is a cross-sectional view illustrating another modified semiconductor device structure according to some embodiments of this disclosure.

[0049] Figure 5 This is a cross-sectional view illustrating another modified semiconductor device structure according to some embodiments of the present disclosure.

[0050] Figure 6 This is a flowchart illustrating a method for manufacturing a semiconductor device structure according to some embodiments of the present disclosure.

[0051] Figure 7This is a cross-sectional view illustrating an intermediate stage in the fabrication of isolation structures and well regions during the formation of a semiconductor element structure according to some embodiments of the present invention.

[0052] Figure 8 This is a cross-sectional view illustrating an intermediate stage in the formation of an opening between isolation structures during the formation of a semiconductor element structure according to some embodiments of the present invention.

[0053] Figure 9 This is a cross-sectional view illustrating an intermediate stage in the fabrication of a dielectric layer during the formation of a semiconductor device structure according to some embodiments of the present invention.

[0054] Figure 10 This is a cross-sectional view illustrating an intermediate stage in the fabrication of an electrode layer during the formation of a semiconductor device structure according to some embodiments of the present invention.

[0055] Figure 11 This is a cross-sectional view illustrating an intermediate stage of ion implantation of an electrode layer during the formation of a semiconductor device structure according to some embodiments of the present invention.

[0056] Figure 12 This is a cross-sectional view illustrating an intermediate stage of ion implantation of an electrode layer during the formation of a semiconductor device structure according to some embodiments of the present invention.

[0057] Figure 13 This is a cross-sectional view illustrating an intermediate stage of grinding the electrode layer during the formation of a semiconductor device structure according to some embodiments of the present invention.

[0058] Figure 14 This is a cross-sectional view illustrating an intermediate stage in the fabrication of source / drain regions during the formation of a semiconductor device structure according to some embodiments of the present invention.

[0059] Figure 15 This is a cross-sectional view illustrating an intermediate stage in the fabrication of an interlayer dielectric layer during the formation of a semiconductor device structure according to some embodiments of the present invention.

[0060] Figure 16 This is a cross-sectional view illustrating an intermediate stage in the fabrication of a patterned mask over an interlayer dielectric layer during the formation of a semiconductor device structure according to some embodiments of the present invention.

[0061] Figure 17 This is a cross-sectional view illustrating a stage during the formation of a semiconductor device structure, in which interlayer dielectric layers and intermediate dielectric layers are partially removed, according to some embodiments of the present invention.

[0062] Figure 18 This is a cross-sectional view illustrating an intermediate stage of ion implantation of an electrode layer during the formation of a semiconductor device structure according to some embodiments of the present invention.

[0063] Figure 19 This is a cross-sectional view illustrating an intermediate stage of ion implantation of an electrode layer during the formation of a semiconductor device structure according to some embodiments of the present invention.

[0064] Figure 20 This is a cross-sectional view illustrating an intermediate stage in the fabrication of an opening in a semiconductor substrate during the formation of a semiconductor element structure according to some embodiments of the present invention.

[0065] Figure 21 This is a cross-sectional view illustrating an intermediate stage in the fabrication of a conductive layer during the formation of a semiconductor device structure according to some embodiments of the present invention.

[0066] Figure 22 This is a cross-sectional view illustrating an intermediate stage in the fabrication of a conductive structure during the formation of a semiconductor element structure according to some embodiments of the present invention.

[0067] Figure 23 This is a cross-sectional view illustrating an intermediate stage in the fabrication of a substrate during the formation of a semiconductor device structure according to some embodiments of the present invention.

[0068] Figure 24 This is a cross-sectional view illustrating an intermediate stage in the fabrication of contact holes during the formation of a semiconductor element structure according to some embodiments of the present invention.

[0069] Figure 25 This is a cross-sectional view illustrating an intermediate stage during the formation of a semiconductor device structure after the removal of the substrate, according to some embodiments of the present invention.

[0070] The reference numerals in the attached figures are explained as follows:

[0071] 10: Method

[0072] 100: Transistor

[0073] 100P: P-type metal-oxide-semiconductor transistor

[0074] 100N: N-type metal-oxide-semiconductor transistor

[0075] 101: Semiconductor substrate

[0076] 101T: Top Surface

[0077] 103: Well Area

[0078] 105a: Isolation structure

[0079] 105b: Isolation Structure

[0080] 105c: Isolation structure

[0081] 110a: Open

[0082] 110b: Open

[0083] 110a': Opening

[0084] 110b': Open

[0085] 107: Patterned Mask

[0086] 113: Dielectric layer

[0087] 113': Dielectric layer

[0088] 115: Electrode layer

[0089] 115a: Gate electrode

[0090] 115b: Resistance electrode

[0091] 117: Patterned Mask

[0092] 119: Patterned Mask

[0093] 121a: Source / Drain Region

[0094] 121b: Source / Drain Region

[0095] 123: Interlayer dielectric layer

[0096] 123': Interlayer dielectric layer

[0097] 123'T: Top surface

[0098] 125: Patterned Mask

[0099] 130a: Open

[0100] 130a': Opening

[0101] 130b: Open

[0102] 130b': Opening

[0103] 130c: Open

[0104] 130d: Opening

[0105] 130a1: Contact hole

[0106] 130b1: Contact hole

[0107] 131a: Barrier layer

[0108] 131b: Barrier Layer

[0109] 133a: Conductive via

[0110] 133a1: Lower part

[0111] 133a2: Upper part

[0112] 133a3: peripheral surface

[0113] 133a4: peripheral surface

[0114] 133aS: Sidewall

[0115] 133aB: Bottom surface

[0116] 133b: Conductive via

[0117] 133b1: Lower part

[0118] 133b2: Upper part

[0119] 133b3: peripheral surface

[0120] 133b4: peripheral surface

[0121] 133c: Conductive via

[0122] 133d: Conductive via

[0123] 134a: Conductive contact

[0124] 134b: Conductive contact

[0125] 135a: Conductive layer

[0126] 135b: Conductive layer

[0127] 135c: Conductive layer

[0128] 136a: Conductive contact

[0129] 136b: Conductive contact

[0130] 137: Interconnection Structure

[0131] 139: Patterned Mask

[0132] 140: Opening

[0133] 143: Conductive layer

[0134] 145: Conductive Structure

[0135] 160: Ion implantation process

[0136] 170: Ion implantation process

[0137] 180: Ion implantation process

[0138] 190: Ion implantation process

[0139] 200: Resistance

[0140] 202: Sacrificial Liner

[0141] 300a: Semiconductor device structure

[0142] 300b: Semiconductor Component Structure

[0143] 300c: Semiconductor device structure

[0144] 300d: Semiconductor device structure

[0145] 1131: Part One

[0146] 1133: Part Two

[0147] AA: Active Zone

[0148] BB: Active Zone

[0149] B1: Bottom surface

[0150] B2: Bottom surface

[0151] CD1: First critical size

[0152] CD2: Second critical size

[0153] T1: First thickness

[0154] T2: Second thickness

[0155] W1: Width

[0156] W2: Width

[0157] W3: Width

[0158] W4: Width

[0159] W5: Width

[0160] W6: Width

[0161] S11: Steps

[0162] S13: Steps

[0163] S15: Steps

[0164] S17: Steps

[0165] S19: Steps

[0166] S21-1: Steps

[0167] S21-2: Steps

[0168] S23-1: Steps

[0169] S23-2: Steps

[0170] S25: Steps

[0171] SW1: First sidewall

[0172] SW2: Second sidewall Detailed Implementation

[0173] This disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations described below are provided to simplify this disclosure. Of course, these are merely illustrative and not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature can include embodiments in which the first and second features are formed in direct contact, or embodiments in which an additional feature is formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, element symbols and / or letters may be repeated in various examples in this disclosure. Such repetition is for simplicity and clarity and is not in itself a limitation on the relationship between the various embodiments and / or configurations discussed.

[0174] Furthermore, for ease of description, spatially related terms such as "below," "under," "lower part," "above," "upper part," or other similar terms may be used herein to describe the relative relationship between one element or feature and another shown in the accompanying drawings. In addition to the orientations depicted in the figures, spatially related terms are intended to cover different orientations of the element in use or operation. The element may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relative descriptors used herein may be interpreted accordingly.

[0175] Figure 1 This is a cross-sectional view illustrating a semiconductor device structure 300a according to some embodiments of this disclosure. See also... Figure 1 The semiconductor device structure 300a includes a semiconductor substrate 101, a transistor 100, and a resistor 200. The semiconductor substrate 101 includes a plurality of isolation structures 105a, 105b, and 105c disposed therein. Isolation structures 105a and 105b define the active region AA of the transistor 100, and isolation structures 105b and 105c define the active region BB of the resistor 200. It should be noted that the number of isolation structures in the semiconductor device structure is not limited to three; it can be fewer or more.

[0176] In some embodiments, the semiconductor device structure 300a also includes a gate electrode 115a and source / drain (S / D) regions 121a and 121b in the active region AA of the transistor 100 (i.e., between the isolation structure 105a and the isolation structure 105b). The gate electrode 115a is located between the source / drain regions 121a and 121b, and the gate electrode 115a and the source / drain regions 121a and 121b are disposed in the semiconductor substrate 101.

[0177] In some embodiments, the semiconductor device structure 300a further includes a well region 103 and a resistive electrode 115b in the active region BB of the resistor 200 (i.e., between the isolation structure 105b and the isolation structure 105c). The well region 103 and the resistive electrode 115b are disposed in the semiconductor substrate 101, and the resistive electrode 115b is disposed on the well region 103. Furthermore, the well region 103 is adjacent to the isolation structures 105b and 105c. It should be noted that, according to some embodiments, the isolation structure 105b between the active region AA of the transistor 100 and the active region BB of the resistor 200 is closer to the resistive electrode 115b than to the gate electrode 115a.

[0178] Furthermore, according to some embodiments, the semiconductor device structure 300a includes a dielectric layer 113' disposed on the semiconductor substrate 101. Specifically, the dielectric layer 113' has a first portion 1131 and a second portion 1133, wherein the first portion 1131 and the second portion 1133 are below the top surface 101T of the semiconductor substrate 101, the first portion 1131 is located between the gate electrode 115a and the semiconductor substrate 101, and the second portion 1133 is located between the resistor electrode 115b and the semiconductor substrate 101. In some embodiments, the gate electrode 115a is separated from the semiconductor substrate 101 by the first portion 1131 of the dielectric layer 113', and the resistor electrode 115b is separated from the well region 103 in the semiconductor substrate 101 by the second portion 1133 of the dielectric layer 113'.

[0179] Furthermore, in some embodiments, the resistive electrode 115b is separated from the isolation structures 105b and 105c by a second portion 1133 of the dielectric layer 113'. In some embodiments, the isolation structures 105a, 105b, and 105c are covered by the dielectric layer 113', and the source / drain regions 121a and 121b are partially covered by the dielectric layer 113'.

[0180] See also Figure 1According to some embodiments, the semiconductor device structure 300a includes an interlayer dielectric layer 123' disposed above the dielectric layer 113', and an interconnect structure 137 disposed above the interlayer dielectric layer 123' and protruding into the interlayer dielectric layer 123'. More specifically, the interconnect structure 137 includes a plurality of conductive contacts 134a and 134b, a plurality of conductive vias 133c and 133d, and a plurality of conductive layers 135a, 135b, and 135c.

[0181] Conductive contact 134a may be disposed in interlayer dielectric layer 123' and may be electrically connected to source / drain region 121a. In some embodiments, conductive contact 134a includes barrier layer 131a and conductive via 133a surrounded by barrier layer 131a. Conductive via 133a may extend from top surface 123'T of interlayer dielectric layer 123', through interlayer dielectric layer 123' and dielectric layer 113', and reach top surface 101T of semiconductor substrate 101, and barrier layer 131a may extend into source / drain region 121a. It should be noted that barrier layer 131a has a first thickness T1 on sidewall 133aS of conductive via 133a, and barrier layer 131a has a second thickness T2 below bottom surface 133aB of conductive via 133a. In some embodiments, a barrier layer 131a is formed by an anisotropic deposition process, such that a first thickness T1 is less than a second thickness T2. In some embodiments, the anisotropic deposition process for forming the barrier layer 131a includes a physical vapor deposition (PVD) process. Similarly, in some embodiments, the conductive contact 134b includes the barrier layer 131b and a conductive via 133b surrounded by the barrier layer 131b. The characteristics of the conductive contact 134b are similar to those of the conductive contact 134a, and will not be described again here.

[0182] Conductive vias 133c and 133d can be disposed in the interlayer dielectric layer 123' and can be electrically connected to the resistive electrode 115b. In some embodiments, conductive vias 133c and 133d extend from the top surface 123'T of the interlayer dielectric layer 123', pass through the interlayer dielectric layer 123', and reach the top surface 101T of the semiconductor substrate 101.

[0183] Conductive layers 135a, 135b, and 135c are disposed on the interlayer dielectric layer 123'. In particular, a conductive contact 134a is disposed on the source / drain region 121a, and a conductive layer 135a is disposed on the conductive contact 134a. The source / drain region 121a is electrically connected to the conductive layer 135a via the conductive contact 134a, and the conductive layer 135a is used to electrically connect the source / drain region 121a to other components.

[0184] In some embodiments, a conductive contact 134b is provided on the source / drain region 121b, a conductive via 133c is provided on the portion of the resistive electrode 115b adjacent to the isolation structure 105b, and a conductive layer 135b is provided on the conductive contact 134b and the conductive via 133c. The conductive contact 134b and the conductive via 133c are covered by the conductive layer 135b. It should be noted that the source / drain region 121b of the transistor 100 is electrically connected to the resistive electrode 115b of the resistor 200 via the interconnect structure 137 (i.e., the conductive contact 134b, the conductive layer 135b, and the conductive via 133c). Therefore, the transistor 100 and the resistor 200 are connected in series.

[0185] In some embodiments, a conductive via 133d is provided on the portion of the resistive electrode 115b adjacent to the isolation structure 105c, and a conductive layer 135c is provided on the conductive via 133d. The resistive electrode 115b is electrically connected to the conductive layer 135c via the conductive via 133d, and the conductive layer 135c is used to electrically connect the resistor 200 to other components.

[0186] Figure 2 yes Figure 1 The circuit diagram of semiconductor element structure 300a is shown. (See also...) Figure 1 and Figure 2 The transistor 100 of the semiconductor device structure 300a can be a P-type metal-oxide-semiconductor (PMOS) transistor 100P, and the PMOS transistor 100P is connected in series with the resistor 200. Alternatively, the transistor 100 of the semiconductor device structure 300a can be an N-type metal-oxide-semiconductor (NMOS) transistor 100N, and the NMOS transistor 100N is connected in series with the resistor 200.

[0187] Figure 3 This is a cross-sectional view illustrating a modified semiconductor device structure 300b according to some embodiments of the present disclosure. Similar to... Figure 1 Semiconductor device structure 300a and semiconductor device structure 300b include transistor 100 and resistor 200. The difference between semiconductor device structure 300a and semiconductor device structure 300b lies in the connection method between transistor 100 and resistor 200.

[0188] See Figure 3According to some embodiments, the semiconductor device structure 300b includes a conductive structure 145 disposed in the semiconductor substrate 101 and above the isolation structure 105b. In some embodiments, the conductive structure 145 is covered by an interlayer dielectric layer 123', and the conductive structure 145 is disposed between the source / drain region 121b of the transistor 100 and the resistive electrode 115b of the resistor 200. It should be noted that the source / drain region 121b is electrically connected to the resistive electrode 115b via the conductive structure 145.

[0189] In some embodiments, the conductive structure 145 directly contacts the source / drain region 121b and the resistive electrode 115b, and the conductive structure 145 is not covered by the dielectric layer 113'. Furthermore, in some embodiments, the semiconductor device structure 300b does not contain conductive vias 133b and 133c, nor the conductive layer 135b, and the interconnect structure 137 of the semiconductor device structure 300b includes conductive contacts 134a (i.e., conductive vias 133a and barrier layer 131a), conductive vias 133d, and conductive layers 135a and 135c. Figure 2 It can be Figure 3 The circuit diagram of semiconductor element structure 300b is shown.

[0190] Figure 4 This is a cross-sectional view illustrating another modified semiconductor device structure 300c according to some embodiments of this disclosure. Similar to... Figure 1 Semiconductor device structure 300a and semiconductor device structure 300c include transistor 100 and resistor 200. The difference between semiconductor device structure 300a and semiconductor device structure 300c is that conductive contacts 134a and 134b in semiconductor device structure 300a are replaced by conductive contacts 136a and 136b in semiconductor device structure 300c.

[0191] See Figure 4According to some embodiments, the semiconductor device structure 300c includes conductive contacts 136a and 136b. Conductive contact 136a includes a lower portion 133a1 protruding into the source / drain region 121a and an upper portion 133a2 located between the top surface 101T of the semiconductor substrate 101 and the conductive layer 135a. Conductive contact 136b includes a lower portion 133b1 protruding into the source / drain region 121b and an upper portion 133b2 located between the top surface 101T of the semiconductor substrate 101 and the conductive layer 135b. The lower portions 133a1 and 133b1 of conductive contacts 136a and 136b extend into the semiconductor substrate 101, which can increase the contact area between the conductive contact 136a (or conductive contact 136b) and the semiconductor substrate 101 on which the transistor 100 is disposed. Therefore, the contact resistance between the gate electrode 115a and the conductive contact 136a (or conductive contact 136b) can be effectively reduced.

[0192] In some embodiments, the lower portions 133a1 and 133b1 of the conductive contacts 136a and 136b in the semiconductor substrate 101 do not directly contact any isolation structures 105a, 105b, and 105c in the semiconductor substrate 101. The lower portions 133a1 and 133b1 of the conductive contacts 136a and 136b are below the top surface 101T of the semiconductor substrate 101 and may have a first critical dimension CD1, while the upper portions 133a2 and 133b2 of the conductive contacts 136a and 136b are above the top surface 101T of the semiconductor substrate 101 and may have a second critical dimension CD2 greater than the first critical dimension CD1. In some embodiments, the first critical dimension CD1 gradually decreases at positions where the distance from the top surface 101T of the semiconductor substrate 101 increases, while the second critical dimension CD2 remains constant. Specifically, the outer peripheral surface 133a3 of the lower portion 133a1 of the conductive contact 136a is discontinuous with the outer peripheral surface 133a4 of the upper portion 133a2 of the conductive contact 136a, and the outer peripheral surface 133b3 of the lower portion 133b1 of the conductive contact 136b is discontinuous with the outer peripheral surface 133b4 of the upper portion 133b2 of the conductive contact 136b. It should be noted that the lower portion 133a1 and the upper portion 133a2 of the conductive contact 136a are made of polycrystalline silicon and are integrally formed. The lower portion 133b1 and the upper portion 133b2 of the conductive contact 136b are integrally formed using the same material as the lower portion 133a1 and the upper portion 133a2. Figure 2 It can be Figure 4 The circuit diagram of semiconductor element structure 300c is shown.

[0193] Figure 5 This is a cross-sectional view illustrating another modified semiconductor device structure 300d according to some embodiments of this disclosure. Similar to... Figure 4 Semiconductor device structure 300c and semiconductor device structure 300d include transistor 100 and resistor 200. The difference between semiconductor device structure 300c and semiconductor device structure 300d lies in the connection method between transistor 100 and resistor 200.

[0194] See Figure 5 According to some embodiments, the semiconductor device structure 300d includes a conductive structure 145 disposed in the semiconductor substrate 101 and above the isolation structure 105b. In some embodiments, the conductive structure 145 is covered by an interlayer dielectric layer 123', and the conductive structure 145 is disposed between the source / drain region 121b of the transistor 100 and the resistive electrode 115b of the resistor 200. It should be noted that the source / drain region 121b is electrically connected to the resistive electrode 115b via the conductive structure 145.

[0195] In some embodiments, the conductive structure 145 directly contacts the source / drain region 121b and the resistive electrode 115b, and the conductive structure 145 is not covered by the dielectric layer 113'. Furthermore, in some embodiments, the semiconductor device structure 300d does not contain the conductive contact 136b, the conductive via 133c, and the conductive layer 135b, and the interconnect structure 137 of the semiconductor device structure 300d includes the conductive contact 136a, the conductive via 133d, and the conductive layers 135a and 135c. Figure 2 It can be Figure 5 The circuit diagram of semiconductor element structure 300d is shown.

[0196] Figure 6 This is a flowchart illustrating a method 10 for manufacturing semiconductor device structures (e.g., semiconductor device structures 300a, 300b, 300c, and 300d). According to some embodiments, method 10 includes steps S11, S13, S15, S17, S19, S21-1, S21-2, S23-1, S23-2, and S25. (The last sentence appears to be incomplete and possibly refers to a different method.) Figures 7 to 25 And detailed explanation Figure 6 Steps S11 to S25 in the process.

[0197] Figures 7 to 17 This is a cross-sectional view illustrating an intermediate stage in the formation of a semiconductor element structure 300a according to some embodiments of the present invention.

[0198] See Figure 7A semiconductor substrate 101 is provided. The semiconductor substrate 101 may be a semiconductor wafer, such as a silicon wafer. In some embodiments, the semiconductor substrate 101 may include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Examples of elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor materials may include, but are not limited to, silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), indium aluminum arsenide (AlInAs), gallium aluminum arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), and / or indium gallium arsenide phosphide (GaInAsP).

[0199] In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 has an epitaxial layer covering a host semiconductor. In some embodiments, the semiconductor substrate 101 is an insulator-on-insulator (SOI) substrate, which may include a substrate, a buried oxide layer on the substrate, and a semiconductor layer on the buried oxide layer, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The SOI substrate can be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0200] See also Figure 7According to some embodiments, a plurality of isolation structures 105a, 105b, and 105c are formed in a semiconductor substrate 101, and a well region 103 is formed between isolation structures 105b and 105c. In some embodiments, isolation structures 105a, 105b, and 105c are shallow trench isolation (STI) structures. Furthermore, isolation structures 105a, 105b, and 105c can define a plurality of active regions, including an active region AA disposed between isolation structures 105a and 105b and an active region BB disposed between isolation structures 105b and 105c. The isolation structures 105a, 105b, and 105c may be made of silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials, and the formation of the isolation structures 105a, 105b, and 105c may include: forming a patterned mask on the semiconductor substrate 101; etching the semiconductor substrate 101 using the patterned mask as a mask to form an opening; depositing a dielectric material in the opening and on the semiconductor substrate 101; and polishing the dielectric material until the semiconductor substrate 101 is exposed.

[0201] In some embodiments, well region 103 is formed by an ion implantation process, and P-type dopant (e.g., boron (B), gallium (Ga), or indium (In)) or N-type dopant (e.g., phosphorus (P) or arsenic (As)) ions can be implanted into a portion of the semiconductor substrate 101 located between isolation structures 105b and 105c to form well region 103. In some embodiments, a patterned mask (not shown) covering the portion of the semiconductor substrate 101 located between isolation structures 105b and 105c can be used in the ion implantation process. The corresponding steps are as follows: Figure 6 Step S11 of method 10 is shown.

[0202] In some embodiments, isolation structures 105a, 105b, and 105c are formed before well region 103 is formed. In some embodiments, well region 103 is formed before isolation structures 105a, 105b, and 105c are formed. Furthermore, the bottom surface B1 of well region 103 is higher than the bottom surface B2 of isolation structures 105a, 105b, and 105c.

[0203] Next, according to some embodiments, a patterned mask 107 is formed on the semiconductor substrate 101, and the patterned mask 107 is used as an etching mask to recess the semiconductor substrate 101 to form openings 110a and 110b, as shown. Figure 8As shown. In some embodiments, opening 110a is located between isolation structure 105a and isolation structure 105b, and opening 110b is located between isolation structure 105b and isolation structure 105c. The corresponding steps are as follows. Figure 6 Step S13 of method 10 is shown.

[0204] A patterned mask 107 can be formed by a deposition process and a patterning process. The deposition process used to form the patterned mask 107 can be a chemical vapor deposition (CVD) process, a high-density plasma chemical vapor deposition (HDPCVD) process, a spin coating process, or other suitable processes. The patterning process for forming the patterned mask 107 can include a photolithography process and an etching process. The photolithography process can include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, and drying (e.g., hard baking). The etching process can include a dry etching process or a wet etching process.

[0205] After the patterned mask 107 is formed, the portion of the semiconductor substrate 101 exposed by the patterned mask 107 is partially removed by an etching process. The etching process can be a wet etching process, a dry etching process, or a combination thereof. In some embodiments, an opening 110b is formed by removing the upper portion of the well region 103, such that the opening 110b is formed on the resulting well region 103.

[0206] In some embodiments, the sidewalls of isolation structures 105b and 105c are partially exposed by openings 110b. For example, isolation structure 105b has a first sidewall SW1 facing isolation structure 105a and a second sidewall SW2 facing isolation structure 105c. The first sidewall SW1 is covered by semiconductor substrate 101, while the second sidewall SW2 is partially exposed by openings 110b. Furthermore, according to some embodiments, opening 110a has a width W1, and opening 110b has a width W2, wherein width W2 is greater than width W1. After forming openings 110a and 110b, patterned mask 107 can be removed.

[0207] According to some embodiments, a dielectric layer 113 is deposited on the semiconductor substrate 101, such as... Figure 9 As shown. In some embodiments, the dielectric layer 113 is compliantly deposited in the openings 110a and 110b, for example, on the sidewalls and bottom surfaces of the openings 110a and 110b, and the isolation structures 105a, 105b, and 105c are covered by the dielectric layer 113. The corresponding steps are as follows. Figure 6As shown in step S15 of method 10, after forming dielectric layer 113, reduced openings 110a' and 110b' are obtained.

[0208] In some embodiments, the dielectric layer 113 comprises silicon oxide, silicon nitride, silicon oxynitride, or multiple layers thereof. In some embodiments, the dielectric layer 113 is made of a high dielectric constant dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, or other similar materials. Furthermore, the dielectric layer 113 can be deposited using compliant deposition processes, such as chemical vapor deposition, atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), other suitable processes, or combinations thereof.

[0209] According to some embodiments, after forming the dielectric layer 113, an electrode layer 115 is formed on the dielectric layer 113, and the openings 110a' and 110b' in the semiconductor substrate 101 are filled by the electrode layer 115, such as... Figure 10 As shown. The corresponding steps are as follows. Figure 6 Step S17 of method 10 is shown.

[0210] In some embodiments, the electrode layer 115 is made of a semiconductor material, such as polycrystalline silicon. In some embodiments, the electrode layer 115 is deposited on the dielectric layer 113 using a chemical vapor deposition process, an atomic layer deposition process, a sputtering process, or one or more other suitable processes.

[0211] Next, according to some embodiments, a patterned mask 117 is formed to cover the active region BB (i.e., the active region of the subsequently formed resistor 200) located between the isolation structures 105b and 105c, and an ion implantation process 160 is performed on the portion of the electrode layer 115 exposed by the patterned mask 117, such as... Figure 11 As shown. In some embodiments, the portion of electrode layer 115 located above well region 103 is covered by patterned mask 117.

[0212] Some processes for forming patterned mask 117 and forming patterned mask 107 (see...) Figure 8 The processes for the electrode layer 115 are similar or identical, so their details will not be repeated. During the ion implantation process 160, a patterned mask 117 is used as the implantation mask to introduce P-type dopants (e.g., boron (B), gallium (Ga), or indium (In)) or N-type dopants (e.g., phosphorus (P) or arsenic (As)) into the electrode layer 115. After the ion implantation process 160, the patterned mask 117 can be removed.

[0213] Next, according to some embodiments, a patterned mask 119 is formed to cover the active region AA (i.e., the active region of the subsequently formed transistor 100) between the isolation structures 105a and 105b, and an ion implantation process 170 is performed on the portion of the electrode layer 115 exposed by the patterned mask 119, such as... Figure 12 As shown. In other embodiments, ion implantation process 170 is performed before ion implantation process 160. The corresponding steps are as follows. Figure 6 Step S19 of method 10 is shown.

[0214] Some processes for forming patterned mask 119 and forming patterned mask 107 (see...) Figure 8 The processes are similar or identical to those of other processes, so their details will not be repeated. During the ion implantation process 170, a patterned mask 119 is used as an implantation mask to introduce P-type dopants (e.g., boron (B), gallium (Ga), or indium (In)) or N-type dopants (e.g., phosphorus (P) or arsenic (As)) into the electrode layer 115.

[0215] It should be noted that, according to some embodiments, to improve conductivity, the portion of electrode layer 115 between isolation structures 105a and 105b is more heavily doped than the portion of electrode layer 115 located between isolation structures 105b and 105c. In some embodiments, the dose in ion implantation process 160 is greater than the dose in ion implantation process 170. After ion implantation process 170 is completed, the patterned mask 119 can be removed. Furthermore, an annealing process can be used to activate the implanted dopants.

[0216] Subsequently, according to some embodiments, the electrode layer 115 is subjected to a polishing process to form the gate electrode 115a in the opening 110a' (see...). Figure 9 ), and a resistive electrode 115b is formed in the opening 110b' (see Figure 9 ),like Figure 13 As shown. In some embodiments, a polishing process is performed until the dielectric layer 113 is exposed, and excess portions of the electrode layer 115 located above the dielectric layer 113 are removed. The corresponding steps are as follows. Figure 6 Step S21-1 of method 10 is shown.

[0217] In some embodiments, the polishing process is a chemical mechanical polishing (CMP) process. In some embodiments, the gate electrode 115a has a width W3, and the resistive electrode 115b has a width W4, wherein the width W4 is greater than the width W3. Furthermore, the required conductivity of the gate electrode 115a is greater than the required conductivity of the resistive electrode 115b. Therefore, the dopant concentration of the gate electrode 115a is greater than the dopant concentration of the resistive electrode 115b.

[0218] According to some embodiments, after forming the gate electrode 115a and the resistor electrode 115b, source / drain regions 121a and 121b are formed in the semiconductor substrate 101 and on opposite sides of the gate electrode 115a, such as... Figure 14 As shown. Source / drain regions 121a and 121b can be formed by ion implantation and / or diffusion, and the implanted dopants can be activated by an annealing process, such as rapid thermal annealing (RTA). The corresponding steps are as follows. Figure 6 Step S23-1 of method 10 is shown.

[0219] In some embodiments, the source / drain regions 121a and 121b, as well region 103, are doped with one or more P-type dopants, such as boron (B), gallium (Ga), or indium (In). In other embodiments, the source / drain regions 121a and 121b, as well region 103, are doped with one or more N-type dopants, such as phosphorus (P) or arsenic (As).

[0220] According to some embodiments, in Figure 14 An interlayer dielectric layer 123 is formed on top of the structure, such as Figure 15 As shown. In some embodiments, the interlayer dielectric layer 123 is made of silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a low dielectric constant dielectric material, and / or other suitable dielectric materials. Furthermore, the interlayer dielectric layer 123 can be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, or other suitable processes.

[0221] Next, according to some embodiments, a patterned mask 125 is formed on the interlayer dielectric layer 123, such as... Figure 16As shown. In some embodiments, the patterned mask 125 has an opening, and a portion of the interlayer dielectric layer 123 is exposed through the opening of the patterned mask 125. Some processes for forming the patterned mask 125 are the same as those for forming the patterned mask 107 (see...). Figure 8 The manufacturing processes are similar or identical to those of other products, so their details will not be repeated.

[0222] Next, according to some embodiments, a patterned mask 125 is used as a mask to perform an etching process on the interlayer dielectric layer 123 and the dielectric layer 113, such as... Figure 17 As shown. After the etching process, openings 130a, 130b, 130c, and 130d are formed. In some embodiments, openings 130a and 130b penetrate the interlayer dielectric layer 123 and the dielectric layer 113, and openings 130a and 130b expose source / drain regions 121a and 121b, respectively. In some embodiments, openings 130c and 130d penetrate the interlayer dielectric layer 123, and openings 130c and 130d partially expose the resistor electrode 115b. After forming openings 130a, 130b, 130c, and 130d, etched interlayer dielectric layer 123' and etched dielectric layer 113' are obtained.

[0223] See you again Figure 1 According to some embodiments, an interconnect structure 137 is formed on the interlayer dielectric layer 123'. As described above, the interconnect structure 137 includes conductive contacts 134a and 134b, conductive vias 133c and 133d, and conductive layers 135a, 135b, and 135c. In some embodiments, conductive contacts 134a and 134b are formed in openings 130a and 130b, respectively, wherein the conductive contact 134a includes a barrier layer 131a covering the sidewalls and bottom surface of the opening 130a (see...). Figure 17 ), and a conductive via 133a disposed on and surrounded by the barrier layer 131a, wherein the conductive contact 134b includes the barrier layer 131b covering the sidewall and bottom surface of the opening 130b (see Figure 17 The conductive vias 133b are disposed on and surrounded by the barrier layer 131a. In some embodiments, conductive vias 133c and 133d are formed in openings 130c and 130d, respectively, and conductive layers 135a, 135b, and 135c are formed on the interlayer dielectric layer 123' to cover conductive contacts 134a and 134b, and conductive vias 133c and 133d. The corresponding steps are as follows: Figure 6 Step S25 of method 10 is shown.

[0224] In some embodiments, the conductive vias 133a, 133b, 133c, and 133d of the interconnect structure 137, as well as the conductive layers 135a, 135b, and 135c, are made of copper (Cu), copper alloys, aluminum (Al), aluminum alloys, tungsten (W), tungsten alloys, titanium (Ti), titanium alloys, tantalum (Ta), tantalum alloys, or combinations thereof. Alternatively, other suitable conductive materials may be used. In some embodiments, the barrier layers 131a and 131b of the conductive contacts 136a and 136b of the interconnect structure 137 are made of titanium (Ti), titanium nitride (TiN), or combinations thereof. Furthermore, the interconnect structure 137 may be formed by one or more deposition processes and subsequent patterning processes. The deposition process can be a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, a metal-organic chemical vapor deposition (MOCVD) process, a sputtering process, an electroplating process, or other suitable deposition processes, and the patterning process can include photolithography and etching processes. Furthermore, in some embodiments, the deposition process of the barrier layers 131a and 131b of the conductive contacts 136a and 136b of the interconnect structure 137 can be an anisotropic deposition process including a physical vapor deposition process. In some embodiments, the interconnect structure 137 includes multiple layers.

[0225] Figures 18 to 19 This is a cross-sectional view illustrating an intermediate stage in the formation of a semiconductor element structure 300a according to some other embodiments of the present invention.

[0226] According to some alternative embodiments, ion implantation process 160 and ion implantation process 170 (see...) Figure 11 and Figure 12 ) was replaced by ion implantation process 180 and ion implantation process 190, such as Figure 18 and Figure 19 As shown. See also Figure 16 Without planting masks, for Figure 10 The structure was subjected to an ion implantation process at 180°.

[0227] Subsequently, according to some embodiments, a patterned mask 139 is formed to cover the active region BB (i.e., the active region of the subsequently formed resistor 200) located between the isolation structures 105b and 105c, and an ion implantation process 190 is performed on the portion of the electrode layer 115 exposed by the patterned mask 139, such as... Figure 19 As shown. Some processes for forming the patterned mask 139 are similar to those for forming the patterned mask 107 (see...). Figure 8 The manufacturing processes are similar or identical to those of other products, so their details will not be repeated.

[0228] It should be noted that the portion of electrode layer 115 located between isolation structures 105a and 105b undergoes one more ion implantation than the portion of electrode layer 115 located between isolation structures 105b and 105c. Therefore, the dopant concentration of the portion of electrode layer 115 located between isolation structures 105a and 105b is greater than that of the portion of electrode layer 115 located between isolation structures 105b and 105c. Consequently, in the obtained semiconductor device structure 300a, the dopant concentration of the gate electrode 115a is greater than that of the resistor electrode 115b.

[0229] Figures 20 to 22 This is a cross-sectional view illustrating an intermediate stage in the formation of a modified semiconductor element structure 300b according to some embodiments of the present invention.

[0230] See Figure 20 According to some embodiments, after polishing the electrode layer 115, the upper portion of the isolation structure 105b is etched to form an opening 140 (see [reference]). Figure 13 An etch mask (not shown) can be used as an etching mask to form the opening 140. In some embodiments, the dielectric layer 113, the semiconductor substrate 101, and the resistive electrode 115b are partially etched to form the opening 140.

[0231] Next, according to some embodiments, a conductive layer 143 is formed on the dielectric layer 113, and the opening 140 is filled by the conductive layer 143, such as... Figure 21 As shown. In some embodiments, the conductive layer 143 is in direct contact with the resistive electrode 115b.

[0232] In some embodiments, the conductive layer 143 is made of copper (Cu), copper alloys, aluminum (Al), aluminum alloys, tungsten (W), tungsten alloys, titanium (Ti), titanium alloys, tantalum (Ta), tantalum alloys, other suitable conductive materials, or combinations thereof. Furthermore, the conductive layer 143 can be formed using chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, sputtering, or other suitable processes.

[0233] After forming the conductive layer 143, according to some embodiments, a planarization process is performed to expose the gate electrode 115a and the resistor electrode 115b, and a conductive structure 145 is formed in the semiconductor substrate 101 and on the isolation structure 105b, such as Figure 22 As shown. The planarization process used to form the conductive structure 145 may include: chemical mechanical polishing, polishing, etching, other suitable processes, or combinations thereof.

[0234] Following the planarization process, according to some embodiments, the top surfaces of the dielectric layer 113, gate electrode 115a, resistive electrode 115b, and conductive structure 145 are substantially coplanar. In the context of this disclosure, the term "substantially" means preferably at least 90%, more preferably 95%, further preferably 98%, and most preferably 99%.

[0235] Subsequently, Figure 22 Structural Figures 14 to 17 The steps shown are for forming semiconductor device structure 300a. As described above, since the connection methods of transistor 100 and resistor 200 between semiconductor device structure 300a and semiconductor device structure 300b are different, openings 130b and 130c (see...) Figure 17 The interconnect structure 137 of the semiconductor element structure 300b (see [reference]) is not formed in the interlayer dielectric layer 123', thus preventing the interconnect structure 137 of the semiconductor element structure 300b from being formed in the interlayer dielectric layer 123'. Figure 3 The structure 300b includes only conductive contacts 136a, conductive vias 133d, and conductive layers 135a and 135c. However, in some other embodiments, the interconnect structure 137 of the semiconductor element structure 300b includes other conductive components for electrical connection with other elements.

[0236] Figures 23 to 25 This is a cross-sectional view illustrating some embodiments according to the present disclosure. Figure 4 This illustrates an intermediate stage in the formation of the semiconductor device structure 300c. It should be noted that... Figure 23 The operations used to form the semiconductor element structure 300c prior to the structure shown are the same as those used to form... Figures 7 to 17 The operation of the semiconductor device structure 300a shown (corresponding steps are as follows) Figure 6 Steps S21 to S23 in method 10 shown are essentially the same. Therefore, since a detailed description has already been provided above, it will not be repeated here.

[0237] See Figure 23According to some embodiments, a sacrificial liner 202 is formed on the sidewalls of openings 130a and 130b. The formation of the sacrificial liner 202 may include: forming a patterned mask (not shown) to cover the active region BB located between isolation structures 105b and 105c; conformally depositing a sacrificial film (not shown) in openings 130a and 130b, on the etched interlayer dielectric layer 123', and on the patterned mask; performing a removal process, such as an anisotropic etching process, to remove the horizontal portions of the sacrificial film located in openings 130a and 130b, and the horizontal portions located on the etched interlayer dielectric layer 123' and the patterned mask, while leaving the vertical portions of the sacrificial film on the sidewalls of openings 130a and 130b and on the patterned mask; and performing a planarization process to remove the patterned mask and the vertical portions of the sacrificial film located on the patterned mask. This forms a sacrificial liner 202 in openings 130a and 130b. In some embodiments, the sacrificial film comprises a dielectric material having etching properties different from those of the semiconductor substrate 101. For example, the sacrificial film may comprise a nitride and may be deposited using chemical vapor deposition, atomic layer deposition, or other similar processes.

[0238] See Figure 24 According to some embodiments, etching removes portions of the semiconductor substrate 101 exposed through openings 130a and 130b (i.e., source / drain regions 121a and 121b). This forms contact holes 130a1 and 130b1, respectively communicating with openings 130a and 130b. The portions of the semiconductor substrate 101 exposed through openings 130a and 130b are anisotropically dry etched, for example, using at least one reactive ion etching (RIE) process to form contact holes 130a1 and 130b1 through openings 130a and 130b. During the etching of the semiconductor substrate 101, the sacrificial substrate 202 functions as a mask.

[0239] See Figure 25 After forming contact holes 130a1 and 130b1, the sacrificial liner 202 is removed, and openings 130a' and 130b' are formed at the locations of openings 130a and 130b, respectively. The sacrificial liner 202 is removed using a stable process, such as a wet etching process. Figure 25 As shown, openings 130a' and 130b' have a substantially uniform first width W5, while contact holes 130a1 and 130b1 have a non-uniform width W6. In some embodiments, the width W6 gradually decreases at locations where the distance from the top surface 101T of the semiconductor substrate 101 increases.

[0240] See you again Figure 4 According to some embodiments, an interconnect structure 137 is formed on the interlayer dielectric layer 123'. As described above, the interconnect structure 137 includes conductive contacts 136a and 136b, conductive vias 133c and 133d, and conductive layers 135a, 135b, and 135c. In some embodiments, openings 130a' and 130b', and contact holes 130a1 and 130b1 are respectively (see...). Figure 25 Conductive contacts 136a and 136b are formed. Conductive contact 136a includes a lower portion 133a1 disposed in contact hole 130a1 and protruding into source / drain region 121a, and an upper portion 133a2 disposed in opening 130a' and between the top surface 101T of semiconductor substrate 101 and conductive layer 135a. Conductive contact 136b includes a lower portion 133b1 disposed in contact hole 130b1 and protruding into source / drain region 121b, and an upper portion 133b2 disposed in opening 130b' and between the top surface 101T of semiconductor substrate 101 and conductive layer 135a. In some embodiments, conductive vias 133c and 133d are formed in openings 130c and 130d, respectively, and conductive layers 135a, 135b, and 135c are formed on the interlayer dielectric layer 123' to cover conductive contacts 136a and 136b, as well as conductive vias 133c and 133d. The corresponding steps are as follows: Figure 6 Step S25 of method 10 is shown.

[0241] This disclosure provides embodiments of semiconductor device structures 300a, 300b, 300c, and 300d. Each semiconductor device structure 300a, 300b, 300c, and 300d includes a transistor 100 (e.g., a P-type metal-oxide-semiconductor transistor 100P or an N-type metal-oxide-semiconductor transistor 100N) and a resistor 200, which are connected in series and formed by an integration process. Specifically, the gate electrode 115a of the transistor 100 and the resistive electrode 115b of the resistor 200 are formed in the semiconductor substrate 101 by the same process steps. Therefore, the resistor 200 can exhibit high sheet resistance without the need for additional masks or process steps. This reduces associated costs and improves the performance of semiconductor device structures 300a, 300b, 300c, and 300d.

[0242] One aspect of this disclosure provides a semiconductor device. This semiconductor device includes: a substrate; a transistor and a resistor disposed in the substrate; a plurality of isolation structures disposed in the substrate, wherein the transistor is disposed between one pair of the plurality of isolation structures, and the resistor is disposed between another pair of the plurality of isolation structures; a dielectric layer disposed on the substrate; and an interconnect structure disposed on and electrically connected to the transistor and the resistor.

[0243] Another aspect of this disclosure provides a semiconductor device. This semiconductor device includes: a plurality of source / drain regions disposed in a substrate; a dielectric layer disposed over the source / drain regions; and a conductive contact penetrating the dielectric layer and entering the source / drain regions. The conductive contact includes: a conductive via; and a barrier layer covering a plurality of sidewalls and a bottom surface of the conductive via. A first thickness of the barrier layer on the plurality of sidewalls of the conductive via is less than a second thickness of the barrier layer below the bottom surface of the conductive via.

[0244] Another aspect of this disclosure provides a semiconductor device. This semiconductor device includes: a substrate having a plurality of isolation structures therein, wherein the plurality of isolation structures define a first active region and a second active region of the substrate; a plurality of source / drain regions disposed in the first active region, and a well region disposed in the second active region; a gate electrode and a resistor electrode disposed in the substrate, wherein the gate electrode is disposed between one pair of the plurality of source / drain regions, and the resistor electrode is disposed above the well region; a dielectric layer disposed on the substrate, wherein a first portion of the dielectric layer is disposed between the gate electrode and the substrate, and a second portion of the dielectric layer is disposed between the resistor electrode and the substrate; an interlayer dielectric layer disposed on the dielectric layer, the gate electrode, and the resistor electrode; a plurality of conductive contacts disposed on the plurality of source / drain regions; and a plurality of conductive layers disposed on the interlayer dielectric layer. Embodiments of this disclosure have several advantageous features. By forming the gate electrode of a transistor and the resistor electrode of a resistor in a semiconductor substrate using the same process steps, high chip resistance can be achieved without the need for additional masks or process steps. This significantly reduces costs and improves the performance of semiconductor device structures, including transistors and resistors.

[0245] Another aspect of this disclosure provides a semiconductor device. This semiconductor device includes: a source / drain region disposed in a substrate; a conductive layer disposed on the substrate; and a conductive contact including: a lower portion protruding into the source / drain region; and an upper portion disposed on the lower portion and between the top surface of the substrate and the conductive layer.

[0246] Another aspect of this disclosure provides a method for manufacturing a semiconductor device. This method includes: providing a semiconductor substrate; forming a plurality of isolation structures and a well region in the semiconductor substrate; recessing the semiconductor substrate to form a plurality of openings between the plurality of isolation structures; depositing a dielectric layer on the semiconductor substrate to form a first opening and a second opening in the substrate, wherein the dielectric layer extends into the first opening and the second opening; forming an electrode layer on the dielectric layer, wherein the electrode layer fills the first opening and the second opening; performing one or more ion implantation processes on the electrode layer; and polishing the electrode layer to form a gate. A gate electrode and a resistor electrode are formed; multiple source / drain regions are formed on the semiconductor substrate and on opposite sides of the gate electrode; an interlayer dielectric layer is formed on the dielectric layer; the interlayer dielectric layer and the dielectric layer are etched to form a third opening and a fourth opening in the interlayer dielectric layer, and an etched interlayer dielectric layer is formed on the semiconductor substrate; multiple conductive contacts are formed in the third opening, and multiple conductive vias are formed in the fourth opening; and an interconnect structure is formed on the etched interlayer dielectric layer, the multiple conductive contacts and the multiple conductive vias.

[0247] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0248] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this document that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor device structure, comprising: One substrate; A transistor and a resistor are disposed on the substrate; Multiple isolation structures are disposed in the substrate, wherein the transistor is disposed between one pair of the multiple isolation structures, and the resistor is disposed between another pair of the multiple isolation structures; A dielectric layer is disposed on the substrate; as well as An interconnect structure is disposed on the transistor and the resistor and electrically connected to the transistor and the resistor.

2. The semiconductor device structure of claim 1, wherein the transistor comprises: One gate electrode; Multiple source / drain regions are disposed on both sides of the gate electrode; as well as A first portion of the dielectric layer is disposed between the gate electrode and the substrate.

3. The semiconductor device structure as claimed in claim 2, wherein the resistor comprises: One resistive electrode; The first well area is located below the resistor electrode; as well as A second portion of the dielectric layer is disposed between the resistive electrode and the well region.

4. The semiconductor device structure of claim 3, wherein one of the plurality of isolation structures is disposed between the transistor and the resistor, and the isolation structure is closer to the resistor than to the transistor.

5. The semiconductor device structure of claim 4, wherein the interconnect structure comprises: Multiple conductive contacts are disposed on the corresponding multiple source / drain regions of the transistor; Multiple conductive vias are disposed on the resistor electrode of the resistor and are electrically connected to the resistor electrode of the resistor; as well as Multiple conductive layers are disposed on the multiple conductive contacts and the multiple conductive vias, and are electrically connected to the multiple source / drain regions of the transistor and the resistive electrode of the resistor.

6. The semiconductor device structure of claim 5, wherein the plurality of conductive contacts penetrate the dielectric layer and enter the plurality of source / drain regions.

7. The semiconductor device structure of claim 6, wherein each of the plurality of conductive contacts comprises: A conductive via is surrounded by a barrier layer.

8. The semiconductor device structure of claim 7, wherein the barrier layer includes a first thickness on the sidewalls of the respective plurality of conductive vias and a second thickness under the respective plurality of bottom surfaces of the conductive vias.

9. The semiconductor device structure of claim 8, wherein the first thickness of the barrier layer is less than the second thickness of the barrier layer.

10. The semiconductor device structure of claim 7, further comprising: An interlayer dielectric layer is disposed between the dielectric layer and the plurality of conductive layers, and surrounds the plurality of conductive contacts and the plurality of conductive vias of the interconnect structure.

11. A semiconductor device structure, comprising: Multiple source / drain regions are disposed on a substrate; A dielectric layer is disposed above the plurality of source / drain regions; as well as A conductive contact penetrates the dielectric layer and enters the plurality of source / drain regions, wherein the conductive contact includes: One conductive via; as well as A barrier layer covers multiple sidewalls and a bottom surface of the conductive via. The first thickness of the barrier layer on the plurality of sidewalls of the conductive via is less than the second thickness of the barrier layer below the bottom surface of the conductive via.

12. The semiconductor device structure of claim 11, further comprising: An interlayer dielectric layer is disposed on the dielectric layer and surrounds the conductive contact; as well as A conductive layer is disposed on top of the interlayer dielectric layer.

13. The semiconductor device structure of claim 12, further comprising: An isolation structure is disposed in the substrate to define a first active region and a second active region; as well as A conductive structure is disposed in the substrate and on the isolation structure.

14. The semiconductor device structure of claim 13, further comprising: A gate electrode is disposed in the first active region and located between the plurality of source / drain regions; as well as A resistive electrode is disposed in a well zone within the second active region.

15. The semiconductor device structure of claim 14, wherein the gate electrode is electrically connected to the resistor electrode via the conductive structure.

16. The semiconductor device structure of claim 14, wherein a first portion of the dielectric layer is disposed between the gate electrode and the substrate, and a second portion of the dielectric layer is disposed between the resistive electrode and the well region.

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