Packaging structure and preparation method thereof

Abstract

The invention provides a packaging structure and a preparation method thereof, and the method comprises the following steps: a semiconductor substrate and a plurality of semiconductor chips are provided, the semiconductor substrate comprises a plurality of bonding regions which are arranged at intervals, and the semiconductor chips are bonded on the bonding regions, projections of the semiconductor chips in the vertical direction are located in the bonding area, and two adjacent semiconductor chips are spaced by a preset distance; forming a diffusion barrier layer covering the exposed upper surface of the semiconductor substrate and the exposed surface of the semiconductor chip; forming a heat dissipation structure at least filling a gap between two adjacent semiconductor chips on the upper surface of the diffusion barrier layer, wherein the heat dissipation structure comprises a seed metal layer and a heat dissipation layer which are stacked in sequence; forming an isolation layer above the heat dissipation layer and bonding a carrier layer on the isolation layer; according to the packaging structure and the preparation method thereof, the heat dissipation performance of the semiconductor chip in the using process is improved, and the heat dissipation performance of the packaging structure with the high integration level is achieved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a packaging structure and its fabrication method. Background Technology

[0002] 3D-IC (three-dimensional integrated circuit) architecture can integrate multiple homogeneous and heterogeneous dies / chiplets into a single design, providing an alternative for system-on-a-chip (SoC) integration. However, conventional 3D integrated circuit packages have poor heat dissipation performance, such as... Figures 1-2 The diagram shows a schematic of the packaging structure and a top view of some parts of the packaging structure, including a semiconductor substrate 01, a semiconductor chip 02, a gap 03, a filling layer 04, and a heat dissipation layer 05. Currently, the filling layer on the top and around the top of the chip unit (including high-bandwidth memory system-on-a-chip) is usually made of TEOS (ethyl silicate), and the TEOS around the chip unit is generally larger than 20μm, which is quite thick. Furthermore, the bottom of the semiconductor chip is the bonding interface, and the heat dissipation of TEOS is very poor. As the performance of semiconductor chips improves, the silicon heat dissipation layer on top is unable to meet the heat dissipation requirements of the semiconductor chip during use, which may affect the performance and lifespan of the chip.

[0003] Therefore, there is an urgent need for a method to fabricate a packaging structure that can improve the heat dissipation performance of a three-dimensional integrated circuit package. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a packaging structure and its preparation method to solve the problem of poor heat dissipation performance of three-dimensional integrated circuit packages in the prior art.

[0005] To achieve the above and other related objectives, the present invention provides a packaging structure and its preparation method, comprising the following steps:

[0006] A semiconductor substrate and a plurality of semiconductor chips are provided. The semiconductor substrate includes a plurality of bonding regions spaced apart. The semiconductor chips are bonded to the bonding regions. The projection of the semiconductor chips in the vertical direction is located within the bonding regions and adjacent semiconductor chips are spaced apart by a preset distance.

[0007] A diffusion barrier layer is formed covering the exposed upper surface of the semiconductor substrate and the exposed surface of the semiconductor chip;

[0008] A seed metal layer is formed to cover the exposed surface of the diffusion barrier layer, and a heat dissipation layer is formed on the exposed surface of the seed metal layer to fill the gap between two adjacent semiconductor chips.

[0009] The excess heat dissipation layer and the seed metal layer on the surface of the diffusion barrier layer located above the semiconductor chip are removed sequentially.

[0010] Optionally, the diffusion barrier layer may be made of SiN.

[0011] Optionally, the method for forming the diffusion barrier layer includes chemical vapor deposition and physical vapor deposition.

[0012] Optionally, the thickness of the heat dissipation layer located in the gap between two adjacent semiconductor chips is greater than the thickness of the diffusion barrier layer; the thickness of the heat dissipation layer located in the gap between two adjacent semiconductor chips is greater than the thickness of the seed metal layer.

[0013] Optionally, the heat dissipation layer may be made of metal.

[0014] Optionally, methods for removing excess heat dissipation layer and seed metal layer from the surface of the diffusion barrier layer located above the semiconductor chip include chemical mechanical polishing, wet etching, and dry etching.

[0015] Optionally, the method for forming the seed metal layer includes chemical vapor deposition and physical vapor deposition.

[0016] Optionally, the method for forming the heat dissipation layer includes electroplating.

[0017] Optionally, the bonding region further includes a first bonding structure, and the lower surface of the semiconductor chip further includes a second bonding structure. The semiconductor chip is bonded to the bonding region by the upper surface of the first bonding structure and the lower surface of the second bonding structure.

[0018] The present invention also provides a packaging structure, which is prepared by the packaging structure preparation method described in any one of the above claims.

[0019] As described above, the packaging structure and its fabrication method of the present invention have the following beneficial effects: By forming the diffusion barrier layer covering the exposed upper surface of the semiconductor substrate and the exposed surface of the semiconductor chip, not only are the semiconductor chip and the metal layer between the semiconductor chips used for signal transmission protected, but the reliability and stability of the packaging structure are improved, ensuring that the performance of the packaging structure is not affected during long-term use. In addition, the diffusion barrier layer also avoids the impact of the subsequent metal heat dissipation layer on the performance of the packaging substrate structure, ensuring that the heat dissipation performance of the heat dissipation layer is fully utilized and improving the heat dissipation efficiency of the packaging structure; by forming a layer surrounding the sidewall of the semiconductor chip and filling adjacent... The heat dissipation layer between the two semiconductor chips improves the heat dissipation performance of the semiconductor chips during use, enhances their performance and lifespan, ensures the package structure operates within a suitable temperature range, improves the reliability of the package structure, reduces thermal stress on the package structure, prevents damage to the package structure due to stress concentration, and achieves heat dissipation performance of a highly integrated package structure. By forming the isolation layer on the upper surface of the heat dissipation structure, metal diffusion of the heat dissipation structure is avoided, ensuring the heat dissipation performance of the heat dissipation structure and the stability of the package structure. Furthermore, by bonding the carrier layer to the isolation layer, effective physical support is provided for subsequent process manufacturing. Attached Figure Description

[0020] Figure 1 The diagram shown is a structural schematic of a packaging structure in the prior art.

[0021] Figure 2 This is a top view of a portion of the packaging structure in the prior art.

[0022] Figure 3 The diagram shown illustrates the fabrication process of the packaging structure of this invention.

[0023] Figure 4 The diagram shows a semiconductor chip bonded to the bonding region as part of the packaging structure fabrication method of the present invention.

[0024] Figure 5 The diagram shown illustrates the structure after the diffusion barrier layer is formed, as described in the preparation method of the packaging structure of the present invention.

[0025] Figure 6 The diagram shown illustrates the structure after the seed metal layer is formed, as described in the preparation method of the packaging structure of the present invention.

[0026] Figure 7 The diagram shown is a schematic diagram of the structure after the heat dissipation layer is formed, which is a method for preparing the packaging structure of the present invention.

[0027] Figure 8 The diagram shows the structure after removing the excess heat dissipation layer and seed metal layer above the semiconductor chip, which is a method for preparing the packaging structure of the present invention.

[0028] Figure 9 The diagram shown is a structural schematic of the bonding carrier layer after the preparation method of the packaging structure of the present invention.

[0029] Figure 10 The diagram shows a schematic of the heat dissipation layer after smoothing, which is a method for preparing the packaging structure of the present invention.

[0030] Figure 11 This diagram shows another structural schematic after bonding the carrier layer, which is a method for preparing the encapsulation structure of the present invention.

[0031] Component designation explanation

[0032] 01 Semiconductor substrate

[0033] 02 Semiconductor Chips

[0034] 03 Filler layer

[0035] 04 Heat dissipation layer

[0036] 1 Semiconductor substrate

[0037] 2 Semiconductor chips

[0038] 3. Diffusion barrier layer

[0039] 4. Heat dissipation structure

[0040] 41 Seed Metal Layer

[0041] 42 Heat dissipation layer

[0042] 5. Isolation layer

[0043] 6. Carrier layer Detailed Implementation

[0044] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0045] Please see Figures 3 to 11It should be understood that the structures, proportions, sizes, etc., illustrated in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art and to facilitate understanding and reading. They are not intended to limit the scope of the invention and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of the invention, should still fall within the scope of the technical content disclosed in this invention. Furthermore, the terms such as "upper," "lower," "left," "right," "middle," and "one" used in this specification are merely for clarity and not intended to limit the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention's implementation.

[0046] Example 1

[0047] This embodiment provides a method for preparing a packaging structure. Figure 3 The diagram shown illustrates the fabrication process of the encapsulation structure, including the following steps:

[0048] S1: A semiconductor substrate and a plurality of semiconductor chips are provided. The semiconductor substrate includes a plurality of bonding regions spaced apart. The semiconductor chips are bonded to the bonding regions. The projection of the semiconductor chips in the vertical direction is located within the bonding regions and the adjacent semiconductor chips are spaced apart by a preset distance.

[0049] S2: Forming a diffusion barrier layer covering the exposed upper surface of the semiconductor substrate and the exposed surface of the semiconductor chip;

[0050] S3: A heat dissipation structure is formed on the upper surface of the diffusion barrier layer to fill the gap between at least two adjacent semiconductor chips. The heat dissipation structure includes a seed metal layer and a heat dissipation layer stacked sequentially.

[0051] S4: An isolation layer is formed above the heat dissipation layer, and a carrier layer is bonded to the isolation layer.

[0052] For details, please refer to Figure 4 In step S1, a semiconductor substrate 1 and a plurality of semiconductor chips 2 are provided. The semiconductor substrate 1 includes a plurality of bonding regions 11 spaced apart. The semiconductor chips 2 are bonded to the bonding regions 11. The projection of the semiconductor chips 2 in the vertical direction is located within the bonding regions 11 and adjacent semiconductor chips 2 are spaced apart by a preset distance.

[0053] Specifically, the semiconductor substrate 1 may be made of silicon, gallium nitride, sapphire, or other suitable materials.

[0054] Specifically, the semiconductor substrate 1 includes a wafer and a wafer provided with passive or active devices.

[0055] Specifically, the size of the semiconductor substrate 1 can be selected according to the actual situation, provided that the performance of the packaging structure is met, and there are no restrictions here.

[0056] As an example, Figure 4 The diagram shows the structure of the semiconductor chip 2 after it is bonded to the bonding region 11. The bonding region 11 also includes a first bonding structure (not shown), and the lower surface of the semiconductor chip 2 also includes a second bonding structure (not shown). The semiconductor chip 2 is bonded to the bonding region 11 by the upper surface of the first bonding structure and the lower surface of the second bonding structure.

[0057] Specifically, the first bonding structure includes at least a first dielectric layer (not shown) and a first bonding electrode (not shown) embedded in the first dielectric layer, and the second bonding structure includes at least a second dielectric layer (not shown) and a second bonding electrode (not shown) embedded in the second dielectric layer. When the upper surface of the first bonding structure and the lower surface of the second bonding structure are bonded together, the first bonding electrode and the second bonding electrode correspond one-to-one.

[0058] Specifically, the number of semiconductor chips 2 can be selected according to the actual situation, provided that the performance of the packaging structure is met, and there is no limit to this.

[0059] Specifically, the semiconductor chip 2 is made of silicon or other suitable materials.

[0060] Specifically, while meeting the performance requirements of the packaging structure, the spacing between two adjacent semiconductor chips 2 can be selected according to the actual situation and is not limited here.

[0061] For details, please refer to Figure 5 Step S2 is performed to form a diffusion barrier layer 3 covering the exposed upper surface of the semiconductor substrate 1 and the exposed surface of the semiconductor chip 2.

[0062] Specifically, Figure 5 The diagram shown is a schematic of the structure after the diffusion barrier layer 3 is formed. The methods for forming the diffusion barrier layer 3 include chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0063] Specifically, the thickness of the diffusion barrier layer 3 can be selected according to the actual situation, provided that the performance of the packaging structure is met, and no restrictions are imposed here.

[0064] As an example, the diffusion barrier layer 3 may be made of SiN or other suitable materials.

[0065] Specifically, by forming a diffusion barrier layer 3 covering the exposed upper surface of the semiconductor substrate 1 and the exposed surface of the semiconductor chip 2, not only are the semiconductor chip 2 and the metal layer between the semiconductor chips 2 used for signal transmission protected, but the reliability and stability of the packaging structure are also improved, ensuring that the performance of the packaging structure is not affected during long-term use. In addition, the diffusion barrier layer 3 also prevents the subsequent heat dissipation layer 5 from affecting the performance of the packaging substrate structure, ensuring that the heat dissipation performance of the heat dissipation layer 5 is fully utilized and improving the heat dissipation efficiency of the packaging structure.

[0066] For details, please refer to Figures 6-8 Step S3 is executed, and a heat dissipation structure 4 is formed on the upper surface of the diffusion barrier layer 3 to at least fill the gap between two adjacent semiconductor chips 2. The heat dissipation structure 4 includes a seed metal layer 41 and a heat dissipation layer 42 stacked sequentially.

[0067] As an example, Figures 6-8 The diagrams shown are schematic diagrams of the structure after the seed metal layer 41 is formed, the structure after the heat dissipation layer 42 is formed, and the structure after removing the excess heat dissipation layer 42 and seed metal layer 41 above the semiconductor chip 2. The formation of the heat dissipation structure 4 includes the following steps: forming a seed metal layer 41 covering the exposed surface of the diffusion barrier layer 3; forming a heat dissipation layer 42 covering the exposed surface of the seed metal layer 41 and filling the gap between two adjacent semiconductor chips 2; and sequentially removing the excess heat dissipation layer 42 and seed metal layer 41 on the surface of the diffusion barrier layer 3 above the semiconductor chip 2 to obtain the heat dissipation structure 4. The upper surface of the heat dissipation layer 42 is flush with the upper surface of the diffusion barrier layer 3 above the semiconductor chip 2.

[0068] As an example, methods for forming the seed metal layer 41 include chemical vapor deposition and physical vapor deposition. In this embodiment, the method for forming the seed metal layer 41 is physical vapor deposition.

[0069] Specifically, the seed metal layer 41 is made of copper or other suitable conductive metal materials.

[0070] Specifically, by forming a seed metal layer 41 on the upper surface of the diffusion barrier layer 3, a good adhesion is formed between the seed metal layer 41 and the diffusion barrier layer 3, preventing the subsequent heat dissipation layer 42 from falling off, ensuring the uniform growth of the heat dissipation layer 42, and the seed metal layer 41 also has a certain heat dissipation performance.

[0071] As an example, the material of the heat dissipation layer 42 includes metallic materials, such as copper, aluminum, silver or other metallic materials with high thermal conductivity. It should be noted that the material of the heat dissipation layer 42 is not limited to the above-mentioned metallic materials, and other materials with high thermal conductivity can also be used as the heat dissipation layer 42.

[0072] As an example, methods for forming the heat dissipation layer 42 include electroplating or other suitable methods.

[0073] Specifically, the thickness of the heat dissipation layer 42 located in the gap between two adjacent semiconductor chips 2 is greater than the thickness of the diffusion barrier layer 3; the thickness of the heat dissipation layer 42 located in the gap between two adjacent semiconductor chips 2 is greater than the thickness of the seed metal layer 4. It should be noted that, while ensuring the heat dissipation performance of the semiconductor chip 2 during operation, the thickness of the heat dissipation layer 42 on the sidewall of the semiconductor chip 2 must be sufficiently thick. That is, by setting the thickness of the heat dissipation layer 42 located in the gap between two adjacent semiconductor chips 2 to be greater than the thickness of the diffusion barrier layer 3 and the seed metal layer 41, the heat dissipation performance of the packaging structure can be fully guaranteed.

[0074] Specifically, methods for removing excess heat dissipation layer 42 and seed metal layer 41 from the surface of diffusion barrier layer 3 above semiconductor chip 1 include chemical mechanical polishing, dry etching, wet etching, or other suitable methods. In this embodiment, the method for removing excess heat dissipation layer 42 and seed metal layer 41 is chemical mechanical polishing.

[0075] Specifically, after removing the excess heat dissipation layer 42 and seed metal layer 41, the upper surfaces of the heat dissipation layer 42 and seed metal layer 41 are flush with the upper surface of the diffusion barrier layer 3 located above the semiconductor chip 2.

[0076] Specifically, removing the excess heat dissipation layer 42 and seed metal layer 41 optimizes the packaging structure, improves the long-term stability of the packaging structure, and provides convenience for subsequent processes.

[0077] Specifically, by forming a heat dissipation structure 4 that surrounds the sidewall of the semiconductor chip 2 and fills the gap between two adjacent semiconductor chips 2, the heat dissipation performance of the semiconductor chip 2 during use is improved, thereby enhancing the performance and lifespan of the semiconductor chip 2. This ensures that the packaging structure operates within a suitable temperature range, guarantees the reliability of the packaging structure, reduces the thermal stress of the packaging structure, prevents damage to the packaging structure due to stress concentration, and achieves heat dissipation performance of a highly integrated packaging structure.

[0078] For details, please refer to Figure 9 Step S4 is executed, an isolation layer 5 is formed above the heat dissipation structure 4, and a carrier layer 6 is bonded to the isolation layer 5.

[0079] Specifically, the methods for forming the isolation layer 5 include chemical vapor deposition, physical vapor deposition, or other suitable materials.

[0080] As an example, the material of the isolation layer 5 may include silicon dioxide or other suitable materials.

[0081] Specifically, the isolation layer 5 covers the diffusion barrier layer 3 and the upper surface of the heat dissipation structure 4.

[0082] Specifically, carrier layer 6 includes a wafer and a wafer equipped with passive or active devices.

[0083] Specifically, Figure 9 The diagram shown is a schematic of a structure after bonding the carrier layer 6. The carrier layer 6 is bonded to the semiconductor substrate 1 through the isolation layer 5.

[0084] Specifically, the isolation layer 5 covers the diffusion barrier layer 3 and the upper surface of the heat dissipation structure 4, preventing metal diffusion of the heat dissipation structure 4, ensuring the heat dissipation performance of the heat dissipation structure 4 and the stability of the packaging structure. The isolation layer 5 is also used to bond the carrier layer 6 to the semiconductor substrate 1.

[0085] Specifically, by bonding the carrier layer 6 to the isolation layer 5, effective physical support is provided for subsequent process manufacturing.

[0086] The packaging structure fabrication method of this embodiment forms a diffusion barrier layer 3 covering the exposed upper surface of the semiconductor substrate 1 and the exposed surface of the semiconductor chip 2. This not only protects the metal layer used for signal transmission between the semiconductor chips 2 and the semiconductor chips 2 themselves, but also improves the reliability and stability of the packaging structure, ensuring that the performance of the packaging structure is not affected during long-term use. In addition, the diffusion barrier layer 3 also prevents the subsequent metal heat dissipation layer 42 from affecting the performance of the packaging substrate structure, ensuring that the heat dissipation performance of the heat dissipation layer 42 is fully utilized and improving the heat dissipation efficiency of the packaging structure. By forming a heat dissipation structure 4 surrounding the four sidewalls of the semiconductor chip 2, This improves the heat dissipation performance of the semiconductor chip 2 during use, enhances its performance and lifespan, ensures the packaging structure operates within a suitable temperature range, guarantees the reliability of the packaging structure, reduces thermal stress on the packaging structure, prevents damage to the packaging structure due to stress concentration, and achieves heat dissipation performance of a highly integrated packaging structure. By forming an isolation layer 5 covering the diffusion barrier layer 3 and the upper surface of the heat dissipation structure 4, metal diffusion of the heat dissipation structure 4 is avoided, ensuring the heat dissipation performance of the heat dissipation structure 4 and the stability of the packaging structure. Furthermore, by bonding a carrier layer 6 to the isolation layer 5, effective physical support is provided for subsequent process manufacturing.

[0087] Example 2

[0088] This embodiment provides a packaging structure, which is prepared by the packaging structure preparation method described in Embodiment 1. The packaging structure includes: a semiconductor substrate 1, multiple semiconductor chips 2, a diffusion barrier layer 3, a diffusion structure 4, an isolation layer 5, and a carrier layer 6. The semiconductor substrate 1 includes multiple spaced bonding regions 11, and the semiconductor chips 2 are bonded to the bonding regions 11. The projection of the semiconductor chips 2 in the vertical direction is located within the bonding regions 11, and adjacent semiconductor chips 2 are spaced apart by a predetermined distance. The diffusion barrier layer 3 covers the exposed upper surface of the semiconductor substrate 1 and the exposed surface of the semiconductor chips 2. The heat dissipation structure 4 is located on the upper surface of the diffusion barrier layer 3 and at least fills the gap between adjacent semiconductor chips 2. The heat dissipation structure 4 includes a seed metal layer 41 and a heat dissipation layer 42 stacked sequentially. The isolation layer 5 is located above the heat dissipation structure 4, and the carrier layer 6 is bonded above the isolation layer.

[0089] Specifically, the bonding region 11 also includes a first bonding structure (not shown), and the lower surface of the semiconductor chip 2 also includes a second bonding structure (not shown). The semiconductor chip 2 is bonded to the bonding region 11 by the upper surface of the first bonding structure and the lower surface of the second bonding structure.

[0090] Specifically, the first bonding structure includes at least a first dielectric layer (not shown) and a first bonding electrode (not shown) embedded in the first dielectric layer, and the second bonding structure includes at least a second dielectric layer (not shown) and a second bonding electrode (not shown) embedded in the second dielectric layer. When the upper surface of the first bonding structure and the lower surface of the second bonding structure are bonded together, the first bonding electrode and the second bonding electrode correspond one-to-one.

[0091] Specifically, the upper surfaces of the heat dissipation layer 42 and the seed metal layer 41 are flush with the upper surface of the diffusion barrier layer 3 located above the semiconductor chip 2.

[0092] Specifically, the isolation layer 5 covers the diffusion barrier layer 3 and the upper surface of the heat dissipation structure 4.

[0093] The heat dissipation structure 4 formed by the packaging structure in this embodiment surrounds the four sidewalls of the semiconductor chip 2 and fills the gap between two adjacent semiconductor chips 2, which improves the heat dissipation performance of the semiconductor chip 2 during use, improves the performance and service life of the semiconductor chip 2, ensures that the packaging structure works within a suitable temperature range, improves the reliability of the packaging structure, reduces the thermal stress of the packaging structure, prevents the packaging structure from being damaged due to stress concentration, and achieves heat dissipation performance of a highly integrated packaging structure.

[0094] Example 3

[0095] This embodiment provides another method for preparing a packaging structure. Figures 10 to 11The diagrams shown are schematic diagrams of the structure after the heat dissipation layer 42 has been smoothed and another schematic diagram of the structure after the bonding carrier layer 6 has been bonded. The difference between the preparation method of the packaging structure in this embodiment and the preparation method of the packaging structure described in Embodiment 1 is that the formation of the heat dissipation structure 4 includes the following steps: forming a seed metal layer 41 covering the exposed surface of the diffusion barrier layer 3, forming a heat dissipation layer 42 covering the exposed surface of the seed metal layer 41 and filling the gap between two adjacent semiconductor chips 2, and smoothing the upper surface of the heat dissipation layer 42 to obtain the heat dissipation structure 4. The upper surface of the heat dissipation layer 42 is higher than the upper surface of the diffusion barrier layer 3 located above the semiconductor chip 2.

[0096] Specifically, the upper surface of the heat dissipation layer 42 is higher than the upper surface of the diffusion barrier layer 3 located above the semiconductor chip 2.

[0097] Specifically, the isolation layer 5 covers the upper surface of the heat dissipation layer 42.

[0098] As an example, the material of the isolation layer 5 may include doped silicon carbide, silicon nitride, or other suitable materials.

[0099] Specifically, methods for smoothing the upper surface of the heat dissipation layer 42 include chemical mechanical polishing or other suitable methods.

[0100] The packaging structure fabrication method of this embodiment further improves the heat dissipation effect of the semiconductor chip 2 by setting the upper surface of the heat dissipation layer 42 to be higher than the upper surface of the diffusion barrier layer 3 located above the semiconductor chip 2, and forming a heat dissipation structure 4 that surrounds the four side walls and the upper surface of the semiconductor chip 2.

[0101] Example 4

[0102] This embodiment provides another packaging structure, which is prepared by the packaging structure preparation method described in Embodiment 3. The packaging structure includes: a semiconductor substrate 1, multiple semiconductor chips 2, a diffusion barrier layer 3, a diffusion structure 4, an isolation layer 5, and a carrier layer 6. The semiconductor substrate 1 includes multiple spaced bonding regions 11, and the semiconductor chips 2 are bonded to the bonding regions 11. The vertical projection of the semiconductor chips 2 is located within the bonding regions 11, and adjacent semiconductor chips 2 are spaced apart by a predetermined distance. The diffusion barrier layer 3 covers the exposed upper surface of the semiconductor substrate 1 and the exposed surface of the semiconductor chips 2. The heat dissipation structure 4 is located on the upper surface of the diffusion barrier layer 3 and at least fills the gap between adjacent semiconductor chips 2. The heat dissipation structure 4 includes a seed metal layer 41 and a heat dissipation layer 42 stacked sequentially. The isolation layer 5 is located above the heat dissipation structure 4, and the carrier layer 6 is bonded above the isolation layer.

[0103] Specifically, the bonding region 11 also includes a first bonding structure (not shown), and the lower surface of the semiconductor chip 2 also includes a second bonding structure (not shown). The semiconductor chip 2 is bonded to the bonding region 11 by the upper surface of the first bonding structure and the lower surface of the second bonding structure.

[0104] Specifically, the first bonding structure includes at least a first dielectric layer (not shown) and a first bonding electrode (not shown) embedded in the first dielectric layer, and the second bonding structure includes at least a second dielectric layer (not shown) and a second bonding electrode (not shown) embedded in the second dielectric layer. When the upper surface of the first bonding structure and the lower surface of the second bonding structure are bonded together, the first bonding electrode and the second bonding electrode correspond one-to-one.

[0105] Specifically, the upper surface of the heat dissipation layer 42 is higher than the upper surface of the diffusion barrier layer 3 located above the semiconductor chip 2.

[0106] Specifically, the isolation layer 5 covers the upper surface of the heat dissipation layer 42.

[0107] In this embodiment, the heat dissipation structure 4 of the packaging structure surrounds the four sidewalls and the top surface of the semiconductor chip 2, further improving the heat dissipation effect of the semiconductor chip 2.

[0108] In summary, the packaging structure fabrication method of the present invention, by forming a diffusion barrier layer covering the exposed upper surface of the semiconductor substrate and the exposed surface of the semiconductor chip, not only protects the metal layer used for signal transmission between semiconductor chips and the semiconductor chip itself, improving the reliability and stability of the packaging structure and ensuring that the performance of the packaging structure is not affected during long-term use, but also prevents the subsequent metal heat dissipation layer from affecting the performance of the packaging substrate structure, ensuring that the heat dissipation performance of the heat dissipation layer is fully utilized and improving the heat dissipation efficiency of the packaging structure. By forming a heat dissipation layer surrounding the sidewalls of the semiconductor chip and filling the gap between two adjacent semiconductor chips, the heat dissipation performance of the semiconductor chip during use is improved, thereby improving the performance and lifespan of the semiconductor chip, ensuring that the packaging structure operates within a suitable temperature range, ensuring the reliability of the packaging structure, reducing the thermal stress of the packaging structure, preventing damage to the packaging structure due to stress concentration, and achieving heat dissipation performance of a highly integrated packaging structure. By forming an isolation layer located on the upper surface of the heat dissipation structure, metal diffusion of the heat dissipation structure is prevented, ensuring the heat dissipation performance of the heat dissipation structure and the stability of the packaging structure, and by bonding a carrier layer on the isolation layer, effective physical support is provided for subsequent process fabrication. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0109] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a packaging structure, characterized in that, Includes the following steps: A semiconductor substrate and a plurality of semiconductor chips are provided. The semiconductor substrate includes a plurality of bonding regions spaced apart. The semiconductor chips are bonded to the bonding regions. The projection of the semiconductor chips in the vertical direction is located within the bonding regions and adjacent semiconductor chips are spaced apart by a preset distance. A diffusion barrier layer is formed covering the exposed upper surface of the semiconductor substrate and the exposed surface of the semiconductor chip; A heat dissipation structure is formed on the upper surface of the diffusion barrier layer to at least fill the gap between two adjacent semiconductor chips. The heat dissipation structure includes a seed metal layer and a heat dissipation layer stacked sequentially. An isolation layer is formed above the heat dissipation structure, and a carrier layer is bonded to the isolation layer.

2. The method for preparing the packaging structure according to claim 1, characterized in that: The diffusion barrier layer is made of silicon nitride.

3. The method for preparing the packaging structure according to claim 1, characterized in that, The heat dissipation structure is formed by the following steps: forming a seed metal layer covering the exposed surface of the diffusion barrier layer, forming a heat dissipation layer covering the exposed surface of the seed metal layer and filling the gap between two adjacent semiconductor chips, and smoothing the upper surface of the heat dissipation layer to obtain the heat dissipation structure, wherein the upper surface of the heat dissipation layer is higher than the upper surface of the diffusion barrier layer located above the semiconductor chips.

4. The method for preparing the packaging structure according to claim 4, characterized in that: The material of the isolation layer includes doped silicon carbide and silicon nitride.

5. The method for preparing the packaging structure according to claim 1, characterized in that, The heat dissipation structure is formed by the following steps: forming a seed metal layer covering the exposed surface of the diffusion barrier layer; forming a heat dissipation layer covering the exposed surface of the seed metal layer and filling the gap between two adjacent semiconductor chips; and sequentially removing excess heat dissipation layer and seed metal layer from the surface of the diffusion barrier layer above the semiconductor chips to obtain the heat dissipation structure, wherein the upper surface of the heat dissipation layer is flush with the upper surface of the diffusion barrier layer above the semiconductor chips.

6. The method for preparing the packaging structure according to claim 5, characterized in that: The material of the isolation layer includes silicon dioxide.

7. The method for preparing the packaging structure according to claim 1, characterized in that: The heat dissipation layer is made of metal.

8. The method for preparing the packaging structure according to claim 1, characterized in that: The method for forming the heat dissipation layer includes electroplating.

9. The method for preparing the packaging structure according to claim 1, characterized in that: The bonding region further includes a first bonding structure, and the lower surface of the semiconductor chip further includes a second bonding structure. The semiconductor chip is bonded to the bonding region by the upper surface of the first bonding structure and the lower surface of the second bonding structure.

10. A packaging structure, characterized in that, The encapsulation structure is prepared using the encapsulation structure preparation method described in any one of claims 1 to 9.

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