Non-operational-amplifier ferroelectric capacitor in-memory computing accelerator and in-memory computing system

Abstract

The invention relates to the field of semiconductor devices, and discloses an in-memory computing accelerator and an in-memory computing system for a ferroelectric capacitor without an operational amplifier, a word line WL and a word line anti-WLB are parallel to each other, and a bit line BL is located in the vertical direction of the word line WL and the word line anti-WLB; one end of the first capacitor is connected with the bit line BL, and the other end is connected with the word line WL; one end of the second capacitor is connected with the bit line BL, and the other end of the second capacitor is connected with the word line reverse WLB. According to the calculation accelerator in the ferroelectric capacitor memory, by optimizing an array structure and a read-out mechanism, high power consumption caused by OPAMP is eliminated, meanwhile, high calculation precision and energy efficiency are kept, and the calculation accelerator is suitable for a high-efficiency reasoning task of an edge-end binary neural network BNN.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and in particular to an operational amplifier-free ferroelectric capacitor in-memory computing accelerator and in-memory computing system. Background Technology

[0002] With the rapid development of artificial intelligence algorithms, the demand for high-efficiency computing architectures is becoming increasingly urgent. In-memory computing (CIM) architecture demonstrates significant advantages by reducing data movement between the processor and memory. Traditional resistive computing, such as... Figure 1 In the -a configuration, in-memory computing arrays suffer from high static power consumption and significant IR voltage drop. In contrast, such as Figure 1 In the -b category, CIM arrays based on ferroelectric capacitors (FeCAP) offer higher energy efficiency. However, the readout circuitry of existing FeCAP cross arrays (FCA) must use operational amplifiers (OPAMPs), which consume a significant portion of the total system power, severely limiting further improvements in system energy efficiency.

[0003] As disclosed in prior art 1, CN200810101920.7, a cross-type ferroelectric memory array structure belonging to the field of integrated circuit design and manufacturing technology is described. This array structure uses cross-type ferroelectric memory cells as its basic components. Each ferroelectric memory cell shares control lines CL with memory cells in the same row or column in both the horizontal and vertical directions. Memory cells in the same column share data signal lines BL in the column direction, and memory cells in the same row share BL in the row direction. BL is not shared between rows and columns.

[0004] As disclosed in prior art 2, CN202510742476.0, an in-memory encryption method based on a cross-matrix ferroelectric capacitor array belongs to the field of data security and computational security. This invention employs a cross-matrix ferroelectric capacitor (FeCAP) array as both the key array and the complementary key array. Through a diagonal data encoding mode and a coupled signal subtraction circuit, the resulting operation performs array-level XOR operations between the plaintext and the key, achieving highly parallel in-memory XOR encryption. Summary of the Invention

[0005] This invention addresses the problems of existing ferroelectric capacitor in-memory computing accelerators, which suffer from the presence of an opamp, resulting in high energy consumption and severely impacting system energy efficiency; the need for a reference capacitor during charge transfer, increasing circuit complexity and area; and the high power consumption of the read circuit, limiting further improvement in overall energy efficiency. The invention provides an opamp-free ferroelectric capacitor in-memory computing accelerator and in-memory computing system.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution: An op-amp-free ferroelectric capacitor in-memory computing accelerator includes a ferroelectric capacitor cross array, a timing control circuit, a decoder and driver, and an analog-to-digital converter. Ferroelectric capacitor cross array is used to store binary weights, timing control circuit is used to control read and write calculation timing, decoder and driver are used for address decoding and voltage driving, analog-to-digital converter is used for voltage quantization; Its ferroelectric capacitor cross array includes array bit lines BL, array word lines WL, and array word lines inverse WLB; The word line WL and the reverse word line WLB are parallel to each other, and the position line BL is located in the vertical direction of the word line WL and the reverse word line WLB. The word line WL and the word line WLB are connected by a first capacitor and a second capacitor; one end of the first capacitor is connected to the bit line BL and the other end is connected to the word line WL; one end of the second capacitor is connected to the bit line BL and the other end is connected to the word line WLB.

[0007] Preferably, the ferroelectric capacitor cross array uses a weight mapping method of a binary neural network (BNN) to adjust the first capacitor and the second capacitor.

[0008] Preferably, the ferroelectric capacitor cross array adjusts the first and second capacitors using a weight mapping method of a binary neural network (BNN). Specifically, when the weight is +1, the first capacitor is in a high-capacitance state C. HCS The second capacitor is in a low capacitance state C. LCS When the weight is -1, the first capacitor is in a low capacitance state C. LCS The second capacitor is in a high capacitance state, C. HCS .

[0009] Preferably, the ferroelectric capacitor cross array outputs voltage in an array manner, including: Step 1: Precharge all bit lines BL, word lines WL and reverse word lines WLB to the common-mode voltage Vcm; Step 2: Charge sharing. Different voltages are applied to WL and WLB according to the weighted input values, and net charge is generated on the bit line through capacitive coupling. Step 3, Voltage Output: The total charge on the bit line is directly converted into voltage through the total capacitance Ctotal. Output; the formula for output voltage is: in, Where C is the output voltage, and Ctotal is the total capacitance constant across BL. For input data, For network weights, This is the small-signal read voltage of the ferroelectric capacitor. This represents the total charge generated on the bit line during calculation.

[0010] Preferably, different voltages are applied to WL and WLB according to the input weight value, and a net charge is generated on the bit line through capacitive coupling. When the input weight value is +1, the voltage applied to WL and WLB is VP, and when the input weight value is -1, the voltage applied to WL and WLB is VN.

[0011] Preferably, the first capacitor and the second capacitor have an MFM structure or an MFS structure.

[0012] To address the aforementioned technical problems, the present invention also provides an operational amplifier-free ferroelectric capacitor memory in-memory computing system, which includes the aforementioned operational amplifier-free ferroelectric capacitor memory in-memory computing accelerator.

[0013] This invention, by adopting the above technical solutions, has significant technical effects: The ferroelectric capacitor in-memory computing accelerator without operational amplifier structure of the present invention eliminates the high power consumption caused by OPAMP by optimizing the array structure and readout mechanism, while maintaining high computing accuracy and energy efficiency. It is particularly suitable for high-performance inference tasks of edge binary neural networks (BNN).

[0014] The energy efficiency of the ferroelectric capacitor in-memory computing accelerator designed in this invention is significantly improved: after removing the OPAMP, the system energy efficiency reaches 121 TOPS / W, which is more than 3 times higher than the existing solution; The ferroelectric capacitor in-memory computing accelerator designed in this invention maintains good accuracy: it achieves an inference accuracy of 82.7% on the CIFAR-10 dataset, which is close to the level of software implementation. The ferroelectric capacitor in-memory computing accelerator designed in this invention has a simplified structure that eliminates the need for a reference capacitor and an OPAMP, thereby reducing circuit area and complexity. The ferroelectric capacitor in-memory computing accelerator designed in this invention has strong compatibility: it is suitable for a variety of binary neural network tasks and supports edge deployment. Attached Figure Description

[0015] Figure 1 -a is a diagram of a resistive in-memory computing architecture.

[0016] Figure 1 -b is a diagram of a capacitor-based in-memory computing architecture.

[0017] Figure 2 This is a schematic diagram of the traditional FeCAP array structure and working principle.

[0018] Figure 3-a This is a diagram of the FeCAP array structure of the present invention.

[0019] Figure 3-b This is a schematic diagram of the weight value mapping of the present invention.

[0020] Figure 3-a This is a schematic diagram of the FeCAP array structure and working principle of the present invention.

[0021] Figure 4 This is a simulation diagram of the output voltage of the present invention.

[0022] Figure 5 -a is the equivalent circuit diagram of the traditional interface circuit.

[0023] Figure 5 -b is a schematic diagram showing the energy consumption ratio of traditional read circuits in memristor memory architecture and ferroelectric memory architecture (FCA).

[0024] Among them, OPAMP (Operational Amplifier); BNN (Binary Neural Network); CIM (Computer-Integrated Manufacturing); BL (Bit Line); WL (Word Line); WLB (Word-Line Buffer). Detailed Implementation

[0025] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0026] Example 1

[0027] In-memory computing architectures significantly reduce data transfer overhead by embedding computing units within memory. Ferroelectric capacitors (FeCAPs) are ideal for CIMs due to their lack of quiescent current and high energy efficiency. However, existing FeCAP arrays require charge-to-voltage conversion via OPAMPs, resulting in significant power consumption. Figure 2 The FeCAP cross-array in the present invention is completed in two stages: a capacitor charging stage and a charge transfer stage. During the capacitor charging stage, multiplication and accumulation operations are performed. During the charge transfer stage, an OPAMP is used to convert the charge into a voltage output. While the designed FeCAP cross-array can achieve computational functions, the power consumption of the readout circuit (OPAMP + ADC) accounts for more than 59.7% of the total system power consumption, severely limiting energy efficiency improvements.

[0028] Example 2

[0029] An operational amplifier-free ferroelectric capacitor in-memory computing accelerator. Figure 3-a It includes a ferroelectric capacitor cross array, timing control circuit, decoder and driver, and analog-to-digital converter; Ferroelectric capacitor cross array is used to store binary weights, timing control circuit is used to control read and write calculation timing, decoder and driver are used for address decoding and voltage driving, analog-to-digital converter is used for voltage quantization; Its ferroelectric capacitor cross array includes array bit lines BL, array word lines WL, and array word lines inverse WLB; The word line WL and the reverse word line WLB are parallel to each other, and the position line BL is located in the vertical direction of the word line WL and the reverse word line WLB. The word line WL and the word line WLB are connected by a first capacitor and a second capacitor; one end of the first capacitor is connected to the bit line BL and the other end is connected to the word line WL; one end of the second capacitor is connected to the bit line BL and the other end is connected to the word line WLB.

[0030] The ferroelectric capacitor cross array adjusts the first and second capacitors using a weight mapping method of a binary neural network (BNN).

[0031] The ferroelectric capacitor cross array adjusts the first and second capacitors using a weight mapping method of a binary neural network (BNN). Specifically, when the weight is +1, the first capacitor is in a high-capacitance state (C). HCS The second capacitor is in a low capacitance state C. LCS When the weight is -1, the first capacitor is in a low capacitance state C. LCS The second capacitor is in a high capacitance state, C. HCS .

[0032] Ferroelectric capacitor cross arrays output voltage through an array configuration. Figure 3-c Including: Step 1: Voltage preparation stage, all bit lines BL, word lines WL and word line inverse WLB are pre-charged to common mode voltage Vcm; Step 2: Charge sharing. Different voltages are applied to WL and WLB according to the weighted input values, and net charge is generated on the bit line through capacitive coupling. Step 3, Voltage Output: The total charge on the bit line is directly converted into voltage through the total capacitance Ctotal. Output; the formula for output voltage is: in, Ctotal is the output voltage, and Ctotal is the total capacitance (constant) on BL. For input data, For network weights, This is the small-signal read voltage of the ferroelectric capacitor. This represents the total charge generated on the bit line during calculation.

[0033] It adopts a 2C structure with a constant total capacitance per column, avoiding charge integration circuits; the layout is optimized, and the width of the capacitor column is matched with the ADC to improve integration; a 1 / 3 Vw read / write scheme is adopted to suppress write interference.

[0034] Different voltages are applied to WL and WLB based on the input weight values. Figure 3-b In this process, a net charge is generated on the bit lines through capacitive coupling. When the input weight is +1, the applied voltage on WL and WLB is VP; when the input weight is -1, the applied voltage on WL and WLB is VN. This mapping method ensures that the total capacitance of each pair of capacitors is constant (C). HCS + C LCS ), thus making the total capacitance C of each column total This remains unchanged, providing the necessary conditions for direct voltage output.

[0035] The first and second capacitors have an MFM structure.

[0036] Example 3

[0037] An op-amp-free ferroelectric capacitor in-memory computing accelerator includes a ferroelectric capacitor cross array, a timing control circuit, a decoder and driver, and an analog-to-digital converter. Ferroelectric capacitor cross array is used to store binary weights, timing control circuit is used to control read and write calculation timing, decoder and driver are used for address decoding and voltage driving, analog-to-digital converter is used for voltage quantization; Its ferroelectric capacitor cross array includes array bit lines BL, array word lines WL, and array word lines inverse WLB; The word line WL and the reverse word line WLB are parallel to each other, and the position line BL is located in the vertical direction of the word line WL and the reverse word line WLB. The word line WL and the word line WLB are connected by a first capacitor and a second capacitor; one end of the first capacitor is connected to the bit line BL and the other end is connected to the word line WL; one end of the second capacitor is connected to the bit line BL and the other end is connected to the word line WLB.

[0038] The ferroelectric capacitor cross array adjusts the first and second capacitors using a weight mapping method of a binary neural network (BNN).

[0039] The ferroelectric capacitor cross array adjusts the first and second capacitors using a weight mapping method of a binary neural network (BNN). Specifically, when the weight is +1, the first capacitor is in a high-capacitance state (C). HCS The second capacitor is in a low capacitance state C. LCS When the weight is -1, the first capacitor is in a low capacitance state C. LCS The second capacitor is in a high capacitance state, C. HCS .

[0040] Ferroelectric capacitor cross arrays output voltage through an array configuration, including: Step 1: Precharge all bit lines BL, word lines WL and reverse word lines WLB to the common-mode voltage Vcm; Step 2: Charge sharing. Different voltages are applied to WL and WLB according to the weighted input values, and net charge is generated on the bit line through capacitive coupling. Step 3, Voltage Output: The total charge on the bit line is directly converted into voltage through the total capacitance Ctotal. Output; the formula for output voltage is: in, Ctotal is the output voltage, and Ctotal is the total capacitance (constant) on BL. For input data, For network weights, This is the small-signal read voltage of the ferroelectric capacitor. This represents the total charge generated on the bit line during calculation.

[0041] Different voltages are applied to WL and WLB according to the input weight value, and a net charge is generated on the bit line through capacitive coupling. When the input weight value is +1, the voltage applied to WL and WLB is VP, and when the input weight value is -1, the voltage applied to WL and WLB is VN.

[0042] The first and second capacitors have an MFS structure.

[0043] In this application, the ferroelectric capacitor cross array is 128×128; the ADC accuracy can be adjusted to meet different accuracy requirements. Figure 4 The simulation results show that the output voltage under simulation conditions is consistent with the ideal result, and the circuit calculation results have good linearity.

[0044] Example 4

[0045] Based on the above embodiments, the difference is that the ferroelectric capacitor cross array in this embodiment is 256×256; the ADC accuracy can be adjusted to adapt to different accuracy requirements. It can be implemented using different process nodes such as 22 nm and 28 nm; it can be integrated with other non-volatile memories (such as RRAM and PCM).

[0046] contrast Figure 5 -a Equivalent circuit diagram of traditional interface circuit. The main part of the reading circuit is an integrating circuit composed of operational amplifier negative feedback. The output of the reading circuit is connected to an analog-to-digital converter (ADC) to realize the conversion of analog signals to digital signals. Figure 5-b This diagram illustrates the power consumption of traditional read circuits in memristor-based and ferroelectric memory (FCA) architectures. In FCA architectures, the power consumption of read circuits exceeds 50%, which is a key factor limiting the energy efficiency of FCA chips.

[0047] Example 5

[0048] Based on the above embodiments, this embodiment is an operational amplifier-less ferroelectric capacitor in-memory computing system, which includes an operational amplifier-less ferroelectric capacitor in-memory computing accelerator.

Claims

1. A ferroelectric capacitor in-memory computing accelerator without operational amplifier, comprising a ferroelectric capacitor crossbar array, a timing control circuit, a decoder and driver, and an analog-to-digital converter; the ferroelectric capacitor crossbar array is used for storing binary weights, the timing control circuit is used for controlling read-write computing timing, the decoder and driver are used for address decoding and voltage driving, and the analog-to-digital converter is used for voltage quantization; characterized in that the ferroelectric capacitor crossbar array comprises array bit lines BL, array word lines WL and array word line bars WLB; the word lines WL and the word line bars WLB are parallel to each other, and the bit lines BL are located in the vertical direction of the word lines WL and the word line bars WLB; the word lines WL and the word line bars WLB are connected with first capacitors and second capacitors; one end of the first capacitor is connected with the bit line BL, and the other end is connected with the word line WL; one end of the second capacitor is connected with the bit line BL, and the other end is connected with the word line bar WLB.

2. A ferroelectric capacitor in-memory computing accelerator without operational amplifier according to claim 1, characterized in that, The ferroelectric capacitor crossbar array adjusts the first capacitors and the second capacitors through a weight mapping method of a binary neural network BNN.

3. A ferroelectric capacitor in-memory computing accelerator without operational amplifier according to claim 1, characterized in that, The ferroelectric capacitor cross array adjusts the first capacitor and the second capacitor through a weight mapping method of a binary neural network (BNN), and the adjustment is realized in the following manner: when the weight is +1, the first capacitor is in a high capacitance state C HCS , and the second capacitor is in a low capacitance state C LCS ; when the weight is -1, the first capacitor is in a low capacitance state C LCS , and the second capacitor is in a high capacitance state C HCS .

4. The ferroelectric capacitor in-memory computing accelerator of claim 1, wherein, The ferroelectric capacitor crossbar array outputs voltage in an array manner, comprising: Step 1: all bit lines BL, word lines WL and word line bars WLB are pre-charged to a common-mode voltage Vcm; Step 2: charge sharing, different voltages are applied on WL and WLB according to the input weight value, and net charge is generated on the bit line through capacitive coupling; Step 3, voltage output, total charge on bit line converted directly to voltage by total capacitance Ctotal Output; the output voltage formula is: where Vout is the output voltage Ctotal is the total capacitance constant on the BL, Din is the input data, W is the network weight, Vread is the small signal read voltage of the ferroelectric capacitor, Ntotal is the total number of charges generated on the bit line at the time of calculation.

5. The ferroelectric capacitor in-memory computing accelerator of claim 1, wherein, different voltages are applied on WL and WLB according to the input weight value, and net charge is generated on the bit line through capacitive coupling; when the input weight value is +1, the applied voltage on WL and WLB is VP; when the input weight value is -1, the applied voltage on WL and WLB is VN.

6. The ferroelectric capacitor in-memory computing accelerator of claim 1, wherein, The structure of the first capacitor and the second capacitor comprises an MFM structure or an MFS structure.

7. A ferroelectric capacitor in-memory computing system without an operational amplifier, comprising: The ferroelectric capacitor in-memory computing accelerator without operational amplifier comprises any one of claims 1-6.

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